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| INTEGRATED CIRCUITS DATA SHEET SAA56xx Enhanced TV microcontrollers with On-Screen Display (OSD) Product specification Supersedes data of 2001 Feb 13 File under Integrated Circuits, IC02 2001 Dec 13 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) CONTENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION MICROCONTROLLER MEMORY ORGANISATION POWER-ON RESET POWER SAVING MODES OF OPERATION I/O FACILITY INTERRUPT SYSTEM TIMERS/COUNTERS WATCHDOG TIMER PORT ALTERNATIVE FUNCTIONS PULSE WIDTH MODULATORS I2C-BUS SERIAL I/O UART PERIPHERAL LED SUPPORT EXTERNAL SRAM/ROM INTERFACE 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 MEMORY INTERFACE DATA CAPTURE DISPLAY SAA56xx MEMORY MAPPED REGISTERS (MMRs) IN-SYSTEM PROGRAMMING INTERFACE LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS QUALITY AND RELIABILITY APPLICATION INFORMATION EMC GUIDELINES PACKAGE OUTLINE SOLDERING DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2001 Dec 13 2 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 1 FEATURES SAA56xx * Single-chip higher frequency microcontroller with integrated On-Screen Display (OSD) * Versions available with integrated Data Capture * Both active HIGH and active LOW reset pins * OTP memory for both Program ROM and character sets * In-System Programming (ISP) option for the embedded OTP memories using IEEE1149 (JTAG: Joint Test Action Group) interface * Single power supply: 3.0 to 3.6 V * 5 V tolerant digital inputs and I/O * 32 I/O ports via individual addressable controls * Larger Character ROM, up to 1020 characters of 12 x 10 pixels * Smoothing capability on sized characters * Programmable I/O for push-pull, open-drain and quasi-bidirectional and high-impedance * Two port lines with 8 mA sink (at <0.4 V) capability, for direct drive of LED * Single crystal oscillator for microcontroller, OSD and Data Capture * Power reduction modes: Idle, Standby and Power-down * Byte level I2C-bus up to 400 kHz dual port I/O * 64 Dynamically Redefinable Characters for OSDs * Increased special graphic characters allowing four colours per character * Selectable character height 9, 10, 13 and 16 TV lines * Pin compatibility throughout family * Operating temperature: -20 to +70 C. 2 GENERAL DESCRIPTION The SAA56xx family of microcontrollers are a derivative of the Philips industry-standard 80C51 microcontroller and are intended for use as the central control mechanism in a television receiver. They provide control functions for the television system, OSD and incorporate an integrated Data Capture and display function for either Teletext or Closed Caption. Additional features over the SAA55xx family have been included, e.g. 100/120 Hz (2H/2V only) display timing modes, two page operation (50/60 Hz mode for 16:9, 4:3), higher frequency microcontroller, increased character storage, more 80C51 peripherals and a larger Display memory. For CC operation, only a 50/60 Hz display option is available. As with the rest of the SAA55xx family, the Data Capture hardware can decode and display both 525-line and 625-line World System Teletext (WST), Closed Caption information, Video Programming System (VPS) Information and Wide Screen Signalling (WSS) information. The same display hardware is used for Teletext, Closed Caption and On-Screen Display, which means that the display features available give greater flexibility to differentiate the TV set. The family of devices offers a range of memory variants with Program ROM sizes of 128-kbyte and 192-kbyte, also up to 14 kbytes of RAM. 2001 Dec 13 3 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 3 QUICK REFERENCE DATA SYMBOL Supply VDDX IDDP IDDC IDD(id) IDD(pd) IDDA IDDA(id) IDDA(pd) fxtal Tamb Tstg 4 any supply voltage (VDD to VSS) periphery supply current core supply current Idle mode supply current Power-down mode supply current analog supply current Idle mode analog supply current Power-down mode analog supply current crystal frequency operating ambient temperature storage temperature 3.0 1.0 - - - - - - - -20 -55 3.3 - 15.0 4.6 0.76 45.0 0.87 0.45 12.0 - - 3.6 - PARAMETER MIN. TYP. SAA56xx MAX. UNIT V mA mA mA mA mA mA mA MHz C C 18.0 6.0 1.0 48.0 1.0 0.7 - +70 +125 ORDERING INFORMATION TYPE NUMBER(1) PACKAGE ROM NAME DESCRIPTION VERSION SOT407-1 192-kbyte 128-kbyte 192-kbyte 128-kbyte DATA RAM DATA CAPTURE SAA5667HL/nnnn LQFP100 plastic low profile quad flat package; 100 leads; body SAA5665HL/nnnn 14 x 14 x 1.4 mm SAA5647HL/nnnn SAA5645HL/nnnn Notes 2-kbyte(2) text and line 21 text and line 21 line 21 only line 21 only 1. `nnnn' is a four digit number uniquely referencing the microcontroller program mask. 2. Extendible to 8-kbyte in external SRAM application, see Fig.8. 2001 Dec 13 4 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 5 BLOCK DIAGRAM SAA56xx handbook, full pagewidth I2C-bus, general I/O TV CONTROL AND INTERFACE ROM (128 or 192-kbyte) MICROPROCESSOR (80C51) SRAM 256-byte DRAM (14-kbyte) MEMORY INTERFACE R CVBS DATA CAPTURE DISPLAY G B VDS CVBS DATA CAPTURE TIMING DISPLAY TIMING GSA023 HSYNC VSYNC Fig.1 Block diagram (top level architecture). 2001 Dec 13 5 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 6 6.1 PINNING INFORMATION Pinning SAA56xx 100 P2.0/TPWM 99 VSSC 98 P2.6/PWM5 97 P2.5/PWM4 96 P2.4/PWM3 95 P2.3/PWM2 94 P2.2/PWM1 93 P2.1/PWM0 84 P1.5/SDA1 82 P1.7/SDA0 83 P1.4/SCL1 81 P1.6/SCL0 79 P1.2/INT0 handbook, full pagewidth P2.7/PWM6 P3.0/ADC0 A17_LN P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 A15_LN A14 RD 1 2 3 4 5 6 7 8 9 76 P1.0/INT1 75 VDDP 74 MOVX_RD 73 RESET 72 RESET 71 XTALOUT 70 XTALIN 69 OSCGND 68 MOVX_WR 67 A8 66 A9 65 A10 64 A11 63 VDDC 62 VSSC 61 INTD 60 VSSP 59 P3.6 58 ROMBK0 57 ROMBK1 56 ROMBK2 55 VSYNC 54 P3.5/INT5 53 HSYNC 52 VDS 51 RAMBK0 WR 10 VSSC 11 VSSP 12 P0.5 13 EA 14 A7 15 P0.0/RX 16 P0.1/TX 17 P0.2/INT2 18 PSEN 19 ALE 20 VPE 21 P0.3/INT3 22 A6 23 P0.4/INT4 24 P3.7 25 SAA56xx A5 26 A4 27 P0.6 28 P0.7/T2 29 VSSA 30 CVBS0 31 CVBS1 32 A15_BK 33 SYNC_FILTER 34 IREF 35 A13 36 A12 37 A3 38 A2 39 A1 40 FRAME 41 VPE 42 COR 43 P3.4/PWM7/T2EX 44 VDDA 45 B 46 G 47 R 48 A0 49 77 A16_LN 80 P1.3/T1 78 P1.1/T0 92 AD7 91 AD6 90 AD5 89 AD4 88 AD3 87 AD2 86 AD1 85 AD0 RAMBK1 50 GSA020 Fig.2 Pin configuration. 2001 Dec 13 6 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 6.2 Pin description LQFP100 package PIN 100 93 94 95 96 97 98 1 2 4 5 6 44 54 59 25 11, 62, 99 16 17 18 22 24 13 28 29 30 31 32 34 35 41 21, 42 43 45 46 TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O - I I I/O I O I O - O analog ground core ground DESCRIPTION SAA56xx Table 1 SYMBOL P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 P3.4/PWM7/T2EX P3.5/INT5 P3.6 P3.7 VSSC P0.0/RX P0.1/TX P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5 P0.6 P0.7/T2 VSSA CVBS0 CVBS1 SYNC_FILTER IREF FRAME VPE COR VDDA B Port 2. 8-bit programmable bidirectional port with alternative functions. P2.0/TPWM is the output for the 14-bit high precision PWM; P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6. Port 3. 8-bit programmable bidirectional port with alternative functions. P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility and P3.4/PWM7 is the output for the 6-bit PWM7; P3.4/PWM7/T2EX is the output for the 6-bit PWM7 or the Timer 2 control; P3.5/INT5 is the external Interrupt 5; P3.6 and P3.7 have no alternative functions. Port 0. 8-bit programmable bidirectional port (with alternative functions). P0.0/RX and P0.1/TX are respectively the serial transmit and receive lines for the UART; P0.2/INT2 to P0.4/INT4 are the external interrupts 2 to 4; P0.5 and P0.6 have no alternative functions and have 8 mA current sinking capability for direct drive of LEDs. 2 composite video input selectable via SFR; a positive-going 1 V (peak-to-peak) input is required, connected via a 100 nF capacitor CVBS sync filter input; this pin should be connected to VSSA via a 100 nF capacitor. Reference current input for analog circuits, connected to VSSA via a 24 k resistor. De-interlace output synchronized with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection circuits. OTP programming voltage Open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display. +3.3 V analog power supply pixel rate output of the BLUE colour information 2001 Dec 13 7 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SYMBOL G R VDS HSYNC VSYNC VSSP VDDC OSCGND XTALIN XTALOUT RESET RESET PIN 47 48 52 53 55 12, 60 63 69 70 71 72 73 TYPE O O O I I - - - I O I I DESCRIPTION pixel rate output of the GREEN colour information pixel rate output of the RED colour information video/data switch push-pull output for dot rate fast blanking SAA56xx Schmitt triggered input for a TTL-level version of the horizontal sync pulse; the polarity of this pulse is programmable by register bit TXT1.H POLARITY. Schmitt triggered input for a TTL-level version of the vertical sync pulse; the polarity of this pulse is programmable by register bit TXT1.V POLARITY. periphery ground +3.3 V core power supply crystal oscillator ground 12 MHz crystal oscillator input 12 MHz crystal oscillator output If the reset input is LOW for at least 24 crystal oscillator periods while the oscillator is running, the device is reset (internal pull-up). If the reset input is HIGH for at least 24 crystal oscillator periods while the oscillator is running, the device is reset. This pin should be connected to VDDC via a capacitor if an active HIGH reset is required (internal pull-down). +3.3 V periphery power supply Port 1. 8-bit programmable bidirectional port with alternative functions. P1.0/INT1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse; P1.1/T0 is Timer/counter 0; P1.2/INT0 is external interrupt 0; P1.3/T1 is Timer/counter 1; P1.6/SCL0 is the serial clock input for the I2C-bus; P1.7/SDA0 is the serial data port for the I2C-bus; P1.4/SCL1 is the serial clock input for the I2C-bus; P1.5/SDA1 is the serial data port for the I2C-bus. VDDP P1.0/INT1 P1.1/T0 P1.2/INT0 P1.3/T1 P1.6/SCL0 P1.7/SDA0 P1.4/SCL1 P1.5/SDA1 RD WR EA PSEN ALE AD0 to AD7 A0 to A7 75 76 78 79 80 81 82 83 84 9 10 14 19 20 85 to 92 49, 40, 39, 38, 27, 26, 23, 15 67 to 64, 37, 36, 8 7, 77, 3 68 74 - I/O I/O I/O I/O I/O I/O I/O I/O O O I O O I/O O read control signal to external data memory write control signal to external data memory Control signal used to select external (LOW) or internal (HIGH) program memory (internal pull-up). enable signal for external program memory external latch enable signal; active HIGH address lines A0 to A7 multiplexed with data lines D0 to D7. address lines A0 to A7 A8 to A14 A15_LN to A17_LN MOVX_WR MOVX_RD O O O O address lines A8 to A14 address lines A15 to A17; note 1 MOVX Write for Hitex 80C51 emulation (internal MOVX Write instruction) MOVX Read for Hitex 80C51 emulation (internal MOVX Read instruction) 2001 Dec 13 8 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SYMBOL A15_BK ROMBK0 to ROMBK2 RAMBK0 to RAMBK1 INTD Note PIN 33 58 to 56 51, 50 61 TYPE O O O I DESCRIPTION SAA56xx address line A15 when using ROMBK outputs for external program ROM access ROMBK SFR selection bits for external program ROM access >64 kbytes RAMBK SFR selection bits for external program SRAM data storage >64 kbytes. Use A0 to A14 and A15_BK as lower address bits. interrupt disable for emulation (internal pull-up) 1. A15_LN, A16_LN and A17_LN form a linear address space and may be used as an alternative to A15_BK (pin 33) and ROMBK2 to ROMBK0 (pins 56, 57 and 58) for external program ROM access. 7 MICROCONTROLLER * UART for asynchronous serial communication * External ROM and SRAM compatibility. 8 MEMORY ORGANISATION The functionality of the microcontroller used in this device is described here with reference to the industry standard 80C51 microcontroller. A full description of its functionality can be found in "Handbook IC20 80C51-Based 8-bit Microcontrollers". 7.1 Microcontroller features The device has the capability of a maximum of 192-kbyte Program ROM and 14-kbyte Data RAM internally. 8.1 ROM bank switching * 80C51 microcontroller core standard instruction set and timing * 0.5 s machine cycle * Maximum 192K x 8-bit Program ROM * Maximum of 14K x 8-bit data and display RAM * 15-level interrupt controller with individual enable/disable and two level priority * Up to six external interrupts with programmable detection characteristics * Three 16-bit Timer/counter registers * Watchdog Timer * Auxiliary RAM page pointer * 16-bit Data pointer * Idle, Standby and Power-down modes * 32 general I/O lines * Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals * One 14-bit PWM for Voltage Synthesis Tuner (VST) control * 8-bit Analog-to-Digital Converter (ADC) with four multiplexed inputs * Two high current outputs for directly driving LEDs etc. * I2C-bus byte level interface with dual ports The 128-kbyte Program ROM variant is arranged in four banks of 32 kbytes. One of the 32-kbyte banks is common and is always addressable. The other three banks (Bank 0, Bank 1 and Bank 2) can be selected with SFR ROMBK bits <2:0> (see Table 2 and Fig. 3). The 192-kbyte Program ROM variant is arranged in six banks of 32 kbytes. One of the 32-kbyte banks is common and is always addressable. The other five banks (Bank 0, Bank 1, Bank 2, Bank 3 and Bank 4) can be selected with SFR ROMBK bits <2:0> (see Table 2 and Fig. 3). Table 2 ROM bank selection 0 to 32-kbyte common common common common common reserved reserved reserved 32 to 64-kbyte Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 reserved reserved reserved ROMBK2 ROMBK1 ROMBK0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2001 Dec 13 9 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth Physical address Range: 32 to 64-kbyte FFFFH BANK 0 (32-kbyte) 8000H Physical address Range: 64 to 96-kbyte FFFFH BANK 1 (32-kbyte) 8000H Physical address Physical address Physical address Range: 96 to 128-kbyte Range: 128 to 160-kbyte Range: 160 to 192-kbyte FFFFH BANK 2 (32-kbyte) 8000H FFFFH BANK 3 (32-kbyte) 8000H FFFFH BANK 4 (32-kbyte) 8000H 7FFFH COMMON (32-kbyte) 0000H GSA073 Physical address Range: 0 to 32-kbyte Fig.3 Internal program memory. 2001 Dec 13 10 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 8.2 ROM protection and verification SAA56xx The security bits can be programmed once only and cannot be erased. The SAA56xx security bits are set as shown in Fig.4 for production programmed devices and are set as shown in Fig.5 for production blank devices. SAA56xx devices have a set of security bits allied with each section of the device, i.e. Program ROM, Character ROM and Packet 26 ROM. The security bits are used to prevent the ROM from being overwritten once programmed, and also the contents being verified once programmed. handbook, full pagewidth MEMORY SECURITY BITS SET USER ROM PROGRAMMING VERIFY PROGRAM ROM (128 or 192 kbytes) DISABLED ENABLED CHARACTER ROM (12 kbytes) DISABLED ENABLED PACKET 26 ROM (4 kbytes) DISABLED ENABLED GSA036 Fig.4 Security bits for production programmed devices. handbook, full pagewidth MEMORY SECURITY BITS SET USER ROM PROGRAMMING VERIFY PROGRAM ROM (128 OR 192 kbytes) ENABLED ENABLED CHARACTER ROM (12 kbytes) ENABLED ENABLED PACKET 26 ROM (4 kbytes) ENABLED ENABLED GSA037 Fig.5 Security bits for production blank devices. 2001 Dec 13 11 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 8.3 RAM organisation SAA56xx The upper 128 bytes are not allocated for any special area or functions. Table 3 Bank selection RS0 0 1 0 1 BANK Bank 0 Bank 1 Bank 2 Bank 3 Figure 6 shows the internal Data RAM is organised into two areas: Data memory and the Special Function Registers (SFRs). 8.4 Data memory RS1 0 0 1 1 The Data memory (see Fig.6) is 256 x 8 bits and occupies address range 00H to FFH when using indirect addressing and 00H to 7FH when using direct addressing. The SFRs occupy the address range 80H to FFH and are accessible using direct addressing only. The lower 128 bytes of Data memory are mapped as shown in Fig.7. The lowest 32 bytes are grouped into four banks of eight registers selectable via SFR PSW bits <4:3> (RS1/RS0; see Table 3), the next 16 bytes above the register banks form a block of bit addressable memory space. handbook, halfpage 7FH handbook, halfpage DATA MEMORY SPECIAL FUNCTION REGISTERS 2FH bit-addressable space (bit addresses 00H to 7FH) 20H 1FH 11 = BANK 3 18H 17H 10 = BANK 2 10H 0FH 01 = BANK 1 08H 07H 00 = BANK 0 00H GSA060 FFH upper 128 bytes 80H 7FH lower 128 bytes 00H accessible by direct and indirect addressing MBK956 accessible by indirect addressing only accessible by direct addressing only bank select bits in PSW 4 banks of 8 registers (R0 to R7) Fig.6 Internal Data memory. Fig.7 Lower 128 bytes of internal RAM. 2001 Dec 13 12 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 8.5 SFR memory 2001 Dec 13 13 Philips Semiconductors Enhanced TV microcontrollers with On-Screen Display (OSD) The Special Function Register (SFR) space is used for port latches, timer, peripheral control, acquisition control and display control, etc. These registers can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. Table 4 only presents the additional SFRs of the SAA56xx family over the SAA55xx family of devices. This SFR map table must therefore be read in conjunction with the SAA55xx SFR map table. A description of the new SFR bits is shown in Table 5, which presents the SFRs in alphabetical order. Table 4 SFR memory map NAME P07 SP7 DPL7 DPH7 EX5 PX5 EX5CFG1 SMOD TF1 GATE TL07 TL17 TH07 TH17 P17 GPR17 GPR27 GPR37 GPR47 GPR57 P0CFGA7 P0CFGB7 0 SM0 S0BUF 7 P06 SP6 DPL6 DPH6 EX4 PX4 EX5CFG0 ARD TR1 C/T TL06 TL16 TH06 TH16 P16 GPR16 GPR26 GPR36 GPR46 GPR56 P0CFGA6 P0CFGB6 0 SM1 S0BUF6 6 P05 SP5 DPL5 DPH5 EX3 PX3 EX4CFG1 RFI TF0 M1 TL05 TL15 TH05 TH15 P15 GPR15 GPR25 GPR35 GPR45 GPR55 P0CFGA5 P0CFGB5 0 SM2 S0BUF5 5 P04 SP4 DPL4 DPH4 EX2 PX2 EX4CFG0 WLE TR0 M0 TL04 TL14 TH04 TH14 P14 GPR14 GPR24 GPR34 GPR44 GPR54 P0CFGA4 P0CFGB4 REN S0BUF4 4 P03 SP3 DPL3 DPH3 EUTX PUTX EX3CFG1 GF1 IE1 GATE TL03 TL13 TH03 TH13 P13 GPR13 GPR23 GPR33 GPR43 GPR53 P0CFGA3 P0CFGB3 TB8 S0BUF3 3 P02 SP2 DPL2 DPH2 EURX PURX EX3CFG0 GF0 IT1 C/T TL02 TL12 TH02 TH12 P12 GPR12 GPR22 GPR32 GPR42 GPR52 P0CFGA2 P0CFGB2 SAD2 RB8 S0BUF2 2 P01 SP1 DPL1 DPH1 EUART PUART EX2CFG1 PD IE0 M1 TL01 TL11 TH01 TH11 P11 GPR11 GPR21 GPR31 GPR41 GPR51 P0CFGA1 P0CFGB1 SAD1 TI S0BUF1 1 P00 SP0 DPL0 DPH0 ET2 PT2 EX2CFG0 IDL IT0 M0 TL00 TL10 TH00 TH10 P10 GPR10 GPR20 GPR30 GPR40 GPR50 P0CFGA0 P0CFGB0 SAD0 RI S0BUF0 0 RESET FFH 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H ADD R/W 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH R/W P0 R/W SP R/W DPL R/W DPH R/W IEN1 R/W IP1 R/W EXTINT R/W PCON R/W TCON R/W TMOD R/W TL0 R/W TL1 8CH R/W TH0 8DH R/W TH1 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH R/W P1 R/W GPR1 R/W GPR2 R/W GPR3 R/W GPR4 R/W GPR5 R/W P0CFGA R/W P0CFGB R/W SADB R/W S0CON R/W S0BUF Product specification 00H FFH 00H 00H 00H 00H SAA56xx DC_COMP SAD3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Dec 13 14 Philips Semiconductors ADD R/W NAME 7 GPR67 GPR77 P1CFGA7 P1CFGB7 P27 - 9FE11 BFE7 - GPR87 P2CFGA7 P2CFGB7 EA NOT B 3 6 GPR66 GPR76 P1CFGA6 P1CFGB6 P26 - 9FF11 BFE6 - GPR86 P2CFGA6 P2CFGB6 EBUSY NOT B 2 5 GPR65 GPR75 P1CFGA5 P1CFGB5 P25 - 9FF10 BFE5 - GPR85 P2CFGA5 P2CFGB5 ES2 NOT B 1 CORB OUT B CORB OUT B C MESH ENABLE B ACTIVE PAGE 1 - NOT1 TC1 EXTENDED SPECIAL GRAPHICS 4 GPR64 GPR74 P1CFGA4 P1CFGB4 P24 - 9FF9 BFE4 - GPR84 P2CFGA4 P2CFGB4 ECC NOT B 0 3 GPR63 GPR73 P1CFGA3 P1CFGB3 P23 GPF11 9FF8 BFE3 BFE11 GPR83 P2CFGA3 P2CFGB3 ET1 2 GPR62 GPR72 P1CFGA2 P1CFGB2 P22 GPF10 9FF7 BFE2 BFE10 GPR82 P2CFGA2 P2CFGB2 EX1 1 GPR61 GPR71 P1CFGA1 P1CFGB1 P21 GPF9 9FF6 BFE1 BFE9 GPR81 P2CFGA1 P2CFGB1 ET0 BS B1 PICTURE ON OUT B PICTURE ON OUT B BOX ON 1 B to 23 B PAGE B1 P31 SCRB1 BS1 TS1 OSD LAN1 0 GPR60 GPR70 P1CFGA0 P1CFGB0 P20 GPF8 9FF5 BFE0 BFE8 GPR80 P2CFGA0 P2CFGB0 EX0 BS B0 PICTURE ON IN B PICTURE ON IN B RESET 00H 00H FFH 00H FFH 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H Enhanced TV microcontrollers with On-Screen Display (OSD) 9CH R/W GPR6 9DH R/W GPR7 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H R/W P1CFGA R/W P1CFGB R/W P2 R R R R TXT31 TXT32 TXT33 TXT34 R/W GPR8 R/W P2CFGA R/W P2CFGB R/W IEN0 R/W TXT23 EAST/WEST DRCS B B ENABLE AAH R/W TXT24 ABH R/W TXT25 ACH R/W TXT26 ADH R/W TXT28 B0H B1H B2H B3H B4H R/W P3 R/W TXT27 R/W TXT18 R/W TXT19 R/W TXT20 BKGND OUT BKGND IN B B BKGND OUT BKGND IN B B EXTENDED DRCS TRANS B CORB IN B TEXT OUT B TEXT IN B CORB IN B TEXT OUT B TEXT IN B B MESH ENABLE B DISPLAY BANK B P34 - NOT0 TC0 CHAR SELECT ENABLE 0 0 OSD LANG ENABLE I2C PORT 1 GPF3 SHADOW ENABLE B PAGE B3 P33 BOX ON 24 B PAGE B2 P32 SCRB2 0 0 OSD LAN2 BOX ON 0 B 00H PAGE B0 P30 SCRB0 BS0 TS0 OSD LAN0 00H FFH 00H 00H 00H 00H Product specification MULTI PAGE CC_TXT B 1 - NOT3 TEN DRCS ENABLE DISP LINES1 GPF7 1 - NOT2 TC2 OSD PLANES DISP LINES0 GPF6 SAA56xx B5H B6H R/W TXT21 R TXT22 CHAR SIZE1 CHAR SIZE0 GPF5 GPF4 CC ON GPF2 I2C PORT 0 GPF1 CC/TXT GPFO 02H XXH This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Dec 13 15 Philips Semiconductors ADD R/W B7H B8H B9H NAME 0 0 0 0 0 7 0 PBUSY FORCE ACQ1 0 0 6 0 PES2 FORCE ACQ0 0 0 WSS12 GPR95 P3CFGA5 P3CFGB5 AUTO FRAME ACQ OFF REQ2 - 5 CS4 PCC FORCE DISP1 WSS<3:0> ERROR WSS<7:4> ERROR WSS11 GPR94 P3CFGA4 P3CFGB4 DISABLE HEADER ROLL X26 OFF REQ1 PRD4 4 CS3 PT1 FORCE DISP0 WSS3 WSS7 WSS<10:8> ERROR GPR93 P3CFGA3 P3CFGB3 DISPLAY STATUS ROW ONLY FULL FIELD REQ0 PRD3 B MESH ENABLE TEXT OUT TEXT OUT DOUBLE HEIGHT PKT 26 RECEIVED R3 C3 D3 3 CS2 PX1 SCREEN COL2 WSS2 WSS6 WSS10 GPR92 P3CFGA2 P3CFGB2 DISABLE FRAME FIELD POLARITY SC2 PRD2 C MESH ENABLE TEXT IN TEXT IN 2 CS1 PT0 SCREEN COL1 WSS1 WSS5 WSS9 GPR91 P3CFGA1 P3CFGB1 VPS ON 1 CS0 PX0 SCREEN COL0 WSS0 WSS4 WSS8 GPR90 P3CFGA0 P3CFGB0 INV ON 0 RESET 15H 00H 00H 00H 00H 00H 00H FFH 00H 00H Enhanced TV microcontrollers with On-Screen Display (OSD) R/W CCLIN R/W IP R/W TXT17 WSS1 WSS2 WSS3 BAH R BBH R BCH R WSS<13:11> WSS13 ERROR GPR97 P3CFGA7 P3CFGB7 X24 POSN GPR96 P3CFGA6 P3CFGB6 DISPLAY X24 8-BIT REQ3 - QUAD WIDTH ENABLE BDH R/W GPR9 BEH R/W P3CFGA BFH R/W P3CFGB C0H R/W TXT0 C1H R/W TXT1 C2H R/W TXT2 C3H W TXT3 C4H R/W TXT4 EXT PKT OFF ACQ BANK - OSD BANK ENABLE H POLARITY SC1 PRD1 TRANS ENABLE PICTURE ON OUT PICTURE ON OUT V POLARITY SC0 PRD0 SHADOW ENABLE PICTURE ON IN PICTURE ON IN BOX ON 0 CVBS1/ CVBS0 R0 C0 D0 00H 00H 00H 00H EAST/WEST DISABLE DOUBLE HEIGHT COR OUT COR OUT REVEAL (reserved) 0 A0 C5 D5 COR IN COR IN BOTTOM/ TOP DISABLE SPANISH R4 C4 D4 C5H R/W TXT5 C6H R/W TXT6 C7H R/W TXT7 C8H R/W TXT8 C9H R/W TXT9 CAH R/W TXT10 CBH R/W TXT11 BKGND OUT BKGND IN BKGND OUT BKGND IN STATUS ROW TOP (reserved) 0 CURSOR FREEZE 0 D7 CURSOR ON FLICKER STOP ON CLEAR MEMORY 0 D6 03H 03H 00H Product specification 00H BOX ON 24 BOX ON 1-23 WSS WSS ON RECEIVED R2 C2 D2 R1 C1 D1 SAA56xx 00H 00H 00H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Dec 13 16 Philips Semiconductors ADD R/W CCH R NAME TXT12 7 525/625 SYNC 0 0 6 SPANISH 5 ROM VER3 4 3 2 ROM VER0 1 1 0 VIDEO SIGNAL QUALITY PAGE0 BLOCK0 CCBASE0 P GPR100 TD0 TD8 PW7V0 PW0V0 PW1V0 CCD10 CR0 0 DAT0 GC PW3V0 PW4V0 PW5V0 PW6V0 ACC0 OSD LAN B0 reserved GPR110 PW2V0 GPR120 GPR130 CCD20 RESET XXXX XX1X 00H 00H 20H 00H 00H 00H 40H 40H 40H 40H 00H 00H F8H 00H 00H 40H 40H 40H 40H 00H 00H 00H 00H 40H 00H 00H 00H Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) ROM VER2 ROM VER1 CDH R/W TXT14 CEH R/W TXT15 0 0 CCBASE6 AC GPR106 TD6 1 1 1 1 CCD16 ENSI STAT3 DAT6 ADR5 1 1 1 1 ACC6 TS B1 TC B1 GPR116 1 GPR126 GPR136 CCD26 0 0 CCBASE5 F0 GPR105 TD5 TD13 PW7V5 PW0V5 PW1V5 CCD15 STA STAT2 DAT5 ADR4 PW3V5 PW4V5 PW5V5 PW6V5 ACC5 TS B0 TC B0 GPR115 PW2V5 GPR125 GPR135 CCD25 DISPLAY BANK MICRO BANK CCBASE4 RS1 GPR104 TD4 TD12 PW7V4 PW0V4 PW1V4 CCD14 STO STAT1 DAT4 ADR3 PW3V4 PW4V4 PW5V4 PW6V4 ACC4 OSD PLANES B reserved GPR114 PW2V4 GPR124 GPR134 CCD24 PAGE3 BLOCK3 CCBASE3 RS0 GPR103 TD3 TD11 PW7V3 PW0V3 PW1V3 CCD13 SI STAT0 DAT3 ADR2 PW3V3 PW4V3 PW5V3 PW6V3 ACC3 OSD LANG ENABLE B reserved GPR113 PW2V3 GPR123 GPR133 CCD23 PAGE2 BLOCK2 CCBASE2 OV GPR102 TD2 TD10 PW7V2 PW0V2 PW1V2 CCD12 AA 0 DAT2 ADR1 PW3V2 PW4V2 PW5V2 PW6V2 ACC2 OSD LAN B2 reserved GPR112 PW2V2 GPR122 GPR132 CCD22 PAGE1 BLOCK1 CCBASE1 - GPR101 TD1 TD9 PW7V1 PW0V1 PW1V1 CCD11 CR1 0 DAT1 ADR0 PW3V1 PW4V1 PW5V1 PW6V1 ACC1 OSD LAN B1 reserved GPR111 PW2V1 GPR121 GPR131 CCD21 CFH R/W CCBASE CCBASE7 D0H R/W PSW D1H R/W GPR10 D2H R/W TDACL D3H R/W TDACH D4H R/W PWM7 D5H R/W PWM0 D6H R/W PWM1 D7H R D9H R CCDAT1 S1STA D8H R/W S1CON DAH R/W S1DAT DBH R/W S1ADR DCH R/W PWM3 DDH R/W PWM4 DEH R/W PWM5 DFH R/W PWM6 E0H E1H E2H E3H E4H E5H E6H E7H R/W ACC R/W TXT29 R/W TXT30 R/W GPR11 R/W PWM2 R/W GPR12 R/W GPR13 R CCDAT2 C GPR107 TD7 TPWE PW7E PW0E PW1E CCD17 CR2 STAT4 DAT7 ADR6 PW3E PW4E PW5E PW6E ACC7 TEN B TC B2 GPR117 PW2E GPR127 GPR137 CCD27 SAA56xx This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Dec 13 17 Philips Semiconductors ADD R/W E8H E9H NAME VHI GPR147 GPR157 GPR167 GPR177 GPR187 PKT1-247 - B7 TF2 - RCAP2L7 RCAP2H7 TL27 TH27 VPS RECEIVED GPR197 XRAMP7 STANDBY GPR207 TEST7 WDV7 7 CH1 GPR146 GPR156 GPR166 GPR176 GPR186 PKT1-246 - B6 EXF2 - RCAP2L6 RCAP2H6 TL26 TH26 6 CH0 GPR145 GPR155 GPR165 GPR175 GPR185 PKT1-245 - B5 RCLK0 - RCAP2L5 RCAP2H5 TL25 TH25 5 ST GPR144 GPR154 GPR164 GPR174 GPR184 PKT1-244 - B4 TCLK0 - RCAP2L4 RCAP2H4 TL24 TH24 525 TEXT GPR194 XRAMP4 RAMBK1 GPR204 TEST4 WKEY4 WDV4 4 SAD7 GPR143 GPR153 GPR163 GPR173 GPR183 PKT1-243 - B3 EXEN2 - RCAP2L3 RCAP2H3 TL23 TH23 625 TEXT GPR193 XRAMP3 RAMBK0 GPR203 TEST3 WKEY3 WDV3 3 2 SAD6 GPR142 GPR152 GPR162 GPR172 GPR182 PKT1-242 - B2 TR2 T2RD RCAP2L2 RCAP2H2 TL22 TH22 PKT 8/30 GPR192 XRAMP2 ROMBK2 GPR202 TEST2 WKEY2 WDV2 SAD5 GPR141 GPR151 GPR161 GPR171 GPR181 PKT1-241 PKT1-249 B1 C/T2 T2OE RCAP2L1 RCAP2H1 TL21 TH1 FASTEXT GPR191 XRAMP1 ROMBK1 GPR201 TEST1 WKEY1 WDV1 1 SAD4 GPR140 GPR150 GPR160 GPR170 GPR180 PKT1-240 PKT1-248 B0 CP/RL2 DCEN RCAP2L0 RCAP2H0 TL20 TH20 0 GPR190 XRAMP0 ROMBK0 GPR200 TEST0 WKEY0 WDV0 0 RESET 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H XXXX XXX0 00H 00H 00H 00H 00H 00H 00H Enhanced TV microcontrollers with On-Screen Display (OSD) R/W SAD R/W GPR14 EAH R/W GPR15 EBH R/W GPR16 ECH R/W GPR17 EDH R/W GPR18 EEH R/W TXT35 EFH R/W TXT36 F0H F1H F2H F3H F4H F5H F6H F8H F9H FAH R/W B R/W T2CON R/W T2MOD R/W RCAP2L R/W RCAP2H R/W TL2 R/W TH2 R/W TXT13 R/W GPR19 R/W XRAMP PAGE 525 CLEARING DISPLAY GPR196 XRAMP6 IIC_LUT1 GPR206 TEST6 WKEY6 WDV6 GPR195 XRAMP5 IIC_LUT0 GPR205 TEST5 WKEY5 WDV5 FBH R/W ROMBK FCH R/W GPR20 FDH R FEH W FFH TEST WDTKEY WKEY7 R/W WDT Product specification SAA56xx Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) Table 5 SFR bit description BITS Accumulator (ACC) ACC7 to ACC0 B Register (B) B7 to B0 CC Base Pointer (CCBASE) CCBASE7 to CCBASE0 CC data byte 1 (CCDAT1) CCD17 to CCD10 CC data byte 2 (CCDAT2) CCD26 to CCD20 CC line (CCLIN) CS4 to CS0 Data Pointer High byte (DPH) DPH7 to DPH0 Data Pointer Low byte (DPL) DPL7 to DPL0 Closed Caption slice line using 525-line number Closed Caption second data byte Closed Caption first data byte Closed Caption display base pointer B register value accumulator value FUNCTION SAA56xx data pointer high byte, used with DPL to address auxiliary memory data pointer low byte, used with DPH to address auxiliary memory External Interrupt (EXTINT) (n = 2 to 5) EXnCFG<1:0> = 00 EXnCFG<1:0> = 01 EXnCFG<1:0> = 10 EXnCFG<1:0> = 11 active LOW interrupt rising edge interrupt falling edge interrupt both rising and falling edge interrupt General Purpose Registers (GPR1 to GPR20) (n = 1 to 21) GPRn<7:0> Interrupt Enable Register 0 (IEN0) EA EBUSY ES2 ECC ET1 EX1 ET0 EX0 disable all interrupts (logic 0), or use individual interrupt enable bits (logic 1) enable BUSY interrupt enable I2C-bus interrupt enable Closed Caption interrupt enable Timer 1 interrupt enable external interrupt 1 enable Timer 0 interrupt enable external interrupt 0 general purpose read/write registers available for use by the embedded software 2001 Dec 13 18 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Interrupt Enable Register 1 (IEN1) EX5 EX4 EX3 EX2 EUTX EURX EUART ET2 Interrupt Priority Register 0 (IP) PBUSY PES2 PCC PT1 PX1 PT0 PX0 Interrupt Priority Register 1 (IP1) PX5 PX4 PX3 PX2 PUTX PURX PUART PT2 Port 0 (P0) P07 to P00 Port 1 (P1) P17 to P10 Port 2 (P2) P27 to P20 Port 3 (P3) P34 to P30 Port 3 I/O register connected to external pins Port 2 I/O register connected to external pins Port 1 I/O register connected to external pins Port 0 I/O register connected to external pins priority external interrupt 5 priority external interrupt 4 priority external interrupt 3 priority external interrupt 2 priority UART transmitter interrupt priority UART receiver interrupt priority UART transmitter/receiver interrupt priority Timer 2 interrupt priority EBUSY interrupt priority ES2 interrupt priority ECC interrupt priority Timer 1 interrupt priority external interrupt 1 priority Timer 0 interrupt priority external interrupt 0 enable external interrupt 5 enable external interrupt 4 enable external interrupt 3 enable external interrupt 2 enable UART transmitter interrupt enable UART receiver interrupt enable UART transmitter/receiver interrupt enable Timer 2 interrupt FUNCTION SAA56xx 2001 Dec 13 19 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS FUNCTION SAA56xx Port 0 Configuration A (P0CFGA) and Port 0 Configuration B (P0CFGB) P0CFGA<7:0> and P0CFGB<7:0> These two registers are used to configure Port 0 lines. For example, the configuration of Port 0 pin 3 is controlled by setting bit 3 in both P0CFGA and P0CFGB. P0CFGB 2001 Dec 13 20 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Program Status Word (PSW) C AC F0 RS1 to RS0 carry bit auxiliary carry bit flag 0 register bank selector bits RS<1:0>: 00 = Bank 0 (00H to 07H) 01 = Bank 1 (08H to 0FH) 10 = Bank 2 (10H to 17H) 11 = Bank 3 (18H to 1FH) OV P overflow flag parity bit FUNCTION SAA56xx Pulse Width Modulator 0 Control Register (PWM0) PW0E PW0V5 to PW0V0 activate this PWM and take control of respective port pin (logic 1) pulse width modulator high time Pulse Width Modulator 1 Control Register (PWM1) PW1E PW1V5 to PW1V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 2 Control Register (PWM2) PW2E PW2V5 to PW2V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 3 Control Register (PWM3) PW3E PW3V5 to PW3V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 4 Control Register (PWM4) PW4E PW4V5 to PW4V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 5 Control Register (PWM5) PW5E PW5V5 to PW5V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 6 Control Register (PWM6) PW6E PW6V5 to PW6V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 7 Control Register (PWM7) PW7E PW7V5 to PW7V0 activate this PWM (logic 1) pulse width modulator high time Timer 2 Reload Capture High Byte (RCAP2H) RCAP2H7 to RCAP2H0 Timer 2 capture/reload high byte 2001 Dec 13 21 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Timer 2 Reload Capture Low Byte (RCAP2L) RCAP2L7 to RCAP2L0 ROM Bank (ROMBK) STANDBY IIC_LUT1 to IIC_LUT0 standby activation bit I2C-bus lookup table selection; IIC_LUT<1:0>: 00 = P8xC558 normal mode 01 = P8xC558 fast mode 10 = P8xC558 slow mode 11 = reserved RAMBK1 to RAMBK0 RAM Bank selection bits RAMBK<1:0>: 00 = Bank 0 (0 to 64 kbytes) 01 = Bank 1 (64 to 128 kbytes) 10 = Bank 2 (128 to 192 kbytes) 11 = Bank 3 (192 to 256 kbytes) ROMBK2 to ROMBK0 ROM Bank selection bits ROMBK<2:0>: 000 = Bank 0 (32 to 64 kbytes) 001 = Bank 1 (64 to 96 kbytes) 010 = Bank 2 (96 to 128 kbytes) 011 = Bank 3 (128 to 160 kbytes) 100 = Bank 4 (160 to 192 kbytes) 101 to 111 = reserved UART Buffer (S0BUF) S0BUF7 to S0BUF0 UART Control Register (S0CON) SM0 to SM1 UART mode selection bits SM<0:1>: 00, Mode 0, Shift Register 01, Mode 2, 9-bit UART 10, Mode 1, 8-bit UART (variable baud rate) 11, Mode 3, 9-bit UART (variable baud rate) SM2 UART data buffer Timer 2 capture/reload low byte FUNCTION SAA56xx Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if the received 9th data bit is logic 0. In Mode 1, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if no valid stop bit was received. In Mode 0, SM2 has no influence. Enables serial reception. Set by software to enable reception. Cleared by software to disable reception. Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as desired. In Modes 2 and 3, RB8 is the 9th data bit that was received. In Mode 1, if SM2 is logic 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Loading of RB8 in Modes 1, 2 and 3 depends on SM2. REN TB8 RB8 2001 Dec 13 22 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS TI FUNCTION SAA56xx Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software. Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. RI I2C-bus Slave Address Register (S1ADR) ADR6 to ADR0 GC I2C-bus Control Register (S1CON) CR2 to CR0 clock rate bits; CR<2:0>: (for nominal mode) 000 = 200 kHz bit rate 001 = 7.5 kHz bit rate 010 = 300 kHz bit rate 011 = 400 kHz bit rate 100 = 50 kHz bit rate 101 = 3.75 kHz bit rate 110 = 75 kHz bit rate 111 = 100 kHz bit rate ENSI STA enable I2C-bus interface (logic 1) START flag. When this bit is set in slave mode, the hardware checks the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode, it will generate a repeated START condition. STOP flag. If this bit is set in a master mode, a STOP condition is generated. A STOP condition detected on the I2C-bus clears this bit. This bit may also be set in slave mode, to recover from an error condition. In this case, no STOP condition is generated to the I2C-bus, but the hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware. Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur: * A START condition is generated in master mode * The own slave address has been received during AA = 1 * The general call address has been received while S1ADR.GC and AA = 1 * A data byte has been received or transmitted in master mode (even if arbitration is lost) * A data byte has been received or transmitted as selected slave * A STOP or START condition is received as selected slave receiver or transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software. I2C-bus slave address to which the device will respond enable I2C-bus general call address (logic 1) STO SI 2001 Dec 13 23 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS AA FUNCTION SAA56xx Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions: * Own slave address is received * General call address is received (S1ADR.GC = 1) * A data byte is received, while the device is programmed to be a master receiver * A data byte is received, while the device is selected slave receiver. When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received. I2C-bus Data Register (S1DAT) DAT7 to DAT0 I2C-bus Status Register (S1STA) STAT4 to STAT0 Software ADC Register (SAD) VHI CH1 to CH0 analog input voltage greater than DAC voltage (logic 1) ADC input channel select bits; CH<1:0>: 00 = ADC3 01 = ADC0 10 = ADC1 11 = ADC2 ST(1) SAD7 to SAD4 initiate voltage comparison between ADC input channel and SAD value 4 MSBs of DAC input word I2C-bus interface status I2C-bus data Software ADC Control Register (SADB) DC_COMP SAD3 to SAD0 Stack Pointer (SP) SP7 to SP0 stack pointer value enable DC comparator mode (logic 1) 4 LSBs of SAD value Timer/counter Control Register (TCON) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Timer 1 overflow flag. Set by hardware on Timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn Timer/counter on/off. Timer 0 overflow flag. Set by hardware on Timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn Timer/counter on/off. Interrupt 1 edge flag. Both edges generate flag. Set by hardware when external interrupt edge detected. Cleared by hardware when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify edge/low level triggered external interrupts. Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected. Cleared by hardware when interrupt processed. Interrupt 0 type flag. Set/cleared by software to specify falling edge/low level triggered external interrupts. 24 2001 Dec 13 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Timer/counter2 Control Register (T2CON) TF2 EXF2 RCLK0 TCLK0 EXEN2 FUNCTION SAA56xx Timer 2 overflow flag. Cleared by software. TF2 will not be set when either baud rate generation mode or clock out mode. Timer 2 External Flag. Set on a negative transition on T2EX and EXEN2 = 1. In Auto-reload mode it is toggled on an under or overflow. Cleared by software. Receive clock 0 flag. When set, causes the UART to use Timer 2 overflow pulses. RCLK0 = 0 causes Timer 1 overflow pulses to be used. Transmit clock 0 flag. When set, causes the UART to use Timer 2 overflow pulses. TCLK0 = 0 causes Timer 1 overflow pulses to be used. Timer 2 external enable flag. When set, allows a capture or reload to occur, together with an interrupt, as a result of a negative transition on input T2EX if in capture mode or Auto-reload mode with DCEN reset. If in Auto-reload mode and DCEN is set, this bit has no influence. In the other modes, EXF2 is set and an interrupt is generated on a HIGH-to-LOW transition on T2EX pin. In all modes, EXEN2 = 0 causes Timer 2 to ignore events at T2EX. START/STOP control bit. A logic 1 starts Timer 2. Counter Timer selection bit. A logic 1 selects the counter for Timer 2. Capture/Reload flag. Selection of mode capture or reload. TR2 C/T2 CP/RL2 14-bit PWM MSB Register (TDACH) TPWE TD13 to TD8 14-bit PWM LSB Register (TDACL) TD7 to TD0 Timer 0 High byte (TH0) TH07 to TH00 Timer 1 High byte (TH1) TH17 to TH10 Timer 2 High byte (TH2) TH27 to TH20 Timer 0 Low byte (TL0) TL07 to TL00 Timer 1 Low byte (TL1) TL17 to TL10 Timer 2 Low byte (TL2) TL27 to TL20 8 LSBs of Timer 2 16-bit counter 8 LSBs of Timer 1 16-bit counter 8 LSBs of Timer 0 16-bit counter 8 MSBs of Timer 2 16-bit counter 8 MSBs of Timer 1 16-bit counter 8 MSBs of Timer 0 16-bit counter 8 LSBs of 14-bit number to be output by the 14-bit PWM activate this 14-bit PWM (logic 1) 6 MSBs of 14-bit number to be output by the 14-bit PWM 2001 Dec 13 25 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Timer/counter Mode Control (TMOD) GATE C/T M1 to M0 gating control Timer/counter 1 Counter/Timer 1 selector mode control bits Timer/counter 1; M<1:0>: 00 = 8-bit Timer or 8-bit Counter with divide-by-32 prescaler 01 = 16-bit time interval or event Counter FUNCTION SAA56xx 10 = 8-bit time interval or event Counter with automatic reload upon overflow; reload value stored in TH1 11 = stopped GATE C/T M1 to M0 gating control Timer/counter 0 Counter/Timer 0 selector mode control bits Timer/counter 0; M<1:0>: 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event Counter 10 = 8-bit time interval or event Counter with automatic reload upon overflow; reload value stored in TH0 11 = one 8-bit time interval or event Counter and one 8-bit time interval Counter Timer 2 Mode Control (T2MOD) T2RD T2OE DCEN Text Register 0 (TXT0) X24 POSN DISPLAY X24 AUTO FRAME DISABLE HEADER ROLL DISPLAY STATUS ROW ONLY DISABLE FRAME VPS ON INV ON Text Register 1 (TXT1) EXT PKT OFF 8-BIT ACQ OFF X26 OFF FULL FIELD FIELD POLARITY H POLARITY disable acquisition of extension packets (logic 1) disable checking of packets 0 to 24 written into memory (logic 1) disable writing of data into Display memory (logic 1) disable automatic processing of X/26 data (logic 1) acquire data on any TV line (logic 1) VSYNC pulse in second half of line during even field (logic 1) HSYNC reference edge is negative going (logic 1) store packet 24 in extension packet memory (logic 0) or page memory (logic 1) display X24 from page memory (logic 0) or extension packet memory (logic 1) FRAME output switched off automatically if any video displayed (logic 1) disable writing of rolling headers and time into memory (logic 1) display row 24 only (logic 1) FRAME output always LOW (logic 1) enable capture of VPS data (logic 1) enable capture of inventory page in block 8 (logic 1) Timer 2 Read flag. This bit is set by hardware if following TL2 read and before TH2 read, TH2 is incremented. It is reset on the trailing edge of next TL2 read. Timer 2 output enable bit. When set, pin T2 is configured as a clock output. Down count enable flag. When set, this allows Timer 2 to be configured as an up/down Counter. 2001 Dec 13 26 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS V POLARITY Text Register 2 (TXT2) ACQ BANK REQ3 to REQ0 SC2 to SC0 Text Register 3 (TXT3) PRD4 to PRD0 Text Register 4 (TXT4) OSD BANK ENABLE QUAD WIDTH ENABLE EAST/WEST DISABLE DOUBLE HEIGHT B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE Text Register 5 (TXT5) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN Text Register 6 (TXT6) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN background colour displayed outside Teletext boxes (logic 1) background colour displayed inside Teletext boxes (logic 1) COR active outside Teletext and OSD boxes (logic 1) COR active inside Teletext and OSD boxes (logic 1) TEXT displayed outside Teletext boxes (logic 1) TEXT displayed inside Teletext boxes (logic 1) VIDEO displayed outside Teletext boxes (logic 1) VIDEO displayed inside Teletext boxes (logic 1) background colour displayed outside Teletext boxes (logic 1) background colour displayed inside Teletext boxes (logic 1) COR active outside Teletext and OSD boxes (logic 1) COR active inside Teletext and OSD boxes (logic 1) TEXT displayed outside Teletext boxes (logic 1) TEXT displayed inside Teletext boxes (logic 1) VIDEO displayed outside Teletext boxes (logic 1) VIDEO displayed inside Teletext boxes (logic 1) page request data select acquisition Bank 1 (logic 1) page request start column of page request FUNCTION VSYNC reference edge is negative going (logic 1) SAA56xx alternate OSD location available via graphic attribute, additional 32 locations (logic 1) enable display of quadruple width characters (logic 1) eastern language selection of character codes A0H to FFH (logic 1) disable normal decoding of double height characters (logic 1) enable meshing of black background (logic 1) enable meshing of coloured background (logic 1) display black background as video (logic 1) display shadow/fringe (default SE black) (logic 1) 2001 Dec 13 27 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Text Register 7 (TXT7) STATUS ROW TOP CURSOR ON REVEAL BOTTOM/TOP DOUBLE HEIGHT BOX ON 24 BOX ON 1 to 23 BOX ON 0 Text Register 8 (TXT8) FLICKER STOP ON DISABLE SPANISH PKT 26 WSS RECEIVED(2) RECEIVED(2) disable `Flicker Stopper' circuit (logic 1) FUNCTION SAA56xx Display memory row 24 information above Teletext page (on display row 0) (logic 1) display cursor at position given by TXT9 and TXT10 (logic 1) display characters in area with conceal attribute set (logic 1) Display memory rows 12 to 23 when DOUBLE HEIGHT height bit is set (logic 1) display each character as twice normal height (logic 1) enable display of Teletext boxes in memory row 24 (logic 1) enable display of Teletext boxes in memory row 1 to 23 (logic 1) enable display of Teletext boxes in memory row 0 (logic 1) disable special treatment of Spanish packet 26 characters (logic 1) packet 26 data has been processed (logic 1) WSS data has been processed (logic 1) enable acquisition of WSS data (logic 1) select CVBS1 as source for device (logic 1) WSS ON CVBS1/CVBS0 Text Register 9 (TXT9) CURSOR FREEZE CLEAR A0 R4 to R0(3) Text Register 10 (TXT10) C5 to C0(4) Text Register 11 (TXT11) D7 to D0 Text Register 12 (TXT12) 525/625 SYNC SPANISH ROM VER3 to ROM VER0 VIDEO SIGNAL QUALITY Text Register 13 (TXT13) VPS RECEIVED PAGE CLEARING 525 DISPLAY 525 TEXT 625 TEXT PKT 8/30 MEMORY(1) lock cursor at current position (logic 1) clear memory block pointed to by TXT15 (logic 1) access extension packet memory (logic 1) current memory ROW value current memory COLUMN value data value written or read from memory location defined by TXT9, TXT10 and TXT15 525-line CVBS signal is being received (logic 1) Spanish character set present (logic 1) mask programmable identification for character set acquisition can be synchronized to CVBS (logic 1) VPS data (logic 1) software or power-on page clear in progress (logic 1) 525-line synchronisation for display (logic 1) 525-line WST being received (logic 1) 625-line WST being received (logic 1) packet 8/30/x(625) or packet 4/30/x(525) data detected (logic 1) 2001 Dec 13 28 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS FASTEXT Text Register 14 (TXT14) DISPLAY BANK PAGE3 to PAGE0 Text Register 15 (TXT15) MICRO BANK BLOCK3 to BLOCK0 Text Register 17 (TXT17) FORCE ACQ1 to FORCE ACQ0 FORCE ACQ<1:0>: 00 = automatic selection 01 = force 525 timing, force 525 Teletext standard 10 = force 625 timing, force 625 Teletext standard 11 = force 625 timing, force 525 Teletext standard FORCE DISP1 to FORCE DISP0 FORCE DISP<1:0>: 00 = automatic selection 01 = force display to 525 mode (9 lines per row) 10 = force display to 625 mode (10 lines per row) 11 = not valid (default to 625) upper bank for micro selected (logic 1) current micro block to be accessed by TXT9, TXT10 and TXT11 upper bank for display selected (logic 1) current display page FUNCTION packet x/27 data detected (logic 1) SAA56xx SCREEN COL2 to SCREEN COL0 Defines colour to be displayed instead of TV picture and black background; these bits <2:0> are equivalent to the RGB components. SCREEN COL<2:0>: 000 = transparent 001 = CLUT entry 9 010 = CLUT entry 10 011 = CLUT entry 11 100 = CLUT entry 12 101 = CLUT entry 13 110 = CLUT entry 14 111 = CLUT entry 15 Text Register 18 (TXT18) NOT3 to NOT0 BS1 to BS0 Text Register 19 (TXT19) TEN TC2 to TC0 TS1 to TS0 enable twist character set (logic 1) language control bits (C12/C13/C14) that has twisted character set twist character set selection National Option Table selection, maximum of 31 when used with EAST/WEST bit basic character set selection 2001 Dec 13 29 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Text Register 20 (TXT20) DRCS ENABLE OSD PLANES FUNCTION SAA56xx re-map column 8/9 to DRCS (or column 8/9/A/C if extended DRCS is enabled) TXT and CC modes (logic 1) character code columns 8/9 (or column 8/9/A/C if extended DRCS is enabled) defined as double plane characters (special graphics characters) (logic 1) EXTENDED SPECIAL GRAPHICS extended Special Graphics enabled, user definable range for special graphics characters, in CC mode only (logic 1) CHAR SELECT ENABLE OSD LANG ENABLE OSD LAN2 to OSD LAN0 Text Register 21 (TXT21) DISP LINES1 to DISP LINES0 the number of display lines per character row; DISP LINES<1:0>: 00 = 10 lines per character (defaults to 9 lines in 525 mode) 01 = 13 lines per character 10 = 16 lines per character 11 = reserved CHAR SIZE1 to CHAR SIZE0 character matrix size bits; CHAR SIZE<1:0>: 00 = 10 lines per character (matrix 12 x 10) 01 = 13 lines per character (matrix 12 x 13) 10 = 16 lines per character (matrix 12 x 16) 11 = reserved I2C Port 1 enable I2C-bus Port 1 selection (P1.5/SDA1 and P1.4/SCL1) (logic 1) Closed Caption acquisition on (logic 1) enable I2C-bus Port 0 selection (P1.7/SDA0 and P1.6/SCL0) (logic 1) display configured for CC mode (logic 1) CCON I2C Port 0 CC/TXT Text Register 22 (TXT22) GPF7 to GPF6 reserved GPF5 to GPF4 and GPF2 to GPF0 general purpose register, bits defined by mask programmable bits (Character ROM address 09FEH) GPF3 PWM0, PWM1, PWM2 and PWM3 output on Port 3.0 to Port 3.3 respectively (logic 0) PWM0, PWM1, PWM2 and PWM3 output on Port 2.1 to Port 2.4 respectively (logic 1) enables character set selection in CC display mode (logic 1) enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14 alternative C12/C13/C14 bits for use with OSD menus Text Register 23 (TXT23) NOT B3 to NOT B0 EAST/WEST B DRCS B ENABLE BS B1 to BS B0 National Option Table selection for Page B, maximum of 32 when used with EAST/WEST B bit eastern language selection of character codes A0H to FFH for Page B (logic 1) normal OSD characters used on Page B (logic 0) re-map column 8/9 to DRCS (TXT and CC modes) on Page B (logic 1) basic character set selection for Page B 2001 Dec 13 30 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Text Register 24 (TXT24) BKGND OUT B BKGND IN B COR OUT B COR IN B TEXT OUT B TEXT IN B PICTURE ON OUT B PICTURE ON IN B Text Register 25 (TXT25) BKGND OUT B BKGND IN B COR OUT B COR IN B TEXT OUT B TEXT IN B PICTURE ON OUT B PICTURE ON IN B Text Register 26 (TXT26) EXTENDED DRCS FUNCTION SAA56xx background colour displayed outside Teletext boxes (Teletext page) (logic 1) background colour displayed inside Teletext boxes (Teletext page) (logic 1) COR active outside Teletext and OSD boxes (Teletext page) (logic 1) COR active inside Teletext and OSD boxes (Teletext page) (logic 1) TEXT displayed outside Teletext boxes (Teletext page) (logic 1) TEXT displayed inside Teletext boxes (Teletext page) (logic 1) VIDEO displayed outside Teletext boxes (Teletext page) (logic 1) VIDEO displayed inside Teletext boxes (Teletext page) (logic 1) background colour displayed outside Teletext boxes (Sub-Title/Newsflash page) (logic 1) background colour displayed inside Teletext boxes (Sub-Title/Newsflash page) (logic 1) COR active outside Teletext and OSD boxes (Sub-Title/Newsflash page) (logic 1) COR active inside Teletext and OSD boxes (Sub-Title/Newsflash page) (logic 1) TEXT displayed outside Teletext boxes (Sub-Title/Newsflash page) (logic 1) TEXT displayed inside Teletext boxes (Sub-Title/Newsflash page) (logic 1) VIDEO displayed outside Teletext boxes (Sub-Title/Newsflash page) (logic 1) VIDEO displayed inside Teletext boxes (Sub-Title/Newsflash page) (logic 1) columns 8/9/A/C mapped to DRCS when DRCS characters enabled (allowing 64 DRCS characters) (logic 1); default (logic 0) only columns 8/9 mapped to DRCS when DRCS characters enabled (allowing 32 DRCS characters display black background as video on Page B (logic 1) enable meshing of coloured background on Page B (logic 1) enable meshing of black background on Page B (logic 1) disable display of shadow/fringing on Page B (logic 0) display shadow/ fringe (default SE black) on Page B (logic 1) enable display of Teletext boxes in memory row 24 of Page B (logic 1) enable display of Teletext boxes in memory row 1 to 23 of Page B (logic 1) enable display of Teletext boxes in memory row 0 of Page B (logic 1) TRANS ENABLE B C MESH ENABLE B B MESH ENABLE B SHADOW ENABLE B BOX ON 24 B BOX ON 1 B to 23 B BOX ON 0 B 2001 Dec 13 31 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Text Register 27 (TXT27) SCRB2 to SCRB0 FUNCTION SAA56xx Defines colour to be displayed instead of TV picture and black background for Page B; these bits are equivalent to the RGB components. SCRB<2:0>: 000 = transparent 001 = CLUT entry 9 010 = CLUT entry 10 011 = CLUT entry 11 100 = CLUT entry 12 101 = CLUT entry 13 110 = CLUT entry 14 111 = CLUT entry 15 Text Register 28 (TXT28) MULTI-PAGE conventional internal memory storage of acquisition data (logic 0) enables multi-page acquisition operation for software controlled storage of acquired data in external SRAM (logic 1) display Page B configured for CC mode (logic 1) display Page B active during two page mode (logic 1) select upper bank for display Page B (logic 1) current display page for Page B CC/TXT B ACTIVE PAGE DISPLAY BANK B PAGE B3 to PAGE B0 Text Register 29 (TXT29) TEN B TS B1 to TS B0 OSD PLANES B disable twist function for Page B (logic 0) enable twist character set for Page B (logic 1) twist character set selection for Page B character code columns 8 and 9 defined as single plane characters for display Page B (logic 0) character code columns 8 and 9 defined as double plane characters (special graphics characters) for display Page B (logic 1) enable use of OSD LAN B<2:0> to define language option for display, instead of C12/C13/C14 for display Page B alternative C12/C13/C14 bits for use with OSD menus for display Page B OSD LANG ENABLE B OSD LAN B2 to OSD LAN B0 Text Register 30 (TXT30) TC B2 to TC B0 BOTTOM/TOP B language control bits (C12/C13/C14) that has twist character set for Page B Display memory rows 0 to 11 when double height bit is set on display Page B (logic 0) Display memory rows 12 to 23 when double height bit is set on display Page B (logic 1) display each character as twice normal height on display Page B (logic 1) Display memory row 24 information below Teletext page (on display row 24) on display Page B (logic 0). Display memory row 24 information above Teletext page (on display row 0) on display Page B (logic 1). DOUBLE HEIGHT B STATUS ROW TOP B 2001 Dec 13 32 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS DISPLAY X24 B FUNCTION SAA56xx display row 24 from basic page memory on display Page B (logic 0) display row 24 from appropriate location in extension memory on display Page B (logic 1) display only row 24 on display Page B (logic 1) DISPLAY STATUS ROW ONLY B Text Register 31 (TXT31) GPF11 to GPF10 GPF9 to GPF8 general purpose register, bits defined by mask programmable location (Character ROM address 09FEH) 00 = reserved 01 = 80C51 configured for 12 MHz operation 10 = reserved 11 = reserved Text Register 32 (TXT32) 9FE11 9FF11 to 9FF5 Text Register 33 (TXT33) BFE7 to BFE0 Text Register 34 (TXT34) BFE11 to BFE8 Text Register 35 (TXT35) PKT1-24<7:0> Teletext Packets 1-24 received for blocks 7 to 0, set by hardware and cleared by software. Teletext Packets 1-24 received after a header in any one Vertical Blanking Interval (VBI) (logic 1) mask programmable bits available for UOC configuration (Character ROM address 0BFEH) mask programmable bits available for UOC configuration (Character ROM address 0BFEH) reserved mask programmable bits available for UOC configuration (Character ROM address 09FFH) Text Register 36 (TXT36) PKT1-24<9:8> Watchdog Timer (WDT) WDV7 to WDV0 Watchdog Timer Key (WDTKEY) WKEY7 to WKEY0(5) Wide Screen Signalling 1 (WSS1) WSS<3:0> ERROR WSS3 to WSS0 error in WSS<3:0> (logic 1) signalling bits to define aspect ratio (group 1) Watchdog Timer key Watchdog Timer period Teletext Packets 1-24 received for blocks 9 to 8, set by hardware and cleared by software. Teletext Packets 1-24 received after a header in any one VBI (logic 1) 2001 Dec 13 33 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) BITS Wide Screen Signalling 2 (WSS2) WSS<7:4> ERROR WSS7 to WSS4 Wide Screen Signalling 3 (WSS3) WSS<13:11> ERROR WSS13 to WSS11 WSS<10:8> ERROR WSS10 to WSS8 External RAM Pointer (XRAMP) XRAMP7 to XRAMP0 Notes 1. This flag is set by software and reset by hardware. 2. This flag is set by hardware and must be reset by software. 3. Valid range TXT Mode 0 to 24. 4. Valid range TXT Mode 0 to 39. 5. Must be set to 55H to disable Watchdog Timer when active. error in WSS<13:11> (logic 1) signalling bits to define reserved elements (group 4) error in WSS<10:8> (logic 1) signalling bits to define subtitles (group 3) error in WSS<7:4> (logic 1) signalling bits to define enhanced services (group 2) FUNCTION SAA56xx Upper address byte for MOVX RAM space in direct addressing. To use with one of the R0 to R7 registers to provide the lower address byte. 2001 Dec 13 34 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 8.6 Character set feature bits SAA56xx Features available on the SAA56xx devices are reflected in a specific area of the Character ROM. These sections of the Character ROM are mapped to two Special Function Registers: TXT22 and TXT12. Character ROM address 09FEH is mapped to SFR TXT22, as shown in Table 6 and described in Table 7. Character ROM address 09FFH is mapped to SFR TXT12, as shown in Table 8 and described in Table 9. Table 6 Character ROM - TXT22 mapping 11 X - 10 X - 9 X - 8 X - 7 X 7 6 X 6 5 X 5 4 X 4 3 U 3 2 X 2 1 X 1 0 X 0 MAPPED ITEMS Character ROM; address 09FEH Mapped to TXT22 U = Used, X = Reserved Table 7 Description of Character ROM address 09FEH bits BIT 0 to 2 3 4 to 11 Table 8 reserved 1 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 2.1 to Port 2.4 respectively 0 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 3.0 to Port 3.3 respectively reserved FUNCTION Character ROM - TXT12 mapping 11 X - 10 X - 9 X - 8 X - 7 X - 6 X - 5 X - 4 U 6 3 X 5 2 X 4 1 X 3 0 X 2 MAPPED ITEMS Character ROM; address 09FFH Mapped to TXT12 U = Used, X = Reserved Table 9 Description of Character ROM address 09FFH bits BIT 4 0 to 3, 5 to 11 1 = Spanish character set present 0 = no Spanish character set present reserved FUNCTION 2001 Dec 13 35 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 8.7 MOVX memory 8.7.1 MOVX SPACE PAGE SELECTION SAA56xx The normal 80C51 external memory area has been mapped internally to the device (see Fig.8). This means that the MOVX instruction accesses memory internal to the device. The MOVX RAM page pointer is used to select one of the 256 pages within the MOVX address space, not all pages are allocated, refer to Fig.9 for further detail. A page consists of 256 consecutive bytes. XRAMP only works with internal MOVX memory. handbook, full pagewidth 7FFFH FFFFH 7000H 6FFFH 9000H 8FFFH DYNAMICALLY REDEFINABLE CHARACTERS 8800H 87FFH DISPLAY REGISTERS 87E0H DISPLAY RAM FOR TEXT PAGES (1) 871FH CLUT 2000H 1FFFH DATA RAM (2) 0800H 07FFH 0000H (3) 845FH DISPLAY RAM FOR CLOSED CAPTION (4) 8000H 8700H address range 8460H to 84FFH "Additional Internal Data RAM" GSA021 lower 32 kbytes upper 32 kbytes (1) Both SAA56xx 128 and 192 kbytes have 12 kbytes of Display memory. (2) 0800H to 1FFFH are mapped into 6 kbytes of Bank 0 of external RAM. An external RAM is required to be able to address this memory space (refer to Section 20 and Section 30.1). (3) Both SAA56xx 128 and 192 kbytes have 2 kbytes of Data RAM. (4) Display RAM for Closed Caption and Text is shared. Fig.8 MOVX RAM allocation. 2001 Dec 13 36 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth FFH 00H XRAMP SFR = FFH FFFFH FF00H Not Allocated FFH 00H XRAMP SFR = FFH 4FFFH 4000H Allocated(1) FFH 00H XRAMP SFR = FFH 20FFH 2000H FFH 00H MOVX @ Ri,A MOVX A, @ Ri FFH 00H FFH 00H XRAMP SFR = 00H GSA070 08FFH XRAMP SFR = FEH 0800H Not Allocated 01FFH XRAMP SFR = 01H 0100H 00FFH 0000H MOVX @ DPTR,A MOVX A, @ DPTR Allocated(1) (1) Internal 14-kbyte data and display RAM of the device. Fig.9 Indirect addressing of MOVX RAM. 9 POWER-ON RESET Two reset inputs are present on the device, the RESET pin being active HIGH and RESET pin being active LOW. Only one of these inputs need be connected in the system as they are ORed internally to the device and each pin has the necessary pull-down (for RESET) and pull-up (for RESET) resistors at the pad. An automatic reset can be obtained when VDD is switched on by connecting the RESET pin to VDDP through a 10 F capacitor, providing the VDD rise time does not exceed 1 ms, and the oscillator start-up time does not exceed 10 ms. Alternatively, a capacitor connected to VSSP with a suitable pull-up to VDDP, (e.g. 10 F capacitor; 16 k resistor) can be connected to the RESET pin. To ensure correct initialisation, the RESET/RESET pin must be held HIGH/LOW long enough for the oscillator to settle following power-up, usually a few milliseconds (application specific, typically 10 ms). Once the oscillator is stable, a further 24 crystal clocks are required to generate the reset. Once the above reset condition has been detected, an internal reset signal is triggered (which remains active for 2048 clock cycles). 2001 Dec 13 37 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 10 POWER SAVING MODES OF OPERATION Three power saving modes are incorporated in the SAA56xx device: Standby, Idle and Power-down. When utilizing one of these modes, power to the device (VDDP, VDDC and VDDA) should be maintained, since power saving is achieved by clock gating on a section-by-section basis. 10.1 Standby mode SAA56xx Once in Idle mode, the crystal oscillator continues to run, but the internal clock to the CPU, Acquisition and Display are gated out. However, the clocks to the Memory Interface, I2C-bus, Timer/counters, Watchdog Timer and Pulse Width Modulators are maintained. The CPU state is frozen along with the status of all SFRs. Internal RAM contents are maintained, as are the device output pin values. Since the output values on RGB and VDS are maintained, the Display output must be disabled before entering this mode. There are three methods available to recover from Idle: * Assertion of an enabled interrupt will cause bit IDL to be cleared by hardware, thus terminating Idle mode. The interrupt is serviced and, following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Idle mode. * A second method of exiting Idle is via an interrupt generated by the SAD DC Compare circuit. When the SAA56xx is configured in this mode, detection of an analog threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into Idle. * The third method of terminating Idle mode is with an external hardware reset. Since the oscillator is running, the hardware reset need only be active for 24 crystal clocks at 12 MHz to complete the reset operation. Reset defines all SFRs and Display memory to a pre-defined state, but maintains all other RAM values. Code execution commences with the Program Counter set to `0000'. 10.3 Power-down mode During Standby mode, the Acquisition and Display sections of the device are disabled. The following functions remain active: * 80C51 CPU Core * Memory interface * I2C-bus interface * Timer/counters * Watchdog Timer * UART, SAD, PWMs. To enter Standby mode, the STANDBY bit in the ROMBK register must be set. Once in Standby, the crystal oscillator continues to run, but the internal clocks to Acquisition and Display are gated out. However, the clocks to the 80C51 CPU Core, Memory Interface, I2C-bus, UART, Timer/counters, Watchdog Timer and Pulse Width Modulators are maintained. Since the output values on RGB and VDS are maintained, the display output must be disabled before entering this mode. The Standby mode may be used in conjunction with both Idle and Power-down modes. Hence, prior to entering either Idle or Power-down, the STANDBY bit may be set, thus allowing wake-up of the 80C51 CPU core without fully waking the entire device. (This enables detection of a Remote Control source in a power saving mode.) 10.2 Idle mode During Idle mode, Acquisition, Display and the CPU sections of the device are disabled. The following functions remain active: * Memory interface * I2C-bus interface * Timer/counters * Watchdog Timer * UART, SAD, PWMs. To enter Idle mode, bit IDL in the PCON register must be set. The Watchdog Timer must be disabled prior to entering Idle to prevent the device being reset. In Power-down mode, the crystal oscillator is stopped. The contents of all SFRs and Data memory are maintained, however, the contents of the Auxiliary/Display memory are lost. The port pins maintain the values defined by their associated SFRs. Since the output values on RGB and VDS are maintained, the Display output must be made inactive before entering Power-down mode. The Power-down mode is activated by setting bit PD in the PCON register. It is advisable to disable the Watchdog Timer prior to entering Power-down. Recovery from Power-down takes several milliseconds as the oscillator must be given time to stabilize. 2001 Dec 13 38 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) There are three methods of exiting Power-down: * External interrupt. Since the clock is stopped, an external interrupt needs to be set level sensitive prior to entering Power-down. The interrupt is serviced and, following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Power-down mode. * Interrupt generated by the SAD DC Compare circuit. When SAA56xx is configured in this mode, detection of a certain analog threshold at the input to the SAD may be used to trigger wake-up of the device, i.e. TV Front Panel Key-press. As above, the interrupt is serviced and, following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into Power-down. * External hardware reset. This reset defines all SFRs and Display memory, but maintains all other RAM values. Code execution commences with the Program Counter set to `0000'. 11 I/O FACILITY The SAA56xx devices have 32 I/O lines, each of which can be individually addressed, or form four parallel 8-bit addressable ports: Port 0, Port 1, Port 2 and Port 3. I2C-bus ports (P1.4, P1.5, P1.6 and P1.7) can only be configured as open-drain. 11.1 Port type SAA56xx When a LOW-to-HIGH signal transition is output from the device, the pad is put into push-pull mode for one clock cycle (166 ns) after which the pad goes into open-drain mode. This mode is used to speed up the edges of signal transitions. This is the default mode of operation of the pads after reset. 11.1.3 HIGH-IMPEDANCE (TTL, 5 V TOLERANT) The high-impedance mode can be used for input only operation of the port. When using this configuration, the two output transistors are turned off. 11.1.4 PUSH-PULL (CMOS, 3V3 TOLERANT) The push-pull mode can be used for output only. In this mode, the signal is driven to either 0 V or VDDP, which is nominally 3.3 V. 12 INTERRUPT SYSTEM The device has 15 interrupt sources, each of which can be enabled or disabled. When enabled, each interrupt can be assigned one of two priority levels. There are five interrupts that are common to the 80C51. Two of these are external interrupts (EX0 and EX1); the other three are timer interrupts (ET0, ET1 and ET2). In addition to the conventional 80C51, two application specific interrupts are incorporated internal to the device, with the following functionality: * Closed Caption Data Ready interrupt (ECC). This interrupt is generated when the device is configured in Closed Caption Acquisition mode. The interrupt is activated at the end of the currently selected Slice Line, as defined in the CCLIN SFR. * Display Busy interrupt (EBUSY). An interrupt is generated when the display enters either a Horizontal or Vertical Blanking Period. i.e. indicates when the microcontroller can update the Display RAM without causing undesired effects on the screen. This interrupt can be configured in one of two modes using the Memory Mapped Register (MMR) Configuration Register (address 87FFH, bit TXT/V). - Text Display Busy: An interrupt is generated on each active horizontal display line when the Horizontal Blanking Period is entered. - Vertical Display Busy: An interrupt is generated on each vertical display field when the Vertical Blanking Period is entered. All individual ports can be programmed to function in one of four modes, the mode is defined by two associated Port Configuration Registers: PnCFGA and PnCFGB (where n = port number 0, 1, 2 or 3). The modes available are open-drain, quasi-bidirectional, high-impedance and push-pull. 11.1.1 OPEN-DRAIN (TTL, 5 V TOLERANT) The open-drain mode can be used for bidirectional operation of a port and requires an external pull-up resistor. The pull-up voltage has a maximum value of 5.5 V, to allow connection of the device into a 5 V environment. 11.1.2 QUASI-BIDIRECTIONAL (CMOS, 3V3 TOLERANT) The quasi-bidirectional mode is a combination of open-drain and push-pull. It requires an external pull-up resistor to VDDP (normally 3.3 V). 2001 Dec 13 39 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) There are four interrupts connected to the 80C51 microcontroller peripherals, as follows: * I2C-bus Transmit/Receive * UART Receive * UART Transmit * UART Receive/Transmit. Four additional general purpose external interrupts are incorporated in the SAA56xx with programmable edge detection (INT2 {EX2}, INT3 {EX3}, INT4 {EX4} and INT5 {EX5}). The EXTINT SFR is used to configure each of these interrupts as either level activated, rising edge, falling edge or both edges sensitive, see Table 10. 12.1 Interrupt enable structure 12.3 Interrupt vector address SAA56xx The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. The interrupt vector addresses for each source are shown in Table 12. 12.4 Level/edge interrupt The external interrupt can be programmed to be either level activated or transition activated by setting or clearing the IT0/IT1 bits in the Timer Control SFR (TCON), see Table 11. The external interrupt INT1 differs from the standard 80C51 interrupt in that it is activated on both edges when in edge sensitive mode. This is to allow software pulse width measurement for handling remote control inputs. The four other external interrupts INT2, INT3, INT4 and INT5 are configured using the EXTINT register, as shown in Table 10. Table 10 Configuration of external interrupts (INT2 to INT5) SFR EXTINT; EXnCFG<1:0>; n = 2 to 5 00 01 10 11 MODE level sensitive - active LOW rising edge sensitive falling edge sensitive both edges sensitive Each of the individual interrupts can be enabled or disabled by setting or clearing the relevant bit in the interrupt enable SFRs (IE and IEN1). All interrupt sources can also be globally disabled by clearing bit EA (IE.7), as shown in Fig.10. 12.2 Interrupt enable priority Each interrupt source can be assigned one of two priority levels. The interrupt priorities are defined by the interrupt priority SFRs (IP and IP1). A low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt. A high priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request with the higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence as defined in Table 12. Table 11 External interrupt activation BIT IT0 IT1 LEVEL active LOW - INT0 = negative edge INT1 = positive and negative edge EDGE 2001 Dec 13 40 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) Table 12 Interrupt priority (within same level) SOURCE EX0 ES2 EURX ET0 EBUSY EX2 EX1 ET2 EX3 ET1 EUART EX4 ECC EUTX EX5 lowest PRIORITY WITHIN LEVEL highest INTERRUPT VECTOR 0003H 002BH 0053H 000BH 0033H 005BH 0013H 003BH 0063H 001BH 0043H 006BH 0023H 004BH 0073H RELATED SFR IEN0 IEN0 IEN1 IEN0 IEN0 IEN1 IEN0 IEN1 IEN1 IEN0 IEN1 IEN1 IEN0 IEN1 IEN1 SAA56xx INT NUMBER 0 5 10 1 6 11 2 7 12 3 8 13 4 9 14 2001 Dec 13 41 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth EX0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8 H9 L9 H10 L10 H11 L11 H12 L12 H13 L13 H14 L14 highest priority level 1 highest priority level 0 ES2 EURX ET0 EBUSY EX2 EX1 ET2 EX3 ET1 EUART EX4 ECC EUTX EX5 interrupt source source enable SFR IE<0:6> SFR IEN1<0:7> global enable SFR IE.7 priority control SFR IP<0:6> SFR IP1<0:7> H15 lowest priority level 1 L15 lowest priority level 0 GSA074 Fig.10 Interrupt structure. 2001 Dec 13 42 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 13 TIMERS/COUNTERS Three 16-bit Timers/counters are incorporated: Timer 0, Timer 1 and Timer 2. Each can be configured to operate as either timers or event counters. Timer 2 is new for the SAA56xx, whereas Timer 0 and Timer 1 are standard 80C51 Timer/counters, refer to "Handbook IC20 80C51-Based 8-bit Microcontrollers". Remark: It should be noted that because the SAA56xx uses both clock edges, the division factor is 6 instead of 12. When the Timers/counters are configured as timers, the period depends on the microcontroller clock frequency of 12 MHz. In Timer mode, the register is incremented on every machine cycle, so that machine cycles are counted. Since the machine cycle consists of six oscillator periods, the count rate is 16fclk (where fclk is the microcontroller clock frequency: 12 MHz). In Counter mode, the register is incremented in response to a negative transition at its corresponding external pin T0/T1/T2. Since pins T0/T1/T2 are sampled once per machine cycle, it takes two machine cycles to recognise a transition. This gives a maximum count rate of 112fclk (where fclk is the microcontroller clock frequency, 12 MHz). 13.1 Timer/counter 0 and Timer/counter 1 Table 15 Timer 2 operating mode RCLK0 OR TCLK0 OR CP/RL2 T2OE C/T2 RCLK1 OR TCLK1 0 0 1 X 13.2.1 0 1 X 0 CAPTURE MODE 0 0 X 1 X X X 0 13.2 Timer/counter 2 SAA56xx Timer 2 is controlled using the following SFRs: Table 14 Timer 2 Special Function Registers SFR T2CON T2MOD RCAP2L RCAP2H TL2 TH2 ADDRESS F1H F2H F3H F4H F5H F6H Timer 2 can operate in four different modes (see Table 15): * Auto-reload * Capture * Baud rate generation * Clock output. The count-down option is only possible in the Auto-reload mode with DCEN in T2MOD set and the external trigger input disabled. There are six Special Function Registers used to control Timer/counter 0 and Timer/counter 1. Table 13 Timer/counter 0 and Timer/counter 1 registers SFR TCON TMOD TL0 TH0 TL1 TH1 ADDRESS 88H 89H 8AH 8BH 8CH 8DH OPERATING MODE 16-bit Auto-reload 16-bit Capture Baud rate generation Clock output The Timer/counter function is selected by control bits C/T in the Timer Mode SFR(TMOD). These two Timers/counters have four operating modes, which are selected by bit-pairs (M1 and M0) in TMOD. Details of the modes of operation is given in "Handbook IC20, 80C51-Based 8-Bit Microcontrollers". TL0 and TH0 are the actual Timer/counter registers for Timer 0. TL0 is the low byte and TH0 is the high byte. TL1 and TH1 are the actual Timer/counter registers for Timer 1. TL1 is the low byte and TH1 is the high byte. 2001 Dec 13 43 In the Capture mode, registers RCAP2L/RCAP2H are used to capture the TL2/TH2 data. By setting/clearing bit EXEN2 in T2CON, the external trigger input T2EX (P3.4) can be enabled/disabled. If EXEN2 = 0, Timer 2 is a 16-bit Timer/counter which, upon overflow, sets TF2 flag in T2CON. If EXEN2 = 1, then Timer 2 does the above, but with the added feature that a HIGH-to-LOW transition at T2EX on Port 3.4 causes the current Timer 2 value (TL2/TH2 data) to be captured into RCAP2L/RAP2H, and bit EXF2 in T2CON to be set. Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 13.2.2 AUTO-RELOAD MODE 13.2.6 BAUD RATE GENERATION MODE SAA56xx In the Auto-reload mode, Timer 2 can be programmed to count up/down by clearing/setting bit DCEN in T2MOD. 13.2.3 COUNTING UP (DCEN = 0) In the Auto-reload mode and when counting up, registers RCAP2L/RCAP2H are used to hold a reload value for TL2/TH2 when Timer 2 rolls over. By setting/clearing bit EXEN2 in T2CON, external trigger T2EX on Port 3.4 can be enabled/disabled. If EXEN2 = 0, Timer 2 is a 16-bit timer/counter which, upon overflow, sets TF2 and reloads TL2/TH2 with the reload value in RCAP2L/RCAP2H. If EXEN2 = 1, Timer 2 does the above, but with the added feature that a HIGH-to-LOW transition at the external trigger T2EX on Port 3.4 causes the current RCAP2L/RCAP2H value to be loaded into TL2/TH2 respectively, and bit EXF2 in T2CON to be set. Timer 2 interrupt is set if EXF2 or TF2 is set. 13.2.4 COUNTING UP (DCEN = 1 AND T2EX = 1) In this mode, timer overflow will load TL2 and TH2 with the contents of RCAPL and RCAPH respectively and it will not set TF2. Bit EXF2 will be set if EXEN2 is set and a HIGH-to-LOW transition is detected on pin T2EX (Port 3.4). When Timer 2 is configured for timer operation, the timer increments every state. Normally, as a timer, it would increment every machine cycle. Timer 2 interrupt is set only if EXF2 is set. 13.2.7 CLOCK OUTPUT MODE In this mode Timer 2 counts up. When Timer 2 overflows (FFFFH state), bit TF2 is set. This reloads TL2 and TH2 with the contents of RCAP2L and RCAP2H, respectively. On overflow, bit EXF2 is inverted and hence toggles during operation, so that bit EXF2 can be used as 17th bit, if desired. Timer 2 interrupt will be set only if TF2 is set. 13.2.5 COUNTING DOWN (DCEN = 1 AND T2EX = 0) In the clock output mode, external pin T2 is used as a clock output. A timer overflow causes TL2 and TH2 to be loaded with T2CAPL and T2CAPH, respectively. An overflow toggles bit EXF2, which is connected to pin T2. The frequency of T2 will be half the overflow frequency. Timer overflow will not set TF2. A HIGH-to-LOW transition on the external trigger T2EX on Port 3.4 sets EXF2. It is possible to configure Timer 2 in clock-out mode and baud generator mode simultaneously. Timer 2 interrupt is set only if EXF2 is set. 14 WATCHDOG TIMER The Watchdog Timer is a counter that, once in an overflow state, forces the microcontroller into a reset condition. The purpose of the Watchdog Timer is to reset the microcontroller if it enters an erroneous processor state (possibly caused by electrical noise or RFI) within a reasonable period of time. When enabled, the Watchdog circuit generates a system reset if the user program fails to reload the Watchdog Timer within a specified length of time, known as the Watchdog Interval. The Watchdog Timer consists of an 8-bit counter with a 16-bit prescaler. The prescaler is fed with a signal whose frequency is 16fclk (2 MHz for 12 MHz 80C51 core). The 8-bit counter is incremented every `t' seconds where: 1 6 x 65536 t = 6 ------- x 2 16 = ------------------------- = 32.768 ms f clk 12 MHz In this mode Timer 2 counts down. Underflow will occur when the contents of TL2/TH2 match the contents of RCAP2L/RCAP2H. A Timer 2 roll-over from 0000H to FFFFH is not considered as an underflow. Upon underflow, bit TF2 will be set and registers TL2/TH2 will be loaded with FFFFH. In addition, an underflow will cause bit EXF2 to be inverted, such that it can be used as the 17th bit, if desired. Timer 2 interrupt is set only if TF2 is set. 2001 Dec 13 44 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 14.1 Watchdog Timer operation 16.2 SAA56xx Tuning Pulse Width Modulator (TPWM) The Watchdog Timer operation is activated when bit WLE in the Power Control SFR (PCON) is set. The Watchdog can be disabled by software by loading the value 55H into the Watchdog Timer Key SFR (WDTKEY). This must be performed before entering Idle/Power-down mode to prevent exiting the mode prematurely. Once activated, the Watchdog Timer SFR (WDT) must be reloaded before the timer overflows. Bit WLE must be set to enable loading of the WDT SFR. Once loaded, bit WLE is reset by hardware, to prevent erroneous software from loading the WDT SFR. The value loaded into the WDT defines the Watchdog Interval (WI): WI = ( 256 - WDT ) x t For a 12 MHz microcontroller clock, t = 32.768 ms. The range of intervals is from WDT = 00H, this gives 8.38 ms to WDT = FFH, which gives 32.768 ms. 15 PORT ALTERNATIVE FUNCTIONS Ports 1, 2 and 3 are shared with alternative functions to enable control of external devices and circuits. These functions are enabled by setting the appropriate SFR and also writing a logic 1 to the port bit that the function occupies. 16 PULSE WIDTH MODULATORS The device has eight 6-bit PWM outputs for analog control of e.g. volume, balance, bass, treble, brightness, contrast, hue and saturation. The PWM outputs generate pulse patterns with a repetition rate of 21.33 s, with the high time equal to the PWM SFR value multiplied by 0.33 s. The analog value is determined by the ratio of the high time to the repetition time. A DC voltage proportional to the PWM setting is obtained by means of an external integration network (low-pass filter). 16.1 PWM control The device has a single 14-bit TPWM that can be used for Voltage Synthesis Tuning. The method of operation is similar to the normal PWM, except that the repetition period is 42.66 s. 16.2.1 TPWM CONTROL Two SFRs are used to control the TPWM: TDACL and TDACH. The TPWM is enabled by setting bit TPWE in the TDACH SFR. The most significant bits TD<13:7> alter the high period between 0 and 42.33 s. The seven least significant bits TD<6:0> extend certain pulses by a further 0.33 s. For example, if TD<6:0> = 01H, 1 in 128 periods will be extended by 0.33 s. If TD<6:0> = 02H, 2 in 128 periods will be extended. The TPWM will not start to output a new value until TDACH has been written to. Therefore, if the value is to be changed, TDACL should be written before TDACH. 16.3 Software ADC (SAD) Four successive approximation ADCs can be implemented in software by using the on-board 8-bit Digital-to-Analog Converter and Analog Comparator. 16.3.1 SAD CONTROL The control of the required analog input is done using channel select bits CH<1:0> in the SAD SFR. This selects the required analog input to be passed to one of the inputs of the comparator. The second comparator input is generated by the DAC, whose value is set by bits SAD<7:0> in the SAD and SADB SFRs. A comparison between the two inputs is made when the start compare bit ST in the SAD SFR is set. This must be at least one instruction cycle after the SAD<7:0> value has been set. The result of the comparison is given on VHI one instruction cycle after bit ST is set. 16.3.2 SAD INPUT VOLTAGE The relevant PWM is enabled by setting the PWM enable bit PWxE in the PWMx Control Register. The high time is defined by the value PWxV<5:0>. The external analog voltage that is used for comparison with the internally generated DAC voltage does not have the same voltage range due to the 5 V tolerance of the pin. It is limited to VDDP - Vtn where Vtn is a maximum of 0.75 V. For further details, refer to the "SAA55XX and SAA56XX Software Analogue to Digital Converter Application Note SPG/AN99022". 2001 Dec 13 45 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 16.3.3 SAD DC COMPARATOR MODE SAA56xx The SAD module (see Fig.11) incorporates a DC Comparator mode, which is selected using the `DC_COMP' control bit in the SADB SFR. This mode enables the microcontroller to detect a threshold crossing at the input to the selected analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) of the software ADC. A level sensitive interrupt is generated when the analog input voltage level at the pin falls below the analog output level of the SAD DAC. This mode is intended to provide the device with a wake-up mechanism from Power-down or Idle mode when a key-press on the front panel of the TV is detected. The following software sequence should be used when utilizing this mode for Power-down or Idle mode: 1. Disable INT1 using the IEN0 SFR. 2. Set INT1 to level sensitive using the TCON SFR. 3. Set the DAC digital input level to the desired threshold level using SAD/SADB SFRs and select the required input pin (P3.0, P3.1, P3.2 or P3,3) using CH1 and CH0 in the SAD SFR. 4. Enter DC Compare mode by setting the `DC_COMP' enable bit in the SADB SFR. 5. Enable INT1 using the IEN0 SFR. 6. Enter Power-down/Idle mode. Upon wake-up, the SAD should be restored to its conventional operating mode by disabling the `DC_COMP' control bit. handbook, halfpage VDDP ADC0 ADC1 ADC2 ADC3 CH<1:0> VHI MUX 4:1 SAD<3:0> 8-BIT DAC SADB<3:0> MBK960 Fig.11 SAD block diagram. 2001 Dec 13 46 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 17 I2C-BUS SERIAL I/O The I2C-bus consists of a serial data line (SDA) and a serial clock line (SCL). The definition of the I2C-bus protocol can be found in "The I2C-bus and how to use it (including specification). Philips Semiconductors". The device operates in four modes: * Master transmitter * Master receiver * Slave transmitter * Slave receiver. The microcontroller peripheral is controlled by the Serial Control SFR (S1CON) and its status is indicated by the Status SFR (S1STA). Information is transmitted/received to/from the I2C-bus using the Data SFR (S1DAT). The Slave Address SFR (S1ADR) is used to configure the slave address of the peripheral. The byte level I2C-bus serial port is identical to the I2C-bus serial port on the P8xC558, except for the clock rate selection bits CR<2:0>. The operation of the subsystem is described in detail in the "P8xC558 data sheet". 17.1 I2C-bus modes 17.1.2 SAA56xx FAST MODE (IIC_LUT<1:0> = 01) This option accommodates the P8xC558 I2C-bus doubled rates, as shown in Table 17. Table 17 I2C-bus serial rates in `P8xC558 fast mode' CR2 CR1 CR0 0 0 0 0 1 1 1 1 17.1.3 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 12 MHz DIVISOR 30 800 20 15 120 1600 80 60 I2C-BUS BIT FREQUENCY (kHz) 400 15 600 800 100 7.5 150 200 SLOW MODE' (IIC_LUT<1:0> = 10) This option accommodates the P8xC558 I2C-bus rates, divided by 2, as shown in Table 18. Table 18 I2C-bus serial rates `P8xC558 slow mode' CR2 CR1 CR0 0 0 0 0 1 1 1 1 17.2 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 12 MHz DIVISOR 120 3200 80 60 480 6400 320 240 I2C-BUS BIT FREQUENCY (kHz) 100 3.75 150 200 25 1.875 37.5 50 Three different I2C-bus selection tables for CR<2:0> can be configured using the ROMBK SFR (IIC_LUT<1:0>), as shown in Table 16. 17.1.1 NOMINAL MODE (IIC_LUT<1:0> = 00) This option accommodates the P8xC558 I2C-bus, refer to "Handbook IC20, 80C51-Based 8-Bit Microcontrollers". The various serial rates are shown in Table 16: Table 16 I2C-bus serial rates in `P8xC558 nominal mode' CR2 CR1 CR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 12 MHz DIVISOR 60 1600 40 30 240 3200 160 120 I2C-BUS BIT FREQUENCY (kHz) 200 7.5 300 400 50 3.75 75 100 I2C-bus port selection Two I2C-bus ports are available: SCL0/SDA0 and SCL1/SDA1. The ports are selected by using TXT21.I2C Port 0 and TXT21.I2C Port 1. When a port is enabled, any information transmitted from the device goes onto the enabled port. Information transmitted to the device can only be acted on if the port is enabled. If both ports are enabled, then data transmitted from the device is seen on both ports. However, data transmitted to the device on one port cannot be seen on the other port. 2001 Dec 13 47 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 18 UART PERIPHERAL The 80C51 microcontroller incorporates a full duplex UART with a single byte receive buffer, meaning that it can commence reception of a second byte before the first is read from the receive buffer. This register is implemented twice. Writing to S0BUF writes to the transmit buffer. Reading from S0BUF reads from the receive buffer. Only hardware can read from the transmit buffer and write to the receive buffer. For further details please refer to the "SAA56xx UART Operation Application Note SPG/AN01010". The UARTs TX and RX pins connect to P0.1 and P0.0, respectively. Two registers (S0CON, S0BUF) and one bit (SMOD in PCON register) control the UART. Table 19 UART Special Function Registers SFR S0CON S0BUF 18.1 UART modes ADDRESS 99H 9AH SAA56xx In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. In the other modes, reception is initiated by the incoming start bit if REN = 1. 18.2 UART multiprocessor communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, nine data bits are received. The 9th bit goes into RB8, followed by a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in S0CON. A way to use this feature in multiprocessor systems is as follows. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte. The 9th bit is logic 1 in an address byte and logic 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte reception. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will follow. The slaves that were not being addressed leave their SM2 bits set and carry on the task they were performing. Bit SM2 has no effect in Mode 0; in Mode 1, it can be used to check the validity of the stop bit. When receiving in Mode 1 (if SM2 = 1), the receive interrupt will not be activated unless a valid stop bit is received. 18.3 S0BUF registers The serial port can operate in four modes: * Mode 0: Serial data enters and exits through RX. TX outputs the shift clock. Eight bits are transmitted and received (LSB first). The baud rate is fixed at 16fclk. * Mode 1: Ten bits are transmitted (through TX) or received (through RX): a start bit (logic 0), eight data bits (LSB first) and a stop bit (logic 1). On receive, the stop bit goes into RB8 in SFR S0CON. The baud rate can be varied at either Timer 1 or Timer 2 overflow rate. * Mode 2: Eleven bits are transmitted (through TX) or received (through RX): start bit (logic 0), eight data bits (LSB first), a 9th data bit and a stop bit (logic 1). On transmit, the 9th data bit, TB8 in S0CON, can be assigned the value of logic 0 or logic 1. For example, the parity bit could be moved into TB8. On receive, the 9th data bit goes into RB8 in S0CON, while the stop bit is ignored. The baud rate can be programmed to either 1 f 1 32 clk or 16fclk. * Mode 3: Eleven bits are transmitted (through TX) or received (through RX): a start bit (logic 0), eight data bits (LSB first), a 9th data bit and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate can be varied at either Timer 1 or Timer 2 overflow rate. This register is implemented twice. Writing to S0BUF writes to the transmit buffer. Reading from S0BUF reads from the receive buffer. Only hardware can read from the transmit buffer and write to the receive buffer. 2001 Dec 13 48 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 18.4 UART baud rates SAA56xx 20 EXTERNAL SRAM/ROM INTERFACE The external address/data bus of the 80C51 microprocessor may be interfaced to: * Additional SRAM Data memory for multi-page acquisition applications * External Program ROM. The application circuit can be achieved using either the multiplexed address and data I/O or the de-multiplexed address and data I/O. External SRAM Data Memory: it is possible to interface up to 256 kbytes of external data memory using pins RAMBK<1:0> and A15_BK. Each of the four Data memory banks is selected by RAMBK<1:0> (SFR ROMBK<4:3>), see Table 20. Figure 12 shows an example of the interfacing connections for external SRAM data memory; see also Section 30. Table 20 RAMBK selection RAMBK<1:0> 00 01 10 11 BANK Bank 0 Bank 1 Bank 2 Bank 3 EXTERNAL ADDRESS RANGE 0 to 64 kbytes 64 to 128 kbytes 128 to 192 kbytes 192 to 256 kbytes For full details of the UART operation please refer to "Handbook IC20,80C51-Based 8-bit Microcontrollers". Remark: fclk used refers to the microcontroller clock frequency (12 MHz). The SAA56xx family of devices uses both clock edges, so the division factor is 6 instead of 12. The serial port can operate with different baud rates, depending on its mode. * Mode 0 (SM0 = 0, SM1 = 0); in shift register mode the baud rate is fixed at 16fclk * Mode 2 (SM0 = 0, SM1 = 1); in this fixed baud rate mode, the baud rate is determined by the SMOD bit in 2 the PCON register: baud rate = ----------------- x f clk 32 * Modes 1 (SM0 = 0, SM1 = 1); and 3 (SM0 = 1, SM1 = 0); in these modes the baud rate is variable and is determined by either Timer 1 or Timer 2; see Section 13. Timer 1: can be used in either Timer or Counter mode, when the baud rate is determined by the timer overflow rate and the value of SMOD as follows: 2 baud rate = ----------------- x Timer 1 overflow rate i.e. baud 32 f clk 2 rate = ----------------- x ----------------------------------------- where T1H is the 32 6 x ( 256 - T1H ) decimal value of the register contents. When Timer 1 is configured for timer operation, it is normal to use the 8-bit auto-reload mode, however 16-bit mode can be used for very low baud rates. In this case the Timer 1 interrupt will need to do a 16-bit software reload. Timer 2: will be placed in Baud generator mode when RCLK0 and/or TCLK0 bits in the T2CON register are set. When Timer 2 is clocked internally it has the following f clk baud rate: --------------------------------------------------------------------16 x [ 65536 - ( TH2, TL2 ) ] Where TH2 and TL2 is the decimal value of the 16-bit contents of there respective SFRs. When Timer 2 is configured as a counter, using pin T2 the baud rate equals the Timer 2 overflow rate divided by 16. 19 LED SUPPORT Port pins P0.5 and P0.6 have an 8 mA current sinking capability to enable LEDs in series with current limiting resistors to be driven directly, without the need for additional buffering circuits. 2001 Dec 13 49 SMOD SMOD SMOD External program ROM (pin EA tied LOW): the internal microcontroller logic makes it possible to only address 192 bytes of external program ROM with linear addressing. Figure 13 shows the interface connections. Remark: For emulating the external program ROM pins A15_BK, ROMBK0, ROMBK1 and ROMBK2 are used to address up to 256 kbytes. With additional glue logic these address lines can be used to address up to 256 kbytes os external ROM. Figure 14 shows the additional glue logic. Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth WR RD RAMBK <1:0> WE OE A <17:16> A15 A <14:8> D <7:0> A <7:0> CE SAA56xx A15_BK A <14:8> AD <7:0> SRAM AD<7:0> ALE LATCH A <7:0> GSA075 Fig.12 External SRAM configuration. handbook, full pagewidth PSEN OE A <17:15> A <14:8> D <7:0> A <7:0> SAA56xx A <17_LN:15_LN> A <14:8> AD <7:0> ROM up to 192 Kbytes AD<7:0> ALE LATCH A <7:0> GSA076 Fig.13 External ROM configuration. 2001 Dec 13 50 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth SAA56XX A<17_LN A<15_LN ROMBK1 ROMBK0 A17 A18 A15 MGU488 ROM Fig.14 Additional glue logic required to address 256 kbytes of external ROM. 21 MEMORY INTERFACE The memory interface controls access to the embedded DRAM, refreshing of the DRAM and page clearing. The DRAM is shared between Data Capture, display and microcontroller sections. The Data Capture section uses the DRAM to store acquired information that has been requested. The display reads from the DRAM information and converts it to RGB values. The microcontroller uses the DRAM as embedded auxiliary RAM. 21.1 Memory structure 21.1.2 DISPLAY RAM The Display RAM is initialised on power-up to a value of 20H throughout. The contents of the Display RAM are maintained when entering Idle mode. If Idle mode is exited using an interrupt, the contents are unchanged, if Idle mode is exited using an external reset, the contents are initialised to 20H. Full Closed Caption display requires display RAM from 8000H to 845FH. The memory from 8460H to 84FFH (must be initialised by the application software) can be utilised as an extension to the dedicated contiguous Auxiliary RAM that occupies 0000H to 07FFH. 21.2 Memory mapping The memory is partitioned into two distinct areas, the dedicated Auxiliary RAM area and the Display RAM area. When not being used for Data Capture or display, the Display RAM area can be used as an extension to the auxiliary RAM area. 21.1.1 AUXILIARY RAM The Auxiliary RAM is not initialised at power-up and must be initialised by the application software. Its contents are maintained during Idle mode and Standby mode, but are lost if Power-down mode is entered. The dedicated auxiliary RAM area occupies 2 kbytes, with an address range from 0000H to 07FFH. The Display RAM occupies a maximum of 12 kbytes with an address range from 2000H to 5000H for TXT mode and 8000H to 84FFH for CC mode (see Fig.15). Although having different address ranges, the two modes occupy physically the same DRAM area. 2001 Dec 13 51 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 21.3 CCBASE SFR 21.4 Addressing memory SAA56xx The SAA56xx incorporates a CCBASE SFR, which enables CC Display data to be accessed from any 1-kbyte partition within the Display memory. This SFR allows the CC Base address for Closed Caption Display memory to overlap Teletext memory at the following hexadecimal boundaries of the 80C51 microcontroller `MOVX' address space: 2000H (same as SAA55x default), 2400H, 2800H, 2C00H, 3000H, 3400H, 3800H, 3C00H, 4000H, 4400H, 4800H, 4C00H, 5000H, 5400H, 5800H, 5C00H, 6000H, 6400H, 6800H and 6C00H. The reset value for the CCBASE Address SFR is 20H, thus ensuring software compatibility with other variants in the SAA55xx family. Register bits CCBASE1 and CCBASE0 must always be set to zero at 1-kbyte boundaries. Figure 15 shows the default setting for the CC Display memory. The memory can be addressed by the microcontroller in two ways, either directly using a MOVX command or via SFRs, depending on what address is required. The dedicated Auxiliary RAM, and Display memory in the range 8000H to 86FFH can only be accessed using the MOVX command. The Display memory in the range 2000H to 47FFH can either be directly accessed using the MOVX command, or via the SFRs. 21.4.1 TXT DISPLAY MEMORY SFR ACCESS lower 32 handbook, halfpage kbytes upper 32 kbytes 7FFFH FFFFH When in TXT mode (see Fig.16), the Display memory is configured as 40 columns wide by 25 rows and occupies 1K x 8-bit of memory. There can be a maximum of 12 display pages. Using TXT15.BLOCK<3:0> and TXT15.MICRO BANK, the required display page can be selected to be written to. The row and column within that block is selected using TXT9.R<4:0> and TXT10.C<5:0>. The data at the selected position can be read or written using TXT11.D<7:0>. Whenever a read or write is performed on TXT11, the row values stored in TXT9 and column value stored in TXT10 are automatically incremented. For rows 0 to 24, the column value is incremented up to a maximum of 39, at which point it resets to 0 and increments the row counter value. When row 25 column 23 is reached, the values of the row and column are both reset to 0. Writing values outside the valid range for TXT9 or TXT10 will cause undetermined operation of the auto-incrementing function for accesses to TXT11. 21.4.2 TXT DISPLAY MEMORY MOVX ACCESS 5000H TXT BLOCK 19 TXT BLOCK 10 TXT BLOCK 8 TXT BLOCK 7 TXT BLOCK 6 TXT BLOCK 5 TXT BLOCK 4 TXT BLOCK 3 TXT BLOCK 2 TXT BLOCK 1 TXT BLOCK 9 TXT BLOCK 0 4C00H 4800H 4400H 4000H 3C00H 3800H 3400H 3000H 2C00H 2800H 2400H 2000H For the generation of OSD displays that use this mode of access, it is important to understand the mapping of the MOVX address onto the display row and column value. This mapping of row and column onto address is shown in Table 21. The values shown are added onto a base address for the required memory block (see Fig.16) to give a 16-bit address. 0800H AUXILIARY 0000H GSA061 84FFH CC DISPLAY 8000H Fig.15 DRAM memory mapping. 2001 Dec 13 52 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) Table 21 Column and row to `MOVX' address (lower 10 bits of address in hexadecimal) ROW Row 0 Row 1 : : Row 23 Row 24 Row 25 COL. 0 000 020 : : 2E0 300 320 ..... ..... ..... : : ..... ..... ..... COL. 23 017 037 : : 3F7 317 337 ..... ..... ..... : : ..... ..... COL. 31 01F 03F : : 2FF 31F COL. 32 3F8 3F0 : : 340 338 ..... ..... ..... : : ..... ..... SAA56xx COL. 39 3FF 3F7 : : 347 33F handbook, full pagewidth 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 control data 10 C Column 20 30 39 9 10 23 non-displayable data (byte 10 reserved) active position TXT9.R<4:0> = 01H, TXT10.C<5:0> = 0AH, TXT11 = 43H MBK962 Fig.16 TXT memory map. 2001 Dec 13 53 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 21.5 Page clearing 21.5.2 SOFTWARE PAGE CLEAR SAA56xx Page clearing is performed on request from the Data Capture section or the microcontroller, under the control of the embedded software. At power-on and reset, the whole of the page memory is cleared. Bit TXT13.PAGE CLEARING is set while this takes place. 21.5.1 DATA CAPTURE PAGE CLEAR The software can also initiate a page clear by setting bit TXT9.CLEAR MEMORY. Now, every location in the memory block pointed to by TXT15.BLOCK<3:0> is cleared to a space code (20H). Bit CLEAR MEMORY is not latched, so the software does not have to reset it after it has been set. Only one page can be cleared in a TV line. Therefore, if the software requests a page clear, it will be carried out on the next TV line on which the Data Capture hardware does not force the page to be cleared. A flag (TXT13.PAGE CLEARING) is provided to indicate that a software requested page clear is being carried out. The flag is set when a logic 1 is written to bit TXT9.CLEAR MEMORY and is reset when the page clear has been completed. All locations are cleared to 00H if bit TXT0.INV ON = 1 and a page clear is initiated on Block 8. 21.6 Multi-page operations When a page header is acquired for the first time after a new page request or a page header is acquired with the erase (C4) bit set, the page memory is `cleared' to spaces before the rest of the page arrives. When this occurs, the space code (20H) is written into every location of rows 1 to 23 of the basic page memory, the appropriate packet 27 row of the extension packet memory and the row where Teletext packet 24 is written. This last row is either row 24 of the basic page memory (if the TXT0.X24 POSN bit is set) or row 0 of the extension packet memory (if the bit is not set). Page clearing is done before the end of the TV line in which the header arrived which initiated the page clear. This means that the 1 field gap between the page header and the rest of the page which is necessary for many Teletext decoders is not required. When using SAA56xx in a multi-page application with external SRAM, bit TXT28.MULTI PAGE should be set. This allows the 80C51 microcontroller to copy acquired data between internal Display memory and external SRAM without hindrance. 2001 Dec 13 54 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 22 DATA CAPTURE The Data Capture section (see Fig.17) takes in the analog Composite Video and Blanking Signal (CVBS), and extracts the required data from it in the digital domain. The data is then decoded and stored in memory. The first stage converts the analog CVBS signal to digital form, using ADC sampling at 12 MHz. Data and clock recovery is then performed by a Multi-rate Video Input Processor (MulVIP). Next, the following types of data are extracted: WST Teletext (625/525), VPS, Closed Caption (CC) and WSS. The extracted data is stored in either memory (DRAM) via the Memory Interface or in SFR locations. 22.1 Data Capture features * Data Capture for WSS bit decoding SAA56xx * Data Capture for VPS data (PDC system A) * Automatic selection between 525 WST/625 WST * Automatic selection between 625 WST/VPS on line 16 of Vertical Blanking Interval (VBI) * Real-time capture and decoding for WST Teletext in hardware, to enable optimized microprocessor throughput * Up to 12 pages stored on-chip * Inventory of transmitted Teletext pages stored in the Transmitted Page Table and Subtitle Page Table * Automatic detection of Fastext transmission * Real-time packet 26 engine in hardware for processing accented, G2 and G3 characters * Signal quality detector for WST/VPS data types * Comprehensive Teletext language coverage * Full-Field and VBI Data Capture of WST data. * Two CVBS inputs * Video Signal Quality detector * Data Capture for 625-line WST * Data Capture for 525-line WST * Data Capture for line 21 data service (Closed Caption) handbook, full pagewidth CVBS0 CVBS1 CVBS SWITCH CVBS ADC data<7:0> DATA SLICER AND CLOCK RECOVERY TTC TTD SYNC SEPARATOR VCS ACQUISITION TIMING SYNC_FILTER ACQUISITION FOR WST/VPS output data to memory interface ACQUISITION FOR CC/WSS output data to SFRs MBK963 Fig.17 Data Capture block diagram. 2001 Dec 13 55 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 22.1.1 CVBS SWITCH SAA56xx 22.1.6.1 Making a page request The CVBS switch is used to select the required analog input, depending on the value of TXT8.CVBS1/CVBS0. 22.1.2 ANALOG-TO-DIGITAL CONVERTER The output of the CVBS switch is passed to a Differential-to-Single-Ended Converter (DIVIS, not shown in Fig.17), although here it is used in single-ended configuration with a reference. A full-flash ADC with a sampling rate of 12 MHz converts the analog output of the DIVIS to a digital representation. 22.1.3 MULTI-RATE VIDEO INPUT PROCESSOR (MULVIP) A page is requested by writing a series of bytes into the TXT3.PRD<4:0> SFR, which corresponds to the number of the page required. The bytes written into TXT3 are stored in a RAM with an auto-incrementing address. The start address for the RAM is set using the TXT2.SC<2:0> (to define which part of the page request is being written) and TXT2.REQ<3:0> (along with TXT2.ACQ BANK) is used to define which of the 12 page request blocks is being modified. If TXT2.REQ<3:0> is greater than 09H, then data being written to TXT3 is ignored (applies to Bank 0 and Bank 1). Table 23 shows the contents of the page request RAM. Up to 12 pages of Teletext can be acquired on the 12 page device, when TXT1.EXT PKT OFF is set to logic 1, and up to 10 pages can be acquired when this bit is set to logic 0. Table 23 The contents of the Page request RAM START COLUMN 0 1 2 3 4 PRD4 Do Care Magazine Do Care Page Tens PRD3 PRD2 PRD1 PRD0 HOLD MAG2 MAG1 MAG0 PT3 PT2 PU2 X HU2 PT1 PU1 HT1 HU1 PT0 PU0 HT0 HU0 The MulVIP (used for data and clock recovery) is a Digital Signal Processor designed to extract the data and recover the clock from a digitized CVBS signal. 22.1.4 DATA STANDARDS AND CLOCK RATES The data standards and clock rates that can be recovered are shown in Table 22. Table 22 Data standards and clock rates DATA STANDARD 625 WST 525 WST VPS WSS Closed Caption 22.1.5 CLOCK RATE 6.9375 MHz 5.7272 MHz 5.0 MHz 5.0 MHz 500 kHz Do Care PU3 Page Units Do Care Hour Tens Do Care Hours Units Do Care Minutes Tens Do Care Minutes Units X X HU3 DATA CAPTURE TIMING 5 The Data Capture timing section uses the synchronisation information extracted from the CVBS signal to generate the required horizontal and vertical reference timings. The timing section automatically recognizes and selects the appropriate timings for either 625 (50 Hz) synchronisation or 525 (60 Hz) synchronisation. A TXT12.VIDEO SIGNAL QUALITY flag is set when the timing section is locked correctly to the incoming CVBS signal. When TXT12.VIDEO SIGNAL QUALITY is set, another flag TXT12.525/625 SYNC can be used to identify the standard. 22.1.6 ACQUISITION X MT2 MT1 MT0 6 MU3 MU2 MU1 MU0 7 X X E1 E0 The acquisition section extracts the relevant information from the serial stream of data from the MulVIP and stores it in memory. If the `Do Care' bit for part of the page number is set to logic 0, then that part of the page number is ignored when the Teletext decoder is deciding whether a page being received off-air should be stored or not. For example, if the `Do Care' bits for the four subcode digits are all set to logic 0, then every subcode version of the page will be captured. 2001 Dec 13 56 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) When bit HOLD is set to a logic 0, the Teletext decoder will not recognise any page as having the correct page number and no pages will be captured. In addition to providing the user requested hold function, this bit should be used to prevent the inadvertent capture of an unwanted page when a new page request is being made. For example, if the previous page request was for page 100 and this was being changed to page 234, it would be possible to capture page 200 if this arrived after only the requested magazine number had been changed. Bits E1 and E0 control the error checking, which should be carried out on packets 1 to 23 when the page being requested is captured. This is described in more detail in Section 22.1.6.3. For a multi-page device, each packet can only be written into one place in the Teletext RAM. Therefore, if a page matches more than one of the page requests, the data is written into the area of memory corresponding to the lowest numbered matching page request. At power-up, each page request defaults to any page, hold on and error check Mode 0. SAA56xx The last eight characters of the page header are used to provide a time display and are always extracted from every valid page header as it arrives and written into the display block. Bit TXT0.DISABLE HEADER ROLL prevents any data being written into row 0 of the page memory, except when a page is acquired off-air, i.e. rolling headers and time are not written into the memory. Bit TXT1.ACQ OFF prevents any data being written into the memory by the Teletext acquisition section. When a parallel magazine mode transmission is being received, only headers in the magazine of the page requested are considered valid for the purposes of rolling headers and time. Only one magazine is used even if the Do Care magazine bit is set to logic 0. When a serial magazine mode transmission is being received, all page headers are considered to be valid. 22.1.6.3 Error checking 22.1.6.2 Rolling headers and time When a new page is requested, it is conventional for the decoder to turn the header row of the display green and to display each page header as it arrives until the correct page is found. When a page request is changed (i.e. when the TXT3 SFR is written to), a flag (PBLF) is written into bit 5, column 9, row 25 of the corresponding block of the page memory. The state of the flag for each block is updated every TV line 1. If it is set for the current display block, the acquisition section writes all valid page headers that arrive into the display block and automatically writes an alphanumeric green character into column 7 of row 0 of the display block every TV line. When a requested page header is acquired for the first time, rows 1 to 23 of the relevant memory block are cleared to space, i.e. have 20H written into every column, before the rest of the page arrives. Row 24 is also cleared if bit TXT0.X24 POSN is set. If bit TXT1.EXT PKT OFF is set, the extension packets corresponding to the page are also cleared. Teletext packets are error checked before they are written into the page memory. The error checking carried out depends on the packet number, the byte number, the error check mode bits in the page request data and bit TXT1.8-BIT (see Fig.18). If an uncorrectable error occurs in one of the Hamming checked addressing and control bytes in the page header or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory is set, to act as an error flag to the software. If uncorrectable errors are detected in any other Hamming checked data, the byte is not written into the memory. 2001 Dec 13 57 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx Packet X/0 handbook, full pagewidth '8-bit' bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/1-23 '8-bit' bit = 0, error check mode = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/24 '8-bit' bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/27/0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet 8/30/0,1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet 8/30/2,3,4-15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 MGK465 8-bit data odd parity checked 8/4 Hamming checked Fig.18 Error checking. 2001 Dec 13 58 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 22.1.6.4 Teletext memory organisation SAA56xx Packet 0, the page header, is split into two parts when it is written into the text memory. The first eight bytes of the header contain control and addressing information. They are Hamming decoded and written into columns 0 to 7 of row 25, which also contains the magazine number of the acquired page and the PBLF flag. However, the last 14 bytes are unused and may be used by the software, if necessary. The Teletext memory is divided into two banks of ten blocks. Normally, when bit TXT1.EXT PKT OFF is logic 0, each of blocks 0 to 8 contains a Teletext page arranged in the same way as the basic page memory of the page device (see Fig.19) and Block 9 contains extension packets (applies to Bank 0 and Bank 1), see Fig.20. When bit TXT1.EXT PKT OFF is logic 1, no extension packets are captured and Block 9 of both Bank 0 and Bank 1 of the memory are used to store two other pages. The number of the memory block into which a page is written corresponds to the page request number (TXT2.REQ<3:0>) which resulted in the capture of the page. handbook, full pagewidth Basic Page Blocks (0 to 9 Bank 0; 0 and 9 Bank 1) 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 Control Data 9 10(3) 6 7 8 Packet X/0 Packet X/1 Packet X/2 Packet X/3 Packet X/4 Packet X/5 Packet X/6 Packet X/7 Packet X/8 Packet X/9 Packet X/10 Packet X/11 Packet X/12 Packet X/13 Packet X/14 Packet X/15 Packet X/16 Packet X/17 Packet X/18 Packet X/19 Packet X/20 Packet X/21 Packet X/22 Packet X/23 Packet X/24(1) VPS Data(2) 23 GSA071 39 OSD only (1) If `X24 POSN' bit = 1. (2) VPS data only in block 9 of either bank 0 or bank 1. (3) Byte 10 reserved. Fig.19 Packet storage locations. 2001 Dec 13 59 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx Extension handbook, full pagewidth Packet (Block 9 Bank 0) Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 Packet X/24 for page in block 0(1) Packet X/27/0 for page in block 0 Packet 8/30/0.1 Packet 8/30/2.3 Packet X/24 for page in block 1(1) Packet X/27/0 for page in block 1 Packet X/24 for page in block 2(1) Packet X/27/0 for page in block 2 Packet X/24 for page in block 3(1) Packet X/27/0 for page in block 3 Packet X/24 for page in block 4(1) Packet X/27/0 for page in block 4 Packet X/24 for page in block 5(1) Packet X/27/0 for page in block 5 Packet X/24 for page in block 6(1) Packet X/27/0 for page in block 6 Packet X/24 for page in block 7(1) Packet X/27/0 for page in block 7 Packet X/24 for page in block 8(1) Packet X/27/0 for page in block 8 Packet 8/30/4-15 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Extension Packet (Block 9 Bank 1) Packet X/24 for page in block 0(1) Packet X/27/0 for page in block 0 Packet 8/30/0.1 Packet 8/30/2.3 Packet 8/30/4-15 VPS Data 9 10(2) 23 0 VPS Data 9 10(2) 23 GSA072 (1) If `X24 POSN' bit = 0. (2) Byte 10 reserved. Fig.20 Extension packet storage locations. 2001 Dec 13 60 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 22.1.6.5 Row 25 data contents SAA56xx The magazine serial bit (C11) indicates whether the magazine transmission is serial or parallel. This affects how the acquisition section operates and is dealt with automatically. The newsflash (C5), subtitle (C6), suppress header (C7), inhibit display (C10) and language control (C12 to 14) bits are dealt with automatically by the display section. The update bit (C8) has no effect on the hardware. The remaining 32 bytes of the page header are parity checked and written into columns 8 to 39 of row 0. Bytes that pass the parity check have the MSB set to a logic 0 and are written into page memory. Bytes with parity errors are not written into the memory. The Hamming error flags are set if the on-board 8/4 Hamming checker detects that there has been an uncorrectable (2-bit) error in the associated byte. It is possible for the page to still be acquired if some of the page address information contains uncorrectable errors if that part of the page request was a `Don't Care'. There is no error flag for the magazine number because an uncorrectable error in this information prevents the page being acquired. The interrupt sequence (C9) bit is automatically dealt with by the acquisition section, so that rolling headers do not contain a discontinuity in the page number sequence. Table 24 The data in row 25 of the basic page memory COL 0 1 2 3 4 5 6 7 8 9 10 to 23 BIT 7 0 0 0 0 0 0 0 0 0 0 - BIT 6 0 0 0 0 0 0 0 0 0 0 - BIT 5 0 0 0 0 0 0 0 0 0 PBLF - BIT 4 Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error FOUND 0 unused BIT 3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0 - BIT 2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0 - BIT 1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0 - BIT 0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0 - 2001 Dec 13 61 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 22.1.6.6 Inventory page SAA56xx The bit for a particular page in the TPT is set when a page header is received for that page. The bit in the SPT is set when a page header for the page is received which has the `subtitle' page header control bit (C6) set. The bit for a particular page in the TPT is set when a page header is received for that page. The bit in the SPT is set when a page header for the page is received which has the `subtitle' page header control bit (C6) set. If bit TXT0.INV ON is a logic 1, memory block 8 of Bank 0 is used as an inventory page.This consists of two tables: the Transmitted Page Table (TPT) and the Subtitle Page Table (SPT); see Fig.21. In each table, every possible combination of the page tens and units digit, 00H to FFH, is represented by a byte, see Fig.22. Each bit of these bytes corresponds to a magazine number so each page number, from 100H to 8FFH, is represented by a bit in the table. 0 handbook, full pagewidth 39 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 Transmitted Pages Table Subtitle Pages Table Unused Unused Unused Unused Unused Unused Unused Unused Unused 23 MGD165 Fig.21 Inventory page organisation. 2001 Dec 13 62 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx Bytes in the table handbook, full pagewidth column 0 8 16 24 32 39 row n n+1 n+6 n+7 bits in each byte xe0 xe1 xe2 xe3 xe4 xe5 xe6 xe7 xe8 xe9 xea xeb xec xed xee xfef xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xfa xfb xfc xfd xfe xff bit 7 7xx 6xx 5xx 4xx 3xx 2xx 1xx 0 8xx xc0 xc1 xc2 xc3 xc4 xc5 xc6 xc7 xc8 xc9 xca xcb xcc xcd xce xcf xd0 xd1 xd2 xd3 xd4 xd5 xd6 xd7 xd8 xd9 xda xdb xdc xdd xde xdf x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x2a x2b x2c x2d x2e x2f x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 x3a x3b x3c x3d x3e x3f x00 x01 x02 x03 x04 x05 x06 x07 x08 x09 x0a x0b x0c x0d x0e x0f x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x1a x1b x1c x1d x1e x1f MGD160 Fig.22 Transmitted/subtitle page organisation. 22.1.6.7 Packet 26 processing One of the uses of packet 26 is to transmit characters that are not in the basic Teletext character set. The family automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in the character set, automatically writes the appropriate character code into the correct location in the Teletext memory. This is not a full implementation of the packet 26 specification allowed for in level 2 Teletext, and so is often referred to as level 1.5. By convention, the packets 26 for a page are transmitted before the normal packets. To prevent the default character data overwriting the packet 26 data, there is a mechanism which prevents packet 26 data from being overwritten. The mechanism is disabled when the Spanish national option is detected because the Spanish transmission system sends even parity (i.e. incorrect) characters in the basic page locations corresponding to the characters sent via packet 26 and these will not overwrite the packet 26 characters anyway. The special treatment of the Spanish national option is disabled if bit TXT12.SPANISH is cleared (logic 0) or if bit TXT8.DISABLE SPANISH is set (logic 1). Packet 26 data is processed regardless of bit TXT1.EXT PKT OFF, but setting bit TXT1.X26 OFF disables packet 26 processing. Bit TXT8.PKT26 RECEIVED is set by the hardware whenever the packet 26 decoding hardware writes a character into the page memory. The flag can be reset by writing a logic 0 into the SFR bit. 22.1.6.8 525-line World System Teletext The 525-line format (see Fig.23) is similar to the 625-line format but the data rate is lower and there are fewer data bytes per packet (32 rather than 40). There are still 40 characters per display row so extra packets are sent, each containing the last eight characters for four rows. These packets can be identified by the `tabulation bit' (T), which replaces one of the magazine bits in 525-line Teletext. When an ordinary packet with T = 1 is received, the decoder puts the data into the four rows, starting with that corresponding to the packet number, but with the two LSBs set to logic 0. For example, a packet 9 with T = 1 (packet X/1/9) contains data for rows 8, 9, 10 and 11. The error checking carried out on data from packets with T = 1 depends on the setting of bit TXT1.8-BIT and the error checking control bits in the page request data and is the same as that applied to the data written into the same memory location in the 625-line format. The rolling time display (the last eight characters in row 0) is taken from any packets X/1/1, 2 or 3 received. In parallel magazine mode, only packets in the correct magazine are used for the rolling time. Packet number X/1/0 is ignored. 63 2001 Dec 13 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) The tabulation bit is also used with extension packets. The first eight data bytes of packet X/1/24 are used to extend the Fastext prompt row to 40 characters. These characters are written into whichever part of the memory the packet 24 is being written into (determined by the `X24 POSN' bit). Packets X/0/27/0 contain five Fastext page links and the link control byte. They are captured, Hamming checked and stored in the same way as are packets X/27/0 in 625-line text. Packets X/1/27/0 are not captured. Because there are only two magazine bits in 525-line text, packets with the magazine bits all set to a logic 0 are referred to as being in magazine 4. Therefore, the broadcast service data packet is packet 4/30, rather than packet 8/30. SAA56xx As in 625-line text, the first 20 bytes of packet 4/30 contain encoded data that is decoded in the same way as in packet 8/30. The last 12 bytes of the packet contains half of the parity encoded status message. Packet 4/0/30 contains the first half of the message and packet 4/1/30 contains the second half. The last four bytes of the message are not written into memory. The first 20 bytes of the each version of the packet are the same, so they are stored whenever either version of the packet is acquired. In 525-line text, each packet 26 only contains ten 24/18 Hamming encoded data triplets, rather than the 13 found in 625-line text. The tabulation bit is used as an extra bit (the MSB) of the designation code, allowing 32 packet 26s to be transmitted for each page. The last byte of each packet 26 is ignored. handbook, full pagewidth 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 6 7 8 Packet X/0/0 Packet X/0/1 Packet X/0/2 Packet X/0/3 Packet X/0/4 Packet X/0/5 Packet X/0/6 Packet X/0/7 Packet X/0/8 Packet X/0/9 Packet X/0/10 Packet X/0/11 Packet X/0/12 Packet X/0/13 Packet X/0/14 Packet X/0/15 Packet X/0/16 Packet X/0/17 Packet X/0/18 Packet X/0/19 Packet X/0/20 Packet X/0/21 Packet X/0/22 Packet X/0/23 Packet X/0/24(1) Packet X/1/4 Rolling time Packet X/1/1 39 OSD only aw/ag Packet X/1/8 Packet X/1/12 Packet X/1/16 Packet X/1/20 Packet X/1 /24(1) GSA004 Control Data 9 10(2) 23 (1) If X24 POSN bit = 1. (2) Byte 10 reserved. Fig.23 Packet storage locations, 525-line. 2001 Dec 13 64 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 22.1.6.9 Fastext detection 22.1.7 WST ACQUISITION SAA56xx When a packet 27, designation code 0 is detected, whether or not it is acquired, bit TXT13.FASTEXT is set. If the device is receiving 525-line Teletext, a packet X/0/27/0 is required to set the flag. The flag can be reset by writing a logic 0 into the SFR bit. When a packet 8/30 is detected (or a packet 4/30 when the device is receiving a 525-line transmission), flag TXT13.PKT 8/30 is set. The flag can be reset by writing a logic 0 into the SFR bit. The SAA56xx family is capable of acquiring Level 1.5 625-line and 525-line World System Teletext. 22.1.8 WSS ACQUISITION The WSS data transmitted on line 23 gives information on the aspect ratio and display position of the transmitted picture, the position of subtitles and on the camera/film mode. Some additional bits are reserved for future use. A total of 14 data bits are transmitted. All of the available data bits transmitted by the WSS signal are captured and stored in SFRs WSS1, WSS2 and WSS3. The bits are stored as groups of related bits and an error flag is provided for each group to indicate when a transmission error has been detected in one or more of the bits in the group. WSS data is only acquired when the TXT8.WSS ON bit is set. Bit TXT8.WSS RECEIVED is set by the hardware whenever WSS data is acquired. The flag can be reset by writing a logic 0 into the SFR bit. 22.1.9 CLOSED CAPTION ACQUISITION 22.1.6.10 Broadcast Service Data Detection When a packet 8/30 is detected (or a packet 4/30 when the device is receiving a 525-line transmission), flag TXT13. PKT 8/30 is set. The flag can be reset by writing a logic 0 into the SFR bit. 22.1.6.11 VPS acquisition When bit TXT0.VPS ON is set, any VPS data present on line 16, field 0 of the CVBS signal at the input of the Teletext decoder is error checked and stored in row 25, block 9 of the basic page memory, see Fig.24. The device automatically detects whether Teletext or VPS is being transmitted on this line and decodes the data appropriately. Each VPS byte in the memory consists of four biphase decoded data bits (bits 0 to 3), a biphase error flag (bit 4) and three logic 0s (bits 5 to 7). The most significant bit of the VPS data cannot be set to logic 1. Bit TXT13.VPS Received is set by the hardware whenever VPS data is acquired. Full details of the VPS system can be found in the specification "Domestic Video Program Delivery Control System (PDC); EBU Tech. 3262-E". The US Closed Caption data is transmitted on line 21 (525-line timings) and is used for Captioning information, Text information and Extended Data Services. Full details can be found in the document "Recommended Practise for Line 21 Data Service EIA-608". Closed Caption data is only acquired when bit TXT21.CC ON is set. Two bytes of data are stored per field in SFRs. The first byte is stored in CCDAT1 and the second byte is stored in CCDAT2. The value in the CCDAT registers is reset to 00H at the start of the Closed Caption line defined by CCLIN.CS<4:0>. At the end of the Closed Caption line, an interrupt is generated if IEN0.ECC is active. The Closed Caption data is software-processed to convert it into a displayable format. handbook, full pagewidth column 0 row 25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 teletext page header data VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 VPS byte 15 VPS byte 4 VPS byte 5 MBK964 Fig.24 VPS data storage. 2001 Dec 13 65 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23 DISPLAY The display section (see Fig.25) is based on the requirements for a Level 1.5 WST Teletext and US Closed Caption. There are some enhancements for use with locally generated on-screen displays. The display section reads the contents of the Display memory and interprets the control/character codes. From this information and other global settings, the display produces the required RGB signals and Video/Data (Fast Blanking) signal for a TV signal processing device. SAA56xx The display is synchronized to the TV signal processing device by horizontal and vertical sync signals from external circuits (Slave Sync mode). All display timings are derived from these signals. The SAA56xx display section incorporates a number of enhancements over the rest of the SAA55xx family, including 100 Hz (2H/2V only) operation, two page mode (50/60 Hz only), increased DRCS/Special Graphics and a larger Character ROM. handbook, full pagewidth HSYNC VSYNC PHASE SELECTOR CLK DISPLAY TIMING PAGE B 12/24 MHz display address data control address MICROPROCESSOR INTERFACE data FUNCTION REGISTERS FOR PAGE A AND PAGE B PARALLEL/SERIAL CONVERTER WITH SMOOTHING AND FRINGING to memory interface from memory interface address data DISPLAY DATA ADDRESSING FOR PAGE A AND PAGE B data ATTRIBUTE HANDLING FOR PAGE A AND PAGE B DATA BUFFER data CHARACTER ROM AND DRCs CHARACTER FONT ADDRESSING CLUT RAM address DAC DAC DAC GSA062 R G B FB Fig.25 Display block diagram. 2001 Dec 13 66 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.1 Display features 23.2 Display modes SAA56xx * Teletext and Enhanced OSD modes * Level 1.5 WST features * US Closed Caption features * 50/60 Hz or 100/120 Hz display timing modes * Two page operation (50/60 Hz only) * Serial and parallel display attributes * Single/double/quadruple width and height for characters * Smoothing capability of double size, double width, double height and quadruple size characters * Scrolling of display region * Variable flash rate controlled by software * Globally selectable scan lines per row 9/10/13/16 * Globally selectable character matrix (H x V) 12 x 9, 12 x 10, 12 x 13 and 12 x 16 * Italics * Soft colours using CLUT with 4096 colour palette * Underline * Overline * Fringing (shadow) selectable from N-S-E-W direction * Fringe colour selectable * Meshing of defined area * Contrast reduction of defined area (both CC and Teletext display modes * Cursor * Special graphics characters with two planes, allowing four colours per character * 64 dynamically redefinable characters for OSDs * Up to 4 WST character sets (G0/G2) user programmable in a single device (e.g. Latin, Cyrillic, Greek and Arabic) * G1 Mosaic graphics, Limited G3 Line drawing characters * WST character sets and Closed Caption character set user programmable in a single device. The display section has two distinct modes with different features available in each: * TXT: This is the WST mode with additional serial and global attributes. A TXT window is configured as a fixed 25 rows with 40 characters per row. * CC: This is the US Closed Caption mode. A CC window is configured as a maximum of 16 rows with a maximum of 48 characters per row. In both of the above modes, the character matrix and TV lines per row can be defined. There is an option of a character matrix (H x V) of 12 x 9, 12 x 10, 12 x 13, or 12 x 16, which have 9, 10, 13 and 16 TV lines per display row, respectively. Table 25 gives the possible number of display rows for each combination, as allowed by the hardware. Table 25 Maximum number of display rows CHARACTER MATRIX 12 x 9 12 x 10 12 x 13 12 x 16 MAX NUMBER OF DISPLAY ROWS TXT 625 25 25 21 17 TXT 525 25 23 18 14 CC 16 16 16 14 SFR TXT21 and memory mapped registers are used to control the mode selection. The features will now be described and their function in each of the modes given. If the feature is different in either mode then this is stated. 2001 Dec 13 67 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.2.1 FEATURES AVAILABLE AND CHARACTERS IN EACH MODE SAA56xx Table 26 shows a list of features available in each mode, and also if the setting is a serial/parallel attribute, or has a global effect on all the display. Table 26 Display features and characters in each mode FEATURE Flash Boxes Horizontal size Vertical size Italic Foreground colours Background colours Soft colours (CLUT) Underline Overline Fringe Fringe colour Meshing of background Fast Blanking Polarity Screen colour DRCS Character matrix (H x V) Number of rows Number of columns Number of characters displayable Cursor Special graphics (2 planes per character) Scroll Smoothing Contrast reduction serial TXT/OSD (serial) x1, x2 or x4 (serial) x1 or x2 (serial); x4 (global) n/a 8 (serial) 8 (serial) 16 from 4096 n/a n/a N+S+E+W 16 (global) black or colour (global) yes 16 (global) 64 (global) 12 x 9, 12 x 10, 12 x 13 or 12 x 16 25 40 1000 yes 32 no yes (global) yes (global) TXT serial serial x1 or x2 (serial) x1 or x2 (serial) serial 8 + 8 (parallel) 16 (serial) 16 from 4096 serial serial N+S+E+W 16 (serial) all (global) yes 16 (global) 64 (global) 12 x 9, 12 x 10, 12 x 13 or 12 x 16 16 48 768 yes 32 (default), 128 if extended special graphics on yes yes (global) yes (serial) CC 2001 Dec 13 68 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.3 Display timing modes SAA56xx The display can be configured for either 50/60 Hz or 100/120 Hz (2H/2V only) using the display configuration MMR 87FFH. Table 27 Display timing modes DISPLAY TIMING (MMR 87FFH) 100 HZ BIT 0 X 1 23.3.1 TWO_PAGE BIT 0 1 0 DOUBLE WINDOW OPERATION 1H/1V 1H/1V 1H/1V; 2H/2V 12 MHz 24 MHz 24 MHz 40 (single window) 80 (double window) 40 (single window) SUPPORTED HSYNC/VSYNC RATE DISPLAY CLOCK NUMBER OF CHARACTERS This mode enables two different pages to be displayed side-by-side for use with 16:9 TV screens. The display section clock runs at 24 MHz in this mode. Fig.26 shows the combination of two page display possible on the SAA56xx device. Two page mode is selected using MMR 87FFH bit 0. The two pages displayed are separated by two character spaces to allow the display logic to switch correctly from one window to the other. The facility is restricted to 1H/1V (i.e. 50/60Hz display TVs). Two control bits exist in double window mode to select Closed Caption display or text display in each window: TXT21.CC/TXT for Page A and TXT28.CC_TXT B for Page B. TXT: When displaying two Teletext pages side by side, the memory block being displayed in Page A is selected using SFR TXT14<3:0> and for Page B using SFR TXT28<3:0>. The Data Capture section writes the header and time information only to the memory block corresponding to the active page. This active page is determined with the TXT28.ACTIVE PAGE bit. When set to logic 0, Page A is active, set to logic 1, Page B is active. Operation of the REVEAL bit (TXT7.5) and CURSOR ON bit (TXT7.6) only affects the active page. CC: When CC display mode is selected in two page mode, only one window may be used for CC/OSD and the other either Text or Video. Two page CC display (either captions or OSD) side-by-side is not possible because there is only one area of memory available for the CC data. 23.3.2 SINGLE WINDOW OPERATION At reset, the device defaults to single window mode, which corresponds to 87FFH bit 0 set to logic 0. In this mode, the settings applying to the window displayed are those that would apply to Page A in double window mode. For 2H/2V display TVs, the 100 Hz bit, MMR 87FFH bit 1, must be set to logic 1 to fit a whole display window. For 1H/1V display TVs, when MMR 87FFH bit 1 is set to logic 0, the display window occupies the whole screen, whereas if MMR 87FFH bit 1 is set to logic 1, only half the screen would be occupied by the display window. This latter configuration would give the same kind of display as in the double window mode with Page A: CC or Text Page B: Video. 2001 Dec 13 69 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx ok, full pagewidth Screen Colour Area Page A Text OSD Page B Text OSD Screen Colour Area Page A Text Page B Text OSD Screen Colour Area Page A Text Page B Text Subtitle Screen Colour Area Page A Text Subtitle Page B Text Screen Colour Area Page A Video Page B Text OSD Screen Colour Area Page A Text Page B Video Screen Colour Area Page A Text Page B Text Screen Colour Area Page A Text OSD Page B Video Screen Colour Area Page A Page B CC Video Screen Colour Area Page A Video Page B CC Screen Colour Area Page A Video Page B CC OSD Screen Colour Area Page A CC OSD Page B Video Screen Colour Area Page A CC OSD Page B Text Screen Colour Area Page A Text Page B CC OSD GSA077 Fig.26 Two-page Text/CC/video combinations. 2001 Dec 13 70 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.4 Display feature descriptions 23.4.3 SIZE SAA56xx All display features are now described in detail for both TXT and CC modes. 23.4.1 FLASH The size of the characters can be modified in both the horizontal and vertical directions. CC: Two sizes are available in both the horizontal and vertical directions. The sizes available are normal (x1), double (x2) height/width and any combination of these. The attribute setting is always valid for the whole row of a display window. Mixing of sizes within a row is not possible. TXT: Three horizontal sizes are available: normal (x1), double (x2), quadruple (x4). The control characters `normal size' (0CH/BCH) enable normal size. The `double width' or double size (0EH/BEH/0FH/BFH) control characters enable double width characters. Any two consecutive combinations of `double width' or `double size' (0EH/BEH/0FH/BFH) control characters activate quadruple width characters, provided quadruple width characters are enabled by TXT4.QUAD WIDTH ENABLE. Three vertical sizes are available normal (x1), double (x2) and quadruple (x4). The control characters `normal size' (0CH/BCH) enable normal size, the `double height' or `double size' (0DH/BDH/0FH/BFH) enable double height characters. Quadruple height characters are achieved by using double height characters and setting the global attributes TXT7.DOUBLE HEIGHT (expand) and TXT7.BOTTOM/TOP. If double height characters are used in Teletext mode, single height characters in the lower row of the double height character are automatically disabled. 23.4.4 ITALIC Flashing causes the foreground colour pixels to be displayed as the background pixels. The flash frequency is controlled by software setting and resetting the MMR Status (see Table 41) at the appropriate interval. CC: This attribute is valid from the time set (see Table 33) until the end of the row of a display window, or until otherwise modified. TXT: This attribute is set by the control character `flash' (08H) (see Fig.35) and remains valid until the end of a row of a display window, or until reset by the control character `steady' (09H). 23.4.2 BOXES CC: This attribute is valid from the time set until the end of a row of a display window, or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then it is set from the next character onwards. In text mode (within CC mode), the background colour is displayed regardless of the setting of the box attribute bit. Boxes take effect only during mixed mode. Where boxes are set in this mode, the background colour is displayed. Character locations where boxes are not set show video/screen colour (depending on the setting in the MMR Display Control) instead of the background colour. TXT: Two types of boxes exist: the Teletext box and the OSD box. The Teletext box is activated by the `start box' control character (0BH), Two start box characters are required to begin a Teletext box, with the box starting between the two characters. The box ends at the end of the line or after an `end box' control character. TXT mode can also use OSD boxes, which are started using size implying OSD control characters (BCH/BDH/BEH/BFH). The box starts after the control character (set after) and ends either at the end of a row of a display window, or at the next size implying OSD character (set at). The attributes flash, Teletext box, conceal, separate graphics, twist and hold graphics are all reset at the start of an OSD box, as they are at the start of the row. OSD boxes are only valid in TV mode, which is defined by TXT5 = 03H and TXT6 = 03H. CC: This attribute is valid from the time set until the end of a row of a display window, or otherwise modified. The attribute causes the character foreground pixels to be offset horizontally by 1 pixel per 4 scan lines (interlaced mode). The base is the bottom left character matrix pixel. The pattern of the character is indented, as shown in Fig.27. TXT: The Italic attribute is not available. 2001 Dec 13 71 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth 12 x 16 character matrix 12 x 13 character matrix 12 x 10 character matrix 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 indented by 7/6/4 indented by 6/5/3 indented by 5/4/2 indented by 4/3/1 indented by 3/2/0 indented by 2/1 indented by 1/0 indented by 0 MBK970 Field 1 Field 2 Fig.27 Italic characters. 23.4.5 COLOURS A Colour Look-Up Table (CLUT) with 16 colour entries is provided. The colours can be programmed from a palette of 4096 (4 bits per R, G and B), as shown in Table 28. The CLUT is defined by writing data to a RAM that resides in the MOVX address space of the 80C51. When set, the colours are global and apply to all display windows. Table 28 CLUT colour values RED<3:0> GREEN<3:0> (B11 TO B8) (B7 TO B4) 0000 0000 ... 1111 1111 23.4.6 0000 0000 ... 1111 1111 BLUE<3:0> (B3 TO B0) 0000 1111 ... 0000 1111 COLOUR ENTRY 0 1 ... 14 15 TXT: The foreground colour is selected via a control character (see Fig.33). The colour control characters takes effect at the start of the next character (`set after') and remain valid until the end of a row of a display window, or until modified by a control character. Only eight foreground colours are available. The TEXT foreground control characters map to the CLUT entries, as shown in Table 29. Table 29 Foreground CLUT mapping CONTROL CODE 00H 01H 02H 03H 04H 05H 06H 07H DEFINED COLOUR black red green yellow blue magenta cyan white CLUT ENTRY 0 1 2 3 4 5 6 7 FOREGROUND COLOUR CC: The foreground colour can be chosen from eight colours on a character by character basis. Two sets of eight colours are provided. A serial attribute switches between the banks (see Table 33 Serial Mode 1, bit 7). The colours are the CLUT entries 0 to 7 or 8 to 15. 2001 Dec 13 72 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.4.7 BACKGROUND COLOUR 23.4.9 UNDERLINE SAA56xx CC: This attribute is valid from the time set until the end of a row of a display window, or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then the colour is set from the next character onwards. The background colour can be chosen from all 16 CLUT entries. TXT: The control character `New background' (1DH) is used to change the background colour to the current foreground colour. The selection is immediate (set at) and remains valid until the end of a row of a display window, or until otherwise modified. The TEXT background control characters map to the CLUT entries, as shown in Table 30. Table 30 Background CLUT mapping CONTROL CODE 00H + 1DH 01H + 1DH 02H + 1DH 03H + 1DH 04H + 1DH 05H + 1DH 06H + 1DH 07H + 1DH 23.4.8 DEFINED COLOUR black red green yellow blue magenta cyan white CLUT ENTRY 8 9 10 11 12 13 14 15 The underline attribute causes the characters to have the bottom scan line of the character cell forced to foreground colour, including spaces. If background duration is set, then underline is set until the end of the display window. CC: The underline attribute (see Table 33, bit 4) is valid from the time set until the end of row of a display window, or otherwise modified. TXT: This attribute is not available. 23.4.10 OVERLINE The overline attribute causes the characters to have the top scan line of the character cell forced to foreground colour, including spaces. If background duration is set, then overline is set until the end of the display window. CC: The overline attribute (see Table 33, bit 5) is valid from the time set until the end of a row of a display window, or otherwise modified. Overlining of italic characters is not possible. TXT: This attribute is not available. 23.4.11 END OF ROW CC: The number of characters in a row is flexible and can be determined by the end of row attribute (see Table 33, bit 9). However, the maximum number of character positions displayed is determined by the setting of the MMR Text Area Start or Text Area Start B, and MMR Text Area End or Text Area End B. Note that, when using the end of row attribute, the next character location after the attribute should always be occupied by a `space'. TXT: This attribute is not available, the row length is fixed at 40 characters. BACKGROUND DURATION When set, the attribute takes effect from the current position until the end of the display window. This is defined in the MMR Text Area End in single window mode and in double window mode for Page A, with MMR Text Area End B for Page B. CC: The background duration attribute (see Table 33, bit 8) in combination with the End Of Row attribute (see Table 33, bit 9) forces the background colour to be displayed on the row until the end of the text area is reached. TXT: This attribute is not available. 2001 Dec 13 73 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.4.12 FRINGING A fringe (shadow) can be defined around characters. The fringe direction is individually selectable in any of the North, South, East and West directions using the MMR Fringing Control. The colour of the fringe can also be defined as one of the entries in the CLUT, again using MMR Fringing Control. An example of fringing is shown in Fig.28. SAA56xx CC: The fringe attribute (see Table 33, bit 9) is valid from the time set until the end of a row of a display window, or otherwise modified. TXT: Bit TXT4.SHADOW ENABLE controls the display of fringing in single page mode and in double Page A. Bit TXT26.SHADOW ENABLE B controls the display of fringing for Page B in double window mode. When set, all the alphanumeric characters being displayed are shadowed, graphics characters are not shadowed. handbook, full pagewidth MBK972 Fig.28 South and south-east fringing. 23.4.13 MESHING This attribute affects the background colour being displayed. Alternate pixels are displayed as the background colour or video. The structure is offset by one pixel from scan line to scan line, thus achieving a checker board display of the background colour and video. An example of meshing and meshing/fringing is shown in Fig.29. CC: The setting of the MSH bit in MMR Display Control has the effect of meshing any background colour. TXT: There are two meshing attributes. One only affects black background colours TXT4.B MESH ENABLE in single window mode or in double window mode for Page A, and TXT26.B MESH ENABLE B for Page B. A second only affects backgrounds other than black TXT4.C MESH ENABLE in single window mode or in double window mode for Page A, and TXT26.C MESH ENABLE B for Page B. A black background is defined as CLUT entry 8, a non-black background is defined as CLUT entry 9 to 15. 2001 Dec 13 74 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth MBK973 Fig.29 Meshing and meshing/fringing (south + east). Fig.0 Meshing and meshing/fringing (south + west). 23.4.14 CURSOR The cursor operates by reversing the background (see Fig.30) and foreground colours in the character position pointed to by the current cursor position in the active page. The cursor is enabled using TXT7.CURSOR ON. When set, the row on which the cursor appears is defined by TXT9.R<4:0>; the column is defined by TXT10.C<5:0>. The active page is defined by TXT28.ACTIVE PAGE in double window mode and the displayed window is in single window mode. The position of the cursor can be fixed using TXT9.CURSOR FREEZE. CC: The valid range for row is 0 to 15. The valid range for column is 0 to 47. The cursor remains rectangular at all times, its shape is not affected by italic attribute, therefore it is not advised to use the cursor with italic characters. TXT: The valid range for row positioning is 0 to 24. The valid range for column is 0 to 39. handbook, full pagewidth AB C D E F MBK971 Fig.30 Cursor display. 2001 Dec 13 75 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.4.15 DYNAMICALLY REDEFINABLE CHARACTERS (DRCS) A number of DRCs are available (see Fig.31). These are mapped onto the normal character codes, and replace the predefined Character ROM value. By default there are 32 DRCs occupying the character codes 80H to 8FH. The SAA56xx family of devices offers 32 additional DRCs over the SAA55xx by setting TXT26. The first 16 of them occupy the character codes A0 to AF, the second 16 occupy the character codes C0 to CF. SAA56xx The remapping of the standard OSD to the DRCs is activated when the TXT20.DRCS ENABLE bit for single page mode or for Page A in double window mode, and TXT23.DRCS B ENABLE for Page B in double window mode. Each character is stored in a matrix of 12 x 16 x 1 (V x H x planes), this allows for all possible character matrices to be defined within a single location. handbook, full pagewidth address (HEX) 8800 881F 8820 883F 8840 885F 8BC0 8BDF 8BE0 8BFF CHARACTER 0 CHARACTER 1 CHARACTER 2 character code 80H 81H 82H character 0 address (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F CHARACTER 30 CHARACTER 31 CHARACTER 32 CHARACTER 33 9EH 9FH A0H A1H CHARACTER 46 additional DRCs for TXT26.7 = 1 CHARACTER 47 CHARACTER 48 CHARACTER 49 AEH AFH C0H C1H 12 bits GSA063 CHARACTER 62 CHARACTER 63 CEH CFH The SAA56xx family of devices offers 32 additional DRCs over the SAA55xx by setting TXT26.7. The first 16 of them occupy character codes A0 to AF, the second 16 occupy character codes C0 to CF. Fig.31 Organisation of DRC RAM. 2001 Dec 13 76 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.4.16 DEFINING CHARACTERS The DRC RAM is mapped into the 80C51 RAM address space and starts at location 8800H. The character matrix is 12 bits wide and therefore requires two bytes to be written for each word. The first byte (even addresses), addresses the lower eight bits and the lower nibble of the second byte (odd addresses) addresses the upper four bits. For characters of 9, 10 or 16 lines high, the pixel information starts in the first address and continues sequentially for the required number of addresses. Characters of 13 lines high are defined with an initial offset of one address, to allow for the correct generation of fringing across boundaries of clustered characters (see Fig.32). The characters continue sequentially for 13 lines, after which a further line can again be used for the generation of correct fringing across boundaries of clustered characters. 23.4.17 SPECIAL GRAPHICS CHARACTERS SAA56xx CC/TXT: several special graphics characters (see Fig.33) are provided for improved OSD effects. These characters provide a choice of four colours within a character cell; see Table 31. Each special graphics character uses two consecutive normal characters. Table 31 Special graphics character colour allocation PLANE 1 0 0 1 1 PLANE 0 0 1 0 1 COLOUR ALLOCATION background colour foreground colour CLUT entry 6 CLUT entry 7 By default (for backwards compatibility with the SAA55xx family of devices), there are 16 special graphics characters. They are stored in the character codes 8XH and 9XH of the character table (32 ROM characters), or in the DRCS RAM. The SAA56xx family of devices allow for 32 special graphics characters, if TXT26.EXTENDED DRCS is set. They are stored in character codes 8XH, 9XH, AXH and CXH, or in the DRCs RAM, including the extended location (64 characters). handbook, halfpage top left pixel line number HEX MSB 440 0 003 1 00C 2 030 3 0C0 4 300 5 C00 6 C00 7 300 8 0C0 9 030 10 00C 11 003 12 000 13 1A8 14 000 15 line 13 from character above LSB fringing top line Special graphics characters are activated when the double plane decoding for the special graphics is set by TXT20.OSD PLANES in single window mode or for Page A in double window mode, or by setting TXT29.OSD PLANES B for Page B in double window mode. CC: Additional special graphics characters are allowed in CC OSD mode by enabling the Extended Special Graphics SFR. So when TXT20.5 = 1, any character location can be used as special graphics using bit 14 of its parallel code (see Table 32), extended special graphic attributes. Remark: Fringing, underline, overline and smoothing are not possible for special graphics. If the screen colour is transparent (implicit in mixed mode) and the box attribute is set inside the object, the object is surrounded by video. If the box attribute is not set, the background colour inside the object will also be displayed as transparent. line 1 from character below bottom line fringing line not used bottom right pixel MBK975 Fig.32 13-line high DRCs character format. 2001 Dec 13 77 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth background colour "set at" (Mode 0) serial attribute background colour "set after" (Mode 1) VOLUME background colour foreground colour 7 foreground colour normal character foreground colour 6 special character MGK550 This example could also be done with 8 special characters. Fig.33 Example of a special graphics character. 2001 Dec 13 78 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.4.18 SMOOTHING To improve the appearance of the display, the SAA56xx family of devices incorporates a smoothing algorithm to insert extra pixels for all character sizes other than normal size (see Fig.34). Smoothing is available in both TXT and CC modes. SAA56xx MMR 87E4H bit 4 enables smoothing in single page mode and for Page A in double window mode. MMR 87E4H bit 5 enables smoothing for Page B in double window mode. The appearance of special graphics characters and fringed characters cannot be improved with the smoothing algorithm. handbook, full pagewidth normal size double height smoothing on double size smoothing on double width smoothing on double height smoothing off double size smoothing off double width smoothing off GSA078 Fig.34 Smoothing characters. 2001 Dec 13 79 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.4.19 CONTRAST REDUCTION SAA56xx The coding is done in 15-bit words. The codes are stored sequentially in the Display memory. A maximum of 768 character positions can be defined for a single display. 23.5.2 TXT MODE The device can act on the TV's display circuit to reduce contrast of the video by driving the COR output LOW. Contrast reduction improves the readability of characters in mixed mode. TXT: Bits COR IN in SFRs TXT5 and TXT6 control when the COR output of the device is activated. These bits allow, for example, the display to be set-up so that the areas inside Teletext boxes are contrast reduced when a subtitle is displayed, leaving the rest of the screen displayed as in normal conditions. CC: Here, the contrast reduction is controlled by the contrast reduction attribute (see Table 33). This attribute is valid from the time set until the end of a row of a display window, or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, it is set from the next character onwards. 23.5 Character and attribute coding Character coding is in a serial format, with only one attribute being changed at any single location. The serial attributes take effect either at the position of the attribute (set at), or at the following location (set after). The attribute remains effective until either modified by new serial attributes or until the end of a row of a display window. The default settings at the start of a row are: * Foreground colour white (CLUT address 7) * Background colour black (CLUT address 8) * Horizontal size x1, vertical size x1 (normal size) * Alphanumeric on * Contiguous Mosaic Graphics * Release Mosaics * Flash off * Box off * Conceal off * Twist off. The attributes have individual codes which are defined in the basic character table (see Fig.35). 23.5.3 PARALLEL CHARACTER CODING This section describes the character and attribute coding for each mode. 23.5.1 CC MODE Character coding is split into character oriented attributes (parallel, see Table 32) and character group coding (serial, see Table 33). The serial attributes take effect either at the position of the attribute (set at), or at the following location (set after) and remain effective until either modified by a new serial attribute or until the end of a row of a display window. A serial attribute is represented as a space (the space character itself however is not used for this purpose). The attributes that are still active, e.g. overline and underline, are visible during the display of the space. The default setting at the start of a row is: * 1x size * Flash off * Overline off * Underline off * Italics off * Display mode = superimpose * Fringing off * Background colour duration = 0 * End of row = 0. Table 32 Parallel character coding BITS 0 to 7 8 to 10 11 14 DESCRIPTION 8-bit character code three bits for eight foreground colours mode bit: 0 = parallel code special graphics; see Section 23.4.17 12 to 13 character set selection; see Section 23.11.2 2001 Dec 13 80 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.5.4 SERIAL CHARACTER CODING SAA56xx Table 33 Serial character coding DESCRIPTION BITS SERIAL MODE 0 (`SET AT') CHAR.POS. 1 (`SET AT') 0 to 3 4 bits for 16 background colours 4 Underline switch: 0 = Underline off 1 = Underline on 5 Overline switch: 0 = Overline off 1 = Overline on 6 Display mode: 0 = Superimpose 1 = Boxing 7 Flash switch: 0 = Flash off 1 = Flash on 8 Italic switch: 0 = Italics off 1 = Italics on 9 Fringing switch: 0 = Fringing off 1 = Fringing on 10 Switch for serial coding: 0 = Mode 0 1 = Mode 1 11 12 Mode bit: 1 = serial code Contrast switch: 0 = contrast reduction off 1 = contrast reduction on 4 bits for 16 background colours Horizontal size: 0 = normal 1 = x2 Vertical size: 0 = normal 1 = x2 Display mode: 0 = Superimpose 1 = Boxing Foreground colour switch: 0 = Bank 0 (colours 0 to 7) 1 = Bank 1 (colours 8 to 15) Background colour duration: 0 = stop BGC 1 = set BGC to end of row End of Row 0 = Continue Row 1 = End Row: Switch for serial coding: 0 = Mode 0 1 = Mode 1 Mode bit: 1 = serial code Contrast switch: 0 = contrast reduction off 1 = contrast reduction on CHAR.POS. >1 (`SET AFTER') 4 bits for 16 background colours Underline switch: 0 = Underline off 1 = Underline on Overline switch: 0 = Overline off 1 = Overline on Display mode: 0 = Superimpose 1 = Boxing Foreground colour switch: 0 = Bank 0 (colours 0 to 7) 1 = Bank 1 (colours 8 to 15) Background colour duration (set at): 0 = stop BGC 1 = set BGC to end of row End of Row (set at): 0 = Continue Row 1 = End Row Switch for serial coding: 0 = Mode 0 1 = Mode 1 Mode bit: 1 = serial code Contrast switch: 0 = contrast reduction off 1 = contrast reduction on SERIAL MODE 1 2001 Dec 13 81 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Dec 13 82 1 0 0 0 8 flash conceal display OSD OSD OSD OSD 1 0 0 1 9 steady contiguous graphics separated graphics OSD OSD OSD OSD 1 0 1 0 A end box OSD OSD OSD OSD 1 0 1 1 B start box twist nat opt nat opt OSD OSD OSD OSD normal size OSD double height OSD double width OSD double size OSD 1 1 0 0 C normal height double height black back ground new back ground hold graphics release graphics nat opt nat opt OSD OSD OSD OSD 1 1 0 1 D nat opt nat opt nat opt nat opt OSD OSD OSD OSD 1 1 1 0 E double width double size OSD OSD OSD OSD Philips Semiconductors E/W = 0 B I T S b7 b6 b5 b4 b3 b2 b1 b0 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 0 1 0 2a 3 0 0 1 1 3a 4 nat opt 0 1 0 0 5 0 1 0 1 6 nat opt 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 8a 9 1 0 0 1 9a A 1 0 1 0 B background black back ground red background green background yellow background blue background magenta background cyan background white 1 0 1 1 C 1 1 0 0 D 1 1 0 1 E 1 1 1 0 F 1 1 1 1 D 1 1 0 1 E/W = 1 1 1 1 0 E F 1 1 1 1 Enhanced TV microcontrollers with On-Screen Display (OSD) alpha black alpha red OSD OSD OSD OSD 0 0 0 1 1 OSD OSD OSD OSD 0 0 1 0 2 alpha green alpha yellow OSD OSD OSD OSD 0 0 1 1 3 graphics yellow nat opt OSD OSD OSD OSD 0 1 0 0 4 alpha blue alpha magenta graphics blue graphics magenta nat opt OSD OSD OSD OSD 0 1 0 1 5 OSD OSD OSD OSD 0 1 1 0 6 alpha cyan alpha white graphics cyan graphics white OSD OSD OSD OSD 0 1 1 1 7 OSD OSD OSD OSD handbook, full pagewidth Product specification 1 1 1 1 F nat opt OSD OSD OSD OSD SAA56xx GSA089 nat opt OSD character dependent on the language of page, refer to National Option characters customer definable On-Screen Display character Fig.35 TXT basic character set (Pan-European). Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.6 Screen and global controls SAA56xx TXT: The display mode is controlled by the bits in TXT5 and TXT6 in single window mode or for Page A in double window mode, and by the bits in bytes TXT24 and TXT25 in Page B in double window mode. There are three control functions: Text on, Background on and Picture on (see Table 35). Separate sets of bits are used inside and outside Teletext boxes so that different display modes can be invoked. Bit(s) TXT6 and/or TXT25 are used if the newsflash (C5) or subtitle (C6) bits in row 25 of the basic page memory are set; otherwise, byte TXT5 and/or TXT24 is/are used. This allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, TV picture outside). This will be invoked without any further software intervention when such a page is acquired. When Teletext box control characters are present in the display page memory, the appropriate Box control bit must be set, TXT A number of attributes are available that affect the whole display region of a display window, and cannot be applied selectively to regions of the display. 23.6.1 TV SCAN LINES PER ROW The number of TV scan lines per field used for each display row can be defined, the value is independent of the character size being used. The number of lines can be 10, 13 or 16 per display row. The number of TV scan lines per row is defined by TXT21.DISP LINES<1:0>. A value of nine lines per row can be achieved if the display is forced into 525-line display mode by TXT17.FORCE DISP<1:0>, or if the device is in 10-line mode and the automatic detection circuit within display finds 525-line display syncs. The number of TV lines per row is then set for both the display windows in double window mode. 23.6.2 CHARACTER MATRIX (H x V) There are three different character matrices available: 12 x 10, 12 x 13 and 12 x 16. The selection is made using TXT21.CHAR SIZE<1:0> and is independent of the number of display lines per row. If the character matrix is less than the number of TV scan lines per row, the matrix is padded with blank lines. If the character matrix is greater than the number of TV scan lines, the character is truncated. The character matrix is set for all display windows. 23.6.3 DISPLAY MODES CC: When the superimpose or boxing attribute (see Table 33, Serial Mode 0/1, bit 6) is set, the resulting display depends on the setting of the following screen control mode bits in the MMR Display Control (see Table 34). Table 34 Selection of display modes MOD1 0 0 1 1 MOD0 0 1 0 1 DISPLAY MODE Video Full Text DESCRIPTION Disables all display activities, sets the RGB to true black and VDS to video. Displays screen colour at all locations not covered by character foreground or background colour. The box attribute has no effect. Mixed Screen Colour Displays screen colour at all locations not covered by character foreground, within boxed areas or, background colour. Mixed Video Displays video at all locations not covered by character foreground, within boxed areas or, background colour. 2001 Dec 13 83 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) Table 35 TXT display control bits PICTURE ON 0 0 0 1 1 1 23.7 Screen colour TEXT ON 0 1 1 0 1 1 BACKGROUND ON X 0 1 X 0 1 23.8.2 EFFECT Text mode, black screen SAA56xx Text mode, background always black Text mode Video mode Mixed text and TV mode Text mode, TV picture outside text area DISPLAY MAP Screen colour is displayed from 10.5 to 62.5 ms after the active edge of the HSYNC input, on TV lines 23 to 310 inclusive for a 625-line display, and on TV lines 17 to 260 inclusive for a 525-line display. CC: The screen colour is defined by the MMR Display Control and points to a location in the CLUT table. The screen colour covers the full video width. It is visible when the Full Text or Mixed Screen Colour mode is set and no foreground or background pixels are being displayed. TXT: Register bits TXT17.SCREEN COL<2:0> can be used to define a colour to be displayed instead of TV picture and the black background colour. If the bits are all set to zero, the screen colour is defined as `transparent', and TV picture and background colour are displayed as normal. Otherwise, the bits define CLUT entries 9 to 15. In double window mode, TXT17.SCREEN COL<2:0> applies to Text Area A and TXT27.SCRB<2:0> applies to Text Area B. 23.8 23.8.1 Text display controls TEXT DISPLAY CONFIGURATION (CC MODE) The display map (see Fig.36) allows a flexible allocation of data in the memory to individual rows. Sixteen words are provided in the Display memory for this purpose. The lower ten bits address the first word in the memory where the row data starts. This value is an offset in terms of 16-bit words from the start of Display memory (8000H). The most significant bit enables the display when not within the scroll (dynamic) area (see Table 36). The display memory map is fixed at the first 16 words in the Closed Caption Display memory. Table 36 Display map bit allocation BIT 11 10 9 to 0 FUNCTION Text display enable, valid outside Soft Scroll Area. 0 = disable; 1 = enable. This bit is reserved, should be set to logic 0. Pointer to row data. Two types of areas are possible. The one area is static and the other is dynamic. The dynamic area allows scrolling of a region to take place. The areas cannot cross each other. Only one scroll region is possible. 2001 Dec 13 84 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx Display memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Text area display possible ROW 0 1 2 3 4 10 11 3 4 9 10 11 12 13 14 15 display map entries Enable bit = 0 soft scrolling display possible display possible MBK966 display data Fig.36 Display memory map and data pointers. 23.9 Soft scroll action The MMR Scroll Area, MMR Scroll Range, MMR Top Scroll line and the MMR Status define the dynamic scroll region. The soft scroll area (see Fig.37) is enabled when the SCON bit is set in MMR Status. Fig.38 shows the CC text areas and Fig.39 shows the TXT areas. Bits SSP<3:0> define the position of the soft scroll area window and bits SSH<3:0> define the height of the window. Both are in MMR Scroll Range. Bits STS<3:0> and bits SPS<3:0> define the rows that are scrolled through the window. Both are in MMR Scroll Area. Soft scrolling is done by modifying the Scroll Line value SCL<3:0> in MMR Top Scroll Line and the first Scroll Row value SCR<3:0> in the MMR Status. 2001 Dec 13 85 If the number of rows allocated to the scroll counter is larger than the defined visible scroll area, parts of rows at the top and bottom may be displayed during the scroll function. The registers can be written throughout the field and the values are updated for display with the next field sync. Care should be taken that the register pairs are written to by the software in the same field. Only a region that contains only single height rows or only double height rows can be scrolled. TXT: The display is organised as a fixed size of 25 rows (0 to 24) of 40 columns (0 to 39), This is the standard size for Teletext transmissions. The Control Data in row 25 is not displayed but is used to configure the display page correctly. Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth soft scroll position pointer SSP<3:0> e.g. 6 soft scroll height SSH<3:0> e.g. 4 ROW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usable for OSD display should not be used for OSD display start scroll row STS<3:0> e.g. 3 soft scrolling area should not be used for OSD display usable for OSD display start scroll row SPS<3:0> e.g. 11 MBK967 Fig.37 Soft scroll area. handbook, full pagewidth ROW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 row0 0-63 lines row1 P01 NBC scroll area offset row2 row3 row4 row5 row6 row7 row8 Closed Captioning data row n Closed Captioning data row n+1 Closed Captioning data row n+2 Closed Captioning data row n+3 Closed Captioning data row n+4 row13 row14 visible area for scrolling MBK977 Fig.38 CC text areas. 2001 Dec 13 86 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 control data 9 10 23 39 non-displayable data byte 10 reserved MBK968 Fig.39 TXT text area. 2001 Dec 13 87 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.10 Display positioning 23.10.1 SINGLE WINDOW MODE The display consists of the screen colour covering the whole screen and the text area that is placed within the visible screen area (see Fig.40). SAA56xx The screen colour extends over a large vertical and horizontal range so that no offset is needed. The text area is offset in both directions relative to the vertical and horizontal sync pulses. handbook, full pagewidth horizontal sync screen colour offset = 8 s 6 lines offset text vertical offset SCREEN COLOUR AREA horizontal sync delay TEXT AREA vertical sync 0.25 character offset text area start text area end 56 s MGL150 Fig.40 Display area positioning. 2001 Dec 13 88 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.10.2 DOUBLE WINDOW MODE The display (see Fig.41) consists of the two screen colours covering each half of the screen and two text areas that are placed within the visible screen area. The screen colour extends over a large vertical and horizontal range so that no offset is needed. Both text areas are offset in both directions relative to the vertical and horizontal sync pulses. SAA56xx The second page may be positioned relative to the HSYNC delay using the Page B Position MMR. The visible text area for Page A is controlled using the Text Area Start and Text Area End MMRs. Page B visible text area is controlled using the Text Area Start B and Text Area End B MMRs. handbook, full pagewidth horizontal sync screen colour offset = 8 s 6 lines offset SCREEN COLOUR AREA horizontal sync delay text vertical offset vertical sync TEXT AREA A TEXT AREA B 0.25 character offset text area start A text area end A Page B start 0.25 character offset min. 2 characters spaces 56 s text area start B text area end B GSA079 Fig.41 Page positioning. 2001 Dec 13 89 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.10.3 SCREEN COLOUR DISPLAY AREA This area is covered by the screen colour, and starts with a fixed offset of 8 s from the leading edge of the horizontal sync pulse in the horizontal direction. A vertical offset is not necessary. For a summary, see the following: Horizontal: Start at 8 s after leading edge of horizontal sync for 56 s. Vertical: Line 9, field 1 (321, field 2) to leading edge of vertical sync (line numbering using 625 Standard). 23.10.4 TEXT DISPLAY AREA (SINGLE PAGE) The text area can be defined to start with an offset in both the horizontal and vertical directions. For a summary, see following: Horizontal: Up to 48 full-sized characters per row. Start position setting from 3 to 64 characters relative to HSYNC delay. Fine adjustment in quarter characters. Vertical: 256 Lines (nominal 41 to 297). Start position setting from leading edge of vertical sync, legal values are 4 to 64 lines (line numbering using 625 Standard). The horizontal offset is set in MMR Text Area Start. The offset is done in full-width characters using TAS<5:0>, with quarter characters using HOP<1:0> for fine setting. Values 00H to 03H for TAS<5:0> result in a corrupted display. The width of the text area is defined in the Text Area End Register by setting the end character value TAE<5:0>. This number determines where the background colour of the text area will end if set to extend to the end of the row. It will also terminate the character fetch process, thus eliminating the necessity of a row end attribute. However, this entails writing to all positions. The vertical offset is set in the Text Position Vertical Register. The offset value VOL<5:0> is done in number of TV scan lines. Note that the Text Position Vertical Register should not be set to 00H as the Display Busy interrupt is not generated in these circumstances. 23.10.5 TEXT DISPLAY AREA (TWO_PAGE) Control of Page A in two page mode is as per the control in single page mode. Three extra memory mapped registers control the position of the second page: the Text Area Start B, Text Area End B and the Page B Position Register. SAA56xx Page B positioning register controls the positioning of Text Area B relative to HSYNC delay. A minimum two character gap should be allowed between each page to allow the reset of attributes. The vertical offset must be the same for both pages, i.e. RANGE<1:0> and VOL<5:0> = RANGEB<1:0> and VOLB<5:0> in Text Position Vertical and Vertical Range Registers (MMR 87F1H, MMR 87E3H and MMR 87E4H). The text area can be defined to start with an offset in the horizontal direction, as follows: * Up to 48 full-sized characters per row. Start position setting from 3 to 64 characters relative to value in Page B position register. Fine adjustment in quarter characters. * The horizontal offset is set in the Text Area Start Register. The offset is done in full-width characters using TAS B<5:0>, with quarter characters using HOP B<1:0> for fine setting. * The width of the text area is defined in the Text Area End Register by setting the end character value TAE B<5:0>. This number determines where the background colour of the Text Area B will end if set to extend to the end of the row. It will also terminate the character fetch process thus eliminating the necessity of a row end attribute. However, this entails writing to all positions. 23.11 Character set To facilitate the global nature of the device, the character set can accommodate a large number of characters, which can be stored in different matrices. 23.11.1 CHARACTER MATRICES The character matrices that can be accommodated in both display modes are: (H x V x planes) 12 x 9 x 1, 12 x 10 x 1, 12 x 13 x 1 and 12 x 16 x 1. These modes allow two colours per character position. In CC mode, two additional character matrices are available to allow four colours per character: (H x V x planes) 12 x 13 x 2 and 12 x 16 x 2. The characters are stored physically in ROM in a 12 x 10 or 12 x 16 matrix. 2001 Dec 13 90 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 23.11.2 CHARACTER SET SELECTION Four character sets are available in the device. A set can consist of alphanumeric characters, as required by the WST Teletext or FCC Closed Captioning, Customer definable OSD characters, and Special Graphic characters. CC: Within a Closed Caption information transmission, only one character set can be used for display. This is selected using the Basic Set selection TXT18.BS<1:0> in single window mode and for Page A in double window mode, and TXT23.BS B<1:0> for Page B in double window mode. When selecting a character set in CC mode, the Twist Set selection TXT19.TS<1:0> should be set to the same value as TXT18.BS<1:0> for correct operation. TXT: Two character sets can be displayed at once. These are the basic G0 set or the alternative G0 set (Twist Set). The basic set is selected using TXT18.BS<1:0> in single window mode or for Page A in double window mode, and TXT23.BS B<1:0> for Page B in double window mode. The alternative character set is defined by TXT19.TS<1:0> in single window mode for Page A in double window mode, and TXT29.TS B<6:5> for Page B in double window mode. Since the alternative character set is an option, it can be enabled or disabled using TXT19.TEN for TXT19.TS<1:0> and by TXT29.TEN B for TXT29.TS B<6:5>. Also, the language code that is defined for the alternative set is defined by TXT19.TC<2:0> for TXT19.TS<1:0> and by TXT30.TC B<7:6> for TXT29.TS B<6:5>. The National Option Table is selected using TXT18.NOT<3:0>. A maximum of 31 National Option Tables can be defined when combined with the EAST/WEST control bit located in register TXT4. In CC OSD mode, characters from the four character sets can be displayed on the screen at the same time, providing that all four of the character sets are of the same matrix. This is done using bits 12 to 13 of the parallel code of the character (see Table 37). Table 37 Character set bits coding BITS <13:12> 00 01 10 11 CHARACTER SET set 0 set 1 set 2 set 3 23.12 RGB brightness control SAA56xx A brightness control is provided to adjust the RGB upper output voltage level. The nominal value is 1 V into a 150 resistor, but can be varied between 0.7 and 1.2 V. The brightness is set in the RGB Brightness Register, see Table 38. Table 38 RGB brightness BRI3 TO BRI0 0000 ... 1111 ... highest value RGB BRIGHTNESS lowest value 24 MEMORY MAPPED REGISTERS (MMRs) The memory mapped registers are used to control the display as for the SAA55xx. Some additional MMRs are used for the SAA56xx; see Tables 39 to 41. Table 39 MMR address summary REGISTER NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MEMORY ADDRESS 87F0H 87F1H 87F2H 87F3H 87F4H 87F5H 87F6H 87F7H 87F8H 87F9H 87FAH 87FBH 87FCH 87FDH 87FEH 87FFH 87E0H 87E1H 87E2H 87E3H 87E4H FUNCTION Display Control Text Position Vertical Text Area Start Fringing Control Text Area End Scroll Area Scroll Range RGB Brightness Status Reserved Reserved Reserved HSYNC Delay VSYNC Delay Top Scroll Line Configuration Text Area Start B Text Area End B Page B Position Text Position Vertical B Vertical Range 2001 Dec 13 91 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 40 MMR map 2001 Dec 13 92 Philips Semiconductors Enhanced TV microcontrollers with On-Screen Display (OSD) ADDRESS R/W 87F0H 87F1H 87F2H 87F3H 87F4H 87F5H 87F6H 87F7H 87F8H 87FCH 87FDH 87FEH 87FFH 87E0H 87E1H 87E2H 87E3H 87E4H NAME 7 SRC3 VPOL HOP1 FRC3 - SSH3 SPS3 VDSPOL BUSY - - - - CC HOPB1 - PGB7 - - 6 SRC2 HPOL HOP0 FRC2 - SSH2 SPS2 - FIELD - HSD6 VSD6 - VDEL2 HOPB0 - PGB6 - - 5 SRC1 VOL5 TAS5 FRC1 TAE5 SSH1 SPS1 - SCON SCON HSD5 VSD5 - VDEL1 TASB5 TAEB5 PGB5 VOLB5 4 SRC0 VOL4 TAS4 FRC0 TAE4 SSH0 SPS0 - FLR FLR HSD4 VSD4 - VDEL0 TASB4 TAEB4 PGB4 VOLB4 - 3 VOL3 TAS3 FRDN TAE3 SSP3 STS3 BRI3 SCR3 SCR3 HSD3 VSD3 SCL3 TXT/V TASB3 TAEB3 PGB3 VOLB3 RANGE1 2 MSH VOL2 TAS2 FRDE TAE2 SSP2 STS2 BRI2 SCR2 SCR2 HSD3 VSD2 SCL2 - TASB2 TAEB2 PGB2 VOLB2 RANGE0 1 MOD1 VOL1 TAS1 FRDS TAE1 SSP1 STS1 BRI1 SCR1 SCR1 HSD1 VSD1 SCL1 100 Hz TASB1 TAEB1 PGB1 VOLB1 0 MOD0 VOL0 TAS0 FRDW TAE0 SSP0 STS0 BRI0 SCR0 SCR0 HSD0 VSD0 SCL0 Two_Page TASB0 TAEB0 PGB0 VOLB0 RESET 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H R/W Display Control R/W Text Position Vertical R/W Text Area Start R/W Fringing Control R/W Text Area End R/W Scroll Area R/W Scroll Range R/W RGB Brightness R W R/W HSYNC Delay R/W VSYNC Delay R/W Top Scroll Line R/W Configuration R/W Text Area Start B R/W Text Area End B R/W Page B Position R/W Text Position Vertical B R/W Vertical Range Status SMTHB SMTH RANGEB1 RANGEB0 00H Product specification SAA56xx Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) Table 41 MMR bit definition REGISTER Display Control SRC3 to SRC0 MSH MOD2 to MOD0 screen colour definition meshing all background colours (logic 1) 00 = Video 01 = Full Text 10 = Mixed Screen Colour 11 = Mixed Video Text Position Vertical VPOL HPOL VOL5 to VOL0 Text Area Start HOP1 to HOP0 TAS5 to TAS0 Fringing Control FRC3 to FRC0 FRDN FRDE FRDS FRDW Text Area End TAE5 to TAE0 Scroll Area SSH3 to SSH0 SSP3 to SSP0 Scroll Range SPS3 to SPS0 STS3 to STS0 RGB Brightness VDSPOL VDS polarity 0 = RGB (1), Video (0) 1 = RGB (0), Video (1) BRI3 to BRI0 RGB brightness control stop scroll row start scroll row soft scroll height soft scroll position fringing colour, value address of CLUT fringe in north direction (logic 1) fringe in east direction (logic 1) fringe in south direction (logic 1) fringe in west direction (logic 1) inverted input polarity (logic 1) inverted input polarity (logic 1) display start vertical offset from VSYNC (lines) FUNCTION SAA56xx fine horizontal offset in quarter of characters, in single page mode or for Page A in double window mode text area start, in single page mode or for Page A in double window mode text area end, in full characters, in single page mode or for Page A in double window mode 2001 Dec 13 93 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) REGISTER Status read BUSY FIELD FLR SCR3 to SCR0 Status write SCON FLR SCR3 to SCR0 HSYNC Delay HSD6 to HSD0 VSYNC Delay VSD6 to VSD0 Top Scroll Line SCL3 to SCL0 Configuration CC VDEL2 to VDEL0 Closed Caption mode (logic 1) pixel delay between VDS and RGB output 000 = VDS switched to video, not active 001 = VDS active one pixel earlier then RGB 010 = VDS synchronous to RGB 100 = VDS active one pixel after RGB TXT/V 100 Hz Two_Page Text Area Start B HOP1 to HOP0 TAS5 to TAS0 Text Area End B TAE5 to TAE0 Page B Position PGB7 to PGB0 Text Position Vertical B VOLB5 to VOLB0 Vertical Range SMTHB smoothing on, on Page B (logic 1) Page B position text area end, in full characters fine horizontal offset in quarter of characters text area start BUSY signal switch; horizontal (logic 1) 100 Hz mode select; 100Hz/120Hz timing mode (logic 1) two page mode select; dual page (logic 1) top line for scroll VSYNC delay in number of 8-bit 12 MHz clock cycles HSYNC delay, in full size characters scroll area enabled (logic 1) active flash region background colour only displayed (logic 1) first scroll row access to Display memory could cause display problems (logic 1) even field (logic 1) active flash region background only displayed (logic 1) first scroll row FUNCTION SAA56xx Page B display start vertical offset from VSYNC (lines) should equal VOL5 to VOL0 in double window mode (MMR 87F1H<5:0>) 2001 Dec 13 94 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) REGISTER SMTH RANGE1 to RANGE0 RANGEB1 to RANGEB0 smoothing on, on Page A (logic 1) additional two bits for display vertical offset additional two bits for display vertical offset on Page B FUNCTION SAA56xx 25 IN-SYSTEM PROGRAMMING INTERFACE A serial programming interface is available for late OTP programming. The interface is based on the IEEE1149 (JTAG) standard, but only two instructions are utilized. Table 42 shows which port pins are used for ISP. Care should be taken during system design to ensure the pins used for serial programming do not cause conflict with the application circuit. It is advised to dedicate the port pins (P2.1, P2.2, P2.3 and P2.4) to ISP, and not use them in application. Table 42 Port pins used for ISP PIN P2.0 P2.1 P2.2 P2.3 P2.4 VPE RESET XTALIN NAME EN TCK TMS TDI TDO VPE RESET CLK Test clock Test Mode Select Test Data In Test Data Out However, if it is necessary to use them in application then they must be assigned as output. The device is placed in ISP mode using the RESET pin. Pin P0.2 must be held HIGH during ISP mode. Power to the device during ISP may be sourced either from the application or from an external source. Ground reference between the programmer and the target should be common. For further details, refer to the "In-System Programming Application Note SPG/AN01008". FUNCTION Enables JTAG operations (specific to SAA56xx) 9 V Programming Voltage Device reset/mode selection Device reset/mode selection Clock 12 MHz RESET (alternative) RESET 26 LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 60134). SYMBOL VDDX VI VO IO IIOK Tj Tstg Note 1. For 5 V tolerant I/Os, the maximum value may be 6 V only when VDD is present. PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) DC input or output diode current operating junction temperature storage temperature note 1 CONDITIONS MIN. -0.5 -0.5 -0.5 - - -20 -55 +4.0 VDD + 0.5 10 20 +125 +125 MAX. UNIT V V mA mA C C (VDD + 0.5) or 4.1 V 2001 Dec 13 95 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 27 THERMAL CHARACTERISTICS SYMBOL Tres(j-a) Tres(j-c) PARAMETER package thermal resistance from junction to ambient package thermal resistance from junction to case CONDITIONS in free air SAA56xx VALUE 52 8 UNIT 0C/W 0C/W 28 CHARACTERISTICS VDD = 3.3 V 10%; VSS = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDDX IDDP IDDC IDDC(id) IDDC(pd) IDDA IDDA(id) IDDA(pd) any supply voltage (VDD to VSS) periphery supply current core supply current Idle mode core supply current Power-down mode core supply current analog supply current Idle mode analog supply current Power-down mode analog supply current note 1 3.0 1 - - - - - - 3.3 - 15 4.6 0.76 45 0.87 0.45 3.6 - 18 6 1 48 1 0.7 V mA mA mA mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital inputs RESET VIL VIH Vhys ILI Rpd VIL VIH Vhys ILI Rpu VIL VIH Vhys ILI LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current equivalent pull-down resistance VI = 0 VI = VDD - 1.85 0.44 - 55.73 - 1.73 0.41 VI = VDD VI = 0 - 46.07 - 1.80 0.40 VI = 0 to VDD - - - - - 70.71 - - - - 55.94 - - - - 1.00 5.5 0.58 0.17 92.45 V V V A k RESET, EA, INTD LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current equivalent pull-up resistance 0.98 5.5 0.5 0.00 70.01 V V V A k HSYNC, VSYNC LOW-level input voltage HIGH-level input voltage hysteresis of Schmitt trigger input input leakage current 0.96 5.5 0.56 0.00 V V V A 2001 Dec 13 96 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SYMBOL Digital outputs PARAMETER CONDITIONS MIN. TYP. SAA56xx MAX. UNIT FRAME, VDS, RD, WR, PSEN, ALE, A0 TO A7, A16, A17, MOVX_WR, MOVX_RD, A15_BK, ROMBK0 TO ROMBK2, RAMBK0, RAMBK1 (PUSH-PULL OUTPUTS) VOL VOH tr tf LOW-level output voltage HIGH-level output voltage output rise time output fall time IOL = 3 mA IOH = 3 mA 10% to 90% of VDD, CL = 70 pF 10% to 90% of VDD, CL = 70 pF IOL = 3 mA IOL = -3 mA; push-pull VI = 0 to VDD 10% to 90% of VDD, CL = 70 pF 10% to 90% of VDD, CL = 70 pF - 2.84 7.50 6.70 - - 8.85 7.97 0.13 - 10.90 10.00 V V ns ns COR (OPEN-DRAIN OUTPUT), A8 TO A15 (PUSH-PULL OUTPUTS) VOL VOH ILI tr tf LOW-level output voltage HIGH-level pull-up output voltage input leakage current output rise time output fall time - 2.84 - 7.20 4.90 - - - 8.64 7.34 0.14 - 0.12 11.10 9.40 V V A ns ns Digital input/outputs P0.0 TO P0.4, P0.7, P1.0 TO P1.1, P2.1 TO P2.7, P3.0 TO P3.7 VIL VIH Vhys ILI VOL VOH tr tf LOW-level input voltage HIGH-level input voltage hysteresis of Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time output fall time VI = 0 to VDD IOL = 4 mA IOH = -4 mA push-pull 10% to 90% of VDD, CL = 70 pF push-pull 10% to 90% of VDD, CL = 70 pF - 1.78 0.41 - - 2.81 6.50 5.70 - - - - - - 8.47 7.56 0.98 5.50 0.55 0.01 0.18 - 10.70 10.00 V V V A V V ns ns P1.2, P1.3 AND P2.0 VIL VIH Vhys ILI VOL VOH tr tf LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time output fall time VI = 0 to VDD IOL = 4 mA IOH = -4 mA push-pull 10% to 90% of VDD; CL = 70 pF push-pull 10% to 90% of VDD; CL = 70 pF - 1.80 0.42 - - 2.81 7.00 5.40 - - - - - - 8.47 7.36 0.99 5.50 0.56 0.02 0.17 - 10.50 9.30 V V V A V V ns ns 2001 Dec 13 97 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SYMBOL P0.5 AND P0.6 VIL VIH ILI Vhys VOL VOH tr tf LOW-level input voltage HIGH-level input voltage input leakage current hysteresis voltage of Schmitt trigger input LOW-level output voltage HIGH-level output voltage output rise time output fall time IOL = 8 mA IOH = -8 mA push-pull 10% to 90% of VDD; CL = 70 pF push-pull 10% to 90% of VDD; CL = 70 pF VI = 0 to VDD - 1.82 - 0.42 - 2.76 7.40 4.20 - - - - - - 8.22 4.57 PARAMETER CONDITIONS MIN. TYP. SAA56xx MAX. UNIT 0.98 5.50 0.11 0.58 0.20 - 8.80 5.20 V V A V V V ns ns P1.4 TO P1.7 (OPEN-DRAIN) VIL VIH Vhys ILI VOL tf tf(I2C) LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage output fall time output fall time in relation to the I2C-bus specifications VI = 0 to VDD IOL = 8 mA 10% to 90% of VDD; CL = 70 pF 3 V to 1.5 V at IOL = 3 mA CL = 400 nF - 1.99 0.49 - - 69.70 - - - - - - 83.67 57.80 1.08 5.50 0.60 0.13 0.35 103.30 - V V V A V ns ns AD0 TO AD7 (QUASI-BIDIRECTIONAL) VIL VIH Vhys ILI VOL VOH tr tf LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time output fall time VI = 0, VDD/2, VDD IOL = 3 mA IOL = -3 mA; push-pull 10% to 90% of VDD; CL = 70 pF 10% to 90% of VDD; CL = 70 pF - 1.82 0.40 - - 2.84 7.20 4.90 - - - - - - 8.64 7.34 0.98 5.50 0.58 0.12 0.14 - 11.10 9.40 V V V A V V ns ns 2001 Dec 13 98 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SYMBOL Analog inputs CVBS0 AND CVBS1 Vsync Vvid(p-p) Zsource VIH CI IREF Rgnd VIH CI VPE VIH HIGH-level input voltage - - 9.0 resistor to ground resistor tolerance 2% - 24 - - - sync voltage amplitude video input voltage amplitude (peak-to-peak value) source impedance HIGH-level input voltage input capacitance 0.1 0.7 0 3.0 - 0.3 1.0 - - - 0.6 1.4 PARAMETER CONDITIONS MIN. TYP. SAA56xx MAX. UNIT V V V pF 250 VDDA + 0.3 10 k ADC0 TO ADC3 HIGH-level input voltage input capacitance input range = VDDP - VTN - - VDDA 10 V pF V Analog outputs R, G AND B IOL IOH output current (black level) output current (maximum Intensity) output current (70% of full intensity) Rload CL tr tf load resistor to VSSA load capacitance output rise time output fall time VDDA = 3.3 V VDDA = 3.3 V, intensity level code = 31 decimal VDDA = 3.3 V, intensity level code = 0 decimal resistor tolerance 5% -10 6.0 4.2 - - 10% to 90% full intensity - 10% to 90% full intensity - - 6.67 4.7 150 - 16.1 14.5 +10 7.3 5.1 - 15 - - A mA mA pF ns ns Analog input/output SYNC_FILTER Csync Vsync storage capacitor to ground sync filter level voltage for nominal sync amplitude - 0.35 100 0.55 - 0.75 nF V Crystal oscillator XTALIN VIL VIH CI XTALOUT CO output capacitance - - 10 pF LOW-level input voltage HIGH-level input voltage input capacitance VSSA - - - - - - VDDA 10 V V pF 2001 Dec 13 99 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SYMBOL PARAMETER CONDITIONS MIN. - - Tamb = 25 C Tamb = 25 C Tamb = 25 C Tamb = 25 C Tamb = 25 C - - - - -20 - - TYP. - 30 20 60 SAA56xx MAX. UNIT Crystal specification; notes 2 and 3 fxtal CL C1 Rr Cosc C0 Txtal Xj Xd Notes 1. Peripheral current is dependent on external components and voltage levels on I/Os. 2. Crystal order number 4322 143 05561. 3. If the 4322 143 05561 crystal is not used, then the formulae in the crystal specification should be used. Where CIO = 7 pF, the mean of the capacitances due to the chip at XTALIN and at XTALOUT. Cext is a value for the mean of the stray capacitances due to the external circuit at XTALIN and XTALOUT. The maximum value for the crystal holder capacitance is to ensure start-up, Cosc may need to be reduced from the initially selected value. 4. Cosc(typ) = 2CL - CIO - Cext 5. C0(max) = 35 - 12(Cosc + CIO + Cext) nominal frequency crystal load capacitance crystal motional capacitance resonance resistance capacitors at XTALIN, XTALOUT crystal holder capacitance temperature range adjustment tolerance drift fundamental mode 12 - - - +25 - - MHz pF fF pF pF C note 4 - note 5 +85 50 x 10-6 100 x 10-6 2001 Dec 13 100 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 29 QUALITY AND RELIABILITY SAA56xx This device will meet Philips Semiconductors General Quality Specification for Integrated Circuits "SNW-FQ-611D". The principal requirements are shown in Tables 43 to 45. 29.1 Lot acceptance Table 43 Acceptance tests per lot TEST Mechanical Electrical Note 1. ppm = fraction of defective devices, in parts per million. 29.2 Reliability Performance cumulative target: <80 ppm cumulative target: <100 ppm REQUIREMENTS(1) Table 44 Reliability tests (by process family) TEST High temperature operating life Humidity life CONDITIONS REQUIREMENTS(1) <500 FPM <1000 FPM <2000 FPM 168 hours at Tj = 150 C temperature, humidity, bias 1000 hours, 85 C, 85% RH (or equivalent test) Temperature cycling performance -65 to 150 C Note 1. FPM = fraction of devices failing at test condition, in Failures Per Million. Table 45 Reliability tests (by device type) TEST ESD and latch-up CONDITIONS REQUIREMENTS ESD Human body model 100 pF, 1.5 k 2000 V ESD Machine model 200 pF, 0 200 V latch-up 100 mA, 1.5 x VDD(max) 2001 Dec 13 101 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... k, full pagewidth 2001 Dec 13 102 30 APPLICATION INFORMATION Philips Semiconductors Enhanced TV microcontrollers with On-Screen Display (OSD) 40 V VDD VDD 47 F VSS VSS VSS P2.0/TPWM VDD 100 nF VSS VDD EA 14 100 93 94 95 96 97 98 1 2 4 5 6 11 16 17 18 22 24 13 28 29 30 31 32 34 35 A0 A1 A2 VSS VSS VDD RC VDD Vtune PH2369 EEPROM SCL PCF8582E SDA VDD VDD 84 83 82 81 80 79 78 76 75 73 71 70 P1.5/SDA1 P1.4/SCL1 P1.7/SDA0 P1.6/SCL0 P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDP RESET XTALOUT XTALIN OSCGND VDDC VSSP VSYNC HSYNC VDS R G B VDDA VDD 150 to TV's display circuits VSS VDD 12 MHz 56 pF 100 nF VDD 47 F VSS field flyback line flyback VDD 10 F VDD IR RECEIVER TV control signals brightness contrast saturation hue volume (L) volume (R) VSS VAFC AV status P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 program+ VSS program- TV control signals VHF-L VHF-H menu UHF VSSC P0.0/RX P0.1/TX P0.2/INT2 P0.3/INT3 P0.4/INT4 SAA56xx (SOT407-1) 69 63 12, 60 55 53 52 48 47 46 45 44 43 21, 42 41 72 RESET minus(-) P0.5 plus(+) VSS VDD 1 k 1 k VSSA VSS CVBS (IF) 100 nF CVBS (SCART) 100 nF CVBS0 CVBS1 SYNC_FILTER IREF 100 nF VSS 24 k P0.6 P0.7/T2 P3.4/PWM7/T2EX COR VPE FRAME VSS VDD VSS VDD Product specification GSA080 SAA56xx VDD Bidirectional ports have been configured as open-drain, output ports have been configured as push-pull. Fig.42 Application diagram. Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 30.1 30.1.1 External SRAM implementation APPLICATION DIAGRAM SAA56xx handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12 RAMBK1 50 A0 49 48 47 46 45 44 43 42 41 40 39 SAA56xx 38 37 36 35 34 33 32 31 30 29 28 27 26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 RAMBK0 A1 A2 A3 A12 A13 A15_BK A4 A5 345 678 A8 A9 A10 A11 A7 OE RD/WR A14 RD WR D7 D6 D5 D4 D3 D2 D1 D0 SRAM A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GSA081 Fig.43 Application diagram for multipage. 2001 Dec 13 103 A6 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 30.1.2 APPLICATION NOTES SAA56xx 30.1.3.1 Symbol explanations Ports AD0 to AD7 of the microcontroller can be connected to pins D0 to D7 of the SRAM in any order. For the addressing, the lower group of address lines (A0 to A8) and the upper group of address lines (A9 to A14, A15_BK, RAMBK0 and RAMBK1) may be connected in any order within the groups, provided that the full 256 kbytes of external SRAM is used. Fig.43 shows the application diagram for multipage. When using an external SRAM smaller than 256 kbytes, the relevant number of bits from the microcontroller address bus should be disconnected, always removing the most significant bits first. For power saving modes, it might be advisable to control the CE pin of the SRAM module(s) using one of the microcontroller ports to de-select the SRAM. 30.1.3 EXTERNAL DATA MEMORY ACCESS Each timing symbol has five characters. The first character is always `t' (time). Depending on their positions, the other characters indicate the name of a signal or the logical status of that signal. The designations are: A = Address C = Clock D = Input data H = Logic level HIGH I = Instruction (program memory contents) L = Logic level LOW, or ALE P = PSEN Q = Output data R = RD signal t = Time V = Valid W = WR signal X = No longer a valid logic level Z = Float Examples: tAVLL = Time for address valid to ALE LOW. tLLPL = Time for ALE to PSEN LOW. Table 46 External data memory access See Figs. 44 and 45. SYMBOL tRLRH tWLWH tRLDV tRHDX tRHDZ tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH Note 1. The external SRAM is intended to be used with the multipage software, therefore only the 12 MHz clock microcontroller timings are provided. PARAMETER RD pulse width WR pulse width Data hold after RD Data float after RD ALE LOW to RD or WR LOW Address valid to WR LOW or RD LOW Data valid to WR LOW Data hold after WR RD LOW to address float RD or WR HIGH to ALE HIGH TYPICAL(1) UNIT 250 250 0 tbd 132 172 89 15 tbd 40 ns ns ns ns ns ns ns ns ns ns ns RD LOW to valid data in 198 2001 Dec 13 104 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) SAA56xx handbook, full pagewidth ALE t WHLH PSEN t LLWL RD t LLAX tAVLL AD<0:7> A0-A7 tAVWL A<0:14>, A15_BK, RAMBK<0:1> GSA082 t RLRH t RLDV t RLAZ t RHDX DATA IN t RHDZ A0-A7 INSTR IN Fig.44 External data memory read cycle. handbook, full pagewidth ALE t WHLH PSEN t LLWL WR t LLAX tAVLL AD<0:7> A0-A7 tAVWL A<0:14>, A15_BK, RAMBK<0:1> GSA083 t WLWH t QVWX DATA OUT t WHQX A0-A7 FROM PCL INSTR IN Fig.45 External data memory write cycle. 2001 Dec 13 105 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 31 EMC GUIDELINES Optimization of circuit return paths and minimization of common mode emission will be assisted by using a double sided printed-circuit board with low inductance ground plane. On a single sided printed-circuit board, a local ground plane under the whole IC should be present, as shown in Fig.46. This should be connected by the widest possible connection back to the PCB ground connection, and bulk electrolytic decoupling capacitor. It should preferably not connect to other grounds on the way and no wire links should be present in this connection. The use of wire links increases ground bounce by introducing inductance into the ground. The supply pins can be decoupled at the pin to the ground plane under the IC. This is easily accomplished using surface mount capacitors, which are more effective than leaded components at high frequency. SAA56xx Using a device socket will unfortunately add to the area and inductance of the external bypass loop. A ferrite bead or inductor with resistive characteristics at high frequencies may be utilised in the supply line close to the decoupling capacitor to provide a high impedance. To prevent pollution by conduction onto the signal lines (which may then radiate), signals connected to the VDD supply via a pull-up resistor should not be connected to the IC side of this ferrite component. Pin OSCGND should be connected only to the crystal load capacitors and not the local or circuit GND. Physical connection distances to associated active devices should be short. Output traces should be routed with close proximity mutually coupled ground return paths. handbook, full pagewidth GND +3.3 V electrolytic decoupling capacitor (2 F) other GND connections VDDC VDDP VDDA VSSP ferrite beads SM decoupling capacitors (10 to 100 nF) under-IC GND plane GND connection note: no wire links under-IC GND plane VSSC VSSA IC MBK979 Fig.46 Power supply connections for EMC. 2001 Dec 13 106 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 32 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SAA56xx SOT407-1 c y X 75 76 51 50 ZE A e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3) A1 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o o 16.25 16.25 15.75 15.75 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 00-01-19 00-02-01 2001 Dec 13 107 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 33 SOLDERING 33.1 Introduction to soldering surface mount packages SAA56xx If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 33.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 33.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 33.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2001 Dec 13 108 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 33.5 Suitability of surface mount IC packages for wave and reflow soldering methods SAA56xx SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 34 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 2001 Dec 13 109 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) 35 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 37 PURCHASE OF PHILIPS I2C COMPONENTS 36 DISCLAIMERS SAA56xx Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Dec 13 110 Philips Semiconductors Product specification Enhanced TV microcontrollers with On-Screen Display (OSD) NOTES SAA56xx 2001 Dec 13 111 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2001 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/03/pp112 Date of release: 2001 Dec 13 Document order number: 9397 750 08998 |
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