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| uPSD3234A, uPSD3234BV uPSD3233B, uPSD3233BV Flash Programmable System Devices with 8032 Microcontroller Core and 64 Kbit SRAM FEATURES SUMMARY FAST 8-BIT 8032 MCU - 40MHz at 5.0V, 24MHz at 3.3V - Core, 12-clocks per instruction DUAL FLASH MEMORIES WITH MEMORY MANAGEMENT - Place either memory into 8032 program address space or data address space - READ-while-WRITE operation for InApplication Programming and EEPROM emulation - Single voltage program and erase - 100K minimum erase cycles, 15-year retention CLOCK, RESET, AND SUPPLY MANAGEMENT - SRAM is Battery Backup capable - Normal, Idle, and Power Down Modes - Power-on and Low Voltage reset supervisor - Programmable Watchdog Timer PROGRAMMABLE LOGIC, GENERAL PURPOSE - 16 macrocells - Implements state machines, glue-logic, and so forth COMMUNICATION INTERFACES - USB v1.1, low-speed 1.5Mbps, 3 endpoints - I2C Master/Slave bus controller - Two UARTs with independent baud rate - Six I/O ports with up to 46 I/O pins - 8032 Address/Data bus available on TQFP80 package - 5 PWM outputs, 8-bit resolution JTAG IN-SYSTEM PROGRAMMING - Program the entire device in as little as 10 seconds Figure 1. Packages TQFP52 (T) 52-lead, Thin, Quad Flat TQFP80 (U) 80-lead, Thin, Qual Flat A/D CONVERTER - Four channels, 8-bit resolution, 10s TIMERS AND INTERRUPTS - Three 8032 standard 16-bit timers - 10 Interrupt sources with two external interrupt pins Single Supply Voltage - 4.5 to 5.5V - 3.0 to 3.6V November 2004 1/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 1. Device Summary Part Number uPSD3233B-40T6 uPSD3233BV-24T6 uPSD3233B-40U6 uPSD3233BV-24U6 UPSD3234A-40T6 UPSD3234A-40U6 uPSD3234BV-24U6 Max 1st 2nd SRAM Clock Flash Flash GPIO (bytes) (MHz) (bytes) (bytes) 40 24 40 24 40 40 24 128K 128K 128K 128K 256K 256K 256K 32K 32K 32K 32K 32K 32K 32K 8K 8K 8K 8K 8K 8K 8K 37 37 46 46 37 46 46 USB No No No No Yes Yes No 8032 Bus No No Yes Yes No Yes Yes VCC (V) 4.5-5.5 3.0-3.6 4.5-5.5 3.0-3.6 4.5-5.5 4.5-5.5 3.0-3.6 Pkg. Temp. TQFP52 -40C to 85C TQFP52 -40C to 85C TQFP80 -40C to 85C TQFP80 -40C to 85C TQFP52 -40C to 85C TQFP80 -40C to 85C TQFP80 -40C to 85C 2/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 52-PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 XRAM-DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Boolean Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Relative Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Machine Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 uPSD3200 HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 External Int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0 and 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USART Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 35 . . . . 35 . . . . 35 . . . . 35 . . . . 35 . . . . 35 . . . . 35 . . . . 36 . . . . 37 . . . . 37 . . . . 39 POWER-SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Power-Down Mode . . . . . Power Control Register. . Idle Mode . . . . . . . . . . . . . Power-Down Mode . . . . . ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 40 . . . . 40 . . . . 41 . . . . 41 I/O PORTS (MCU MODULE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PORT Type and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SUPERVISORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 External Reset . . . . . . . . . . . . . . . Low VDD Voltage Reset . . . . . . . Watchdog Timer Overflow . . . . . USB Reset . . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 46 . . . . 46 . . . . 46 . . . . 46 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Timer 0 and Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Multiprocessor Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PULSE WIDTH MODULATION (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4-channel PWM Unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Programmable Period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Serial Status Register (SxSTA: S1STA, S2STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data Shift Register (SxDAT: S1DAT, S2DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Address Register (SxADR: S1ADR, S2ADR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DDC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Special Function Register for the DDC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Host Type Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 DDC1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DDC2B Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 USB HARDWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV USB related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 External USB Pull-Up Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . 98 PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 99 Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 The Turbo Bit in PSD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 I/O PORTS (PSD MODULE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Ports A and B - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Port C - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Port D - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . 134 Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Functional EMS (Electromagnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Designing Hardened Software To Avoid Noise Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV SUMMARY DESCRIPTION The uPSD323x Series combines a fast 8051based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix including USB, to form an ideal embedded controller. At its core is an industry-standard 8032 MCU operating up to 40MHz. A JTAG serial interface is used for In-System Programming (ISP) in as little as 10 seconds, perfect for manufacturing and lab development. The USB 1.1 low-speed interface has one Control endpoint and two Interrupt endpoints suitable for HID class drivers. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize the 8032 memory structure, offering two independent banks of Flash memory that can be placed at virtually any address within 8032 program or data address space, and easily paged beyond 64K bytes using on-chip programmable decode logic. Figure 2. Block Diagram uPSD323x (3) 16-bit Timer/ Counters (2) External Interrupts 8032 MCU Core Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. General purpose programmable logic (PLD) is included to build an endless variety of glue-logic, saving external logic devices. The PLD is configured using the software development tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge. The uPSD323x also includes supervisor functions such as a programmable watchdog timer and lowvoltage reset. 1st Flash Memory: 128K or 256K Bytes Programmable Decode and Page Logic P3.0:7 I2C 2nd Flash Memory: 32K Bytes SRAM: 8K Bytes UART0 (8) GPIO, Port A (80-pin only) PA0:7 PB0:7 PD1:2 SYSTEM BUS (8) GPIO, Port 3 P1.0:7 (8) GPIO, Port 1 General Purpose Programmable Logic, 16 Macrocells (8) GPIO, Port B (2) GPIO, Port D (4) GPIO, Port C (4) 8-bit ADC PC0:7 UART1 JTAG ISP 8032 Address/Data/Control Bus (80-pin device only) Supervisor: Watchdog and Low-Voltage Reset VCC, VDD, GND, Reset, Crystal In (5) 8-bit PWM MCU Bus P4.0:7 USB+, USB- (8) GPIO, Port 4 USB v1.1 Dedicated Pins AI10429 7/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 3. TQFP52 Connections 41 P1.7/ADC3 40 P1.6/ADC2 44 RESET_ 46 VREF 45 GND 52 PB0 51 PB1 50 PB2 49 PB3 48 PB4 47 PB5 43 PB6 PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 USB-(1) 5 PC4/TERR_ 6 USB+ 7 VCC 8 GND 9 PC3/TSTAT 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13 42 PB7 39 P1.5/ADC1 38 P1.4/ADC0 37 P1.3/TXD1 36 P1.2/RXD1 35 P1.1/T2X 34 P1.0/T2 33 VCC 32 XTAL2 31 XTAL1 30 P3.7/SCL1 29 P3.6/SDA1 28 P3.5/T1 27 P3.4/T0 P4.7/PWM4 14 P4.6/PWM3 15 P4.5/PWM2 16 P4.4/PWM1 17 P4.3/PWM0 18 GND 19 P4.2/DDC VSYNC 20 P4.1/DDC SCL 21 P4.0/DDC SDA 22 P3.0/RXD 23 P3.1/TXD 24 P3.2/EXINT0 25 P3.3/EXINT1 26 AI07423b Note: 1. Pull-up resistor required on pin 5 (2k for 3V devices, 7.5k for 5V devices) for all 52-pin devices, with or without USB function. 8/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 4. TQFP80 Connections 79 P3.2/EXINT0 75 P3.0/RXD0 64 P1.7/ADC3 61 P1.6/ADC2 77 P3.1/TXD0 68 RESET_ 63 PSEN_ 70 VREF 69 GND 72 PB5 71 NC(2) PD2 1 P3.3 /EXINT1 2 PD1/CLKIN 3 ALE 4 PC7 5 JTAG/TDO 6 JTAG/TDI 7 USB-(1) 8 PC4/TERR_ 9 USB+ 10 NC(2) 11 VCC 12 GND 13 PC3/TSTAT 14 PC2/VSTBY 15 JTAG TCK 16 NC(2) 17 P4.7/PWM4 18 P4.6/PWM3 19 JTAG TMS 20 62 WR_ 65 RD_ 80 PB0 78 PB1 76 PB2 74 PB3 73 PB4 67 PB6 66 PB7 60 P1.5/ADC1 59 P1.4/ADC0 58 P1.3/TXD1 57 A11 56 P1.2/RXD1 55 A10 54 P1.1/TX2 53 A9 52 P1.0/T2 51 A8 50 VCC 49 XTAL2 48 XTAL1 47 AD7 46 P3.7/SCL1 45 AD6 44 P3.6/SDA1 43 AD5 42 P3.5/T1 41 AD4 PA7 21 PA6 22 P4.5/PWM2 23 PA5 24 P4.4/PWM1 25 PA4 26 P4.3/PWM0 27 PA3 28 GND 29 P4.2/DDC VSYNC 30 P4.1/DDC SCL 31 PA2 32 P4.0/DDC SDA 33 PA1 34 PA0 35 AD0 36 AD1 37 AD2 38 AD3 39 P3.4/T0 40 AI07424b Note: 1. Pull-up resistor required on pin 8 (2k for 3V devices, 7.5k for 5V devices) for all 82-pin devices, with or without USB function. 2. NC = Not Connected 9/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 2. 80-Pin Package Pin Description Port Pin Signal Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 T2 TX2 RxD1 TxD1 ADC0 ADC1 ADC2 ADC3 A8 A9 A10 A11 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 RxD0 TxD0 EXINT0 EXINT1 T0 T1 SDA1 SCL1 DDC SDA DDC SCL DDC VSYNC PWM0 Function Pin No. In/Out Basic 36 37 38 39 41 43 45 47 52 54 56 58 59 60 61 64 51 53 55 57 75 77 79 2 40 42 44 46 33 31 30 27 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O External Bus Multiplexed Address/Data bus A1/D1 Multiplexed Address/Data bus A0/D0 Multiplexed Address/Data bus A2/D2 Multiplexed Address/Data bus A3/D3 Multiplexed Address/Data bus A4/D4 Multiplexed Address/Data bus A5/D5 Multiplexed Address/Data bus A6/D6 Multiplexed Address/Data bus A7/D7 General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin External Bus, Address A8 External Bus, Address A9 External Bus, Address A10 External Bus, Address A11 General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin 8-bit Pulse Width Modulation output 0 UART Receive UART Transmit Interrupt 0 input / Timer 0 gate control Interrupt 1 input / Timer 1 gate control Counter 0 input Counter 1 input I2C Bus serial data I/O I2C Bus clock I/O Timer 2 Count input Timer 2 Trigger input 2nd UART Receive 2nd UART Transmit ADC Channel 0 input ADC Channel 1 input ADC Channel 2 input ADC Channel 3 input Alternate 10/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Signal Name PWM1 PWM2 PWM3 PWM4 USB- VREF RD_ WR_ PSEN_ ALE RESET_ XTAL1 XTAL2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Function Pin No. In/Out Basic 25 23 19 18 8 70 65 62 63 4 68 48 49 35 34 32 28 26 24 22 21 80 78 76 74 73 72 67 66 I/O I/O I/O I/O I/O O O O O O I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General I/O port pin General I/O port pin General I/O port pin General I/O port pin Pull-up resistor required (2k for 3V devices, 7.5k for 5V devices) Reference Voltage input for ADC READ signal, external bus WRITE signal, external bus PSEN signal, external bus Address Latch signal, external bus Active low RESET input Oscillator input pin for system clock Oscillator output pin for system clock General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin 1. 2. 3. PLD Macro-cell outputs PLD inputs Latched Address Out (A0A7) 1. 2. 3. 4. PLD Macro-cell outputs PLD inputs Latched Address Out (A0A7) Peripheral I/O Mode Alternate 8-bit Pulse Width Modulation output 1 8-bit Pulse Width Modulation output 2 8-bit Pulse Width Modulation output 3 Programmable 8-bit Pulse Width modulation output 4 Port Pin P4.4 P4.5 P4.6 P4.7 11/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Signal Name JTAG TMS JTAG TCK PC2 PC3 PC4 VSTBY TSTAT TERR_ JTAG TDI JTAG TDO PC7 PD1 PD2 Vcc Vcc GND GND GND USB+ NC NC NC CLKIN Function Pin No. 20 16 15 14 9 7 6 5 3 1 12 50 13 29 69 10 11 17 71 In/Out Basic I I I/O I/O I/O I O I/O I/O I/O JTAG pin JTAG pin General I/O port pin General I/O port pin General I/O port pin JTAG pin JTAG pin General I/O port pin General I/O port pin General I/O port pin 1. 2. 1. 2. PLD I/O Clock input to PLD and APD PLD I/O Chip select to PSD Module 1. 2. 3. 4. 5. PLD Macro-cell outputs PLD inputs SRAM stand by voltage input (VSTBY) SRAM battery-on indicator (PC4) JTAG pins are dedicated pins Alternate Port Pin 52-PIN PACKAGE I/O PORT The 52-pin package members of the uPSD323X Devices have the same port pins as those of the 80-pin package except: Port 0 (P0.0-P0.7, external address/data bus AD0-AD7) Port 2 (P2.0-P2.3, external address bus A8A11) Port A (PA0-PA7) Port D (PD2) Bus control signal (RD,WR,PSEN,ALE) Pin 5 requires a pull-up resistor (2k for 3V devices, 7.5k for 5V devices) for all devices, with or without USB function. 12/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV ARCHITECTURE OVERVIEW Memory Organization The uPSD323X Devices's standard 8032 Core has separate 64KB address spaces for Program memory and Data Memory. Program memory is where the 8032 executes instructions from. Data memory is used to hold data variables. Flash memory can be mapped in either program or data space. The Flash memory consists of two flash memory blocks: the main Flash (1 or 2Mbit) and the Secondary Flash (256Kbit). Except during flash memory programming or update, Flash memory can only be read, not written to. A Page Register is used to access memory beyond the 64K bytes address space. Refer to the PSD Module for details on mapping of the Flash memory. Figure 5. Memory Map and Address Space MAIN FLASH EXT. RAM The 8032 core has two types of data memory (internal and external) that can be read and written. The internal SRAM consists of 256 bytes, and includes the stack area. The SFR (Special Function Registers) occupies the upper 128 bytes of the internal SRAM, the registers can be accessed by Direct addressing only. There are two separate blocks of external SRAM inside the uPSD323X Devices: one 256 bytes block is assigned for DDC data storage. Another 8K bytes resides in the PSD Module that can be mapped to any address space defined by the user. INT. RAM FF SECONDARY FLASH 128KB OR 7F 32KB 256KB Indirect or Direct Addressing Indirect Addressing SFR FFFF Direct Addressing EXT. RAM (DDC) 256B 8KB 0 FF00 Flash Memory Space Internal RAM Space (256 Bytes) External RAM Space (MOVX) AI06635 Registers The 8032 has several registers; these are the Program Counter (PC), Accumulator (A), B Register (B), the Stack Pointer (SP), the Program Status Word (PSW), General purpose registers (R0 to R7), and DPTR (Data Pointer register). Figure 6. 8032 MCU Registers A B SP PCH PCL PSW R0-R7 DPTR(DPH) DPTR(DPL) Accumulator B Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3) Data Pointer Register AI06636 13/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Accumulator. The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional tests. The Accumulator can be used as a 16-bit register with B Register as shown below. Figure 7. Configuration of BA 16-bit Registers B B A Two 8-bit Registers can be used as a "BA" 16-bit Registers AI06637 A B Register. The B Register is the 8-bit general purpose register, used for an arithmetic operation such as multiply, division with Accumulator Stack Pointer. The Stack Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07h after reset. This causes the stack to begin at location 08h. Figure 8. Stack Pointer Stack Area (30h-FFh) Bit 15 00h Hardware Fixed Bit 8 Bit 7 SP 00h-FFh Bit 0 SP (Stack Pointer) could be in 00h-FFh AI06638 Program Counter. The Program Counter is a 16bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In RESET state, the program counter has reset routine address (PCH:00h, PCL:00h). Program Status Word. The Program Status Word (PSW) contains several bits that reflect the current state of the CPU and select Internal RAM (00h to 1Fh: Bank0 to Bank3). The PSW is described in Figure 9., page 15. It contains the Carry flag, the Auxiliary carry flag, the Half Carry (for BCD operation), the general purpose flag, the Register bank select flags, the Overflow flag, and Parity flag. [Carry Flag, CY]. This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Auxiliary Carry Flag, AC]. After operation, this is set when there is a carry from Bit 3 of ALU or there is no borrow from Bit 4 of ALU. [Register Bank Select Flags, RS0, RS1]. This flags select one of four bank(00~07H:bank0, 08~0Fh:bank1, 10~17h:bank2, 17~1Fh:bank3) in Internal RAM. [Overflow Flag, OV]. This flag is set to '1' when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127 (7Fh) or -128 (80h). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, Bit 6 of memory is copied to this flag. [Parity Flag, P]. This flag reflect on number of Accumulator's 1. If number of Accumulator's 1 is odd, P=0. otherwise P=1. Sum of adding Accumulator's 1 to P is always even. R0~R7. General purpose 8-bit registers that are locked in the lower portion of internal data area. Data Pointer Register. Data Pointer Register is 16-bit wide which consists of two-8bit registers, DPH and DPL. This register is used as a data pointer for the data transmission with external data memory in the PSD Module. 14/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 9. PSW (Program Status Word) Register MSB PSW Carry Flag Auxillary Carry Flag General Purpose Flag Register Bank Select Flags (to select Bank0-3) CY AC FO RS1 RS0 OV LSB P Reset Value 00h Parity Flag Bit not assigned Overflow Flag AI06639 Program Memory The program memory consists of two Flash memory: 128 KByte (or 256 KByte) Main Flash and 32 KByte of Secondary Flash. The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data memory space during Flash memory update or programming. After reset, the CPU begins execution from location 0000h. As shown in Figure 10, each interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for example, is assigned to location 0003h. If External Interrupt 0 is going to be used, its service routine must begin at location 0003h. If the interrupt is not going to be used, its service location is available as general purpose Pro-gram Memory. The interrupt service locations are spaced at 8byte intervals: 0003h for External Interrupt 0, 000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1 and so forth. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. Data memory The internal data memory is divided into four physically separated blocks: 256 bytes of internal RAM, 128 bytes of Special Function Registers (SFRs) areas, 256 bytes of external RAM (XRAM-DDC) and 8K bytes (XRAM-PSD) in the PSD Module. RAM Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack depth is only limited by the available internal RAM space of 256 bytes. Figure 10. Interrupt Location of Program Memory Interrupt Location * * * * * 008Bh * * * * 0013h 8 Bytes 000Bh 0003h Reset 0000h AI06640 XRAM-DDC The 256 bytes of XRAM-DDC used to support DDC interface is also available for system usage by indirect addressing through the address pointer DDCADR and data I/O buffer RAMBUF. The address pointer (DDCADR) is equipped with the post increment capability to facilitate the transfer of data in bulk (for details refer to DDC Interface part). However, it is also possible to address the RAM through MOVX command as normally used in the internal RAM extension of 80C51 derivatives. XRAM-DDC FF00 to FFFF is directly addressable as external data memory locations FF00 to FFFF via MOVX-DPTR instruction or via MOVX-Ri instruction. When XRAM-DDC is disabled, the address space FF00 to FFFF can be assigned to other resources. XRAM-PSD The 8K bytes of XRAM-PSD resides in the PSD Module and can be mapped to any address space through the DPLD (Decoding PLD) as defined by the user in PSDsoft Development tool. The XRAMPSD has a battery backup feature that allow the data to be retained in the event of a power lost. The battery is connected to the Port C PC2 pin. This pin must be configured in PSDSoft to be battery back-up. 15/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV SFR The SFRs can only be addressed directly in the address range from 80h to FFh. Table 15., page 28 gives an overview of the Special Function Registers. Sixteen address in the SFRs space are both-byte and bit-addressable. The bitaddressable SFRs are those whose address ends in 0h and 8h. The bit addresses in this area are 80h to FFh. Table 3. RAM Address Byte Address (in Hexadecimal) FFh 30h msb 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1Fh Register Bank 3 18h 17h Register Bank 2 10h 0Fh Register Bank 1 08h 07h Register Bank 0 00h 0 8 7 AI06642 Addressing Modes The addressing modes in uPSD323X Devices instruction set are as follows Direct addressing Indirect addressing Register addressing Register-specific addressing Immediate constants addressing Indexed addressing (1) Direct addressing. In a direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRs (80~FFH RAM) can be directly addressed. Example: mov A, 3EH ; A <----- RAM[3E] Figure 11. Direct Addressing Program Memory Byte Address (in Decimal) 255 48 Bit Address (Hex) lsb 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 24 23 16 15 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 3Eh 04 A AI06641 (2) Indirect addressing. In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit "data pointer" register, DPTR. Example: mov @R1, #40 H ;[R1] <-----40H Figure 12. Indirect Addressing Program Memory 55h 40h R1 55 16/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV (3) Register addressing. The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of four banks is selected at execution time by the two bank select bits in the PSW. Example: mov PSW, #0001000B ; select Bank0 mov A, #30H mov R1, A (4) Register-specific addressing. Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point it. The opcode itself does that. (5) Immediate constants addressing. The value of a constant can follow the opcode in Program memory. Example: mov A, #10H. (6) Indexed addressing. Only Program memory can be accessed with indexed addressing, and it can only be read. This addressing mode is intended for reading look-up tables in Program memory. A 16-bit base register (either DPTR or PC) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in Program memory is formed by adding the Accumulator data to the base pointer. Example: movc A, @A+DPTR Figure 13. Indexed Addressing ACC 3Ah DPTR 1E73h Program Memory Arithmetic Instructions The arithmetic instructions is listed in Table 4., page 18. The table indicates the addressing modes that can be used with each instruction to access the 3Eh AI06643 17/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 4. Arithmetic Instructions Addressing Modes Mnemonic ADD A, Accumulator only X X Data Pointer only Accumulator only X X Accumulator and B only Accumulator and B only Accumulator only Logical Instructions Table 5., page 19 shows list of uPSD323X Devices logical instructions. The instructions that perform Boolean operations (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bitby-bit basis. That is, if the Accumulator contains 00110101B and byte contains 01010011B, then: ANL A, If the operation is in response to an interrupt, not using the Accumulator saves the time and effort to push it onto the stack in the service routine. The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right. For a left rotation, the MSB rolls into the LSB position. For a right rotation, the LSB rolls into the MSB position. The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This is a useful operation in BCD manipulations. For example, if the Accumulator contains a binary number which is known to be less than 100, it can be quickly converted to BCD by the following code: MOVE B,#10 DIV AB SWAP A ADD A,B Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator, and the ones digit in the B register. The SWAP and ADD instructions move the tens digit to the high nibble of the Accumulator, and the ones digit to the low nibble. 18/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 5. Logical Instructions Addressing Modes Mnemonic ANL A, 19/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Data Transfers Internal RAM. Table 6 shows the menu of instructions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used with each one. The MOV The XCH A, Table 6. Data Transfer Instructions that Access Internal Data Memory Space Addressing Modes Mnemonic MOV A, 20/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV First, pointers R1 and R0 are set up to point to the two bytes containing the last four BCD digits. Then a loop is executed which leaves the last byte, location 2EH, holding the last two digits of the shifted number. The pointers are decremented, and the loop is repeated for location 2DH. The CJNE instruction (Compare and Jump if Not equal) is a loop control that will be described later. The loop executed from LOOP to CJNE for R1 = 2EH, 2DH, 2CH, and 2BH. At that point the digit that was originally shifted out on the right has propagated to location 2AH. Since that location should be left with 0s, the lost digit is moved to the Accumulator. Table 7. Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes) 2A MOV MOV MOV MOV MOV A,2Eh 2Eh,2Dh 2Dh,2Ch 2Ch,2Bh 2Bh,#0 00 00 00 00 00 2B 12 12 12 12 00 2C 34 34 34 12 12 2D 56 56 34 34 34 2E 78 56 56 56 56 ACC 78 78 78 78 78 Table 8. Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes) 2A CLR XCH XCH XCH XCH A A,2Bh A,2Ch A,2Dh A,2Eh 00 00 00 00 00 2B 12 00 00 00 00 2C 34 34 12 12 12 2D 56 56 56 34 34 2E 78 78 78 78 56 ACC 00 12 34 56 78 Table 9. Shifting a BCD Number One Digit to the Right 2A MOV MOV R1,#2Eh R0,#2Dh 00 00 2B 12 12 2C 34 34 2D 56 56 2E 78 78 ACC xx xx ; loop for R1 = 2Eh LOOP: MOV XCHD SWAP MOV DEC DEC CNJE A,@R1 A,@R0 A @R1,A R1 R0 R1,#2Ah,LOOP 00 00 00 00 00 00 00 12 12 12 12 12 12 12 34 34 34 34 34 34 34 56 58 58 58 58 58 58 78 78 78 67 67 67 67 78 76 67 67 67 67 67 ; loop for R1 = 2Dh ; loop for R1 = 2Ch ; loop for R1 = 2Bh 00 00 08 12 18 01 38 23 23 45 45 45 67 67 67 45 23 01 CLR XCH A A,2Ah 08 00 01 01 23 23 45 45 67 67 00 08 21/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV External RAM. Table 10 shows a list of the Data Transfer instructions that access external Data Memory. Only indirect addressing can be used. The choice is whether to use a one-byte address, @Ri, where Ri can be either R0 or R1 of the selected register bank, or a two-byte address, @DTPR. Note: In all external Data RAM accesses, the Accumulator is always either the destination or source of the data. Lookup Tables. Table 11 shows the two instructions that are available for reading lookup tables in Program Memory. Since these instructions access only Program Memory, the lookup tables can only be read, not updated. The mnemonic is MOVC for "move constant." The first MOVC instruction in Table 11 can accommodate a table of up to 256 entries numbered 0 through 255. The number of the desired entry is loaded into the Accumulator, and the Data Pointer is set up to point to the beginning of the table. Then: MOVC A, @A+DPTR copies the desired table entry into the Accumulator. The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table base, and the table is accessed through a subroutine. First the number of the desired en-try is loaded into the Accumulator, and the subroutine is called: MOV A , ENTRY NUMBER CALL TABLE The subroutine "TABLE" would look like this: TABLE: MOVC A , @A+PC RET The table itself immediately follows the RET (return) instruction is Program Memory. This type of table can have up to 255 entries, numbered 1 through 255. Number 0 cannot be used, because at the time the MOVC instruction is executed, the PC contains the address of the RET instruction. An entry numbered 0 would be the RET opcode itself. Table 10. Data Transfer Instruction that Access External Data Memory Space Address Width 8 bits 8 bits 16 bits 16 bits Mnemonic MOVX A,@Ri MOVX @Ri,A MOVX A,@DPTR MOVX @DPTR,a Operation READ external RAM @Ri WRITE external RAM @Ri READ external RAM @DPTR WRITE external RAM @DPTR Table 11. Lookup Table READ Instruction Mnemonic MOVC A,@A+DPTR MOVC A,@A+PC Operation READ program memory at (A+DPTR) READ program memory at (A+PC) 22/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Boolean Instructions The uPSD323X Devices contain a complete Boolean (single-bit) processor. One page of the internal RAM contains 128 address-able bits, and the SFR space can support up to 128 addressable bits as well. All of the port lines are bit-addressable, and each one can be treated as a separate singlebit port. The instructions that access these bits are not just conditional branches, but a complete menu of move, set, clear, complement, OR and AND instructions. These kinds of bit operations are not easily obtained in other architectures with any amount of byte-oriented software. The instruction set for the Boolean processor is shown in Table 12. All bits accesses are by direct addressing. Bit addresses 00h through 7Fh are in the Lower 128, and bit ad-dresses 80h through FFh are in SFR space. Note how easily an internal flag can be moved to a port pin: MOV C,FLAG MOV P1.0,C In this example, FLAG is the name of any addressable bit in the Lower 128 or SFR space. An I/O line (the LSB of Port 1, in this case) is set or cleared depending on whether the Flag Bit is '1' or '0.' The Carry Bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that refer to the Carry Bit as C assemble as Carry-specific instructions (CLR C, etc.). The Carry Bit also has a direct address, since it resides in the PSW register, which is bit-addressable. Note: The Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive OR) operation. An XRL operation is simple to implement in software. Suppose, for example, it is required to form the Exclusive OR of two bits: C = bit 1 .XRL. bit2 The software to do that could be as follows: MOV C , bit1 JNB bit2, OVER CPL C OVER: (continue) First, Bit 1 is moved to the Carry. If bit2 = 0, then C now contains the correct result. That is, Bit 1 .XRL. bit2 = bit1 if bit2 = 0. On the other hand, if bit2 = 1, C now contains the complement of the correct result. It need only be inverted (CPL C) to complete the operation. This code uses the JNB instruction, one of a series of bit-test instructions which execute a jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is not set (JNC, JNB). In the above case, Bit 2 is being tested, and if bit2 = 0, the CPL C instruction is jumped over. JBC executes the jump if the addressed bit is set, and also clears the bit. Thus a flag can be tested and cleared in one operation. All the PSW bits are directly addressable, so the Parity Bit, or the general-purpose flags, for example, are also available to the bit-test instructions. Table 12. Boolean Instructions Mnemonic ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C CLR C CLR bit SETB C SETB bit CPL C CPL bit JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel Operation C = A .AND. bit C = C .AND. .NOT. bit C = A .OR. bit C = C .OR. .NOT. bit C = bit bit = C C=0 bit = 0 C=1 bit = 1 C = .NOT. C bit = .NOT. bit Jump if C =1 Jump if C = 0 Jump if bit =1 Jump if bit = 0 Jump if bit = 1; CLR bit Relative Offset The destination address for these jumps is specified to the assembler by a label or by an actual address in Program memory. How-ever, the destination address assembles to a relative offset byte. This is a signed (two's complement) offset byte which is added to the PC in two's complement arithmetic if the jump is executed. The range of the jump is therefore -128 to +127 Program Memory bytes relative to the first byte following the instruction. 23/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Jump Instructions Table 13 shows the list of unconditional jump instructions. The table lists a single "JMP add" instruction, but in fact there are three SJMP, LJMP, and AJMP, which differ in the format of the destination address. JMP is a generic mnemonic which can be used if the programmer does not care which way the jump is en-coded. The SJMP instruction encodes the destination address as a relative offset, as described above. The instruction is 2 bytes long, consisting of the opcode and the relative offset byte. The jump distance is limited to a range of -128 to +127 bytes relative to the instruction following the SJMP. The LJMP instruction encodes the destination address as a 16-bit constant. The instruction is 3 bytes long, consisting of the opcode and two address bytes. The destination address can be anywhere in the 64K Program Memory space. The AJMP instruction encodes the destination address as an 11-bit constant. The instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address bits, followed by another byte containing the low 8 bits of the destination address. When the instruction is executed, these 11 bits are simply substituted for the low 11 bits in the PC. The high 5 bits stay the same. Hence the destination has to be within the same 2K block as the instruction following the AJMP. In all cases the programmer specifies the destination address to the assembler in the same way: as a label or as a 16-bit constant. The assembler will put the destination address into the correct format for the given instruction. If the format required by the instruction will not support the distance to the specified destination address, a "Destination out of range" message is written into the List file. The JMP @A+DPTR instruction supports case jumps. The destination address is computed at execution time as the sum of the 16-bit DPTR register and the Accumulator. Typically. DPTR is set up with the address of a jump table. In a 5-way branch, for ex-ample, an integer 0 through 4 is loaded into the Accumulator. The code to be executed might be as follows: MOV DPTR,#JUMP TABLE MOV A,INDEX_NUMBER RL A JMP @A+DPTR The RL A instruction converts the index number (0 through 4) to an even number on the range 0 through 8, because each entry in the jump table is 2 bytes long: JUMP TABLE: AJMP CASE 0 AJMP CASE 1 AJMP CASE 2 AJMP CASE 3 AJMP CASE 4 Table 13 shows a single "CALL addr" instruction, but there are two of them, LCALL and ACALL, which differ in the format in which the subroutine address is given to the CPU. CALL is a generic mnemonic which can be used if the programmer does not care which way the address is encoded. The LCALL instruction uses the 16-bit address format, and the subroutine can be anywhere in the 64K Program Memory space. The ACALL instruction uses the 11-bit format, and the subroutine must be in the same 2K block as the instruction following the ACALL. In any case, the programmer specifies the subroutine address to the assembler in the same way: as a label or as a 16-bit constant. The assembler will put the address into the correct format for the given instructions. Subroutines should end with a RET instruction, which returns execution to the instruction following the CALL. RETI is used to return from an interrupt service routine. The only difference between RET and RETI is that RETI tells the interrupt control system that the interrupt in progress is done. If there is no interrupt in progress at the time RETI is executed, then the RETI is functionally identical to RET. Table 13. Unconditional Jump Instructions Mnemonic JMP addr JMP @A+DPTR CALL addr RET RETI NOP Operation Jump to addr Jump to A+DPTR Call Subroutine at addr Return from subroutine Return from interrupt No operation 24/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 14 shows the list of conditional jumps available to the uPSD323X Devices user. All of these jumps specify the destination address by the relative offset method, and so are limited to a jump distance of -128 to +127 bytes from the instruction following the conditional jump instruction. Important to note, however, the user specifies to the assembler the actual destination address the same way as the other jumps: as a label or a 16-bit constant. There is no Zero Bit in the PSW. The JZ and JNZ instructions test the Accumulator data for that condition. The DJNZ instruction (Decrement and Jump if Not Zero) is for loop control. To execute a loop N times, load a counter byte with N and terminate the loop with a DJNZ to the beginning of the loop, as shown below for N = 10: MOV COUNTER,#10 LOOP: (begin loop) * * * (end loop) DJNZ COUNTER, LOOP (continue) The CJNE instruction (Compare and Jump if Not Equal) can also be used for loop control as in Table 9., page 21. Two bytes are specified in the operand field of the instruction. The jump is executed only if the two bytes are not equal. In the example of Table 9., page 21 Shifting a BCD Number One Digits to the Right, the two bytes were data in R1 and the constant 2Ah. The initial data in R1 was 2Eh. Every time the loop was executed, R1 was decremented, and the looping was to continue until the R1 data reached 2Ah. Another application of this instruction is in "greater than, less than" comparisons. The two bytes in the operand field are taken as unsigned integers. If the first is less than the second, then the Carry Bit is set (1). If the first is greater than or equal to the second, then the Carry Bit is cleared Machine Cycles A machine cycle consists of a sequence of six states, numbered S1 through S6. Each state time lasts for two oscillator periods. Thus, a machine cycle takes 12 oscillator periods or 1s if the oscillator frequency is 12MHz. Refer to Figure 14., page 26. Each state is divided into a Phase 1 half and a Phase 2 half. State Sequence in uPSD323X Devices shows that retrieve/execute sequences in states and phases for various kinds of instructions. Normally two program retrievals are generated during each machine cycle, even if the instruction being executed does not require it. If the instruction being executed does not need more code bytes, the CPU simply ignores the extra retrieval, and the Program Counter is not incremented. Execution of a one-cycle instruction (Figure 14., page 26) begins during State 1 of the machine cycle, when the opcode is latched into the Instruction Register. A second retrieve occurs during S4 of the same machine cycle. Execution is complete at the end of State 6 of this machine cycle. The MOVX instructions take two machine cycles to execute. No program retrieval is generated during the second cycle of a MOVX instruction. This is the only time program retrievals are skipped. The retrieve/execute sequence for MOVX instruction is shown in Figure 14., page 26 (d). Table 14. Conditional Jump Instructions Addressing Modes Mnemonic JZ rel JNZ rel DJNZ 25/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 14. State Sequence in uPSD323X Devices Osc. (XTAL2) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 Read opcode S1 S2 S3 Read next opcode and discard S4 S5 S6 Read next opcode a. 1-Byte, 1-Cycle Instruction, e.g. INC A Read 2nd Byte S3 S4 S5 S6 Read next opcode Read opcode S1 S2 b. 2-Byte, 1-Cycle Instruction, e.g. ADD A, adrs Read next opcode and discard S3 S4 S5 S6 Read next opcode and discard S1 S2 S3 Read next opcode and discard S4 S5 S6 Read next opcode Read opcode S1 S2 c. 1-Byte, 2-Cycle Instruction, e.g. INC DPTR Read next opcode and discard S3 S4 S5 Addr S6 No Fetch No ALE No Fetch Read next opcode S6 Read opcode (MOVX) S1 S2 S1 S2 Data S3 S4 S5 d. 1-Byte, 2-Cycle MOVX Instruction Access External Memory AI06822 26/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV uPSD3200 HARDWARE DESCRIPTION The uPSD323X Devices has a modular architecture with two main functional modules: the MCU Module and the PSD Module. The MCU Module consists of a standard 8032 core, peripherals and other system supporting functions. The PSD Module provides configurable Program and Data memories to the 8032 CPU core. In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general logic implementation. Ports A,B,C, and D are general purpose programmable I/O ports Figure 15. uPSD323X Devices Functional Modules Port 3, UART, Intr, Timers,I2C Port 1, Timers and 2nd UART and ADC Port 4 PWM and DDC Dedicated USB Pins that have a port architecture which is different from Ports 0-4 in the MCU Module. The PSD Module communicates with the CPU Core through the internal address, data bus (A0A15, D0-D7) and control signals (RD_, WR_, PSEN_ , ALE, RESET_). The user defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space. Port 3 8032 Core 2 UARTs Interrupt Port 1 I2C 3 Timer / Counters 256 Byte SRAM 4 Channel ADC PWM 5 Channels USB DDC Reset Logic & w/ 256 Byte LVD & WDT Transceiver SRAM MCU MODULE 8032 Internal Bus A0-A15 RD,PSEN WR,ALE PSD MODULE Page Register Decode PLD 1Mb or 2Mb Main Flash 256Kb Secondary Flash 64Kb SRAM Bus Interface D0-D7 Reset Port 0, 2 Ext. Bus PSD Internal Bus JTAG ISP CPLD - 16 MACROCELLS VCC, GND, XTAL Port C, JTAG, PLD I/O and GPIO Port A & B, PLD I/O and GPIO Port D GPIO Dedicated Pins AI06619C 27/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV MCU MODULE DISCRIPTION This section provides a detail description of the MCU Module system functions and Peripherals, including: Special Function Registers Timers/Counter Interrupts PWM Supervisory Function (LVD and Watchdog) USART Power Saving Modes I2C Bus On-chip Oscillator ADC I/O Ports USB Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 15. Note: In the SFRs not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. READ accesses to these addresses will in general return random data, and WRITE accesses will have no effect. User software should write '0s' to these unimplemented locations. Table 15. SFR Memory Map F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 B(1) UISTA(1) ACC(1) S1CON(1) PSW(1) T2CON(1) P4(1) IP(1) P3(1) IE(1) P2(1) SCON P1(1) TCON(1) P0(1) PWMCON SBUF P1SFS TMOD SP TL0 DPL PSCL0L PSCL0H PWM4P PWM0 SCON2 PSCL1L PWM4W PWM1 SBUF2 P3SFS TL1 DPH P4SFS TH0 ASCL TH1 PCON ADAT ACON PWM2 PWM3 PSCL1H WDKEY WDRST IEA IPA UIEN USCL S1STA S1SETUP T2MOD S1DAT S2SETUP RCAP2L RCAP2H S1ADR S2CON RAMBUF TL2 S2STA DDCDAT TH2 UCON0 UCON1 UCON2 USTA UADR UDT1 S2DAT UDR0 UDT0 S2ADR FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 DDCADR DDCCON Note: 1. Register can be bit addressing 28/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 16. List of all SFR SFR Reg Name Addr 80 81 82 83 87 88 P0 SP DPL DPH PCON TCON SMOD TF1 SMOD1 LVREN ADSFINT RCLK1 TR1 TF0 TR0 IE1 TCLK1 IT1 PD IE0 IDLE IT0 Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value FF 07 00 00 00 00 Port 0 Stack Ptr Data Ptr Low Data Ptr High Power Ctrl Timer / Cntr Control Timer / Cntr Mode Control Timer 0 Low Timer 1 Low Timer 0 High Timer 1 High Port 1 Port 1 Select Register Port 3 Select Register Port 4 Select Register 8-bit Prescaler for ADC clock ADC Data Register ADC Control Register Serial Control Register Serial Buffer 2nd UART Ctrl Register 2nd UART Serial Buffer Port 2 PWM Control Polarity 89 8A 8B 8C 8D 90 91 93 94 TMOD TL0 TL1 TH0 TH1 P1 P1SFS P3SFS P4SFS Gate C/T M1 M0 Gate C/T M1 M0 00 00 00 00 00 FF P1S7 P3S7 P4S7 P1S6 P3S6 P4S6 P1S5 P1S4 00 00 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0 00 95 ASCL 00 96 97 ADAT ACON ADAT7 ADAT6 ADAT5 ADEN ADAT4 ADAT3 ADS1 ADAT2 ADS0 ADAT1 ADST ADAT0 ADSF 00 00 98 99 9A 9B A0 SCON SBUF SCON2 SBUF2 P2 SM0 SM1 SM2 REN TB8 RB8 TI RI 00 00 SM0 SM1 SM2 REN TB8 RB8 TI RI 00 00 FF A1 PWMCON PWML PWMP PWME CFG4 CFG3 CFG2 CFG1 CFG0 00 29/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV SFR Reg Name Addr Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value PWM0 Output Duty Cycle PWM1 Output Duty Cycle PWM2 Output Duty Cycle PWM3 Output Duty Cycle Watch Dog Reset Interrupt Enable (2nd) Interrupt Enable A2 PWM0 00 A3 PWM1 00 A4 PWM2 00 A5 PWM3 00 A6 A7 A8 A9 AA AB AE B0 B1 B2 B3 B4 B7 B8 C0 C8 C9 WDRST IEA IE EDDC EA ET2 ES2 ES ET1 EX1 EI2C ET0 EUSB EX0 00 00 00 PWM4P PWM4W WDKEY P3 PSCL0L PSCL0H PSCL1L PSCL1H IPA IP P4 T2CON T2MOD TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 DCEN PDDC PT2 PS2 PS PT1 PX1 PI2C PT0 PUSB PX0 00 00 00 FF 00 00 00 00 00 00 FF 00 00 PWM 4 Period PWM 4 Pulse Width Watch Dog Key Register Port 3 Prescaler 0 Low (8-bit) Prescaler 0 High (8-bit) Prescaler 1 Low (8-bit) Prescaler 1 High (8-bit) Interrupt Priority (2nd) Interrupt Priority New Port 4 Timer 2 Control Timer 2 Mode 30/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV SFR Reg Name Addr CA CB CC CD D0 RCAP2L RCAP2H TL2 TH2 PSW CY AC FO RS1 RS0 OV P Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value 00 00 00 00 00 00 00 XX 00 00 -- CR2 GC EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT ENI1 Stop STA Intr STO TX-Md ADDR Bbusy AA Blost CR1 ACK_R M0 CR0 SLV 00 00 00 00 00 CR2 GC EN1 Stop STA Intr STO TX-Md ADDR Bbusy AA Blost CR1 ACK_R CR0 SLV 00 00 00 00 00 00 Timer 2 Reload low Timer 2 Reload High Timer 2 Low byte Timer 2 High byte Program Status Word DDC I2C (S1) Setup I2C (S2) Setup DDC Ram Buffer DDC Data xmit register Addr pointer register DDC Control Register DDC I2C Control Reg DDC I2C Status Data Hold Register DDC I2C address I2C Bus Control Reg I2C Bus Status Data Hold Register I2C address Accumulator 8-bit Prescaler for USB logic USB Endpt1 Data Xmit D1 S1SETUP D2 S2SETUP D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 RAMBUF DDCDAT DDCADR DDCCON S1CON S1STA S1DAT S1ADR S2CON S2STA S2DAT S2ADR ACC USCL E6 UDT1 UDT1.7 UDT1.6 UDT1.5 UDT1.4 UDT1.3 UDT1.2 UDT1.1 UDT1.0 00 31/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV SFR Reg Name Addr E7 UDT0 Bit Register Name 7 UDT0.7 6 5 4 3 2 1 0 Reset Comments Value 00 USB Endpt0 Data Xmit USB Interrupt Status USB Interrupt Enable USB Endpt0 Xmit Control USB Endpt1 Xmit Control USB Control Register USB Endpt0 Status USB Address Register USB Endpt0 Data Recv B Register UDT0.6 UDT0.5 UDT0.4 UDT0.3 UDT0.2 UDT0.1 UDT0.0 E8 UISTA SUSPND -- RSTF TXD0F RXD0F RXD1F EOPF RESUMF 00 E9 UIEN SUSPNDI E TSEQ0 TSEQ1 -- RSEQ RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMI E 00 EA EB EC ED UCON0 UCON1 UCON2 USTA STALL0 EP12SEL -- SETUP TX0E -- -- IN RX0E TP0SIZ3 TP0SiZ2 TP0SIZ1 TP0SIZ0 00 00 00 00 FRESUM TP1SIZ3 TP1SiZ2 TP1SIZ1 TP1SIZ0 SOUT OUT EP2E EP1E STALL2 STALL1 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 EE UADR USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 00 EF F0 UDR0 B UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0 00 00 32/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 17. PSD Module Register Address Offset CSIOP Addr Offset 00 02 04 06 08 0A 0C 01 03 05 07 09 0B 0D 10 12 14 16 18 1A 11 13 15 17 1B 20 Bit Register Name Register Name 7 Data In (Port A) 6 5 4 3 2 1 0 Reads Port pins as input 00 00 00 00 Reset Value Comments Control (Port A) Configure pin between I/O or Address Out Mode. Bit = 0 selects I/O Data Out (Port A) Direction (Port A) Drive (Port A) Input Macrocell (Port A) Enable Out (Port A) Data In (Port B) Control (Port B) Data Out (Port B) Direction (Port B) Drive (Port B) Input Macrocell (Port B) Enable Out (Port B) Data In (Port C) Data Out (Port C) Direction (Port C) Drive (Port C) Input Macrocell (Port C) Enable Out (Port C) Data In (Port D) Data Out (Port D) Direction (Port D) Drive (Port D) Enable Out (Port D) Output Macrocells AB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Latched data for output to Port pins, I/O Output Mode Configures Port pin as input or output. Bit = 0 selects input Configures Port pin between CMOS, Open Drain or Slew rate. Bit = 0 selects CMOS Reads latched value on Input Macrocells Reads the status of the output enable control to the Port pin driver. Bit = 0 indicates pin is in input mode. 00 00 00 00 00 00 00 Only Bit 1 and 2 are used 00 00 00 Only Bit 1 and 2 are used Only Bit 1 and 2 are used Only Bit 1 and 2 are used Only Bit 1 and 2 are used 33/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV CSIOP Addr Offset 21 22 23 C0 Bit Register Name Register Name 7 Output Macrocells BC Mask Macrocells AB Mask Macrocells BC Primary Flash Protection Sec7_ Prot Sec6_ Sec5_ Sec4_ Sec3_ Sec2_ Sec1_ Prot Prot Prot Prot Prot Prot * * PLD Mcells clk PLD array Ale * Sec3_ Sec2_ Sec1_ Prot Prot Prot APD enable Sec0_ Prot Sec0_ Prot Bit = 1 sector is protected Security Bit = 1 device is secured 00 Control PLD power consumption Blocking inputs to PLD array Page Register Configure 8032 Program and Data Space 6 5 4 3 2 1 0 Reset Value Comments C2 Secondary Flash Security Protection _Bit B0 PMMR0 * * PLD PLD arrayTurbo clk PLD array Cntl2 PLD array Cntl1 * PLD array Cntl0 * B4 E0 PMMR2 Page * * * 00 00 E2 VM Periphmode * * FL_ data Boot_ data FL_ code Boot_ code SR_ code Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft) * indicates bit is not used and need to set to '0.' 34/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV INTERRUPT SYSTEM There are interrupt requests from 10 sources as follows. INT0 external interrupt 2nd USART Interrupt Timer 0 Interrupt I2C Interrupt INT1 External Interrupt (or ADC Interrupt) DDC Interrupt Timer 1 Interrupt USB Interrupt USART Interrupt Timer 2 Interrupt External Int0 - The INT0 can be either level-active or transition-active depending on Bit IT0 in register TCON. The flag that actually generates this interrupt is Bit IE0 in TCON. - When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. - If the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. Timer 0 and 1 Interrupts - Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1 which are set by an overflow of their respective Timer/Counter registers (except for Timer 0 in Mode 3). - These flags are cleared by the internal hardware when the interrupt is serviced. Timer 2 Interrupt - Timer 2 Interrupt is generated by TF2 which is set by an overflow of Timer 2. This flag has to be cleared by the software - not by hardware. - It is also generated by the T2EX signal (Timer 2 External Interrupt P1.1) which is controlled by EXEN2 and EXF2 Bits in the T2CON register. I2C Interrupt - The interrupt of the I2C is generated by Bit INTR in the register S2STA. - This flag is cleared by hardware. External Int1 - The INT1 can be either level active or transition active depending on Bit IT1 in register TCON. The flag that actually generates this interrupt is Bit IE1 in TCON. - When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. - If the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. - The ADC can take over the External INT1 to generate an interrupt on conversion being completed DDC Interrupt - The DDC Interrupt is generated either by Bit INTR in the S1STA register for DC2B protocol or by Bit DDC Interrupt in the DDCCON register for DDC1 protocol or by Bit SWHINT Bit in the DDCCON register when DDC protocol is changed from DDC1 to DDC2. - Flags except the INTR have to be cleared by the software. INTR flag is cleared by hardware. USB Interrupt - The USB Interrupt is generated when endpoint0 has transmitted a packet or received a packet, when endpoint1 or endpoint2 has transmitted a packet, when the suspend or resume state is detected and every EOP received. - When the USB Interrupt is generated, the corresponding request flag must be cleared by software. The interrupt service routine will have to check the various USB registers to determine the source and clear the corresponding flag. - Please see the dedicated interrupt control registers for the USB peripheral for more information. 35/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV USART Interrupt - The USART Interrupt is generated by RI (receive interrupt) OR TI (transmit interrupt). - When the USART Interrupt is generated, the corresponding request flag must be cleared by software. The interrupt service routine will have to check the various USART registers to Figure 16. Interrupt System Interrupt Sources INT0 USART IE / IP / IPA Priority High Low - determine the source and clear the corresponding flag. Both USART's are identical, except for the additional interrupt controls in the Bit 4 of the additional interrupt control registers (A7H, B7H) Timer 0 I2C Interrupt Polling INT1 DDC Timer 1 USB 2nd USART Timer 2 Global Enable AI06646 Table 18. SFR Register SFR Addr A7 A8 B7 B8 Reg Name IEA IE IPA IP Bit Register Name 7 EDDC EA PDDC -- 6 -- -- -- -- 5 -- ET2 -- PT2 4 ES2 ES PS2 PS 3 -- ET1 -- PT1 2 -- EX1 -- PX1 1 EI2C ET0 PI2C PT0 0 EUSB EX0 PUSB PX0 Reset Comments Value 00 00 00 00 Interrupt Enable (2nd) Interrupt Enable Interrupt Priority (2nd) Interrupt Priority 36/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Interrupt Priority Structure Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority special function register IP and IPA. 0 = low priority 1 = high priority A low priority interrupt may be interrupted by a high priority interrupt level interrupt. A high priority interrupt routine cannot be interrupted by any other interrupt source. If two interrupts of different priority occur simultaneously, the high priority level request is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence. Interrupts Enable Structure Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function register IE and IEA. All Table 20. Description of the IE Bits Bit Symbol Function Disable all interrupts: 0: no interrupt with be acknowledged 1: each interrupt source is individually enabled or disabled by setting or clearing its enable bit Reserved Enable Timer 2 Interrupt Enable USART Interrupt Enable Timer 1 Interrupt Enable external Interrupt (Int1) Enable Timer 0 Interrupt Enable external Interrupt (Int0) interrupt source can also be globally disabled by clearing Bit EA in IE. Table 19. Priority Levels Source Int0 2nd USART Timer 0 IC Int1 DDC Timer 1 USB 1st USART Timer 2+EXF2 Priority with Level 0 (highest) 1 2 3 4 5 6 7 8 9 (lowest) 7 EA 6 5 4 3 2 1 0 -- ET2 ES ET1 EX1 ET0 EX0 Table 21. Description of the IEA Bits Bit 7 6 5 4 3 2 1 0 Symbol EDDC -- -- ES2 -- -- EI2C EUSB Enable DDC Interrupt Not used Not used Enable 2nd USART Interrupt Not used Not used Enable IC Interrupt Enable USB Interrupt Function 37/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 22. Description of the IP Bits Bit 7 6 5 4 3 2 1 0 Symbol -- -- PT2 PS PT1 PX1 PT0 PX0 Reserved Reserved Timer 2 Interrupt priority level USART Interrupt priority level Timer 1 Interrupt priority level External Interrupt (Int1) priority level Timer 0 Interrupt priority level External Interrupt (Int0) priority level Function Table 23. Description of the IPA Bits Bit 7 6 5 4 3 2 1 0 Symbol PDDC -- -- PS2 -- -- PI2C PUSB DDC Interrupt priority level Not used Not used 2nd USART Interrupt priority level Not used Not used IC Interrupt priority level USB Interrupt priority level Function 38/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV How Interrupts are Handled The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this H/W generated LCALL is not blocked by any of the following conditions: - An interrupt of equal priority or higher priority level is already in progress. - The current machine cycle is not the final cycle in the execution of the instruction in progress. - The instruction in progress is RETI or any access to the interrupt priority or interrupt enable registers. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note: If an interrupt flag is active but being responded to for one of the above mentioned conditions, if the flag is still inactive when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate service routine. The hardware generated LCALL pushes the contents of the Program Counter on to the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 24. Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note: A simple RET instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible. Table 24. Vector Addresses Source Int0 2nd USART Timer 0 IC Int1 DDC Timer 1 USB 1st USART Timer 2+EXF2 Vector Address 0003h 004Bh 000Bh 0043h 0013h 003Bh 001Bh 0033h 0023h 002Bh 39/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV POWER-SAVING MODE Two software selectable modes of reduced power consumption are implemented. Idle Mode The following Functions are Switched Off. CPU (Halted) The following Function Remain Active During Idle Mode. External Interrupts Timer 0, Timer 1, Timer 2 DDC Interface PWM Units USB Interface USART 8-bit ADC I2C Interface Note: Interrupt or RESET terminates the Idle Mode. Power-Down Mode System Clock Halted LVD Logic Remains Active SRAM contents remains unchanged The SFRs retain their value until a RESET is asserted Note: The only way to exit Power-down Mode is a RESET. Table 25. Power-Saving Mode Power Consumption Mode Idle Power-down Addr/Data Maintain Data Maintain Data Ports1,3,4 Maintain Data Maintain Data PWM Active Disable I2C Active Disable DDC Active Disable USB Active Disable Power Control Register The Idle and Power-down Modes are activated by software via the PCON register. Table 26. Pin Status During Idle and Power-down Mode SFR Addr 87 Reg Name PCON Bit Register Name 7 SMOD 6 5 4 3 2 TCLK1 1 PD 0 IDLE Reset Comments Value 00 Power Ctrl SMOD1 LVREN ADSFINT RCLK1 Table 27. Description of the PCON Bits Bit 7 6 5 4 3 2 1 0 Symbol SMOD SMOD1 LVREN ADSFINT RCLK1(1) TCLK1(1) PD IDL Double baud data rate bit UART Double baud data rate bit 2nd UART LVR disable bit (active High) Enable ADC Interrupt Received clock flag (UART 2) Transmit clock flag (UART 2) Activate Power-down Mode (High enable) Activate Idle Mode (High enable) Function Note: 1. See the T2CON register for details of the flag description 40/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Idle Mode The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before Idle Mode is activated. Once in the Idle Mode, the CPU status is preserved in its entirety: Stack pointer, Program counter, Program status word, Accumulator, RAM and All other registers maintain their data during Idle Mode. There are three ways to terminate the Idle Mode. - Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware terminating Idle mode. The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic '1' to PCON.0. External hardware reset: the hardware reset is required to be active for two machine cycle to complete the RESET operation. - Internal reset: the microcontroller restarts after 3 machine cycles in all cases. Power-Down Mode The instruction that sets PCON.1 is the last executed prior to going into the Power-down Mode. Once in Power-down Mode, the oscillator is stopped. The contents of the on-chip RAM and the Special Function Register are preserved. The Power-down Mode can be terminated by an external RESET. - 41/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV I/O PORTS (MCU MODULE) The MCU Module has five ports: Port 0, Port 1, Port 2, Port 3, and Port 4. (Refer to the PSD Module section on I/O ports A,B,C and D). Ports P0 and P2 are dedicated for the external address and data bus and is not available in the 52-pin package devices. Port 1 - Port 3 are the same as in the standard 8032 micro-controllers, with the exception of the additional special peripheral functions. All ports are bi-directional. Pins of which the alternative function is not used may be used as normal bi-directional I/O. The use of Port 1- Port 4 pins as alternative functions are carried out automatically by the uPSD323X Devices provided the associated SFR Bit is set HIGH. The following SFR registers (Tables 29, 30, and 31) are used to control the mapping of alternate functions onto the I/O port bits. Port 1 alternate Table 28. I/O Port Functions Port Name Port 1 Main Function GPIO Alternate Timer 2 - Bits 0,1 2nd UART - Bits 2,3 ADC - Bits 4..7 UART - Bits 0,1 Interrupt - Bits 2,3 Timers - Bits 4,5 I2C - Bits 6,7 DDC - Bits 0..2 PWM - Bits 3..7 functions are controlled using the P1SFS register, except for Timer 2 and the 2nd UART which are enabled by their configuration registers. P1.0 to P1.3 are default to GPIO after reset. Port 3 pins 6 and 7 have been modified from the standard 8032. These pins that were used for READ and WRITE control signals are now GPIO or I2C bus pins. The READ and WRITE pins are assigned to dedicated pins. Port 3 (I2C) and Port 4 alternate functions are controlled using the P3SFS and P4SFS Special Function Selection registers. After a reset, the I/O pins default to GPIO. The alternate function is enabled if the corresponding bit in the PXSFS register is set to '1.' Other Port 3 alternative functions (UART, Interrupt, and Timer/Counter) are enabled by their configuration register and do not require setting of the bits in P3SFS. Port 3 GPIO Port 4 USB +/- GPIO USB +/- Only Table 29. P1SFS (91H) 7 0=Port 1.7 1=ACH3 6 0=Port 1.6 1=ACH2 5 0=Port 1.5 1=ACH1 4 0=Port 1.4 1=ACH0 3 2 1 0 Bits Reserved Bits Reserved Table 30. P3SFS (93H) 7 6 5 4 3 2 1 0 0 = Port 3.7 0 = Port 3.6 1 = SCL 1 = SDA from I2C unit from I2C unit Bits are reserved. Table 31. P4SFS (94H) 7 0=Port 4.7 1=PWM 4 6 0=Port 4.6 1=PWM 3 5 0=Port 4.5 1=PWM 2 4 0=Port 4.4 1=PWM 1 3 0=Port 4.3 1=PWM 0 2 0=Port 4.2 1=VSYNC 1 0=Port 4.1 1=DDC SCL 0 0=Port 4.0 1=DDC SDA 42/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PORT Type and Description Figure 17. PORT Type and Description (Part 1) Symbol RESET In / Out I Circuit Description * Schmitt input with internal pull-up CMOS compatible interface NFC : 400ns NFC WR, RD,ALE, PSEN O Output only XTAL1, XTAL2 I On-chip oscillator On-chip feedback resistor Stop in the power down mode External clock input available CMOS compatible interface xon O PORT0 I/O Bidirectional I/O port Schmitt input Address Output ( Push-Pull ) CMOS compatible interface AI06653 43/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 18. PORT Type and Description (Part 2) Symbol PORT1 <3:0>, PORT3, PORT4<7:3,1:0> PORT2 In/ Out I/O Circuit Function Bidirectional I/O port with internal pull-ups Schmitt input CMOS compatible interface PORT1 < 7:4 > I/O Bidirectional I/O port with internal pull-ups Schmitt input CMOS compatible interface Analog input option an_enb PORT4.2 I/O Bidirectional I/O port with internal pull-ups Schmitt input. TTL compatible interface Pull-up when reset Address Latch Enable Program Strobe Enable USB - , USB + I/O Bidirectional I/O port Schmitt input TTL compatible interface + - AI06654 44/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV OSCILLATOR The oscillator circuit of the uPSD323X Devices is a single stage inverting amplifier in a Pierce oscillator configuration. The circuitry between XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete Figure 19. Oscillator the oscillator circuit. Both are operated in parallel resonance. XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the uPSD323X Devices externally, XTAL1 is driven from an external source and XTAL2 left open-circuit. XTAL1 XTAL2 XTAL1 XTAL2 8 to 40 MHz External Clock AI06620 SUPERVISORY There are four ways to invoke a reset and initialize the uPSD323X Devices. Via the external RESET pin Via the internal LVR Block. Via USB bus reset signaling. Via Watch Dog timer Figure 20. RESET Configuration The RESET mechanism is illustrated in Figure 20. Each RESET source will cause an internal reset signal active. The CPU responds by executing an internal reset and puts the internal registers in a defined state. This internal reset is also routed as an active low reset input to the PSD Module. Reset Noise Cancel WDT S Q R RSTE 10ms Timer 10ms at 40Mhz 50ms at 8Mhz CPU Clock Sync CPU & PERI. LVR PSD_RST "Active Low USB Reset AI06621 45/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV External Reset The RESET pin is connected to a Schmitt trigger for noise reduction. A RESET is accomplished by holding the RESET pin LOW for at least 1ms at power up while the oscillator is running. Refer to AC spec on other RESET timing requirements. Low VDD Voltage Reset An internal reset is generated by the LVR circuit when the VDD drops below the reset threshold. After VDD reaching back up to the reset threshold, the RESET signal will remain asserted for 10ms before it is released. On initial power-up the LVR is enabled (default). After power-up the LVR can be disabled via the LVREN Bit in the PCON Register. Note: The LVR logic is still functional in both the Idle and Power-down Modes. The reset threshold: 5V operation: 4V +/- 0.25V 3.3V operation: 2.5V +/-0.2V This logic supports approximately 0.1V of hysteresis and 1s noise-cancelling delay. Watchdog Timer Overflow The Watchdog timer generates an internal reset when its 22-bit counter overflows. See Watchdog Timer section for details. USB Reset The USB reset is generated by a detection on the USB bus RESET signal. A single-end zero on its upstream port for 4 to 8 times will set RSTF Bit in UISTA register. If Bit 6 (RSTE) of the UIEN Register is set, the detection will also generate the RESET signal to reset the CPU and other peripherals in the MCU. 46/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV WATCHDOG TIMER The hardware watchdog timer (WDT) resets the uPSD323X Devices when it overflows. The WDT is intended as a recovery method in situations where the CPU may be subjected to a software upset. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the processor running out of control. In the Idle Mode the watchdog timer and reset circuitry remain active. The WDT consists of a 22-bit counter, the Watchdog Timer RESET (WDRST) SFR and Watchdog Key Register (WDKEY). Since the WDT is automatically enabled while the processor is running. the user only needs to be concerned with servicing it. The 22-bit counter overflows when it reaches 4194304 (3FFFFFH). The WDT increments once every machine cycle. This means the user must reset the WDT at least every 4194304 machine cycles (1.258 seconds at 40MHz). To reset the WDT the user must write a value between 00-7EH to the WDRST register. The value that is written to the WDRST is loaded to the 7MSB of the 22-bit counter. This allows the user to pre-loaded the counter to an initial value to generate a flexible Watchdog time out period. Writing a "00" to WDRST clears the counter. The watchdog timer is controlled by the watchdog key register, WDKEY. Only pattern 01010101 (=55H), disables the watchdog timer. The rest of pattern combinations will keep the watchdog timer enabled. This security key will prevent the watchdog timer from being terminated abnormally when the function of the watchdog timer is needed. In Idle Mode, the oscillator continues to run. To prevent the WDT from resetting the processor while in Idle, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle Mode. Watchdog reset pulse width depends on the clock frequency. The reset period is TfOSC x 12 x 222. The RESET pulse width is TfOSC x 12 x 215. Table 32. Watchdog Timer Key Register (WDKEY: 0AEH) 7 WDKEY7 6 WDKEY6 5 WDKEY5 4 WDKEY4 3 WDKEY3 2 WDKEY2 1 WDKEY1 0 WDKEY0 Table 33. Description of the WDKEY Bits Bit 7 to 0 Symbol WDKEY7 to WDKEY0 Function Enable or disable watchdog timer. 01010101 (=55h): disable watchdog timer. Others: enable watchdog timer 47/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 21. RESET Pulse Width Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz) Reset period (1.258 second at 40Mhz) (about 6.291 seconds at 8Mhz) AI06823 Table 34. Watchdog Timer Clear Register (WDRST: 0A6H) 7 Reserved 6 WDRST6 5 WDRST5 4 WDRST4 3 WDRST3 2 WDRST2 1 WDRST1 0 WDRST0 Table 35. Description of the WDRST Bits Bit 7 6 to 0 Symbol -- WDRST6 to WDRST0 Reserved To reset watchdog timer, write any value beteen 00h and 7Eh to this register. This value is loaded to the 7 most significant bits of the 22-bit counter. For example: MOV WDRST,#1EH Function Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled. 48/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2) The uPSD323X Devices has three 16-bit Timer/ Counter registers: Timer 0, Timer 1 and Timer 2. All of them can be configured to operate either as timers or event counters and are compatible with standard 8032 architecture. In the "Timer" function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 6 CPU clock periods, the count rate is 1/6 of the CPU clock frequency or 1/12 of the oscillator frequency (fOSC). In the "Counter" function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle Table 36. Control Register (TCON) 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 following the one in which the transition was detected. Since it takes 2 machine cycles (24 fOSC clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the fOSC. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full cycle. In addition to the "Timer" or "Counter" selection, Timer 0 and Timer 1 have four operating modes from which to select. Timer 0 and Timer 1 The "Timer" or "Counter" function is selected by control bits C/ T in the Special Function Register TMOD. These Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for Timers/ Counters. Mode 3 is different. The four operating modes are de-scribed in the following text. Table 37. Description of the TCON Bits Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Function Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off Timer 0 Overflow Flag. Set by hardier on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off Interrupt 1 Edge Flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed Interrupt 1 Type Control Bit. Set/cleared by software to specify falling-edge/low-level triggered external interrupt Interrupt 0 Edge Flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed Interrupt 0 Type Control Bit. Set/cleared by software to specify falling-edge/low-level triggered external interrupt 49/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Mode 0. Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 22., page 51 shows the Mode 0 operation as it applies to Timer1. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all '1s' to all '0s,' it sets the Timer Interrupt Flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or /INT1 = 1. (Setting GATE = 1 allows the Timer to be controlled by external input /INT1, to facilitate pulse width measurements). TR1 is a control bit in the Special Function Register TCON (TCON Control Register). GATE is in TMOD. Table 38. TMOD Register (TMOD) 7 Gate 6 C/T 5 M1 4 M0 3 Gate 2 C/T 1 M1 0 M0 The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag does not clear the registers. Mode 0 operation is the same for the Timer0 as for Timer1. Substitute TR0, TF0, and /INT0 for the corresponding Timer1 signals in Figure 22., page 51. There are two different GATE Bits, one for Timer1 and one for Timer0. Mode 1. Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. Table 39. Description of the TMOD Bits Bit 7 6 5 4 Symbol Gate C/T M1 M0 Timer 1 Timer Function Gating control when set. Timer/Counter 1 is enabled only while INT1 pin is High and TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 control bit is set Timer or Counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from T1 input pin) (M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler (M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler. (M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be reloaded into TL1 each time it overflows (M1,M0)=(1,1): Timer/Counter 1 stopped Gating control when set. Timer/Counter 0 is enabled only while INT0 pin is High and TR0 control pin is set. When cleared, Timer 0 is enabled whenever TR0 control bit is set Timer or Counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from T0 input pin) Timer 0 (M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler (M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler. (M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be reloaded into TL0 each time it overflows (M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard TImer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits 3 2 1 Gate C/T M1 0 M0 50/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 22. Timer/Counter Mode 0: 13-bit Counter fOSC / 12 C/T = 0 TL1 (5 bits) Control TH1 (8 bits) TF1 Interrupt T1 pin C/T = 1 TR1 Gate INT1 pin AI06622 Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload fOSC / 12 C/T = 0 TL1 (8 bits) Control TF1 Interrupt T1 pin C/T = 1 TR1 Gate INT1 pin TH1 (8 bits) AI06623 51/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 24. Timer/Counter Mode 3: Two 8-bit Counters fOSC / 12 C/T = 0 TL0 (8 bits) Control TF0 Interrupt T0 pin C/T = 1 TR0 Gate INT0 pin fOSC / 12 Control TH1 (8 bits) TF1 Interrupt TR1 AI06624 52/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Mode 2. Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 23., page 51. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Mode 3. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 24., page 52. TL0 uses the Timer 0 control Bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the "Timer 1" Interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. With Timer 0 in Mode 3, an uPSD323X Devices can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. Timer 2 Like Timers 0 and 1, Timer 2 can operate as either an event timer or as an event counter. This is selected by Bit C/T2 in the special function register T2CON. It has three operating modes: capture, autoload, and baud rate generator, which are selected by bits in the T2CON as shown in Table 41., page 54. In the Capture Mode there are two options which are selected by Bit EXEN2 in T2CON. if EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which upon overflowing sets Bit TF2, the Timer 2 Overflow Bit, which can be used to generate an interrupt. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes Bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt. The Capture Mode is illustrated in Figure 25., page 55. In the Auto-reload Mode, there are again two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload and set EXF2. The Auto-reload Mode is illustrated in Standard Serial Interface (UART) Figure 26., page 55. The Baud Rate Generation Mode is selected by (RCLK, RCLK1)=1 and/or (TCLK, TCLK1)=1. It will be described in conjunction with the serial port. Table 40. Timer/Counter 2 Control Register (T2CON) 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2 53/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 41. Description of the T2CON Bits Bit 7 Symbol TF2 Function Timer 2 overflow flag. Set by a Timer 2 overflow, and must be cleared by software. TF2 will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared by software Receive clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be used for the receive clock Transmit clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be used for the transmit clock Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2=0 causes Time 2 to ignore events at T2EX Start/stop control for Timer 2. A logic 1 starts the timer Timer or Counter select for Timer 2. Cleared for timer operation (input from internal system clock, tCPU); set for external event counter operation (negative edge triggered) Capture/reload flag. When set, capture will occur on negative transition of T2EX if EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow 6 EXF2 5 RCLK(1) 4 TCLK(1) 3 2 1 EXEN2 TR2 C/T2 0 CP/RL2 Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK. Table 42. Timer/Counter2 Operating Modes T2CON Mode RxCLK or TxCLK 0 16-bit Autoreload 0 0 0 0 16-bit Capture 0 1 Baud Rate Generator 1 Off x x x 1 0 x x 1 x 1 x 1 1 x x 1 0 CP/ RL2 0 0 0 0 1 TR2 1 1 1 1 1 T2MOD DECN T2CON EXEN P1.1 T2EX Remarks Internal reload upon overflow reload trigger (falling edge) Down counting Up counting 16-bit Timer/Counter (only up counting) Capture (TH1,TL2) (RCAP2H,RCAP2L) No overflow interrupt request (TF2) Extra External Interrupt (Timer 2) Timer 2 stops fOSC/12 MAX fOSC/24 Input Clock External (P1.0/T2) 0 0 1 1 x 0 1 x x 0 x 0 1 x x x fOSC/12 MAX fOSC/24 fOSC/12 MAX fOSC/24 -- -- Note: = falling edge 54/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 25. Timer 2 in Capture Mode fOSC / 12 C/T2 = 0 TL2 (8 bits) Control TH2 (8 bits) TF2 T2 pin C/T2 = 1 TR2 Capture RCAP2L RCAP2H Timer 2 Interrupt Transition Detector T2EX pin Control EXP2 EXEN2 AI06625 Figure 26. Timer 2 in Auto-Reload Mode fOSC / 12 C/T2 = 0 TL2 (8 bits) Control TH2 (8 bits) TF2 T2 pin C/T2 = 1 TR2 Reload RCAP2L RCAP2H Timer 2 Interrupt Transition Detector T2EX pin Control EXP2 EXEN2 AI06626 55/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV STANDARD SERIAL INTERFACE (UART) The uPSD323X Devices provides two standard 8032 UART serial ports. The first port is connected to pin P3.0 (RX) and P3.1 (TX). The second port is connected to pin P1.2 (RX) and P1.3(TX). The operation of the two serial ports are the same and are controlled by the SCON and SCON2 registers. The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receivebuffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF (or SBUF2 for the second serial port). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0. Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the fOSC. Mode 1. 10 bits are transmitted (through TxD) or received (through RxD): a start Bit (0), 8 data bits (LSB first), and a Stop Bit (1). On receive, the Stop Bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2. 11 bits are transmitted (through TxD) or received (through RxD): start Bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a Stop Bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of '0' or '1.' Or, for example, the Parity Bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the Stop Bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. Mode 3. 11 bits are transmitted (through TxD) or received (through RxD): a start Bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a Stop Bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a Stop Bit. The port can be programmed such that when the Stop Bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting Bit SM2 in SCON. A way to use this feature in multi-processor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is '1' in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An ad-dress byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 Bit and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the Stop Bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid Stop Bit is received. Serial Port Control Register The serial port control and status register is the Special Function Register SCON (SCON2 for the second port), shown in Figure 27., page 61. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the Serial Port Interrupt Bits (TI and RI). Table 43. Serial Port Control Register (SCON) 7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI 56/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 44. Description of the SCON Bits Bit 7 6 Symbol SM0 SM1 Function (SM1,SM0)=(0,0): Shift Register. Baud rate = fOSC/12 (SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable (SM1,SM0)=(0,1): 8-bit UART. Baud rate = fOSC/64 or fOSC/32 (SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.' In Mode 1, if SM2=1, RI will not be activated if a valid Stop Bit was not received. In Mode 0, SM2 should be '0' Enables serial reception. Set by software to enable reception. Clear by software to disable reception The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used Transmit Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the Stop Bit in the other modes, in any serial transmission. Must be cleared by software Receive Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the Stop Bit in the other modes, in any serial reception (except for SM2). Must be cleared by software 5 SM2 4 3 2 REN TB8 RB8 1 TI 0 RI Baud Rates. The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = fOSC / 12 The baud rate in Mode 2 depends on the value of Bit SMOD = 0 (which is the value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = (2SMOD / 64) x fOSC In the uPSD323X Devices, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. Using Timer 1 to Generate Baud Rates. When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows (see: Mode 1,3 Baud Rate = (2SMOD / 32) x (Timer 1 overflow rate) The Timer 1 Interrupt should be disabled in this application. The Timer itself can be configured for either "timer" or "counter" operation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer" operation, in the Auto-reload Mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1,3 Baud Rate = (2SMOD / 32) x (fOSC / (12 x [256 - (TH1)])) One can achieve very low baud rates with Timer 1 by leaving the Timer 1 Interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 Interrupt to do a 16-bit software reload. Figure 22., page 51 lists various commonly used baud rates and how they can be obtained from Timer 1. Using Timer/Counter 2 to Generate Baud Rates. In the uPSD323X Devices, Timer 2 selected as the baud rate generator by setting TCLK and/or RCLK (see Figure 22., page 51 Timer/ Counter 2 Control Register (T2CON)). Note: The baud rate for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer into its Baud Rate Generator Mode. The RCLK and TCLK Bits in the T2CON register configure UART 1. The RCLK1 and TCLK1 Bits in the PCON register configure UART 2. The Baud Rate Generator Mode is similar to the Auto-reload Mode, in that a roll over in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. Now, the baud rates in Modes 1 and 3 are determined at Timer 2's overflow rate as follows: Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16 57/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 45. Timer 1-Generated Commonly Used Baud Rates Baud Rate fOSC SMOD C/T Mode 0 Max: 1MHz Mode 2 Max: 375K Modes 1, 3: 62.5K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 110 110 12MHz 12MHz 12MHz 11.059MHz 11.059MHz 11.059MHz 11.059MHz 11.059MHz 11.059MHz 6MHz 12MHz X 1 1 1 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 Timer 1 Mode X X 2 2 2 2 2 2 2 2 1 Reload Value X X FFh FDh FDh FAh F4h E8h 1Dh 72h FEEBh The timer can be configured for either "timer" or "counter" operation. In the most typical applications, it is configured for "timer" operation (C/T2 = 0). "Timer" operation is a little different for Timer 2 when it's being used as a baud rate generator. Normally, as a timer it would increment every machine cycle (thus at the 1/6 the CPU clock frequency). In the case, the baud rate is given by the formula: Mode 1,3 Baud Rate = fOSC / (32 x [65536 - (RCAP2H, RCAP2L)] where (RCAP2H, RCAP2L) is the content of RC2H and RC2L taken as a 16-bit unsigned integer. Timer 2 also be used as the Baud Rate Generating Mode. This mode is valid only if RCLK + TCLK = 1 in T2CON or in PCON. Note: A roll-over in TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer Interrupt does not have to be disabled when Timer 2 is in the Baud Rate Generator Mode. Note: If EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt, if desired. It should be noted that when Timer 2 is running (TR2 = 1) in "timer" function in the Baud Rate Generator Mode, one should not try to READ or WRITE TH2 or TL2. Under these conditions the timer is being incremented every state time, and the results of a READ or WRITE may not be accurate. The RC registers may be read, but should not be written to, because a WRITE might overlap a reload and cause WRITE and/or reload errors. Turn the timer off (clear TR2) before accessing the Timer 2 or RC registers, in this case. More About Mode 0. Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the fOSC. Figure 27., page 61 shows a simplified functional diagram of the serial port in Mode 0, and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The "WRITE to SBUF" signal at S6P2 also loads a '1' into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "WRITE to SBUF" and activation of SEND. SEND enables the output of the shift register to the alternate out-put function line of RxD and also enable SHIFT CLOCK to the alternate output function line of TxD. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are shifted to the right one position. 58/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1. Both of these actions occur at S1P1. Both of these actions occur at S1P1 of the 10th machine cycle after "WRITE to SBUF." Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternate output function line of TxD. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sampled at the RxD pin at S5P2 of the same machine cycle. As data bits come in from the right, '1s' shift out to the left. When the '0' that was initially loaded into the right-most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the WRITE to SCON that cleared RI, RECEIVE is cleared as RI is set. More About Mode 1. Ten bits are transmitted (through TxD), or received (through RxD): a start Bit (0), 8 data bits (LSB first). and a Stop Bit (1). On receive, the Stop Bit goes into RB8 in SCON. In the uPSD323X Devices the baud rate is determined by the Timer 1 or Timer 2 over-flow rate. Figure 29., page 62 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The "WRITE to SBUF" signal also loads a '1' into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "WRITE to SBUF" signal.) The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after "WRITE to SBUF." Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its roll-overs with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for an-other 1-to0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the reset of the rest of the frame will proceed. As data bits come in from the right, '1s' shift out to the left. When the start bit arrives at the left-most position in the shift register (which in Mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. R1 = 0, and 2. Either SM2 = 0, or the received Stop Bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the Stop Bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. 59/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV More About Modes 2 and 3. Eleven bits are transmitted (through TxD), or received (through RxD): a Start Bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a Stop Bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of '0' or '1.' On receive, the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 the CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. Figure 31., page 63 and Figure 33., page 64 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The "WRITE to SBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next roll-over in the divide-by16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "WRITE to SBUF" signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a '1' (the Stop Bit) into the 9th bit position of the shift register. There-after, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the out-put position of the shift register, then the Stop Bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by 16 rollover after "WRITE to SUBF." Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the Start Bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, '1s' shift out to the left. When the Start Bit arrives at the left-most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input. 60/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 27. Serial Port Mode 0, Block Diagram Internal Bus Write to SBUF DS Q CL SBUF RxD P3.0 Alt Output Function Zero Detector Start Tx Control S6 Serial Port Interrupt Rx Clock REN R1 Start R Tx Clock T Shift Send Shift Clock Receive Shift Rx Control 76543210 RxD P3.0 Alt Input Function Shift SBUF Read SBUF Internal Bus TxD P3.1 Alt Output Function Input Shift Register Load SBUF AI06824 Figure 28. Serial Port Mode 0, Waveforms Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) T Write to SCON RI Receive Shift RxD (Data In) TxD (Shift Clock) Clear RI S6P2 D0 S3P1 D1 S6P1 D2 D3 D4 D5 D6 D7 Transmit Receive D0 D1 D2 D3 D4 D5 D6 D7 AI06825 61/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 29. Serial Port Mode 1, Block Diagram Timer1 Overflow Timer2 Overflow Write to SBUF /2 0 SMOD 0 TCLK /16 Serial Port Interrupt /16 Sample 1-to-0 Transition Detector Rx Clock Start RI Rx Control 1FFh Load SBUF Shift 1 Start Tx Control Tx Clock TI Shift Data Send 1 Internal Bus TB8 DS Q CL SBUF TxD Zero Detector 0 RCLK 1 Rx Detector Input Shift Register RxD Load SBUF SBUF Read SBUF Internal Bus AI06826 Shift Figure 30. Serial Port Mode 1, Waveforms Tx Clock Write to SBUF Send Data Shift TxD T1 Rx Clock RxD Bit Detector Sample Times Shift RI Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit S1P1 Transmit /16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Receive AI06843 62/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 31. Serial Port Mode 2, Block Diagram Phase2 Clock 1/2*fOSC Write to SBUF /2 0 SMOD Start Tx Control /16 Serial Port Interrupt /16 Sample 1-to-0 Transition Detector Rx Clock Start RI Rx Control 1FFh Load SBUF Shift Tx Clock TI Shift Data Send 1 Internal Bus TB8 DS Q CL SBUF TxD Zero Detector Rx Detector Input Shift Register RxD Load SBUF SBUF Read SBUF Internal Bus AI06844 Shift Figure 32. Serial Port Mode 2, Waveforms Tx Clock Write to SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock RxD Bit Detector Sample Times Shift RI Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit S1P1 Transmit /16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Receive AI06845 63/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 33. Serial Port Mode 3, Block Diagram Timer1 Overflow Timer2 Overflow Write to SBUF /2 0 SMOD 0 TCLK /16 Serial Port Interrupt /16 Sample 1-to-0 Transition Detector Rx Clock Start RI Rx Control 1FFh Load SBUF Shift 1 Start Tx Control Tx Clock TI Shift Data Send 1 Internal Bus TB8 DS Q CL SBUF TxD Zero Detector 0 RCLK 1 Rx Detector Input Shift Register RxD Load SBUF SBUF Read SBUF Internal Bus AI06846 Shift Figure 34. Serial Port Mode 3, Waveforms Tx Clock Write to SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock RxD Bit Detector Sample Times Shift RI Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit S1P1 Transmit /16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Receive AI06847 64/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV ANALOG-TO-DIGITAL CONVERTOR (ADC) The analog to digital (A/D) converter allows conversion of an analog input to a corresponding 8-bit digital value. The A/D module has four analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AVREF of ladder resistance of A/D module. The A/D module has two registers which are the control register ACON and A/D result register ADAT. The register ACON, shown in Table 47., page 66, controls the operation of the A/D converter module. To use analog inputs, I/O is selected by P1SFS register. Also an 8-bit prescaler ASCL divides the main system clock input down to approximately 6MHz clock that is required for the ADC logic. Appropriate values need to be loaded into the prescaler based upon the main MCU clock frequency prior to use. The processing of conversion starts when the Start Bit ADST is set to '1.' After one cycle, it is cleared by hardware. The register ADAT contains the results of the A/D conversion. When conversion is completed, the result is loaded into the ADAT the A/D Conversion Status Bit ADSF is set to '1.' The block diagram of the A/D module is shown in Figure 35. The A/D Status Bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The ASCL should be loaded with a value that results in a clock rate of approximately 6MHz for the ADC using the following formula: ADC clock input = (fOSC / 2) / (Prescaler register value +1) Where fOSC is the MCU clock input frequency The conversion time for the ADC can be calculated as follows: ADC Conversion Time = 8 clock * 8bits * (ADC Clock) ~= 10.67usec (at 6MHz) ADC Interrupt The ADSF Bit in the ACON register is set to '1' when the A/D conversion is complete. The status bit can be driven by the MCU, or it can be configured to generate a falling edge interrupt when the conversion is complete. The ADSF Interrupt is enabled by setting the ADSFINT Bit in the PCON register. Once the bit is set, the external INT1 Interrupt is disabled and the ADSF Interrupt takes over as INT1. INT1 must be configured as if it is an edge interrupt input. The INP1 pin (p3.3) is available for general I/O functions, or Timer1 gate control. Figure 35. A/D Block Diagram AVREF Ladder Resistor Decode ACH0 ACH1 ACH2 ACH3 Input MUX S/H Successive Approximation Circuit Conversion Complete Interrupt ACON ADAT INTERNAL BUS AI06627 65/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 46. ADC SFR Memory Map SFR Addr Reg Name Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value 8-bit Prescaler for ADC clock ADC Data Register ADC Control Register 95 ASCL 00 96 97 ADAT ACON ADAT7 ADAT6 ADAT5 ADEN ADAT4 ADAT3 ADS1 ADAT2 ADS0 ADAT1 ADST ADAT0 ADSF 00 00 Table 47. Description of the ACON Bits Bit 7 to 6 5 4 Symbol -- ADEN -- Reserved ADC Enable Bit: 0 : ADC shut off and consumes no operating current 1 : enable ADC Reserved Function ADS1, ADS0 Analog channel select 3 to 2 0, 0, 1, 1, 0 1 0 1 Channel0 Channel1 Channel2 Channel3 (ACH0) (ACH1) (ACH2) (ACH3) 0 : force to zero 1 : start an ADC; after one cycle, bit is cleared to '0' 0 : A/D conversion is in process 1 : A/D conversion is completed, not in process 1 0 ADST ADSF ADC Start Bit: ADC Status Bit: Table 48. ADC Clock Input MCU Clock Frequency 40MHz 36MHz 24MHz 12MHz Prescaler Register Value 2 2 1 0 ADC Clock 6.7MHz 6MHz 6MHz 6MHz 66/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PULSE WIDTH MODULATION (PWM) The PWM block has the following features: Four-channel, 8-bit PWM unit with 16-bit prescaler One-channel, 8-bit unit with programmable frequency and pulse width PWM Output with programmable polarity 4-channel PWM Unit (PWM 0-3) The 8-bit counter of a PWM counts module 256 (i.e., from 0 to 255, inclusive). The value held in the 8-bit counter is compared to the contents of the Special Function Register (PWM 0-3) of the corresponding PWM. The polarity of the PWM outputs is programmable and selected by the PWML Bit in PWMCON register. Provided the contents of a PWM 0-3 register is greater than the counter value, the corresponding PWM output is set HIGH (with PWML = 0). When the contents of this register is less than or equal to the counter value, the corresponding PWM output is set LOW (with PWML = 0). The pulse-width-ratio is therefore deFigure 36. Four-Channel 8-bit PWM Block Diagram DATA BUS 8 x4 8 fined by the contents of the corresponding Special Function Register (PWM 0-3) of a PWM. By loading the corresponding Special Function Register (PWM 0-3) with either 00H or FFH, the PWM output can be retained at a constant HIGH or LOW level respectively (with PWML = 0). For each PWM unit, there is a 16-bit Prescaler that are used to divide the main system clock to form the input clock for the corresponding PWM unit. This prescaler is used to define the desired repetition rate for the PWM unit. SFR registers B1h B2h are used to hold the 16-bit divisor values. The repetition frequency of the PWM output is given by: fPWM8 = (fOSC / prescaler0) / (2 x 256) And the input clock frequency to the PWM counters is = fOSC / 2 / (prescaler data value + 1) See I/O PORTS (MCU MODULE), page 42 for more information on how to configure the Port 4 pin as PWM output. CPU rd/wr 8-bit PWM0-PWM3 Data Registers x4 8 CPU rd/wr 16-bit Prescaler Register (B2h,B1h) 16 fOSC/2 16-bit Prescaler Counter clock load 8 load 8-bit PWM0-PWM3 Comparators Registers x4 Port4.3 Port4.4 Port4.5 Port4.6 8-bit PWM0-PWM3 Comparators 8-bit Counter Overflow 8 4 PWMCON bit7 (PWML) 8 PWMCON bit5 (PWME) AI06647 67/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 49. PWM SFR Memory Map SFR Reg Name Addr Bit Register Name 7 PWML 6 PWMP 5 PWME 4 CFG4 3 CFG3 2 CFG2 1 CFG1 0 CFG0 Reset Value Comment s PWM Control Polarity PWM0 Output Duty Cycle PWM1 Output Duty Cycle PWM2 Output Duty Cycle PWM3 Output Duty Cycle PWM 4 Period PWM 4 Pulse Width Prescaler 0 Low (8-bit) Prescaler 0 High (8-bit) Prescaler 1 Low (8-bit) Prescaler 1 High (8-bit) A1 PWMCON 00 A2 PWM0 00 A3 PWM1 00 A4 PWM2 00 A5 PWM3 00 AA PWM4P 00 AB PWM4W 00 B1 B2 B3 B4 PSCL0L PSCL0H PSCL1L PSCL1H 00 00 00 00 PWMCON Register Bit Definition: - PWML = PWM 0-3 polarity control - PWMP = PWM 4 polarity control - PWME = PWM enable (0 = disabled, 1= enabled) - - CFG3..CFG0 = PWM 0-3 Output (0 = Open Drain; 1 = Push-Pull) CFG4 = PWM 4 Output (0 = Open Drain; 1 = Push-Pull) 68/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Programmable Period 8-bit PWM The PWM 4 channel can be programmed to provide a PWM output with variable pulse width and period. The PWM 4 has a 16-bit Prescaler, an 8bit Counter, a Pulse Width Register, and a Period Register. The Pulse Width Register defines the PWM pulse width time, while the Period Register defines the period of the PWM. The input clock to the Prescaler is fOSC/2. The PWM 4 channel is assigned to Port 4.7. Figure 37. Programmable PWM 4 Channel Block Diagram DATA BUS 8 8 8 CPU RD/WR 8 8-bit PWM4P Register (Period) 8-bit PWM4W Register (Width) 8 8 CPU RD/WR 16-bit Prescaler Register (B4h, B3h) 8-bit PWM4 Comparator Register PWM4 Control 8-bit PWM4 Comparator Register Load Port 4.7 8 8 16 fOSC / 2 16-bit Prescaler Counter Load PWMCON Bit 5 (PWME) 8-bit Counter Clock Reset AI07091 8-bit PWM4 Comparator Match 8-bit PWM4 Comparator PWMCON Bit 6 (PWMP) 8 8 69/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PWM 4 Channel Operation The 16-bit Prescaler1 divides the input clock (fOSC/2) to the desired frequency, the resulting clock runs the 8-bit Counter of the PWM 4 channel. The input clock frequency to the PWM 4 Counter is: f PWM4 = (fOSC/2)/(Prescaler1 data value +1) When the Prescaler1 Register (B4h, B3h) is set to data value '0,' the maximum input clock frequency to the PWM 4 Counter is fOSC/2 and can be as high as 20MHz. The PWM 4 Counter is a free-running, 8-bit counter. The output of the counter is compared to the Compare Registers, which are loaded with data from the Pulse Width Register (PWM4W, ABh) and the Period Register (PWM4P, AAh). The Pulse Width Register defines the pulse duration or the Pulse Width, while the Period Register defines the period of the PWM. When the PWM 4 channel is enabled, the register values are loaded into the Comparator Registers and are compared to the Counter output. When the content of the counter is equal to or greater than the value in the Pulse Width Register, it sets the PWM 4 output to low (with PWMP Bit = 0). When the Period Register equals to the PWM4 Counter, the Counter is cleared, and the PWM 4 channel output is set to logic 'high' level (beginning of the next PWM pulse). The Period Register cannot have a value of "00" and its content should always be greater than the Pulse Width Register. The Prescaler1 Register, Pulse Width Register, and Period Register can be modified while the PWM 4 channel is active. The values of these registers are automatically loaded into the Prescaler Counter and Comparator Registers when the current PWM 4 period ends. The PWMCON Register (Bits 5 and 6) controls the enable/disable and polarity of the PWM 4 channel. Figure 38. PWM 4 With Programmable Pulse Width and Frequency Defined by Period Register PWM4 Defined by Pulse Width Register Switch Level RESET Counter AI07090 70/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV I2C INTERFACE There are two serial I2C ports implemented in the uPSD323X Devices. The serial port supports the twin line I2C-bus, consists of a data line (SDAx) and a clock line (SCLx). Depending on the configuration, the SDA and SCL lines may require pull-up resistors. SDA1, SCL1: the serial port line for DDC Protocol SDA2, SCL2: the serial port line for general I2C bus connection In both I2C interfaces, these lines also function as I/O port lines as follows. SDA1 / P4.0, SCL1 / P4.1, SDA2 / P3.6, SCL2 / P3.7 The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. Figure 39. Block Diagram of the I2C Bus Serial I/O The I2C serial I/O has complete autonomy in byte handling and operates in 4 modes. Master transmitter Master receiver Slave transmitter Slave receiver These functions are controlled by the SFRs. SxCON: the control of byte handling and the operation of 4 mode. SxSTA: the contents of its register may also be used as a vector to various service routines. SxDAT: data shift register. SxADR: slave address register. Slave address recognition is performed by On-Chip H/W. 7 Slave Address 7 SDAx Shift Register Arbitration and Sync. Logic 0 0 Internal Bus SCLx 7 Bus Clock Generator 0 Control Register 7 Status Register 0 AI06649 Table 50. Serial Control Register (SxCON: S1CON, S2CON) 7 CR2 6 ENII 5 STA 4 STO 3 ADDR 2 AA 1 CR1 0 CR0 71/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 51. Description of the SxCON Bits Bit 7 6 Symbol CR2 ENII Function This bit along with Bits CR1and CR0 determines the serial clock frequency when SIO is in the Master Mode. Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high impedance state. START flag. When this bit is set, the SIO H/W checks the status of the I2C-bus and generates a START condition if the bus free. If the bus is busy, the SIO will generate a repeated START condition when this bit is set. STOP flag. With this bit set while in Master Mode a STOP condition is generated. When a STOP condition is detected on the I2C-bus, the I2C hardware clears the STO flag. Note: This bit have to be set before 1 cycle interrupt period of STOP. That is, if this bit is set, STOP condition in Master Mode is generated after 1 cycle interrupt period. This bit is set when address byte was received. Must be cleared by software. Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA) is returned during the acknowledge clock pulse on the SCL line when: * Own slave address is received * A data byte is received while the device is programmed to be a Master Receiver * A data byte is received while the device is a selected Slave Receiver. When this bit is reset, no acknowledge is returned. SIO release SDA line as high during the acknowledge clock pulse. These two bits along with the CR2 Bit determine the serial clock frequency when SIO is in the Master Mode. 5 STA 4 STO 3 ADDR 2 AA 1 0 CR1 CR0 Table 52. Selection of the Serial Clock Frequency SCL in Master Mode CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 fOSC Divisor 12MHz 16 24 30 60 120 240 480 960 375 250 200 100 50 25 12.5 6.25 Bit Rate (kHz) at fOSC 24MHz 750 500 400 200 100 50 25 12.5 36MHz X 750 600 300 150 75 37.5 18.75 40MHz X 833 666 333 166 83 41 20 72/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Serial Status Register (SxSTA: S1STA, S2STA) SxSTA is a "Read-only" register. The contents of this register may be used as a vector to a service routine. This optimized the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2Cbus interface are given Table 54. This flag is set, and an interrupt is generated, after any of the following events occur. 1. Own slave address has been received during AA = 1: ack_int 2. The general call address has been received while GC(SxADR.0) = 1 and AA = 1: Table 53. Serial Status Register (SxSTA) 7 GC 6 STOP 5 INTR 4 TX_MODE 3 BBUSY 2 BLOST 1 /ACK_REP 0 SLV 3. A data byte has been received or transmitted in Master Mode (even if arbitration is lost): ack_int 4. A data byte has been received or transmitted as selected slave: ack_int 5. A stop condition is received as selected slave receiver or transmitter: stop_int Data Shift Register (SxDAT: S1DAT, S2DAT) SxDAT contains the serial data to be transmitted or data which has just been received. The MSB (Bit 7) is transmitted or received first; that is, data shifted from right to left. Table 54. Description of the SxSTA Bits Bit 7 6 5 4 3 2 Symbol GC STOP INTR(1,2) TX_MODE BBUSY BLOST General Call Flag Stop Flag. This bit is set when a STOP condition is received Interrupt Flag. This bit is set when an IC Interrupt condition is requested Transmission Mode Flag. This bit is set when the IC is a transmitter; otherwise this bit is reset Bus Busy Flag. This bit is set when the bus is being used by another master; otherwise, this bit is reset Bus Lost Flag. This bit is set when the master loses the bus contention; otherwise this bit is reset Acknowledge Response Flag. This bit is set when the receiver transmits the not acknowledge signal This bit is reset when the receiver transmits the acknowledge signal Slave Mode Flag. This bit is set when the IC plays role in the Slave Mode; otherwise this bit is reset Function 1 /ACK_REP 0 SLV Note: 1. Interrupt Flag Bit (INTR, SxSTA Bit 5) is cleared by Hardware as reading SxSTA register. 2. I2C Interrupt Flag (INTR) can occur in below case. (except DDC2B Mode at SWENB=0) Table 55. Data Shift Register (SxDAT: S1DAT, S2DAT) 7 SxDAT7 6 SxDAT6 5 SxDAT5 4 SxDAT4 3 SxDAT3 2 SxDAT2 1 SxDAT1 0 SxDAT0 73/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Address Register (SxADR: S1ADR, S2ADR) This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receive/transmitter. The Start/Stop Hold Time Detection and System Clock registers (Tables 57 and 58) are included in Table 56. Address Register (SxADR) 7 SLA6 6 SLA5 5 SLA4 4 SLA3 3 SLA2 2 SLA1 1 SLA0 0 -- the I2C unit to specify the start/stop detection time to work with the large range of MCU frequency values supported. For example, with a system clock of 40MHz. Note: 1. SLA6 to SLA0: Own slave address. Table 57. Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP) Address D1h SFR D2h S2SETUP 00h To control the start/stop hold time detection for the multi-master IC module in Slave Mode Register Name S1SETUP Reset Value 00h Note To control the start/stop hold time detection for the DDC module in Slave Mode Table 58. System Cock of 40MHz S1SETUP, S2SETUP Register Value 00h 80h 81h 82h ... 8Bh ... FFh Number of Sample Clock (fOSC/2 -> 50ns) 1EA 1EA 2EA 3EA ... 12EA ... 128EA Required Start/ Stop Hold Time 50ns 50ns 100ns 150ns ... 600ns ... 6000ns Fast Mode IC Start/Stop hold time specification Note When Bit 7 (enable bit) = 0, the number of sample clock is 1EA (ignore Bit 6 to Bit 0) Table 59. System Clock Setup Examples System Clock 40MHz (fOSC/2 -> 50ns) 30MHz (fOSC/2 -> 66.6ns) 20MHz (fOSC/2 -> 100ns) 8MHz (fOSC/2 -> 250ns) S1SETUP, S2SETUP Register Value 8Bh 89h 86h 83h Number of Sample Clock 12 EA 9 EA 6 EA 3 EA Required Start/Stop Hold Time 600ns 600ns 600ns 750ns 74/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV DDC INTERFACE The basic DDC unit consists of an I2C interface and 256 bytes of SRAM for DDC data storage. The 8032 core is responsible of loading the contents of the SRAM with the DDC data. The DDC unit has the following features: - Supports both DDC1 and DDC2b Modes. - Features 256 bytes of DDC data - initialized by the 8032 Supports fully automatic operation of DDC1 and DDC2b Modes - DDC operates in Slave Mode only. - SW Interrupt Mode available (existing design) The interface signals for the DDC can be mapped to pins in Port 4. The interface consists of the standard VSYNC (P4.2), SDA (P4.0) and SCL (P4.1) DDC signals. The conceptual block diagram is illustrated in Figure 43. - Figure 40. DDC Interface Block Diagram DDC2B/DDC2AB DDC2B+Interface 7 Monitor Address S1ADR0 Monitor Address S1ADR1 1 0 SDA1 S1DAT Arbitration Logic SCL1 Shift Register Bus Clock Generator Internal Bus SICON RAMBUF SISTA DDC1/DDC2 Detection DDC1 Hold Register DDCDAT DDC1 Transmitter RAM Buffer VSYNCEN Address Pointer Initialization Synchronization DDCADR X EX_ SW DAT ENB X DDC1 DDC1 SWH INT EN INT M0 INTR (from SISTA) DDCCON INT AI06628 75/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Special Function Register for the DDC Interface There are eight SFR in the DDC interface: RAMBUF, DDCCON, DDCADR, DDCDAT are DDC registers. S1CON, S1STA, S1DAT, S1ADR are I2C Interface registers, same as the ones described in the standalone I2C bus. DDCDAT Register. DDC1 DATA register for transmission (DDCDAT: 0D5H) 8-bit READ and WRITE register. Indicates DATA BYTE to be transmitted in DDC1 protocol. Table 60. DDC SFR Memory Map SFR Addr Reg Name Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value XX 00 00 -- EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT M0 00 DDC Ram Buffer DDC Data xmit register Addr pointer register DDC Control Register DDCADR Register. Address pointer for DDC interface (DDCADR: 0D6H) 8-bit READ and WRITE register. Address pointer with the capability of the post increment. After each access to RAMBUF register (either by software or by hardware DDC1 interface), the content of this register will be increased by one. It's available both in DDC1, DDC2 (DDC2B, DDC2B+, and DDC2AB) and system operation. D4 RAMBUF D5 DDCDAT D6 DDCADR D7 DDCCON 76/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 61. Description of the DDCON Register Bits Bit 7 6 Symbol -- EX_DAT Reserved 0 = The SRAM has 128 bytes (Default) 1 = The SRAM has 256 bytes Note: This bit is valid for DDC1 & DDC2b Modes 0 = Data is automatically read from SRAM at the current location of DDCADR and sent out via current DDC protocol. (Default) 1 = MCU is interrupted during the current data byte transmission period to load the next byte of data to send out. Note: This bit is valid for DDC1 & DDC2b Modes 0 = Data is automatically read from SRAM at the current location of DDCADR and sent out via current DDC protocol. (Default) 1 = MCU is interrupted during the current data byte transmission period to load the next byte of data to send out. This bit only affects DDC2b Mode Operation: 0 = DDC2b I2C Address is A0/A1 (default) 1 = DDC2b I2C Address is AX. Least 3 significant address bits are ignored. For DDC1 Mode Operation Only: 0 = No DDC1 Interrupt 1 = DDC1 Interrupt request. Set by HW and should be cleared by SW interrupt service routine. Note1: This bit is set in the 9th VCLK at DDC1 Enable Mode. (SWENB=1) 0 = DDC1 Mode is disabled - VSYNC is ignored. The DDC unit will still respond to DDC2b requests. -provided I2C enabled.(Default) 1 = DDC1 Mode is enabled. Set by hardware when the DDC unit switches from DDC1 to DDC2b Modes. 0 = No interrupt request. 1 = Switch to DDC2b Mode (Interrupt pending) Set by HW and should be cleared by SW interrupt service routine. Note1: This bit has no connection with SWENB. Current Mode Indication Bit: 0 = Unit is in DDC1 Mode 1 = Unit is in DDC2b Mode Note: When the DDC unit transitions to DDC2b Mode, the DDC unit will stay in DDC2b Mode until the DDC unit is disabled, or the system is reset. Function 5 SWENB 4 DDC_AX 3 DDC1_Int 2 DDC1EN 1 SWHINT 0 Mode 77/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 62. SWNEB Bit Function DDC1 or DDC2b Mode Disabled SWENB DDCCON.bit2 = 0 (DDC1 Mode Disable) or S1CON.bit6 = 0 (I2C Mode Disable) In this state, the DDC unit is disabled. The DDC SRAM cannot be accessed by the MCU. No MCU interrupt and no DDC activity will occur. MCU cannot access internal DDC SRAM: DDC SRAM address space is re-assigned to external data space. In this state, the DDC unit is disabled, BUT with SWENB=1, the MCU can access the SRAM. This state is used to load the DDC SRAM with the correct data for automatic modes. No MCU interrupt and no DDC activity will occur. MCU can access DDC SRAM: data space FF00hFFFFh is dedicated to DDC SRAM. DDC1 or DDC2b Mode Enabled DDCCON.bit2 = 1 (DDC1 Mode Enable) or S1CON.bit6 = 1 (I2C Mode Enable) In this state, the DDC is enabled and the unit is in automatic mode. The DDC SRAM cannot be accessed by the MCU - only the DDC unit has access. MCU cannot access internal DDC SRAM: data space FF00h-FFFFh is dedicated to DDC SRAM. In this state, the DDC SRAM can be accessed by the MCU. The DDC unit does not use the DDC SRAM when SWENB=1. Since the DDC unit is in manual mode, the DDC unit generates an MCU interrupt for each byte transferred. The byte transferred is held in the I2C S1DAT SFR register. MCU can access DDC SRAM. 0 1 78/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Host Type Detection The detection procedure conforms to the sequences proposed by VESA Monitor Display Data Channel (DDC) specification. The monitor needs to determine the type of host system: Figure 41. Host Type Detection DDC1 or OLD type host. DDC2B host (Host is master, monitor is always slave) DDC2B+/DDC2AB(ACCESS.bus) host. Power on Communication isidle Is VSYNC present? EDID sent continously using VSYNC as clock Is DDC2 clock present? Stop sending of EDID switch to DDC2 communication mode DDC2 communication is idle. Has a command been received? Is 2B+/A.B command detected? Is it DDC2B command? Is DDC2B+/DDC2AB? Respond to DDC2B command Respond to DDC2B+/ DDC2AB command AI06644 79/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV DDC1 Protocol DDC1 is primitive and a point to point interface. The monitor is always put at "Transmit only" mode. In the initialization phase, 9 clock cycles on VCLK pin will be given for the internal synchronization. During this period, the SDA pin will be kept at high impedance state. If DDC1 hardware mode is used, the following procedure is recommended to proceed DDC1 operation. 1. Reset DDC1 enable (by default, DDC1 enable is cleared as LOW after Power-on Reset). 2. Set SWENB as high (the default value is zero.) 3. Depending on the data size of EDID data, set EX_DAT as LOW (128 bytes) or HIGH (256 bytes). 4. By using bulky moving commands (DDCADR, RAMBUF involved) to move the entire EDID data to RAM buffer. 5. Reset SWENB to LOW. 6. Reset DDCADR to 00h. 7. Set DDC1 enable as HIGH. In case SWENB is set as high, interrupt service routine is finished within 133 machine cycle in 40MHz System clock. The maximum VSYNC (VCLK) frequency is 25Khz (40s). And the 9th clock of VSYNC (VCLK) is interrupt period. So the machine cycle be needed is calculated as below. For example, When 40MHz system clock, 40s = 133 x (25ns x 12); 133 machine cycle. 12MHz system clock, 40s = 40 x (83.3ns x 12); 40 machine cycle. 8MHz system clock, 40s = 26 x (125ns x 12); 26 machine cycle. Note: If EX_DAT equals to LOW, it is meant the lower part is occupied by DDC1 operation and the upper part is still free to the system. Nevertheless, the effect of the post increment just applies to the part related to DDC1 operation. In other words, the system program is still able to address the locations from 128 to 255 in the RAM buffer through MOVX command but without the facility of the post increment. For example, the case of accessing 200 of the RAM Buffer: MOV R0, #200, and MOVX A, @R0 Figure 42. Transmission Protocol in the DDC1 Interface Max=40us SC VCLK DDC1INT DDC1EN SD Hi-Z B B B B B B B B HiZ B 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 tSU(DDC1) t H(VCLK) t L(VCLK) t DOV AI06652 80/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV DDC2B Protocol DDC2B is constructed based on the Philips I2C interface. However, in the level of DDC2B, PC host is fixed as the master and the monitor is always regarded as the slave. Both master and slave can be operated as a transmitter or receiver, but the master device determines which mode is activated. In this protocol, address pointer is also used. According to DDC2B specification, A0 (for WRITE Mode) and A1 (for READ Mode) are assigned as the default address of monitors. The reception of the incoming data in WRITE Mode or the updating of the outgoing data in READ Mode should be finished within the specified time limit. If software in the slave's side cannot react to the master in time, based on I2C protocol, SCL pin can be stretched low to inhibit the further action from the master. The transaction can be proceeded in either byte or burst format. Figure 43. Conceptual Structure of the DDC Interface DDC Interrupt vector address ( 0023H ) Check Mode flag in DDCCON Mode = 1 Mode = 1 Mode = 0 DDC2B/DDC2AB command received SWENB =1 DDC2B/DDC2AB Utilities DDC2B SWENB =1 DDC2B Utilities SWENB =0 DDC1.DDC2B Utilities I2C ServiceRoutines DDC Transmitter (H/W) I2C interface (H/W) AI06645 81/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV USB HARDWARE The characteristics of USB hardware are as follows: Complies with the Universal Serial Bus specification Rev. 1.1 Integrated SIE (Serial Interface Engine), FIFO memory and transceiver Low speed (1.5Mbit/s) device capability Supports control endpoint0 and interrupt endpoint1 and 2 USB clock input must be 6MHz (requires MCU clock frequency to be 12, 24, or 36MHz). The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels equal to VDD from the standard logic to interface with the physical layer of the Universal Serial Bus. It is capable of receiving and transmitting serial data at low speed (1.5Mb/s). The SIE is the digital-front-end of the USB block. This module recovers the 1.5MHz clock, detects the USB sync word and handles all low-level USB protocols and error checking. The bit-clock recovery circuit recovers the clock from the incoming Table 63. USB Address Register (UADR: 0EEh) 7 USBEN 6 UADD6 5 UADD5 4 UADD4 3 UADD3 2 UADD2 1 UADD1 0 UADD0 USB data stream and is able to track jitter and frequency drift according to the USB specification. The SIE also translates the electrical USB signals into bytes or signals. Depending upon the device USB address and the USB endpoint. Address, the USB data is directed to the correct endpoint on SIE interface. The data transfer of this H/W could be of type control or interrupt. The device's USB address and the enabling of the endpoints are programmable in the SIE configuration header. USB related registers The USB block is controlled via seven registers in the memory: (UADR, UCON0, UCON1, UCON2, UISTA, UIEN, and USTA). Three memory locations on chip which communicate the USB block are: USB endpoint0 data transmit register (UDT0) USB endpoint0 data receive register (UDR0) USB endpoint1 data transmit register (UDT1) Table 64. Description of the UADR Bits Bit Symbol R/W Function USB Function Enable Bit. When USBEN is clear, the USB module will not respond to any tokens from host. RESET clears this bit. Specify the USB address of the device. RESET clears these bits. 7 USBEN R/W 6 to 0 UADD6 to UADD0 R/W Table 65. USB Interrupt Enable Register (UIEN: 0E9h) 7 SUSPNDI 6 RSTE 5 RSTFIE 4 TXD0IE 3 RXD0IE 2 TXD1IE 1 EOPIE 0 RESUMI 82/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 66. Description of the UIEN Bits Bit 7 6 5 4 3 2 1 0 Symbol SUSPNDI RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMI R/W R/W R/W R/W R/W R/W R/W R/W R/W Enable SUSPND Interrupt Enable USB Reset; also resets the CPU and PSD Modules when bit is set to '1.' Enable RSTF (USB Bus Reset Flag) Interrupt Enable TXD0 Interrupt Enable RXD0 Interrupt Enable TXD1 Interrupt Enable EOP Interrupt Enable USB Resume Interrupt when it is the Suspend Mode Function Table 67. USB Interrupt Status Register (UISTA: 0E8h) 7 SUSPND 6 -- 5 RSTF 4 TXD0F 3 RXD0F 2 TXD1F 1 EOPF 0 RESUMF 83/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 68. Description of the UISTA Bits Bit Symbol R/W Function USB Suspend Mode Flag. To save power, this bit should be set if a 3ms constant idle state is detected on USB bus. Setting this bit stops the clock to the USB and causes the USB module to enter Suspend Mode. Software must clear this bit after the Resume flag (RESUMF) is set while this Resume Interrupt Flag is serviced Reserved USB Reset Flag. This bit is set when a valid RESET signal state is detected on the D+ and D- lines. When the RSTE bit in the UIEN Register is set, this reset detection will also generate an internal reset signal to reset the CPU and other peripherals including the USB module. Endpoint0 Data Transmit Flag. This bit is set after the data stored in Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag. To enable the next data packet transmission, TX0E must also be set. If TXD0F Bit is not cleared, a NAK handshake will be returned in the next IN transactions. RESET clears this bit. Endpoint0 Data Receive Flag. This bit is set after the USB module has received a data packet and responded with ACK handshake packet. Software must clear this flag after all of the received data has been read. Software must also set RX0E Bit to one to enable the next data packet reception. If RXD0F Bit is not cleared, a NAK handshake will be returned in the next OUT transaction. RESET clears this bit. Endpoint1 / Endpoint2 Data Transmit Flag. This bit is shared by Endpoints 1 and Endpoints 2. It is set after the data stored in the shared Endpoint 1/ Endpoint 2 transmit buffer has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag. To enable the next data packet transmission, TX1E must also be set. If TXD1F Bit is not cleared, a NAK handshake will be returned in the next IN transaction. RESET clears this bit. End of Packet Flag. This bit is set when a valid End of Packet sequence is detected on the D+ and D-line. Software must clear this flag. RESET clears this bit. Resume Flag. This bit is set when USB bus activity is detected while the SUSPND Bit is set. Software must clear this flag. RESET clears this bit. 7 SUSPND R/W 6 -- -- 5 RSTF R 4 TXD0F R/W 3 RXD0F R/W 2 TXD1F R/W 1 EOPF R/W 0 RESUMF R/W Table 69. USB Endpoint0 Transmit Control Register (UCON0: 0EAh) 7 TSEQ0 6 STALL0 5 TX0E 4 RX0E 3 TP0SIZ3 2 TP0SIZ2 1 TP0SIZ1 0 TP0SIZ0 84/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 70. Description of the UCON0 Bits Bit Symbol R/W Function Endpoint0 Data Sequence Bit. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction. Toggling of this bit must be controlled by software. RESET clears this bit Endpoint0 Force Stall Bit. This bit causes Endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. The USB hardware clears this bit when a SETUP token is received. RESET clears this bit. Endpoint0 Transmit Enable. This bit enables a transmit to occur when the USB Host Controller sends an IN token to Endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more Endpoint 0 data needs to be transmitted. If this bit is '0' or the TXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 IN tokens. RESET clears this bit. Endpoint0 receive enable. This bit enables a receive to occur when the USB Host Controller sends an OUT token to Endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is '0' or the RXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 OUT tokens. RESET clears this bit. The number of transmit data bytes. These bits are cleared by RESET. 7 TSEQ0 R/W 6 STALL0 R/W 5 TX0E R/W 4 RX0E R/W 3 to 0 TP0SIZ3 to TP0SIZ0 R/W Table 71. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh) 7 TSEQ1 6 EP12SEL 5 TX1E 4 FRESUM 3 TP1SIZ3 2 TP1SIZ2 1 TP1SIZ1 0 TP1SIZ0 85/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 72. Description of the UCON1 Bits Bit Symbol R/W Function Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2. Toggling of this bit must be controlled by software. RESET clears this bit. Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1, 1=Endpoint 2) This bit specifies whether the data inside the registers UDT1 are used for Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2 USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1, STALL2=0, and EP2E=1) except that the EP12SEL Bit is configured for Endpoint 1, the USB responds with a NAK handshake packet. RESET clears this bit. Endpoint1 / Endpoint2 Transmit Enable. This bit enables a transmit to occur when the USB Host Controller send an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint enable bit, EP1E or EP2E Bit in the UCON2 register, should also be set. Software should set the TX1E Bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted. If this bit is '0' or TXD1F is set, the USB will respond with a NAK handshake to any Endpoint 1 or Endpoint 2 directed IN token. RESET clears this bit. Force Resume. This bit forces a resume state ("K" on non-idle state) on the USB data lines to initiate a remote wake-up. Software should control the timing of the forced resume to be between 10ms and 15ms. Setting this bit will not cause the RESUMF Bit to set. The number of transmit data bytes. These bits are cleared by RESET. 7 TSEQ1 R/W 6 EP12SEL R/W 5 TX1E R/W 4 FRESUM R/W 3 to 0 TP1SIZ3 to TP1SIZ0 R/W Table 73. USB Control Register (UCON2: 0ECh) 7 -- 6 -- 5 -- 4 SOUT 3 EP2E 2 EP1E 1 STALL2 0 STALL1 Table 74. Description of the UCON2 Bits Bit 7 to 5 4 3 2 1 0 Symbol -- SOUT EP2E EP1E STALL2 STALL1 R/W -- R/W R/W R/W R/W R/W Reserved Status out is used to automatically respond to the OUT of a control READ transfer Endpoint2 enable. RESET clears this bit Endpoint1 enable. RESET clears this bit Endpoint2 Force Stall Bit. RESET clears this bit Endpoint1 Force Stall Bit. RESET clears this bit Function Table 75. USB Endpoint0 Status Register (USTA: 0EDh) 7 RSEQ 6 SETUP 5 IN 4 OUT 3 RP0SIZ3 2 RP0SIZ2 1 RP0SIZ1 0 RP0SIZ0 86/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 76. Description of the USTA Bits Bit 7 Symbol RSEQ R/W R/W Function Endpoint0 receive data packet PID. (0=DATA0, 1=DATA1) This bit will be compared with the type of data packet last received for Endpoint0 SETUP Token Detect Bit. This bit is set when the received token packet is a SEPUP token, PID = b1101. IN Token Detect Bit. This bit is set when the received token packet is an IN token. OUT Token Detect Bit. This bit is set when the received token packet is an OUT token. The number of data bytes received in a DATA packet 6 5 4 3 to 0 SETUP IN OUT RP0SIZ3 to RP0SIZ0 R R R R Table 77. USB Endpoint0 Data Receive Register (UDR0: 0EFh) 7 UDR0.7 6 UDR0.6 5 UDR0.5 4 UDR0.4 3 UDR0.3 2 UDR0.2 1 UDR0.1 0 UDR0.0 Table 78. USB Endpoint0 Data Transmit Register (UDT0: 0E7h) 7 UDT0.7 6 UDT0.6 5 UDT0.5 4 UDT0.4 3 UDT0.3 2 UDT0.2 1 UDT0.1 0 UDT0.0 Table 79. USB Endpoint1 Data Transmit Register (UDT1: 0E6h) 7 UDT1.7 6 UDT1.6 5 UDT1.5 4 UDT1.4 3 UDT1.3 2 UDT1.2 1 UDT1.1 0 UDT1.0 87/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV The USCL 8-bit Prescaler Register for USB is at E1h. The USCL should be loaded with a value that results in a clock rate of 6MHz for the USB using the following formula: USB clock input = (fOSC / 2) / (Prescaler register value +1) Where fOSC is the MCU clock input frequency. Table 80. USB SFR Memory Map SFR Reg Addr Name Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value 8-bit Prescaler for USB logic USB Endpt1 Data Xmit USB Endpt0 Data Xmit USB Interrupt Status USB Interrupt Enable USB Endpt0 Xmit Control USB Endpt1 Xmit Control USB Control Register USB Endpt0 Status USB Address Register USB Endpt0 Data Recv Note: USB works ONLY with the MCU Clock frequencies of 12, 24, or 36MHz. The Prescaler values for these frequencies are 0, 1, and 2. E1 USCL 00 E6 E7 UDT1 UDT0 UDT1.7 UDT0.7 UDT1.6 UDT0.6 UDT1.5 UDT0.5 UDT1.4 UDT0.4 UDT1.3 UDT0.3 UDT1.2 UDT0.2 UDT1.1 UDT0.1 UDT1.0 UDT0.0 00 00 E8 UISTA SUSPND -- RSTF TXD0F RXD0F RXD1F EOPF RESUMF 00 E9 UIEN SUSPNDIE RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMIE 00 EA UCON0 EB UCON1 EC UCON2 ED USTA TSEQ0 TSEQ1 -- RSEQ STALL0 EP12SEL -- SETUP TX0E -- -- IN RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 00 00 00 00 FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 SOUT OUT EP2E EP1E STALL2 STALL1 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 EE UADR USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 00 EF UDR0 UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0 00 88/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Transceiver USB Physical Layer Characteristics. The following section describes the uPSD323X Devices compliance to the Chapter 7 Electrical section of the USB Specification, Revision 1.1. The section contains all signaling, and physical layer specifications necessary to describe a low speed USB function. Low Speed Driver Characteristics. The uPSD323X Devices use a differential output driver to drive the Low Speed USB data signal onto the USB cable. The output swings between the differential high and low state are well balanced to minimize signal skew. The slew rate control on the driver minimizes the radiated noise and cross talk on the USB cable. The driver's outputs support three-state operation to achieve bi-directional half duplex operation. The uPSD323X Devices driver Figure 44. Low Speed Driver Signal Waveforms One Bit Time 1.5 Mb/s tolerates a voltage on the signal pins of -0.5V to 3.6V with respect to local ground reference without damage. The driver tolerates this voltage for 10.0s while the driver is active and driving, and tolerates this condition indefinitely when the driver is in its high impedance state. A low speed USB connection is made through an unshielded, untwisted wire cable a maximum of 3 meters in length. The rise and fall time of the signals on this cable are well controlled to reduce RFI emissions while limiting delays, signaling skews and distortions. The uPSD323X Devices driver reaches the specified static signal levels with smooth rise and fall times, resulting in segments between low speed devices and the ports to which they are connected. VSE(max) Driver Signal Pins Signal pins pass output spec levels with minimal reflections and ringing VSE(min) VSS AI06629 89/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Receiver Characteristics The uPSD323X Devices has a differential input receiver which is able to accept the USB data signal. The receiver features an input sensitivity of at least 200mV when both differential data inputs are in the range of at least 0.8V to 2.5V with respect to its local ground reference. This is the common mode range, as shown in Figure 45. The receiver tolerates static input voltages between -0.5V to 3.8V with respect to its local ground reference without damage. In addition to the differential receiver, there is a single-ended receiver for each of the two data lines. The single-ended receivers have a switching threshold between 0.8V and 2.0V (TTL inputs). Figure 45. Differential Input Sensitivity Over Entire Common Mode Range 1.0 Minimum Differential Sensitivity (volts) 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Common Mode Input Voltage (volts) 2.6 2.8 3.0 3.2 AI06630 90/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV External USB Pull-Up Resistor The USB system specifies a pull-up resistor on the D- pin for low-speed peripherals. The USB Spec 1.1 describes a 1.5k pull-up resistor to a 3.3V supply. An approved alternative method is a 7.5k pull-up to the USB VCC supply. This alterna- tive is defined for low-speed devices with an integrated cable. The chip is specified for the 7.5k pull-up. This eliminates the need for an external 3.3V regulator, or for a pin dedicated to providing a 3.3V output from the chip. Figure 46. USB Data Signal Timing and Voltage Levels tR VOH VCR VOL 10% DD+ 90% 90% tF 10% AI06631 Figure 47. Receiver Jitter Tolerance TPERIOD Differential Data Lines TJR TJR1 TJR2 Consecutive Transitions N*TPERIOD+TJR1 Paired Transitions N*TPERIOD+TJR2 AI06632 91/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 48. Differential to EOP Transition Skew and EOP Width TPERIOD Crossover Point Differential Data Lines Crossover Point Extended Diff. Data to SE0 Skew N*TPERIOD+TDEOP Source EOP Width: TEOPT Receiver EOP Width TEOPR1, TEOPR2 AI06633 Figure 49. Differential Data Jitter TPERIOD Crossover Points Differential Data Lines Consecutive Transitions N*TPERIOD+TxJR1 Paired Transitions N*TPERIOD+TxJR2 AI06634 92/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 81. Transceiver DC Characteristics Symb VOH VOL VDI VCM VSE CIN IIO RPU RPD Parameter Static Output High Static Output Low Differential Input Sensitivity Differential Input Common Mode Single Ended Receiver Threshold Transceiver Capacitance Data Line (D+, D-) Leakage External Bus Pull-up Resistance, DExternal Bus Pull-down Resistance Test Conditions(1) 15k 5% to GND(2,3) Notes 2, 3 |(D+) - (D-)|, Figure 47., page 91 Figure 47., page 91 -- -- 0V < (D+,D-) < 3.3 7.5k 2% to VCC 15k 5% Min 2.8 -- 0.2 0.8 0.8 -- -10 7.35 14.25 Max 3.6 0.3 -- 2.5 2.0 20 10 7.65 15.75 Unit V V V V V pF A k k Note: 1. VCC = 5V 10%; VSS = 0V; TA = 0 to 70C. 2. Level guaranteed for range of VCC = 4.5V to 5.5V. 3. With RPU, external idle resistor, 7.52%, D- to VCC . Table 82. Transceiver AC Characteristics Symb tDRATE tDJR1 tDJR2 tDEOP tEOPR1 tEOPR2 tEOPT tUDJ1 tUDJ2 tR tF tRFM VCRS Note: 1. 2. 3. 4. 5. 6. Parameter Low Speed Data Rate Receiver Data Jitter Tolerance Differential Input Sensitivity Differential to EOP Transition Skew EOP Width at Receiver EOP Width at Receiver Source EOP Width Differential Driver Jitter Differential Driver Jitter USB Data Transition Rise Time USB Data Transition Fall Time Rise/Fall Time Matching Output Signal Crossover Volt age Test Conditions(1) Ave. bit rate (1.5Mb/s 1.5%) To next transition, Figure 47., page 91(5) For paired transition, Figure 47., page 91(5) Figure 48., page 92(5) Rejects as EOP(5,6) Accepts as EOP(5) -- To next transition, Figure 49., page 92 To paired transition, Figure 49., page 92 Notes 2, 3, 4 Notes 2, 3, 4 tR / tF -- Min 1.4775 -75 -45 -40 165 675 -1.25 -95 -150 75 75 80 1.3 Max 1.5225 75 45 100 -- -- 1.50 95 150 300 300 120 2.0 Unit Mbit/s ns ns ns ns ns s ns ns ns ns % V VCC = 5V 10%; VSS = 0V; TA = 0 to 70C. Level guaranteed for range of VCC = 4.5V to 5.5V. With RPU, external idle resistor, 7.52%, D- to VCC . CL of 50pF(75ns) to 350pF (300ns). Measured at crossover point of differential data signals. USB specification indicates 330ns. 93/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PSD MODULE The PSD Module provides configurable Program and Data memories to the 8032 CPU core (MCU). In addition, it has its own set of I/ O ports and a PLD with 16 macrocells for general logic implementation. Ports A,B,C, and D are general purpose programmable I/O ports that have a port architecture which is different from the I/O ports in the MCU Module. The PSD Module communicates with the MCU Module through the internal address, data bus (A0-A15, D0-D7) and control signals (RD, WR, PSEN, ALE, RESET). The user defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space. Figure 50., page 95 shows the functional blocks in the PSD Module. Functional Overview - 1 or 2 Mbit Flash memory. This is the main Flash memory. It is divided into eight equalsized blocks that can be accessed with userspecified addresses. - Secondary 256 Kbit Flash boot memory. It is divided into four equal-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. - 64 Kbit SRAM. The SRAM's contents can be protected from a power failure by connecting an external battery. - CPLD with 16 Output Micro Cells (OMCs} and 20 Input Micro Cells (IMCs). The CPLD may be used to efficiently implement a variety of logic functions for internal and external control. Examples include state machines, loadable shift registers, and loadable counters. - - - - - - Decode PLD (DPLD) that decodes address for selection of memory blocks in the PSD Module. Configurable I/O ports (Port A,B,C and D) that can be used for the following functions: MCU I/Os PLD I/Os Latched MCU address output Special function I/Os. I/O ports may be configured as open-drain outputs. Built-in JTAG compliant serial port allows fullchip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. Internal page register that can be used to expand the 8032 MCU Module address space by a factor of 256. Internal programmable Power Management Unit (PMU) that supports a low-power mode called Power-down Mode. The PMU can automatically detect a lack of the 8032 CPU core activity and put the PSD Module into Power-down Mode. Erase/WRITE cycles: Flash memory - 100,000 minimum PLD - 1,000 minimum Data Retention: 15 year minimum (for Main Flash memory, Boot, PLD and Configuration bits) 94/170 ADDRESS/DATA/CONTROL BUS 8032 Bus PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 8 SECTORS POWER MANGMT UNIT 1 OR 2 MBIT PRIMARY FLASH MEMORY 8 VSTDBY (PC2) WR_, RD_, PSEN_, ALE, RESET_, A0-A15 BUS Interface FLASH DECODE PLD (DPLD) 73 SECTOR SELECTS SRAM SELECT PERIP I/O MODE SELECTS CSIOP BUS Interface 73 FLASH ISP CPLD (CPLD) 2 EXT CS TO PORT D 16 OUTPUT MACROCELLS PORT A ,B & C 20 INPUT MACROCELLS CLKIN PORT A ,B & C RUNTIME CONTROL AND I/O REGISTERS 64 KBIT BATTERY BACKUP SRAM SECTOR SELECTS 256 KBIT SECONDARY NON-VOLATILE MEMORY (BOOT OR DATA) 4 SECTORS Figure 50. PSD Module Block Diagram PA0 - PA7 PORT A PROG. PORT D0 - D7 PROG. PORT PORT B PB0 - PB7 PROG. PORT GLOBAL CONFIG. & SECURITY CLKIN MACROCELL FEEDBACK OR PORT INPUT PORT C PC0 - PC7 PROG. PORT CLKIN (PD1) PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT D PD1 - PD2 AI05797 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV 95/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV In-System Programming (ISP) Using the JTAG signals on Port C, the entire PSD Module device can be programmed or erased without the use of the MCU. The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD Module Configuration blocks can be programmed through the JTAG port or a device programmer. Table 83 indicates which programming methods can program different functional blocks of the PSD Module. Table 83. Methods of Programming Different Functional Blocks of the PSD Module Functional Block Primary Flash Memory Secondary Flash Memory PLD Array (DPLD and CPLD) PSD Module Configuration JTAG Programming Yes Yes Yes Yes Device Programmer Yes Yes Yes Yes Yes Yes No No IAP 96/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV DEVELOPMENT SYSTEM The uPSD3200 is supported by PSDsoft, a Windows-based software development tool (Windows-95, Windows-98, Windows-NT). A PSD Module design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD Module pin functions and memory map information. The general design flow is shown in Figure 51. PSDsoft is available from our web site (the adFigure 51. PSDsoft Express Development Tool Choose PSD dress is given on the back page of this data sheet) or other distribution channels. PSDsoft directly supports a low cost device programmer from ST: FlashLINK (JTAG). The programmer may be purchased through your local distributor/representative. The uPSD3200 is also supported by third party device programmers. See our web site for the current list. Define PSD Pin and Node Functions Point and click definition of PSD pin functions, internal nodes, and MCU system memory map Define General Purpose Logic in CPLD Point and click definition of combinatorial and registered logic in CPLD. Access HDL is available if needed C Code Generation GENERATE C CODE SPECIFIC TO PSD FUNCTIONS Merge MCU Firmware with PSD Module Configuration A composite object file is created containing MCU firmware and PSD configuration MCU FIRMWARE HEX OR S-RECORD FORMAT USER'S CHOICE OF 8032 COMPILER/LINKER *.OBJ FILE PSD Programmer FlashLINK (JTAG) *.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS AI05798 97/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET Table 84 shows the offset addresses to the PSD Module registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal Table 84. Register Address Offset Register Name Data In Control Data Out Direction Drive Select Input Macrocell Enable Out Output Macrocells AB Output Macrocells BC Mask Macrocells AB Mask Macrocells BC Primary Flash Protection Secondary Flash memory Protection PMMR0 PMMR2 Page VM Note: 1. Other registers that are not part of the I/O ports. PSD Module registers. Table 84 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. Port A 00 02 04 06 08 0A 0C 20 Port B 01 03 05 07 09 0B 0D 20 21 Port C 10 Port D 11 Other(1) Description Reads Port pin as input, MCU I/O Input Mode Selects mode between MCU I/O or Address Out 12 14 16 18 1A 13 15 17 Stores data for output to Port pins, MCU I/O Output Mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads Input Macrocells 1B Reads the status of the output enable to the I/O Port driver READ - reads output of macrocells AB WRITE - loads macrocell flip-flops 21 READ - reads output of macrocells BC WRITE - loads macrocell flip-flops Blocks writing to the Output Macrocells AB 22 22 23 23 C0 C2 B0 B4 E0 E2 Blocks writing to the Output Macrocells BC Read-only - Primary Flash Sector Protection Read-only - PSD Module Security and Secondary Flash memory Sector Protection Power Management Register 0 Power Management Register 2 Page Register Places PSD Module memory areas in Program and/or Data space on an individual basis. 98/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PSD MODULE DETAILED OPERATION As shown in Figure 15., page 27, the PSD Module consists of five major types of functional blocks: Memory Block PLD Blocks I/O Ports Power Management Unit (PMU) JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. Memory Block Select Signals The DPLD generates the Select signals for all the internal memory blocks (see PLDs, page 112). Each of the eight sectors of the primary Flash memory has a Select signal (FS0-FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in Program or Data space. Ready/Busy (PC3). This signal can be used to output the Ready/Busy status of the Flash memory. The output on Ready/Busy (PC3) is a '0' (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a '1' (Ready) when no WRITE or Erase cycle is in progress. Memory Operation. The primary Flash memory and secondary Flash memory are addressed through the MCU Bus. The MCU can access these memories in one of two ways: - The MCU can execute a typical bus WRITE or READ operation. - The MCU can execute a specific Flash memory instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table 85., page 101. Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM device. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3). MEMORY BLOCKS The PSD Module has the following memory blocks: Primary Flash memory Secondary Flash memory SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft Express. Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configuration. 99/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD Module and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations. The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ Mode (Flash memory is read like a ROM device). The Flash memory supports the instructions summarized in Table 85: Flash memory: - Erase memory by chip or sector - Suspend or resume sector erase - Program a Byte - RESET to READ Mode - Read Sector Protection Status - Bypass These instructions are detailed in Table 85. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address signals A15-A12 are Don't Care during the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0CSBOOT3) is High. 100/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 85. Instructions Instruction READ(5) READ Sector Protection(6,8,13) Program a Flash Byte(13) Flash Sector Erase(7,13) Flash Bulk Erase(13) Suspend Sector Erase(11) Resume Sector Erase(12) RESET(6) Unlock Bypass Unlock Bypass Program(9) Unlock Bypass Reset(10) Note: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. FS0-FS7 or CSBOOT0CSBOOT3 1 1 1 1 1 1 1 1 1 1 1 Cycle 1 "Read" RD @ RA AAh@ X555h AAh@ X555h AAh@ X555h AAh@ X555h B0h@ XXXXh 30h@ XXXXh F0h@ XXXXh AAh@ X555h A0h@ XXXXh 90h@ XXXXh Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 55h@ XAAAh 55h@ XAAAh 55h@ XAAAh 55h@ XAAAh 90h@ X555h A0h@ X555h 80h@ X555h 80h@ X555h Read status @ XX02h PD@ PA AAh@ X555h AAh@ X555h 55h@ XAAAh 55h@ XAAAh 30h@ SA 10h@ X555h 30h7@ next SA 55h@ XAAAh PD@ PA 00h@ XXXXh 20h@ X555h All bus cycles are WRITE bus cycles, except the ones with the "Read" label All values are in hexadecimal: X = Don't care. Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data READ from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0). PA is an even address for PSD in Word Programming Mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High). Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft Express. Only address Bits A11-A0 are used in instruction decoding. No Unlock or instruction cycles are required when the device is in the READ Mode The RESET instruction is required to return to the READ Mode after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80s. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass Mode. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase Mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 101/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Power-down Instruction and Power-up Mode Power-up Mode. The PSD Module internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held Low, and WRITE Strobe (WR, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of WRITE Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO. READ Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. READ Memory Contents. Primary Flash memory and secondary Flash memory are placed in the READ Mode after Power-up, chip reset, or a Reset Flash instruction (see Table 85., page 101). The MCU can read the memory contents of the primary Flash memory or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction. READ Memory Sector Protection Status. The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 85., page 101). During the READ operation, address Bits A6, A1, and A0 must be '0,' '1,' and '0,' respectively, while Sector Select (FS0FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory or secondary Flash memory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See Flash Memory Sector Protect, page 107, for register definitions. Reading the Erase/Program Status Bits. The Flash memory provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 86., page 103. The status bits can be read as many times as needed. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See Programming Flash Memory, page 104, for details. Data Polling Flag (DQ7). When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7) (in a READ operation). - Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. - During an Erase cycle, the Data Polling Flag Bit (DQ7) outputs a '0.' After completion of the cycle, the Data Polling Flag Bit (DQ7) outputs the last bit programmed (it is a '1' after erasing). - If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored. - If all the Flash memory sectors to be erased are protected, the Data Polling Flag Bit (DQ7) is reset to '0' for about 100s, and then returns to the previous addressed byte. No erasure is performed. 102/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Toggle Flag (DQ6). The Flash memory offers another way for determining when the Program cycle is completed. During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0CSBOOT3 is true, the Toggle Flag Bit (DQ6) toggles from '0' to '1' and '1' to '0' on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling stops and the data READ on the Data Bus D0-D7 is the addressed memory byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive Reads yield the same output data. - The Toggle Flag Bit (DQ6) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). - If the byte to be programmed belongs to a protected Flash memory sector, the instruction is ignored. - If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6) toggles to '0' for about 100s and then returns to the previous addressed byte. Error Flag (DQ5). During a normal Program or Erase cycle, the Error Flag Bit (DQ5) is to '0.' This Table 86. Status Bit Functional Block FS0-FS7/ CSBOOT0CSBOOT3 VIH(3) DQ7(2) DQ6(2) DQ5(2) DQ4(1,2) DQ3(2) DQ2(1,2) DQ1(1,2) Erase Timeout DQ0(1,2) bit is set to '1' when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error Flag Bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, '0', to the erased state, '1,' which is not valid. The Error Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5) is reset after a Reset Flash instruction. Erase Time-out Flag (DQ3). The Erase Timeout Flag Bit (DQ3) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag Bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100s + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag Bit (DQ3) is set to '1.' Flash Memory Data Polling Toggle Flag Error Flag X X X X Note: 1. X = Not guaranteed value, can be read either '1' or '0.' 2. DQ7-DQ0 represent the Data Bus bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High. 103/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Programming Flash Memory Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all '1s' (FFh), and is programmed by setting selected bits to '0.' The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may program Flash memory byte-bybyte. The primary and secondary Flash memories require the MCU to send an instruction to program a byte or to erase sectors (see Table 85., page 101). Once the MCU issues a Flash memory Program or Erase instruction, it must check for the status bits for completion. The embedded algorithms that are invoked support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PC3). Data Polling. Polling on the Data Polling Flag Bit (DQ7) is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 52 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Data Polling Flag Bit (DQ7) of this location becomes the complement of b7 of the original data byte to be programmed. The MCU continues to poll this location, comparing the Data Polling Flag Bit (DQ7) and monitoring the Error Flag Bit (DQ5). When the Data Polling Flag Bit (DQ7) matches b7 of the original data, and the Error Flag Bit (DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,' the MCU should test the Data Polling Flag Bit (DQ7) again since the Data Polling Flag Bit (DQ7) may have changed simultaneously with the Error Flag Bit (DQ5) (see Figure 52). The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 52 still applies. However, the Data Polling Flag Bit (DQ7) is '0' until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The MCU can read any location within the sector being erased to get the Data Polling Flag Bit (DQ7) and the Error Flag Bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Polling algorithms. Figure 52. Data Polling Flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO YES DQ5 =1 YES READ DQ7 DQ7 = DATA NO FAIL YES PASS AI01369B 104/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Data Toggle. Checking the Toggle Flag Bit (DQ6) is a method of determining whether a Program or Erase cycle is in progress or has completed. Figure 53 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Toggle Flag Bit (DQ6) of this location toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle Flag Bit (DQ6) and monitoring the Error Flag Bit (DQ5). When the Toggle Flag Bit (DQ6) stops toggling (two consecutive reads yield the same value), and the Error Flag Bit (DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,' the MCU should test the Toggle Flag Bit (DQ6) again, since the Toggle Flag Bit (DQ6) may have changed simultaneously with the Error Flag Bit (DQ5) (see Figure 53). The Error Flag Bit(DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 53 still applies. the Toggle Flag Bit (DQ6) toggles until the Erase cycle is complete. A 1 on the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The MCU can read any location within the sector being erased to get the Toggle Flag Bit (DQ6) and the Error Flag Bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms. Figure 53. Data Toggle Flowchart START READ DQ5 & DQ6 DQ6 = TOGGLE YES NO NO DQ5 =1 YES READ DQ6 DQ6 = TOGGLE YES FAIL NO PASS AI01370B 105/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Unlock Bypass. The Unlock Bypass instructions allow the system to program bytes to the Flash memories faster than using the standard Program instruction. The Unlock Bypass Mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass code, 20h (as shown in Table 85., page 101). The Flash memory then enters the Unlock Bypass Mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. These instructions dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total Flash memory programming. During the Unlock Bypass Mode, only the Unlock Bypass Program and Unlock Bypass Reset Flash instructions are valid. To exit the Unlock Bypass Mode, the system must issue the two-cycle Unlock Bypass Reset Flash instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don't Care for both cycles. The Flash memory then returns to READ Mode. Erasing Flash Memory Flash Bulk Erase. The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 85. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the READ Flash memory status. During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in Programming Flash Memory, page 104. The Error Flag Bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD Module automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. Flash Sector Erase. The Sector Erase instruction uses six WRITE operations, as described in Table 85., page 101. Additional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the time-out period of about 100s. The input of a new Sector Erase code restarts the time-out period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,' the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3) is '1,' the time-out period has expired and the embedded algorithm is busy erasing the Flash memory sector(s). Before and during Erase time-out, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the device to READ Mode. During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in Programming Flash Memory, page 104. During execution of the Erase cycle, the Flash memory accepts only RESET and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. 106/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Suspend Sector Erase. When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 85., page 101). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ Mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag Bit (DQ6) stops toggling when the internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6) stops toggling between 0.1s and 15s after the Suspend Sector Erase instruction has been executed. The Flash memory is then automatically set to READ Mode. If an Suspend Sector Erase instruction was executed, the following rules apply: - Attempting to read from a Flash memory sector that was being erased outputs invalid data. - Reading from a Flash sector that was not being erased is valid. - The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed). - If a Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase. If a Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 85., page 101.) Specific Features Flash Memory Sector Protect. Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated through the JTAG Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Express Configuration program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection registers (in the CSIOP block). See Tables 87 and 88. Table 87. Sector Protection/Security Bit Definition - Flash Protection Register Bit 7 Sec7_Prot Bit 6 Sec6_Prot Bit 5 Sec5_Prot Bit 4 Sec4_Prot Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot Note: 1. Bit Definitions: Sec_Prot 1 = Primary Flash memory or secondary Flash memory Sector is write-protected. Sec_Prot 0 = Primary Flash memory or secondary Flash memory Sector is not write-protected. Table 88. Sector Protection/Security Bit Definition - Secondary Flash Protection Register Bit 7 Security_Bit Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot Note: 1. Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write-protected. Sec_Prot 0 = Secondary Flash memory Sector is not write-protected. Security_Bit 0 = Security Bit in device has not been set; 1 = Security Bit in device has been set. 107/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Reset Flash. The Reset Flash instruction consists of one WRITE cycle (see Table 85., page 101). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and 55h to AAAh). It must be executed after: - Reading the Flash Protection Status or Flash ID - An Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1' during a Flash memory Program or Erase cycle. The Reset Flash instruction puts the Flash memory back into normal READ Mode. If an Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1' the Flash memory is put back into normal READ Mode within 25s of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ Mode within 25s. Reset (RESET) Signal. A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash memory to the READ Mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25s to return to the READ Mode. It is recommended that the Reset (RESET) pulse (except for Power-on RESET, as described in RESET TIMING AND DEVICE STATUS AT RESET, page 132) be at least 25s so that the Flash memory is always ready for the MCU to retreive the bootstrap instructions after the reset cycle is complete. SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to Voltage Stand-by (VSTBY, PC2). If you have an external battery connected to the uPSD3200, the contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs. PC4 can be configured as an output that indicates when power is being drawn from the external battery. Battery-on Indicator (VBATON, PC4) is High with the supply voltage falls below the battery voltage and the battery on Voltage Stand-by (VSTBY, PC2) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Stand-by (VSTBY, PC2) and Battery-on Indicator (VBATON, PC4) are all configured using PSDsoft Express Configuration. Sector Select and SRAM Select Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDsoft Express. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. 2. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O. 108/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Example. FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Note: An equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 54 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest. Memory Select Configuration in Program and Data Spaces. The MCU Core has separate address spaces for Program memory and Data memory. Any of the memories within the PSD Module can reside in either space or both spaces. This is controlled through manipulation of the VM Register that resides in the CSIOP space. The VM Register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. Table 89. VM Register Bit 7 PIO_EN Bit 6 Bit 5 Bit 4 Primary FL_Data 0 = RD can't access Flash memory 1 = RD access Flash memory Bit 3 Secondary Data Bit 2 Primary FL_Code 0 = PSEN can't access Flash memory 1 = PSEN access Flash memory Bit 1 Secondary Code Bit 0 SRAM_Code 0 = PSEN can't access SRAM 1 = PSEN access SRAM For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the primary and secondary Flash memories. This is easily done with the VM Register by using PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it when desired. Table 89 describes the VM Register. Figure 54. Priority Level of Memory and I/O Components in the PSD Module Highest Priority Level 1 SRAM, I /O, or Peripheral I /O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority AI02867D 0 = disable PIO Mode not used not used 0 = RD can't access Secondary Flash memory 0 = PSEN can't access Secondary Flash memory 1= enable PIO Mode not used not used 1 = RD access Secondary Flash memory 1 = PSEN access Secondary Flash memory 109/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Separate Space Mode. Program space is separated from Data space. For example, Program Select Enable (PSEN) is used to access the program code from the primary Flash memory, while READ Strobe (RD) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM Register to be set to 0Ch (see Figure 55). Figure 55. Separate Space Mode Combined Space Modes. The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN) or READ Strobe (RD). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM Register are set to '1' (see Figure 56). DPLD RS0 CSBOOT0-3 FS0-FS7 Primary Flash Memory Secondary Flash Memory SRAM CS OE CS OE CS OE PSEN RD AI02869C Figure 56. Combined Space Mode DPLD RS0 CSBOOT0-3 FS0-FS7 Primary Flash Memory Secondary Flash Memory SRAM RD CS OE CS OE CS OE VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 RD VM REG BIT 0 AI02870C 110/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Page Register The 8-bit Page Register increases the addressing capability of the MCU Core by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. Figure 57 shows the Page Register. The eight flipflops in the register are connected to the internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. Figure 57. Page Register RESET D0 D1 D0 - D7 D2 D3 D4 D5 D6 R/W D7 Q0 Q1 Q2 Q3 Q4 Q5 PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD AND CPLD INTERNAL PSD MODULE SELECTS AND LOGIC Q6 PGR7 Q7 PAGE REGISTER PLD AI05799 111/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PLDS The PLDs bring programmable logic functionality to the uPSD. After specifying the logic for the PLDs in PSDsoft Express, the logic is programmed into the device and available upon Power-up. Table 90. DPLD and CPLD Inputs Input Source MCU Address Bus MCU Control Signals RESET Power-down Port A Input Macrocells(1) Port B Input Macrocells Port C Input Macrocells Port D Inputs Page Register Macrocell AB Feedback Macrocell BC Feedback Flash memory Program Status Bit Input Name A15-A0 PSEN, RD, WR, ALE RST PDN PA7-PA0 PB7-PB0 PC2-4, PC7 PD2-PD1 PGR7-PGR0 MCELLAB.FB7FB0 MCELLBC.FB7FB0 Ready/Busy Number of Signals 16 4 1 1 8 8 4 2 8 8 8 1 Note: 1. These inputs are not available in the 52-pin package. The PSD Module contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in Decode PLD (DPLD), page 114, and Complex PLD (CPLD), page 115. Figure 58., page 113 shows the configuration of the PLDs. The DPLD performs address decoding for Select signals for PSD Module components, such as memory, registers, and I/O ports. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the Output Macrocells (OMC), Input Macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS1-ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDsoft. The PLD input signals consist of internal MCU signals and external inputs from the I/O ports. The input signals are shown in Table 90. The Turbo Bit in PSD Module The PLDs can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo Mode off increases propagation delays while reducing power consumption. See POWER MANAGEMENT, page 128, on how to set the Turbo Bit. Additionally, five bits are available in PMMR2 to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections. 112/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 58. PLD Diagram 8 DATA BUS PAGE REGISTER 73 DECODE PLD 8 4 1 1 2 PRIMARY FLASH MEMORY SELECTS SECONDARY NON-VOLATILE MEMORY SELECTS SRAM SELECT CSIOP SELECT PERIPHERAL SELECTS PLD INPUT BUS 16 OUTPUT MACROCELL FEEDBACK DIRECT MACROCELL ACCESS FROM MCU DATA BUS CPLD 73 PT ALLOC. 16 OUTPUT MACROCELL MACROCELL ALLOC. I/O PORTS MCELLAB TO PORT A OR B1 MCELLBC TO PORT B OR C 8 20 INPUT MACROCELL (PORT A,B,C) 8 2 EXTERNAL CHIP SELECTS TO PORT D DIRECT MACROCELL INPUT TO MCU DATA BUS 20 INPUT MACROCELL & INPUT PORTS 2 PORT D INPUTS AI06600 Note: 1. Ports A is not available in the 52-pin package 113/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Decode PLD (DPLD) The DPLD, shown in Figure 59, is used for decoding the address for PSD Module and external components. The DPLD can be used to generate the following decode signals: - 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) - - - - 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) 1 internal SRAM Select (RS0) signal (two product terms) 1 internal CSIOP Select signal (selects the PSD Module registers) 2 internal Peripheral Select signals (Peripheral I/O Mode). Figure 59. DPLD Logic Array 3 3 3 3 (INPUTS) I /O PORTS (PORT A,B,C)1 MCELLAB.FB [7:0] (FEEDBACKS) MCELLBC.FB [7:0] (FEEDBACKS) PGR0 - PGR7 A[15:0]2 PD[2:1] PDN (APD OUTPUT) PSEN, RD, WR, ALE2 RESET 2 (20) 3 (8) 3 (8) 3 (8) 3 (16) 3 (2) 3 (1) 3 (4) (1) 2 RD_BSY (1) 1 1 1 CSIOP PSEL0 PSEL1 PERIPHERAL I/O MODE SELECT AI06601 CSBOOT 0 CSBOOT 1 CSBOOT 2 CSBOOT 3 3 FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 PRIMARY FLASH MEMORY SECTOR SELECTS RS0 SRAM SELECT I/O DECODER SELECT Note: 1. Port A inputs are not available in the 52-pin package 2. Inputs from the MCU module 114/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate External Chip Select (ECS1-ECS2), routed to Port D. Although External Chip Select (ECS1-ECS2) can be produced by any Output Macrocell (OMC), these External Chip Select (ECS1-ECS2) on Port D do not consume any Output Macrocells (OMC). As shown in Figure 58, the CPLD has the following blocks: - 20 Input Macrocells (IMC) - 16 Output Macrocells (OMC) - Macrocell Allocator - Product Term Allocator Figure 60. Macrocell and I/O Port PLD INPUT BUS PRODUCT TERMS FROM OTHER MACROCELLS MCU ADDRESS / DATA BUS TO OTHER I/O PORTS - AND Array capable of generating up to 137 product terms - Four I/O Ports. Each of the blocks are described in the sections that follow. The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD Module internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures. CPLD MACROCELLS PT PRESET PRODUCT TERM ALLOCATOR MCU DATA IN MCU LOAD DATA LOAD CONTROL I/O PORTS LATCHED ADDRESS OUT DATA WR I/O PIN D Q MUX AND ARRAY UP TO 10 PRODUCT TERMS MACROCELL OUT TO MCU CPLD OUTPUT PR DI LD PT CLOCK D/T MUX Q COMB. /REG SELECT CPLD OUTPUT MACROCELL TO I/O PORT ALLOC. WR PT CLEAR PDR INPUT SELECT PLD INPUT BUS GLOBAL CLOCK CLOCK SELECT D/T/JK FF SELECT CK CL MUX POLARITY SELECT D Q DIR REG. PT OUTPUT ENABLE (OE) MACROCELL FEEDBACK I/O PORT INPUT INPUT MACROCELLS MUX QD PT INPUT LATCH GATE/CLOCK MUX ALE QD G AI06602 115/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are connected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in PSDsoft, the Macrocell Allocator block assigns it to either Port A or B. The same is true for a McellBC output on Port B or C. Table 91 shows the macrocells and port assignment. The Output Macrocell (OMC) architecture is shown in Figure 61., page 117. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output Macrocells (OMC). The polarity of the product term is con- trolled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in PSDsoft. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. Table 91. Output Macrocell Port and Data Bit Assignments Output Macrocell McellAB0 McellAB1 McellAB2 McellAB3 McellAB4 McellAB5 McellAB6 McellAB7 McellBC0 McellBC1 McellBC2 McellBC3 McellBC4 McellBC5 McellBC6 McellBC7 Port Assignment(1,2) Port A0, B0 Port A1, B1 Port A2, B2 Port A3, B3 Port A4, B4 Port A5, B5 Port A6, B6 Port A7, B7 Port B0 Port B1 Port B2, C2 Port B3, C3 Port B4, C4 Port B5 Port B6 Port B7, C7 Native Product Terms 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Maximum Borrowed Product Terms 6 6 6 6 6 6 6 6 5 5 5 5 6 6 6 6 Data Bit for Loading or Reading D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Note: 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package. 2. Port PC0, PC1, PC5, and PC6 are assigned to JTAG pins and are not available as Macrocell outputs. 116/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Product Term Allocator The CPLD has a Product Term Allocator. PSDsoft uses the Product Term Allocator to borrow and place product terms from one macrocell to another. The following list summarizes how product terms are allocated: - McellAB0-McellAB7 all have three native product terms and may borrow up to six more - McellBC0-McellBC3 all have four native product terms and may borrow up to five more - McellBC4-McellBC7 all have four native product terms and may borrow up to six more. Each macrocell may only borrow product terms from certain other macrocells. Product terms already in use by one macrocell are not available for another macrocell. If an equation requires more product terms than are available to it, then "external" product terms are required, which consume other Output Macrocells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms. This is called product term expansion. PSDsoft Express performs this expansion as needed. Loading and Reading the Output Macrocells (OMC). The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP block (see the section entitled I/O PORTS (PSD MODULE), page 119). The flip-flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data can be loaded to the Output Macrocells (OMC) on the trailing edge of WRITE Strobe (WR, edge loading) or during the time that WRITE Strobe (WR) is active (level loading). The method of loading is specified in PSDsoft Express Configuration. Figure 61. CPLD Output Macrocell MASK REG. MACROCELL CS RD MCU DATA BUS D[7:0] PT ALLOCATOR WR DIRECTION REGISTER ENABLE (.OE) PRESET(.PR) COMB/REG SELECT AND ARRAY PT PT DIN PR PLD INPUT BUS MUX PT LD POLARITY SELECT CLEAR (.RE) PT CLK CLKIN MUX IN CLR PROGRAMMABLE FF (D/T/JK /SR) PORT DRIVER Q MACROCELL ALLOCATOR I/O PIN FEEDBACK (.FB) PORT INPUT INPUT MACROCELL AI06617 117/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV The OMC Mask Register. There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a '1,' the MCU is blocked from writing to the associated Output Macrocells (OMC). For example, suppose McellAB0McellAB3 are being used for a state machine. You would not want a MCU write to McellAB to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellAB (Mask Macrocell AB) with the value 0Fh. The Output Enable of the OMC. The Output Macrocells (OMC) block can be connected to an I/ O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Express. If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. Figure 62. Input Macrocell MCU DATA BUS D [ 7:0] Input Macrocells (IMC) The CPLD has 20 Input Macrocells (IMC), one for each pin on Ports A and B, and 4 on Port C. The architecture of the Input Macrocells (IMC) is shown in Figure 62. The Input Macrocells (IMC) are individually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the Input Macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE). Each product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the Input Macrocells (IMC) are specified by equations written in PSDsoft (see Application Note AN1171). Outputs of the Input Macrocells (IMC) can be read by the MCU via the IMC buffer. See I/O PORTS (PSD MODULE), page 119. INPUT MACROCELL _ RD ENABLE ( .OE ) OUTPUT MACROCELLS BC AND MACROCELL AB DIRECTION REGISTER PT AND ARRAY PLD INPUT BUS I/O PIN PT PORT DRIVER MUX Q D MUX PT ALE D FF FEEDBACK Q D G LATCH INPUT MACROCELL AI06603 118/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV I/O PORTS (PSD MODULE) There are four programmable I/O ports: Ports A, B, C, and D in the PSD Module. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express Configuration or by the MCU writing to on-chip registers in the CSIOP space. Port A is not available in the 52-pin package. The topics discussed in this section are: General Port architecture Port operating modes Port Configuration Registers (PCR) Port Data Registers Individual Port functionality. General Port Architecture The general architecture of the I/O Port block is shown in Figure 63. Individual Port architectures are shown in Figure 65., page 124 to Figure 68., page 127. In general, once the purpose for a Figure 63. General I/O Port Architecture DATA OUT REG. D WR ADDRESS ALE D G Q ADDRESS OUTPUT MUX PORT PIN Q port pin has been defined, that pin is no longer available for other purposes. Exceptions are noted. As shown in Figure 63, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft Express Configuration. Inputs to the multiplexer include the following: - Output data from the Data Out register - Latched address outputs - CPLD macrocell output - External Chip Select (ECS1-ECS2) from the CPLD. The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the MCU. The Data Out and macrocell outputs, Direction and Control Registers, and port pin input are all connected to the Port Data Buffer (PDB). DATA OUT MACROCELL OUTPUTS EXT CS READ MUX P D B DATA IN OUTPUT SELECT MCU DATA BUS CONTROL REG. D WR DIR REG. D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD- INPUT AI06604 Q ENABLE OUT Q 119/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV The Port pin's tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDsoft, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See Input Macrocell, page 118. Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the MCU writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, and Peripheral I/O Modes are the only modes that must be defined before programming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 92., page 121 summarizes which modes are available on each port. Table 95., page 122 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections. MCU I/O Mode In the MCU I/O Mode, the MCU uses the I/O Ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD Module are mapped into the MCU address space. The addresses of the ports are listed in Table 84., page 98. A port pin can be put into MCU I/O Mode by writing a '0' to the corresponding bit in the Control Register. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term. See Peripheral I/O Mode, page 120. When the pin is configured as an output, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer. See Figure 63., page 119. Ports C and D do not have Control Registers, and are in MCU I/O Mode by default. They can be used for PLD I/O if equations are written for them in PSDabel. PLD I/O Mode The PLD I/O Mode uses a port as an input to the CPLD's Input Macrocells (IMC), and/or as an output from the CPLD's Output Macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by resetting the corresponding bit in the Direction Register to '0.' The corresponding bit in the Direction Register must not be set to '1' if the pin is defined for a PLD input signal in PSDsoft. The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then writing an equation assigning the PLD I/ O to a port. Address Out Mode Address Out Mode can be used to drive latched MCU addresses on to the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a '1' for pins to use Address Out Mode. This must be done by the MCU at run-time. See Table 94., page 121 for the address output pin assignments on Ports A and B for various MCUs. Peripheral I/O Mode Peripheral I/O Mode can be used to interface with external peripherals. In this mode, all of Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O Mode is enabled by setting Bit 7 of the VM Register to a '1.' Figure 64., page 121 shows how Port A acts as a bi-directional buffer for the MCU data bus if Peripheral I/O Mode is enabled. An equation for PSEL0 and/ or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or PSEL1 is low (not active). The PSEN signal should be "ANDed" in the PSEL equations to disable the buffer when PSEL resides in the data space. JTAG In-System Programming (ISP) Port C is JTAG compliant, and can be used for InSystem Programming (ISP). For more information on the JTAG Port, see PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE, page 134. 120/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 64. Peripheral I/O Mode RD PSEL0 PSEL PSEL1 D0 - D7 DATA BUS VM REGISTER BIT 7 PA0 - PA7 WR AI02886 Table 92. Port Operating Modes Port Mode MCU I/O PLD I/O McellAB Outputs McellBC Outputs Additional Ext. CS Outputs PLD Inputs Address Out Peripheral I/O JTAG ISP Yes Yes No No Yes Yes (A7 - 0) Yes No Port A(1) Yes Yes Yes No Yes Yes (A7 - 0) No No Port B Yes No Yes(2) No Yes No No Yes(3) Port C Yes No No Yes Yes No No No Port D Note: 1. Port A is not available in the 52-pin package. 2. On pins PC2, PC3, PC4, and PC7 only. 3. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins. Table 93. Port Operating Mode Settings Mode MCU I/O PLD I/O Address Out (Port A,B) Peripheral I/O (Port A) Defined in PSDsoft Declare pins only Logic equations Declare pins only Logic equations (PSEL0 & 1) 0 N/A 1 N/A Control Register Setting(1) Direction Register Setting(1) 1 = output, 0 = input (Note 2) (Note 2) 1 (Note 2) N/A VM Register Setting(1) N/A N/A N/A PIO Bit = 1 Note: 1. N/A = Not Applicable 2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product term (.oe) from the CPLD AND Array. Table 94. I/O Port Latched Address Output Assignments Port A (PA3-PA0) Address a3-a0 Port A (PA7-PA4) Address a7-a4 Port B (PB3-PB0) Address a3-a0 Port B (PB7-PB4) Address a7-a4 121/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Port Configuration Registers (PCR) Each Port has a set of Port Configuration Registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 84., page 98. The addresses in Table Table 84 are the offsets in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three Port Configuration Registers (PCR), shown in Table 95, are used for setting the Port configurations. The default Power-up state for each register in Table 95 is 00h. Control Register. Any bit reset to '0' in the Control Register sets the corresponding port pin to MCU I/O Mode, and a '1' sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B have an associated Control Register. Direction Register. The Direction Register, in conjunction with the output enable (except for Port D), controls the direction of data flow in the I/O Ports. Any bit set to '1' in the Direction Register causes the corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default mode for all port pins is input. Figure 65., page 124 and Figure 66., page 125 show the Port Architecture diagrams for Ports A/B and C, respectively. The direction of data flow for Ports A, B, and C are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction Register has sole control of a given pin's direction. An example of a configuration for a Port with the three least significant bits set to output and the remainder set to input is shown in Table 98. Since Port D only contains two pins (shown in Figure 68., page 127), the Direction Register for Port D has only two bits active. Drive Select Register. The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a '1.' The default pin drive is CMOS. Note: The slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register is set to '1.' The default rate is slow slew. Table 99., page 123 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for. Table 95. Port Configuration Registers (PCR) Register Name Control Direction Drive Select(1) A,B A,B,C,D A,B,C,D Port MCU Access WRITE/READ WRITE/READ WRITE/READ Note: 1. See Table 99., page 123 for Drive Register Bit definition. Table 96. Port Pin Direction Control, Output Enable P.T. Not Defined Direction Register Bit 0 1 Input Output Port Pin Mode Table 97. Port Pin Direction Control, Output Enable P.T. Defined Direction Register Bit 0 0 1 1 Output Enable P.T. 0 1 0 1 Port Pin Mode Input Output Output Output Table 98. Port Direction Assignment Example Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 1 122/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Port Data Registers The Port Data Registers, shown in Table 100, are used by the MCU to write data to or read data from the ports. Table 100 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described below. Data In. Port pins are connected directly to the Data In buffer. In MCU I/O Input Mode, the pin input is read through the Data In buffer. Data Out Register. Stores output data written by the MCU in the MCU I/O Output Mode. The contents of the Register are driven out to the pins if the Direction Register or the output enable product term is set to '1.' The contents of the register can also be read back by the MCU. Output Macrocells (OMC). The CPLD Output Macrocells (OMC) occupy a location in the MCU's address space. The MCU can read the output of the Output Macrocells (OMC). If the OMC Mask Table 99. Drive Register Pin Assignment Drive Register Port A Port B Port C Port D Bit 7 Open Drain Open Drain Open Drain NA(1) Bit 6 Open Drain Open Drain Open Drain NA(1) Bit 5 Open Drain Open Drain Open Drain NA(1) Bit 4 Open Drain Open Drain Open Drain NA(1) Bit 3 Slew Rate Slew Rate Open Drain NA(1) Bit 2 Slew Rate Slew Rate Open Drain Slew Rate Bit 1 Slew Rate Slew Rate Open Drain Slew Rate Bit 0 Slew Rate Slew Rate Open Drain NA(1) Register Bits are not set, writing to the macrocell loads data to the macrocell flip-flops. See PLDs, page 112. OMC Mask Register. Each OMC Mask Register Bit corresponds to an Output Macrocell (OMC) flipflop. When the OMC Mask Register Bit is set to a '1,' loading data into the Output Macrocell (OMC) flip-flop is blocked. The default value is '0' or unblocked. Input Macrocells (IMC). The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See PLDs, page 112. Enable Out. The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A '1' indicates the driver is in output mode. A '0' indicates the driver is in tri-state and the pin is in input mode. Note: 1. NA = Not Applicable. Table 100. Port Data Registers Register Name Data In Data Out Output Macrocell Mask Macrocell Input Macrocell Enable Out Port A,B,C,D A,B,C,D A,B,C A,B,C A,B,C A,B,C READ - input on pin WRITE/READ READ - outputs of macrocells WRITE - loading macrocells flip-flop WRITE/READ - prevents loading into a given macrocell READ - outputs of the Input Macrocells READ - the output enable control of the port driver MCU Access 123/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Ports A and B - Functionality and Structure Ports A and B have similar functionality and structure, as shown in Figure 65. The two ports can be configured to perform one or more of the following functions: - MCU I/O Mode - CPLD Output - Macrocells McellAB7McellAB0 can be connected to Port A or Port B. McellBC7-McellBC0 can be connected to Port B or Port C. Figure 65. Port A and Port B Structure - - - - CPLD Input - Via the Input Macrocells (IMC). Latched Address output - Provide latched address output as per Table 94., page 121. Open Drain/Slew Rate - pins PA3-PA0 and PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain Mode. Peripheral Mode - Port A only (80-pin package) DATA OUT REG. D WR ADDRESS ALE D G Q Q DATA OUT ADDRESS A[ 7:0] PORT A OR B PIN OUTPUT MUX MACROCELL OUTPUTS READ MUX MCU DATA BUS P D B CONTROL REG. D WR DIR REG. D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL Q Q ENABLE OUT DATA IN OUTPUT SELECT CPLD-INPUT AI06605 124/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Port C - Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 66): - MCU I/O Mode - CPLD Output - McellBC7-McellBC0 outputs can be connected to Port B or Port C. - CPLD Input - via the Input Macrocells (IMC) - In-System Programming (ISP) - JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins for device programming. (See PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE, page 134, for more information on JTAG programming.) Figure 66. Port C Structure DATA OUT REG. D WR 1 OUTPUT MUX PORT C PIN Q DATA OUT Open Drain - Port C pins can be configured in Open Drain Mode - Battery Backup features - PC2 can be configured for a battery input supply, Voltage Stand-by (VSTBY). PC4 can be configured as a Battery-on Indicator (VBATON), indicating when VCC is less than VBAT. Port C does not support Address Out Mode, and therefore no Control Register is required. - SPECIAL FUNCTION MCELLBC[ 7:0] READ MUX MCU DATA BUS P D B DATA IN OUTPUT SELECT ENABLE OUT DIR REG. D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL 1 CONFIGURATION BIT AI06618 Q CPLD - INPUT SPECIAL FUNCTION Note: 1. ISP or battery back-up 125/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Port D - Functionality and Structure Port D has two I/O pins (only one pin, PD1, in the 52-pin package). See Figure 67 and Figure 68., page 127. This port does not support Address Out Mode, and therefore no Control Register is required. Of the eight bits in the Port D registers, only Bits 2 and 1 are used to configure pins PD2 and PD1. Port D can be configured to perform one or more of the following functions: - MCU I/O Mode - CPLD Output - External Chip Select (ECS1ECS2) Figure 67. Port D Structure - CPLD Input - direct input to the CPLD, no Input Macrocells (IMC) - Slew rate - pins can be set up for fast slew rate Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: - CLKIN (PD1) as input to the macrocells flipflops and APD counter - PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. DATA OUT REG. DATA OUT D WR PORT D PIN OUTPUT MUX ECS [ 2:1] READ MUX MCU DATA BUS Q P D B DATA IN OUTPUT SELECT DIR REG. D WR Q CPLD-INPUT ENABLE PRODUCT TERM (.OE) AI06606 126/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV External Chip Select The CPLD also provides two External Chip Select (ECS1-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS1-ECS2) consists of one product Figure 68. Port D External Chip Select Signals term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 68.) ENABLE (.OE) DIRECTION REGISTER PT1 ECS1 POLARITY BIT PD1 PIN CPLD AND ARRAY PLD INPUT BUS ENABLE (.OE) DIRECTION REGISTER PT2 ECS2 PD2 PIN POLARITY BIT AI06607 127/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV POWER MANAGEMENT All PSD Modules offer configurable power saving options. These options may be used individually or in combinations, as follows: - The primary and secondary Flash memory, and SRAM blocks are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into Standby Mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory "wakes up," changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve Memory Standby Mode when no inputs are changing--it happens automatically. - The PLD sections can also achieve Standby Mode when its inputs are not changing, as described in the sections on the Power Management Mode Registers (PMMR). - As with the Power Management Mode, the Automatic Power Down (APD) block allows the PSD Module to reduce to stand-by current automatically. The APD Unit can also block MCU address/data signals from reaching the memories and PLDs. - Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD Unit initiates Power-down Mode (if enabled). Once in Power-down Mode, all address/data Figure 69. APD Unit APD EN PMMR0 BIT 1=1 TRANSITION DETECTION ALE CLR PD CSIOP SELECT FLASH SELECT EDGE DETECT PD PLD SRAM SELECT POWER DOWN (PDN) SELECT DISABLE BUS INTERFACE - - signals are blocked from reaching memory and PLDs, and the memories are deselected internally. This allows the memory and PLDs to remain in Standby Mode even if the address/data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Stand-by Mode, but not the memories. PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories, placing them in Standby Mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit. There is a slight penalty in memory access time when PSD Chip Select Input (CSI, PD2) makes its initial transition from deselected to selected. The PMMRs can be written by the MCU at runtime to manage power. The PSD Module supports "blocking bits" in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 72 and Figure 73., page 135). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. RESET CSI CLKIN APD COUNTER DISABLE FLASH/SRAM AI06608 128/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV The PSD Module has a Turbo Bit in PMMR0. This bit can be set to turn the Turbo Mode off (the default is with Turbo Mode turned on). While Turbo Mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is on. When the Turbo Mode is on, there is a significant DC current component and the AC component is higher. Automatic Power-down (APD) Unit and Powerdown Mode. The APD Unit, shown in Figure 69., page 128, puts the PSD Module into Powerdown Mode by monitoring the activity of Address Strobe (ALE). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE) stops, a fourbit counter starts counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down (PDN) goes High, and the PSD Module enters Power-down Mode, as discussed next. Power-down Mode. By default, if you enable the APD Unit, Power-down Mode is automatically enabled. The device enters Power-down Mode if Address Strobe (ALE) remains inactive for fifteen periods of CLKIN (PD1). The following should be kept in mind when the PSD Module is in Power-down Mode: - If Address Strobe (ALE) starts pulsing again, the PSD Module returns to normal Operating mode. The PSD Module also returns to normal Operating mode if either PSD Chip Select Input (CSI, PD2) is Low or the RESET input is High. - The MCU address/data bus is blocked from all memory and PLDs. - Various signals can be blocked (prior to Power-down Mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common CLKIN (PD1). Note: Blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit. - All memories enter Standby Mode and are drawing standby current. However, the PLD and I/O ports blocks do not go into Standby Mode because you don't want to have to wait for the logic and I/O to "wake-up" before their outputs can change. See Table 101 for Powerdown Mode effects on PSD Module ports. Typical standby current is of the order of microamperes. These standby current values assume that there are no transitions on any PLD input. Other Power Saving Options. The PSD Module offers other reduced power saving options that are independent of the Power-down Mode. Except for the SRAM Stand-by and PSD Chip Select Input (CSI, PD2) features, they are enabled by setting bits in PMMR0 and PMMR2. Figure 70. Enable Power-down Flow Chart RESET - Enable APD Set PMMR0 Bit 1 = 1 OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 2 through 6. No ALE idle for 15 CLKIN clocks? Yes PSD Module in Power Down Mode AI06609 Table 101. Power-down Mode's Effect on Ports Port Function MCU I/O PLD Out Address Out Peripheral I/O Pin Level No Change No Change Undefined Tri-State 129/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PLD Power Management The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By setting the bit to '1,' the Turbo Mode is off and the PLDs consume the specified stand-by current when the inputs are not switching for an extended time of 70ns. The propagation delay time is increased by 10ns (for a 5V device) after the Turbo Bit is set to '1' (turned off) when the inputs change at a composite frequency of less than 15MHz. When the Turbo Bit is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD's DC power, AC power, and propagation delay. When the Turbo Mode is off, the uPSD3200 input clock frequency is reduced by 5MHz from the maximum rated clock frequency. Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power consumption. SRAM Standby Mode (Battery Backup). The SRAM in the PSD Module supports a battery backup mode in which the contents are retained in the event of a power loss. The SRAM has Voltage Stand-by (VSTBY, PC2) that can be connected to an external battery. When VCC becomes lower than VSTBY then the SRAM automatically connects to Voltage Stand-by (VSTBY, PC2) as a power source. The SRAM Standby Current (ISTBY) is typically 0.5 A. The SRAM data retention voltage is 2V minimum. The Battery-on Indicator (VBATON) can be routed to PC4. This signal indicates when the VCC has dropped below VSTBY. PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select Input (CSI). When Low, the signal selects and enables the PSD Module Flash memory, SRAM, and I/O blocks for READ or WRITE operations. A High on PSD Chip Select Input (CSI, PD2) disables the Flash memory, and SRAM, and reduces power consumption. However, the PLD and I/O signals remain operational when PSD Chip Select Input (CSI, PD2) is High. Input Clock CLKIN (PD1) can be turned off, to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output Macrocells (OMC). During Power-down Mode, or, if CLKIN (PD1) is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from the PLD AND Array or the Macrocells block by setting Bits 4 or 5 to a '1' in PMMR0. Input Control Signals The PSD Module provides the option to turn off the MCU signals (WR, RD, PSEN, and Address Strobe (ALE)) to the PLD to save AC power consumption. These control signals are inputs to the PLD AND Array. During Power-down Mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits 2, 3, 4, 5, and 6 to a '1' in PMMR2. Table 102. Power Management Mode Registers PMMR0 Bit 0 Bit 1 Bit 2 X APD Enable 1 = on Automatic Power-down (APD) is enabled. X 0 Not used, and should be set to zero. 0 Not used, and should be set to zero. 0 = off Automatic Power-down (APD) is disabled. 0 = on PLD Turbo Mode is on Bit 3 PLD Turbo 1 = off 0 = on Bit 4 PLD Array clk PLD Turbo Mode is off, saving power. uPSD3200 operates at 5MHz below the maximum rated clock frequency CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN (PD1) Powers-up the PLD when Turbo Bit is '0.' 1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power. 0 = on CLKIN (PD1) input to the PLD macrocells is connected. Bit 5 Bit 6 Bit 7 PLD MCell clk 1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power. X X 0 0 Not used, and should be set to zero. Not used, and should be set to zero. 130/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 103. Power Management Mode Registers PMMR2 Bit 0 Bit 1 Bit 2 X X PLD Array WR PLD Array RD PLD Array PSEN PLD Array ALE X X 0 0 Not used, and should be set to zero. Not used, and should be set to zero. 0 = on WR input to the PLD AND Array is connected. 1 = off WR input to PLD AND Array is disconnected, saving power. 0 = on RD input to the PLD AND Array is connected. 1 = off RD input to PLD AND Array is disconnected, saving power. 0 = on PSEN input to the PLD AND Array is connected. 1 = off PSEN input to PLD AND Array is disconnected, saving power. 0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. 0 0 Not used, and should be set to zero. Not used, and should be set to zero. Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers. Table 104. APD Counter Operation APD Enable Bit 0 1 1 ALE Level X Pulsing 0 or 1 Not Counting Not Counting Counting (Generates PDN after 15 Clocks) APD Counter 131/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV RESET TIMING AND DEVICE STATUS AT RESET Upon Power-up, the PSD Module requires a Reset (RESET) pulse of duration tNLNH-PO after VCC is steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into operating mode. After the rising edge of Reset (RESET), the PSD Module remains in the Reset Mode for an additional period, tOPR, before the first memory access is allowed. The Flash memory is reset to the READ Mode upon Power-up. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must all be Low, WRITE Strobe (WR, CNTL0) High, during Power-on RESET for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of WRITE Strobe (WR). Any Flash memory WRITE cycle initiation is prevented automatically when VCC is below VLKO. Warm RESET Once the device is up and running, the PSD Module can be reset with a pulse of a much shorter duration, tNLNH. The same tOPR period is needed Figure 71. Reset (RESET) Timing before the device is operational after a Warm RESET. Figure 71 shows the timing of the Powerup and Warm RESET. I/O Pin, Register and PLD Status at RESET Table 105 shows the I/O pin, register and PLD status during Power-on RESET, Warm RESET, and Power-down Mode. PLD outputs are always valid during Warm RESET, and they are valid in Poweron RESET once the internal Configuration bits are loaded. This loading is completed typically long before the VCC ramps up to operating level. Once the PLD is active, the state of the outputs are determined by the PLD equations. Reset of Flash Memory Erase and Program Cycles A Reset (RESET) also resets the internal Flash memory state machine. During a Flash memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to the READ Mode within a period of tNLNH-A. VCC VCC(min) tNLNH tNLNH-A Warm Reset tNLNH-PO Power-On Reset tOPR tOPR RESET AI02866b 132/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 105. Status During Power-on RESET, Warm RESET and Power-down Mode Port Configuration MCU I/O PLD Output Address Out Peripheral I/O Power-On RESET Input mode Valid after internal PSD configuration bits are loaded Tri-stated Tri-stated Warm RESET Input mode Valid Tri-stated Tri-stated Power-down Mode Unchanged Depends on inputs to PLD (addresses are blocked in PD Mode) Not defined Tri-stated Register PMMR0 and PMMR2 Macrocells flip-flop status Power-On RESET Cleared to '0' Cleared to '0' by internal Power-on RESET Initialized, based on the selection in PSDsoft Configuration menu Cleared to '0' Warm RESET Unchanged Depends on .re and .pr equations Initialized, based on the selection in PSDsoft Configuration menu Cleared to '0' Power-down Mode Unchanged Depends on .re and .pr equations Unchanged Unchanged VM Register(1) All other registers Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET. 133/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface pins (TMS, TCK, TDI, TDO) are dedicated pins on Port C (see Table 106). All memory blocks (primary and secondary Flash memory), PLD logic, and PSD Module Configuration Register Bits may be programmed through the JTAG Serial Interface block. A blank device can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and Erase cycles. By default, on a blank device (as shipped from the factory or after erasure), four pins on Port C are the basic JTAG signals TMS, TCK, TDI, and TDO. Standard JTAG Signals At power-up, the standard JTAG pins are inputs, waiting for a JTAG serial command from an external JTAG controller device (such as FlashLINK or Automated Test Equipment). When the enabling command is received, TDO becomes an output and the JTAG channel is fully functional. The same command that enables the JTAG channel may optionally enable the two additional JTAG signals, TSTAT and TERR. The RESET input to the uPS3200 should be active during JTAG programming. The active RESET puts the MCU module into RESET Mode while the PSD Module is being programmed. See Application Note AN1153 for more details on JTAG InSystem Programming (ISP). The uPSD323X Devices supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. The PSDsoft Express software tool and FlashLINK JTAG programming cable implement the JTAG In-System-Configuration (ISC) commands. Table 106. JTAG Port Signals Port C Pin PC0 PC1 PC3 PC4 PC5 PC6 JTAG Signals TMS TCK TSTAT TERR TDI TDO Description Mode Select Clock Status (optional) Error Flag (optional) Serial Data In Serial Data Out JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an "ISC_ENABLE" command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on uPDS signals instead of having to scan the status out serially using the standard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low until an "ISC_CLEAR" command is executed or a chip Reset (RESET) pulse is received after an "ISC_DISABLE" command. TSTAT behaves the same as Ready/Busy described in Ready/Busy (PC3), page 99. TSTAT is High when the PSD Module device is in READ Mode (primary and secondary Flash memory contents can be read). TSTAT is Low when Flash memory Program or Erase cycles are in progress, and also when data is being written to the secondary Flash memory. TSTAT and TERR can be configured as opendrain type signals during an "ISC_ENABLE" command. Security and Flash memory Protection When the Security Bit is set, the device cannot be read on a Device Programmer or through the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed. All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part to a non-secured blank state. The Security Bit can be set in PSDsoft Express Configuration. All primary and secondary Flash memory sectors can individually be sector protected against erasures. The sector protect bits can be set in PSDsoft Express Configuration. INITIAL DELIVERY STATE When delivered from ST, the uPSD323X Devices have all bits in the memory and PLDs set to '1.' The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative. 134/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV AC/DC PARAMETERS These tables describe the AD and DC parameters of the uPSD323X Devices: DC Electrical Specification AC Timing Specification PLD Timing - Combinatorial Timing - Synchronous Clock Mode - Asynchronous Clock Mode - Input Macrocell Timing MCU Module Timing - READ Timing - WRITE Timing - Power-down and RESET Timing The following are issues concerning the parameters presented: - In the DC specification the supply current is given for different modes of operation. - The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figures 72 and 73 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. - In the PLD timing parameters, add the required delay when Turbo Bit is '0.' Figure 72. PLD ICC /Frequency Consumption (5V range) 110 100 90 80 ICC - (mA) 70 FF O VCC = 5V %) (100 ON BO TUR 60 TU RB 50 40 30 20 10 0 0 5 BO TUR ON (25% ) O O RB TU F OF PT 100% PT 25% 10 15 20 25 AI02894 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) Figure 73. PLD ICC /Frequency Consumption (3V range) 60 VCC = 3V 50 ICC - (mA) 40 B TUR N( OO 100% ) O FF 30 20 10 TU RB O O TU R B 5 ON (2 %) O RB TU 0 0 5 F OF PT 100% PT 25% 10 15 20 25 AI03100 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) 135/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 107. PSD Module Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off) Conditions MCU Clock Frequency Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = 45 PT = 45/182 = 24.7% = Off Calculation (using typical values) ICC total = ICC(MCUactive) x %MCUactive + ICC(PSDactive) x %PSDactive + IPD(pwrdown) x %pwrdown ICC(MCUactive) IPD(pwrdown) ICC(PSDactive) = 20mA = 250A = ICC(ac) + ICC(dc) = %flash x 2.5mA/MHz x Freq ALE + %SRAM x 1.5mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD) = 0.8 x 2.5mA/MHz x 2MHz + 0.15 x 1.5mA/MHz x 2MHz + 24mA = (4 + 0.45 + 24) mA = 28.45mA ICC total = 20mA x 40% + 28.45mA x 40% + 250A x 60% = 8mA + 11.38mA + 150A = 19.53mA This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/O pins being disconnected and IOUT = 0mA. = 40% = 60% = 8MHz = 2MHz = 80% = 15% = 5% (no additional power above base) = 12MHz 136/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 108. Absolute Maximum Ratings Symbol TSTG TLEAD VIO VCC VPP VESD Storage Temperature Lead Temperature during Soldering (20 seconds max.)(1) Input and Output Voltage (Q = VOH or Hi-Z) Supply Voltage Device Programmer Supply Voltage Electrostatic Discharge Voltage (Human Body Model)(2) -0.5 -0.5 -0.5 -2000 Parameter Min. -65 Max. 125 235 6.5 6.5 14.0 2000 Unit C C V V V V plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 , R2=500 ) 137/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV EMC CHARACTERISTICS Susceptibility test are performed on a sample basis during product characterization. Functional EMS (Electromagnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ESD. Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 Standard. FTB. A burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 Standard. A device reset allows normal operations to be resumed. The test results are given in Table 109, based on the EMS levels and classes defined in Application Note AN1709. Designing Hardened Software To Avoid Noise Problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore, it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for the user's application. Software Recommendations. The software flowchart must include the management of `runaway' conditions, such as: - Corrupted program counter - Unexpected reset - Critical data corruption (e.g., control registers) Prequalification trials. Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see Application Note AN1015). Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU, and DLU) and using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the Application Note AN1181. Electro-Static Discharge (ESD). Electro-Static discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). The Human Body Model is simulated (see Table 110). This test conforms to the JESD22-A114A Standard. Table 109. EMS Test Results Symbol VFESD Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Conditions VDD = 4V; TA = 25C; fOSC = 40MHz; WDT off conforms to IEC 1000-4-2 Level/ Class(1) 3C Note: 1. Data based on characterization results, not tested in production. Table 110. ESD Absolute Maximum Ratings Symbol VESD(HBM) Parameter Electro-static discharge voltage (Human Body Model) Conditions TA = 25C Maximum Value(1) 2000 Unit V Note: 1. Data based on characterization results, not tested in production 138/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV LU. 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output, and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC Latch-up Standard (see Table 111). For more details, refer to the Application Note, AN1181. DLU. Electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro, and the component is put in reset mode. This test conforms to the IEC 1000-4-2 and SAEJ1752/3 Standards (see Table 111). For more details, refer to the Application Note, AN1181. Table 111. Latch-up and Dynamic Latch-up Electrical Sensitivities Symbol LU DLU Parameter Static Latch-up Class Dynamic Latch-up Class Conditions TA = 25C VDD = 5V; TA = 25C; fOSC = 40MHz Level/ Class(1) A A Note: 1. Class description: A Class is an STMicroelectronics internal specification. All of its limits are higher than the JEDEC specifications. This means when a device belongs to "Class A," it exceeds the JEDEC standard. "Class B" strictly covers all of the JEDEC criteria (International standards). 139/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 112. Operating Conditions (5V Devices) Symbol VCC TA Ambient Operating Temperature (Commercial) 0 70 C Supply Voltage Ambient Operating Temperature (Industrial) Parameter Min. 4.5 -40 Max. 5.5 85 Unit V C ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 113. Operating Conditions (3V Devices) Symbol VCC TA Ambient Operating Temperature (Commercial) 0 70 C Supply Voltage Ambient Operating Temperature (Industrial) Parameter Min. 3.0 -40 Max. 3.6 85 Unit V C Table 114. AC Letter Symbols for Timing A C D I L N P Q R W B M Address Clock Input Data Instruction ALE RESET Input or Output PSEN signal Output Data RD signal WR signal VSTBY Output Output Macrocell Table 115. AC Signal Behavior Symbols for Timing t L H V X Z PW Time Logic Level Low or ALE Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width Note: Example: tAVLX = Time from Address Valid to ALE Invalid. Note: Example: tAVLX = Time from Address Valid to ALE Invalid. 140/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 74. Switching Waveforms - Key WAVEFORMS INPUTS OUTPUTS STEADY INPUT STEADY OUTPUT MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI DON'T CARE CHANGING, STATE UNKNOWN OUTPUTS ONLY CENTER LINE IS TRI-STATE AI03102 141/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 116. Major Parameters Parameters/Conditions/ Comments Operating Voltage Operating Temperature MCU Frequency 12MHz (min) for USB; 8MHz (min) for I2C Active Current, Typical (25C operation; 80% Flash and 15% SRAM accesses, 45 PLD product terms used; PLD Turbo mode Off) Idle Current, Typical (CPU halted but some peripherals active; 25C operation; 45 PLD product terms used; PLD Turbo mode Off) Standby Current, Typical (Power-down Mode, requires reset to exit mode; without Low-Voltage Detect (LVD) Supervisor) SRAM Backup Current, Typical (If external battery is attached.) I/O Sink/Source Current Ports A, B, C, and D PLD Macrocells (For registered or combinatorial logic) PLD Inputs (Inputs from pins, macrocell feedback, or MCU addresses) PLD Outputs (Output to pins or internal feedback) PLD Propagation Delay, Typical (PLD input to output, Turbo Mode) 5V Test Conditions - - - 5.0V Value 4.5 to 5.5 -40 to 85 1 Min, 40 Max 3.3V Test Conditions - - - 3.3V Value 3.0 to 3.6 -40 to 85 Unit V C 1 Min, 24 Max MHz 24MHz MCU clock, 12MHz PLD input frequency, 4MHz ALE 72 12MHz MCU clock, 6MHz PLD input frequency, 2MHz ALE 21 mA 24MHz MCU clock, 12MHz PLD input frequency 25 12MHz MCU clock, 1MHz PLD input frequency 7 mA 180A with LVD 110 100A with LVD 60 A - VOL = 0.25V (max); VOH = 3.9V (min) - 0.5 IOL = 8 (max); IOH = -2 (min) 16 - VOL = 0.15V (max); VOH = 2.6V (min) - 0.5 IOL = 4 (max); IOH = -1 (min) 16 A mA - - 69 - 69 - - 16 - 16 - - 15 - 22 ns 142/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 117. DC Characteristics (5V Devices) Symbol Parameter Test Condition (in addition to those in Table 112., page 140) 4.5V < VCC < 5.5V Min. Typ. Max. Unit VIH Input High Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) Input High Voltage (Ports A, B, C, D, 4[Bit 2], USB+, USB-) Input Low Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) Input Low Voltage (Ports A, B, C, D, 4[Bit 2]) Input Low Voltage (USB+, USB-) 0.7VCC VCC + 0.5 VCC + 0.5 0.3VCC V VIH1 4.5V < VCC < 5.5V 2.0 V VIL 4.5V < VCC < 5.5V VSS- 0.5 V 4.5V < VCC < 5.5V 4.5V < VCC < 5.5V IOL = 20A VCC = 4.5V IOL = 8mA VCC = 4.5V IOL = 1.6mA IOL = 3.2mA IOH = -20A VCC = 4.5V IOH = -2mA VCC = 4.5V IOH = -80A IOH = -10A IOH = -800A IOH = -80A IOH = -1A 0.1V hysteresis IOL = 3.2mA -0.5 VSS- 0.5 0.01 0.25 0.8 0.8 0.1 0.45 0.45 0.45 V V V V V V V V V V V V V VIL1 VOL Output Low Voltage (Ports A,B,C,D) VOL1 VOL2 Output Low Voltage (Ports 1,2,3,4, WR, RD) Output Low Voltage (Port 0, ALE, PSEN) 4.4 2.4 2.4 4.05 2.4 4.05 VSTBY - 0.8 3.75 2.0 2.5 2.0 4.49 3.9 VOH Output High Voltage (Ports A,B,C,D) VOH1 Output High Voltage (Ports 1,2,3,4, WR, RD) Output High Voltage (Port 0 in ext. Bus Mode, ALE, PSEN) Output High Voltage VSTBYON Low Voltage RESET XTAL Open Bias Voltage (XTAL1, XTAL2) VCC(min) for Flash Erase and Program SRAM (PSD) Stand-by Voltage SRAM (PSD) Data Retention Voltage Logic '0' Input Current (Ports 1,2,3,4) VOH2 VOH3 VLVR VOP VLKO VSTBY VDF IIL 4.0 4.25 3.0 4.2 VCC - 0.2 V V V V V Only on VSTBY VIN = 0.45V (0V for Port 4[pin 2]) 2 -10 -50 A 143/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Test Condition (in addition to those in Table 112., page 140) VIN = 3.5V (2.5V for Port 4[pin 2]) VCC = 0V VCC > VSTBY VIN = VSS XTAL1 = VCC XTAL2 = VSS VSS < VIN < VCC 0.45 < VOUT < VCC VCC = 5.5V LVD logic disabled LVD logic enabled Active (12MHz) Idle (12MHz) ICC_CPU(2,3,6) Active (24MHz) Idle (24MHz) Active (40MHz) VCC = 5V Idle (40MHz) PLD_TURBO = Off, f = 0MHz(4) PLD_TURBO = On, f = 0MHz Flash memory SRAM PLD AC Base ICC_PSD (AC)6 Note: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Symbol Parameter Min. Typ. Max. Unit ITL ISTBY IIDLE IRST IFR ILI ILO (1) Logic 1-to-0 Transition Current (Ports 1,2,3,4) SRAM (PSD) Stand-by Current (VSTBY input) SRAM (PSD) Idle Current (VSTBY input) Reset Pin Pull-up Current (RESET) XTAL Feedback Resistor Current (XTAL1) Input Leakage Current Output Leakage Current -65 0.5 -0.1 -10 -20 -1 -10 -650 1 0.1 -55 -50 1 10 250 380 20 30 10 38 20 62 30 A A A A A A A A A mA mA mA mA mA mA A/P(5) IPD Power-down Mode VCC = 5V 8 30 15 40 20 0 400 15 0 0 Note 5 2.5 1.5 VCC = 5V PLD Only ICC_PSD (DC)(6) Operating Supply Current 700 30 0 0 A/PT mA mA mA During Flash memory WRITE/Erase Only Read-only, f = 0MHz f = 0MHz Flash memory AC Adder SRAM AC Adder 3.5 3.0 mA/MHz mA/MHz IPD (Power-down Mode) is measured with: XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not in Turbo Mode. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH , tCHCL = 5ns, VIL = VSS+0.5V, VIH = Vcc - 0.5V, XTAL2 = not connected; RESET=VSS; Port 0=VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). ICC_CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS+0.5V, VIH = VCC- 0.5V, XTAL2 = not connected; Port 0 = VCC; RESET=VCC; all other pins are disconnected. PLD is in non-Turbo Mode and none of the inputs are switching. See Figure 72., page 135 for the PLD current calculation. I/O current = 0mA, all I/O pins are disconnected. 144/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 118. DC Characteristics (3V Devices) Symbol Parameter Test Condition (in addition to those in Table 113., page 140) 3.0V < VCC < 3.6V Min. Typ. Max. Unit VIH Input High Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], A, B, C, D, XTAL1, RESET) Input High Voltage (Port 4[Bit 2]) Input High Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) Input Low Voltage (Ports A, B, C, D) Input Low Voltage (Port 4[Bit 2]) 0.7VCC VCC + 0.5 V VIH1 3.0V < VCC < 3.6V 2.0 VCC + 0.5 V VIL 3.0V < VCC < 3.6V VSS- 0.5 0.3VCC V 3.0V < VCC < 3.6V 3.0V < VCC < 3.6V IOL = 20A VCC = 3.0V IOL = 4mA VCC = 3.0V IOL = 1.6mA IOL = 100A IOL = 3.2mA IOL = 200A IOH = -20A VCC = 3.0V IOH = -1mA VCC = 3.0V IOH = -20A IOH = -10A IOH = -800A IOH = -80A IOH = -1A 0.1V hysteresis IOL = 3.2mA -0.5 VSS- 0.5 0.01 0.15 0.8 0.8 0.1 0.45 0.45 0.3 0.45 0.3 V V V V V V V V V V V V V V V VIL1 VOL Output Low Voltage (Ports A,B,C,D) VOL1 Output Low Voltage (Ports 1,2,3,4, WR, RD) Output Low Voltage (Port 0, ALE, PSEN) VOL2 2.9 2.4 2.0 2.7 2.0 2.7 VSTBY - 0.8 2.3 1.0 1.5 2.0 2.99 2.6 VOH Output High Voltage (Ports A,B,C,D) VOH1 Output High Voltage (Ports 1,2,3,4, WR, RD) Output High Voltage (Port 0 in ext. Bus Mode, ALE, PSEN) Output High Voltage VSTBYON Low Voltage Reset XTAL Open Bias Voltage (XTAL1, XTAL2) VCC(min) for Flash Erase and Program SRAM (PSD) Stand-by Voltage SRAM (PSD) Data Retention Voltage Logic '0' Input Current (Ports 1,2,3,4) VOH2 VOH3 VLVR VOP VLKO VSTBY VDF IIL 2.5 2.7 2.0 2.2 VCC - 0.2 V V V V V Only on VSTBY VIN = 0.45V (0V for Port 4[pin 2]) 2 -1 -50 A 145/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Test Condition (in addition to those in Table 113., page 140) VIN = 3.5V (2.5V for Port 4[pin 2]) VCC = 0V VCC > VSTBY VIN = VSS XTAL1 = VCC XTAL2 = VSS VSS < VIN < VCC 0.45 < VOUT < VCC VCC = 3.6V LVD logic disabled LVD logic enabled Active (12MHz) ICC_CPU(2,3,6) Idle (12MHz) Active (24MHz) Idle (24MHz) VCC = 3.6V 8 4 15 8 0 200 10 0 0 Note 5 1.5 0.8 2.0 1.5 mA/MHz mA/MHz 400 25 0 0 -0.1 -10 -20 -1 -10 Symbol Parameter Min. Typ. Max. Unit ITL ISTBY IIDLE IRST IFR ILI ILO (1) Logic 1-to-0 Transition Current (Ports 1,2,3,4) SRAM (PSD) Stand-by Current (VSTBY input) SRAM (PSD) Idle Current (VSTBY input) Reset Pin Pull-up Current (RESET) XTAL Feedback Resistor Current (XTAL1) Input Leakage Current Output Leakage Current -25 0.5 -250 1 0.1 -55 -50 1 10 110 180 10 5 20 10 A A A A A A A A A mA mA mA mA A/PT(5) A/PT mA mA mA IPD Power-down Mode VCC = 3.6V PLD_TURBO = Off, f = 0MHz(4) PLD_TURBO = On, f = 0MHz Flash memory SRAM During Flash memory WRITE/Erase Only Read-only, f = 0MHz f = 0MHz PLD Only ICC_PSD (DC)(6) Operating Supply Current PLD AC Base ICC_PSD (AC)(6) Note: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Flash memory AC Adder SRAM AC Adder IPD (Power-down Mode) is measured with: XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not in Turbo mode. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS+0.5V, VIH = Vcc - 0.5V, XTAL2 = not connected; RESET=VSS; Port 0=VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). ICC_CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS+0.5V, VIH = VCC- 0.5V, XTAL2 = not connected; Port 0 = VCC; RESET=VCC; all other pins are disconnected. PLD is in non-Turbo Mode and none of the inputs are switching. See Figure 72., page 135 for the PLD current calculation. I/O current = 0mA, all I/O pins are disconnected. 146/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 75. External Program Memory READ Cycle tLHLL ALE tAVLL tPLPH tLLIV tPLIV PSEN tLLAX tAZPL PORT 0 A0-A7 tAVIV PORT 2 A8-A11 INSTR IN tPXIX A8-A11 AI06848 tLLPL tPXAV tPXIZ A0-A7 Table 119. External Program Memory AC Characteristics (with the 5V MCU Module) Symbol Parameter(1) 40MHz Oscillator Min tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ(2) tPXAV(2) tAVIV tAZPL ALE pulse width Address set-up to ALE Address hold after ALE ALE Low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN -5 20 70 -5 0 15 tCLCL - 5 5tCLCL - 55 10 60 30 0 tCLCL - 10 35 10 10 55 tCLCL - 15 3tCLCL - 15 3tCLCL - 45 Max Variable Oscillator 1/tCLCL = 24 to 40MHz Min 2tCLCL - 15 tCLCL - 15 tCLCL - 15 4tCLCL - 45 Max ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Conditions (in addition to those in Table 112., page 140, VCC = 4.5 to 5.5V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for other outputs is 80pF 2. Interfacing the uPSD323X Devices to devices with float times up to 20ns is permissible. This limited bus contention does not cause any damage to Port 0 drivers. 147/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 120. External Program Memory AC Characteristics (with the 3V MCU Module) Symbol tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ(2) tPXAV(2) tAVIV tAZPL Parameter ALE pulse width Address set-up to ALE Address hold after ALE ALE Low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN -10 37 148 -10 0 32 tCLCL - 5 5tCLCL - 60 22 95 60 0 tCLCL - 10 (1) 24MHz Oscillator Min 43 17 17 80 Max Variable Oscillator 1/tCLCL = 8 to 24MHz Min 2tCLCL - 40 tCLCL - 25 tCLCL - 25 4tCLCL - 87 tCLCL - 20 3tCLCL - 30 3tCLCL - 65 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. Conditions (in addition to those in Table 113., page 140, VCC = 3.0 to 3.6V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF, for 5V devices, and 50pF for 3V devices; CL for other outputs is 80pF, for 5V devices, and 50pF for 3V devices) 2. Interfacing the uPSD323X Devices to devices with float times up to 35ns is permissible. This limited bus contention does not cause any damage to Port 0 drivers. Table 121. External Clock Drive (with the 5V MCU Module) Symbol tRLRH tWLWH tLLAX2 tRHDX tRHDX Parameter Oscillator period High time Low time Rise time Fall time (1) 40MHz Oscillator Min Max Variable Oscillator 1/tCLCL = 24 to 40MHz Min 25 10 10 Max 41.7 tCLCL - tCLCX tCLCL - tCLCX 10 10 Unit ns ns ns ns ns Note: 1. Conditions (in addition to those in Table 112., page 140, VCC = 4.5 to 5.5V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for other outputs is 80pF Table 122. External Clock Drive (with the 3V MCU Module) Symbol tRLRH tWLWH tLLAX2 tRHDX tRHDX Parameter Oscillator period High time Low time Rise time Fall time (1) 24MHz Oscillator Min Max Variable Oscillator 1/tCLCL = 8 to 24MHz Min 41.7 12 12 Max 125 tCLCL - tCLCX tCLCL - tCLCX 12 12 Unit ns ns ns ns ns Note: 1. Conditions (in addition to those in Table 113., page 140, VCC = 3.0 to 3.6V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF, for 5V devices, and 50pF for 3V devices; CL for other outputs is 80pF, for 5V devices, and 50pF for 3V devices) 148/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 76. External Data Memory READ Cycle ALE tLHLL PSEN tLLDV tLLWL RD tAVLL tLLAX2 PORT 0 A0-A7 from RI or DPL tWHLH tRLRH tRLDV tRLAZ tRHDZ tRHDX DATA IN A0-A7 from PCL INSTR IN tAVWL tAVDV PORT 2 P2.0 to P2.3 or A8-A11 from DPH A8-A11 from PCH AI07088 Figure 77. External Data Memory WRITE Cycle ALE tLHLL PSEN tLLWL WR tAVLL tLLAX PORT 0 A0-A7 from RI or DPL tWHLH tWLWH tQVWX tQVWH DATA OUT tWHQX A0-A7 from PCL INSTR IN tAVWL PORT 2 P2.0 to P2.3 or A8-A11 from DPH A8-A11 from PCH AI07089 149/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 123. External Data Memory AC Characteristics (with the 5V MCU Module) Symbol Parameter(1) 40MHz Oscillator Min tRLRH tWLWH tLLAX2 tRHDX tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD High to ALE High Data valid to WR transition Data set-up before WR Data hold after WR Address float after RD 60 70 10 5 125 5 0 40 0 38 150 150 90 3tCLCL - 15 4tCLCL - 30 tCLCL - 15 tCLCL - 20 7tCLCL - 50 tCLCL - 20 0 tCLCL + 15 120 120 10 75 0 2tCLCL - 12 8tCLCL - 50 9tCLCL - 75 tCLCL + 15 Max Variable Oscillator 1/tCLCL = 24 to 40MHz Min 6tCLCL - 30 6tCLCL - 30 tCLCL - 15 5tCLCL - 50 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Conditions (in addition to those in Table 112., page 140, VCC = 4.5 to 5.5V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for other outputs is 80pF 150/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 124. External Data Memory AC Characteristics (with the 3V MCU Module) Symbol Parameter(1) 24MHz Oscillator Min tRLRH tWLWH tLLAX2 tRHDX tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD High to ALE High Data valid to WR transition Data set-up before WR Data hold after WR Address float after RD 75 67 17 5 170 15 0 67 0 63 200 220 175 3tCLCL - 50 4tCLCL - 97 tCLCL - 25 tCLCL - 37 7tCLCL - 122 tCLCL - 27 0 tCLCL + 25 180 180 56 118 0 2tCLCL - 20 8tCLCL - 133 9tCLCL - 155 tCLCL + 50 Max Variable Oscillator 1/tCLCL = 8 to 24MHz Min 6tCLCL - 70 6tCLCL - 70 2tCLCL - 27 5tCLCL - 90 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Conditions (in addition to those in Table 113., page 140, VCC = 3.0 to 3.6V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF, for 5V devices, and 50pF for 3V devices; CL for other outputs is 80pF, for 5V devices, and 50pF for 3V devices) Table 125. A/D Analog Specification Symbol AVREF VAN IAVDD CAIN NNLE NDNLE NZOE NFSE NGE TCONV Parameter Analog Power Supply Input Voltage Range Analog Input Voltage Range Current Following between VCC and VSS Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero-Offset Error Full Scale Error Gain Error Conversion Time at 8MHz clock Test Condition Min. VSS VSS - 0.3 Typ. Max. VCC AVREF + 0.3 200 2 2 2 2 2 2 20 Unit V V A l.s.b. l.s.b. l.s.b. l.s.b. l.s.b. l.s.b. s 151/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 78. Input to Output Disable / Enable INPUT tER INPUT TO OUTPUT ENABLE/DISABLE tEA AI02863 Table 126. CPLD Combinatorial Timing (5V Devices) Symbol tPD(2) tEA tER tARP tARPW tARD Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any macrocell 10 11 +2 Conditions Min Max 20 21 21 21 PT Turbo Slew Aloc Off rate(1) +2 + 10 + 10 + 10 + 10 + 10 -2 -2 -2 -2 Unit ns ns ns ns ns ns Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) Table 127. CPLD Combinatorial Timing (3V Devices) Symbol tPD(2) tEA tER tARP tARPW tARD Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any macrocell 25 25 +4 Conditions Min Max 40 43 43 40 PT Turbo Slew Aloc Off rate(1) +4 + 20 + 20 + 20 + 20 + 20 -6 -6 -6 -6 Unit ns ns ns ns ns ns Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) 152/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 79. Synchronous Clock Mode Timing - PLD tCH tCL CLKIN tS INPUT tH tCO REGISTERED OUTPUT AI02860 Table 128. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period(2) Clock Input Clock Input Clock Input Any macrocell tCH+tCL 12 Conditions 1/(tS+tCO) 1/(tS+tCO-10) 1/(tCH+tCL) 12 0 6 6 13 11 +2 -2 Min Max 40.0 66.6 83.3 +2 + 10 PT Turbo Slew Aloc Off rate(1) Unit MHz MHz MHz ns ns ns ns ns ns ns Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. 153/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 129. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period(2) Clock Input Clock Input Clock Input Any macrocell tCH+tCL 25 Conditions 1/(tS+tCO) 1/(tS+tCO-10) 1/(tCH+tCL) 20 0 15 10 25 25 +4 -6 Min Max 22.2 28.5 40.0 +4 + 20 PT Aloc Turbo Slew Off rate(1) Unit MHz MHz MHz ns ns ns ns ns ns ns Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. Figure 80. Asynchronous RESET / Preset tARPW RESET/PRESET INPUT tARP REGISTER OUTPUT AI02864 Figure 81. Asynchronous Clock Mode Timing (product term clock) tCHA tCLA CLOCK tSA tHA INPUT tCOA REGISTERED OUTPUT AI02859 154/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 130. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices) Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARDA tMINA Input Setup Time Input Hold Time Clock Input High Time Clock Input Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any macrocell 1/fCNTA 16 Conditions 1/(tSA+tCOA) 1/(tSA+tCOA-10) 1/(tCHA+tCLA) 7 8 9 9 21 11 +2 + 10 + 10 + 10 -2 Min Max 38.4 62.5 71.4 +2 + 10 PT Turbo Slew Aloc Off Rate Unit MHz MHz MHz ns ns ns ns ns ns ns Table 131. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices) Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARD tMINA Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any macrocell 1/fCNTA 36 Conditions 1/(tSA+tCOA) 1/(tSA+tCOA-10) 1/(tCHA+tCLA) 10 12 17 13 36 25 +4 + 20 + 20 + 20 -6 Min Max 21.7 27.8 33.3 +4 + 20 PT Turbo Slew Aloc Off Rate Unit MHz MHz MHz ns ns ns ns ns ns ns 155/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 82. Input Macrocell Timing (product term clock) t INH PT CLOCK t INL t IS INPUT t IH OUTPUT t INO AI03101 Table 132. Input Macrocell Timing (5V Devices) Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 15 9 9 34 +2 + 10 + 10 Max PT Aloc Turbo Off Unit ns ns ns ns ns Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX. Table 133. Input Macrocell Timing (3V Devices) Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 25 12 12 46 +4 + 20 + 20 Max PT Aloc Turbo Off Unit ns ns ns ns ns Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. 156/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 134. Program, WRITE and Erase Times (5V Devices) Symbol Flash Program Flash Bulk Erase(1) (pre-programmed) Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per Sector) tWHWLO tQ7VQV Sector Erase Time-Out DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling) (2) Parameter Min. Typ. 8.5 3 5 1 2.2 14 Max. Unit s 30 s s 30 s s 150 s cycles 100,000 100 30 s ns Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Table 135. Program, WRITE and Erase Times (3V Devices) Symbol Flash Program Flash Bulk Erase(1) (pre-programmed) Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per Sector) tWHWLO tQ7VQV Sector Erase Time-Out DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling) (2) Parameter Min. Typ. 8.5 3 5 1 2.2 14 Max. Unit s 30 s s 30 s s 150 s cycles 100,000 100 30 s ns Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. 157/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 83. Peripheral I/O READ Timing ALE A/D BUS ADDRESS DATA VALID tAVQV (PA) tSLQV (PA) CSI tRLQV (PA) RD tRHQZ (PA) tDVQV (PA) DATA ON PORT A AI06610 Table 136. Port A Peripheral Data Mode READ Timing (5V Devices) Symbol tAVQV-PA tSLQV-PA tRLQV-PA tDVQV-PA tRHQZ-PA Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid Data In to Data Out Valid RD to Data High-Z (Note 2) Conditions (Note 1) Min Max 37 27 32 22 23 Turbo Off + 10 + 10 Unit ns ns ns ns ns Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A. Table 137. Port A Peripheral Data Mode READ Timing (3V Devices) Symbol tAVQV-PA tSLQV-PA tRLQV-PA tDVQV-PA tRHQZ-PA Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid Data In to Data Out Valid RD to Data High-Z (Note 2) Conditions (Note 1) Min Max 50 37 45 38 36 Turbo Off + 20 + 20 Unit ns ns ns ns ns Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A. 158/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 84. Peripheral I/O WRITE Timing ALE A / D BUS ADDRESS DATA OUT tWLQV WR (PA) tWHQZ (PA) tDVQV (PA) PORT A DATA OUT AI06611 Table 138. Port A Peripheral Data Mode WRITE Timing (5V Devices) Symbol tWLQV-PA tDVQV-PA tWHQZ-PA Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state (Note 1) Conditions Min Max 25 22 20 Unit ns ns ns Note: 1. Data stable on Port 0 pins to data on Port A. Table 139. Port A Peripheral Data Mode WRITE Timing (3V Devices) Symbol tWLQV-PA tDVQV-PA tWHQZ-PA Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state (Note 1) Conditions Min Max 42 38 33 Unit ns ns ns Note: 1. Data stable on Port 0 pins to data on Port A. 159/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 85. Reset (RESET) Timing VCC VCC(min) tNLNH tNLNH-A Warm Reset tNLNH-PO Power-On Reset tOPR tOPR RESET AI02866b Table 140. Reset (RESET) Timing (5V Devices) Symbol tNLNH tNLNH-PO tNLNH-A tOPR Parameter RESET Active Low Time(1) Power-on Reset Active Low Time Warm RESET (2) RESET High to Operational Device Conditions Min 150 1 25 120 Max Unit ns ms s ns Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. Table 141. Reset (RESET) Timing (3V Devices) Symbol tNLNH tNLNH-PO tNLNH-A tOPR Parameter RESET Active Low Time(1) Power-on Reset Active Low Time Warm RESET (2) RESET High to Operational Device Conditions Min 300 1 25 300 Max Unit ns ms s ns Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. Table 142. VSTBYON Definitions Timing (5V Devices) Symbol tBVBH tBXBL Parameter VSTBY Detection to VSTBYON Output High VSTBY Off Detection to VSTBYON Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 Max Unit s s Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. Table 143. VSTBYON Timing (3V Devices) Symbol tBVBH tBXBL Parameter VSTBY Detection to VSTBYON Output High VSTBY Off Detection to VSTBYON Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 Max Unit s s Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. 160/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 86. ISC Timing t ISCCH TCK t ISCCL t ISCPSU t ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO AI02865 Table 144. ISC Timing (5V Devices) Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 240 240 7 5 21 21 21 23 23 2 Min Max 20 Unit MHz ns ns MHz ns ns ns ns ns ns ns Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode. 2. For Program or Erase PLD only. 161/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 145. ISC Timing (3V Devices) Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 240 240 12 5 30 30 30 40 40 2 Min Max 12 Unit MHz ns ns MHz ns ns ns ns ns ns ns Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode. 2. For Program or Erase PLD only. Figure 87. MCU Module AC Measurement I/O Waveform VCC - 0.5V 0.2 VCC + 0.9V Test Points 0.2 VCC - 0.1V AI06650 0.45V Note: AC inputs during testing are driven at VCC-0.5V for a logic '1,' and 0.45V for a logic '0.' Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0' Figure 88. PSD Module AC Float I/O Waveform VOH - 0.1V Test Reference Points VLOAD - 0.1V 0.2 VCC - 0.1V VOL + 0.1V AI06651 VLOAD + 0.1V Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs IOL and IOH 20mA 162/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 89. External Clock Cycle Figure 90. Recommended Oscillator Circuits Note: C1, C2 = 30pF 10pF for crystals For ceramic resonators, contact resonator manufacturer Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Figure 91. PSD Module AC Measurement I/O Waveform Figure 92. PSD ModuleAC Measurement Load Circuit 2.01 V 3.0V Test Point 0V AI03103b 195 1.5V Device Under Test CL = 30 pF (Including Scope and Jig Capacitance) AI03104b Table 146. Capacitance Symbol CIN COUT Parameter Input Capacitance (for input pins) Output Capacitance (for input/ output pins) Test Condition VIN = 0V VOUT = 0V Typ.2 4 8 Max. 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. 2. Typical values are for TA = 25C and nominal supply voltages. 163/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PACKAGE MECHANICAL INFORMATION Figure 93. TQFP52 - 52-lead Plastic Thin, Quad, Flat Package Outline D D1 D2 A2 e Ne E2 E1 E b N 1 Nd L1 A CP c QFP-A Note: Drawing is not to scale. A1 L 164/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 147. TQFP52 - 52-lead Plastic Thin, Quad, Flat Package Mechanical Data mm Symb Typ A A1 A2 b c D D1 D2 E E1 E2 e L L1 n Nd Ne CP - 0.65 - 1.00 - - 0.45 - 0 52 13 13 - 0.10 - - 0.75 - 7 0.026 - 0.039 - - 0.018 - 0 52 13 13 - 0.004 - 0.030 - 7 12.00 10.00 - - - - 0.473 0.394 - - - - - - - - - 12.00 10.00 Min - 0.05 1.25 0.02 0.07 - - Max 1.75 0.020 1.55 0.04 0.23 - - Typ - - - - - 0.473 0.394 Min - 0.002 0.049 0.007 0.002 - - Max 0.069 0.008 0.061 0.016 0.009 - - inches 165/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Figure 94. TQFP80 - 80-lead Plastic Thin, Quad, Flat Package Outline D D1 D2 A2 e Ne E2 E1 E b N 1 Nd L1 A CP c QFP-A Note: Drawing is not to scale. A1 L 166/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Table 148. TQFP80 - 80-lead Plastic Thin, Quad, Flat Package Mechanical Data mm Symb Typ A A1 A2 b c D D1 D2 E E1 E2 e L L1 n Nd Ne CP - - - 1.40 0.22 - 14.00 12.00 9.50 14.00 12.00 9.50 0.50 0.60 1.00 3.5 Min - 0.05 1.35 0.17 0.09 - - - - - - - 0.45 - 0 80 20 20 - 0.08 - Max 1.60 0.15 1.45 0.27 0.20 - - - - - - - 0.75 - 7 Typ - - 0.055 0.009 - 0.551 0.472 0.374 0.551 0.472 0.374 0.020 0.024 0.039 3.5 Min - 0.002 0.053 0.007 0.004 - - - - - - - 0.018 - 0 80 20 20 - 0.003 Max 0.063 0.006 0.057 0.011 0.008 - - - - - - - 0.030 - 7 inches 167/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV PART NUMBERING Table 149. Ordering Information Scheme Example: Device Type uPSD = Microcontroller PSD Family 3 = 8032 core PLD Size 2 = 16 Macrocells SRAM Size 3 = 8K bytes Main Flash Memory Size 3 = 128K bytes 4 = 256K bytes IP Mix A = USB, I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) B = I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) Operating Voltage blank = VCC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Speed -24 = 24MHz -40 = 40MHz Package T = 52-pin TQFP U = 80-pin TQFP Temperature Range 1 = 0 to 70C 6 = -40 to 85C Shipping Option Tape & Reel Packing = T uPSD 3 2 3 4 B V - 24 U 6 T For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. 168/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV REVISION HISTORY Table 150. Document Revision History Date November 2002 Version 1.0 First Issue Updates: product information (Figure 3, 4, Table 1, 2); port information (Figure 17, 18, Table 30); interface information (Figure 30, Table 44); remove programming guide; PSD Module information (Figure 50, 51, Table 85); PLD information (Figure 58, 59, Table 91, 92, 93); electrical characteristics (Table 118, 119, 135, 136) Updated references for Product Catalog Reformatted; corrected mechanical dimensions (Table 148) Reformatted; added EMC characteristics (Table 109, 110, 111) Updates according to data brief change request (Figure 3, 4; Table 1, 2, 116) Revision Details 27-Feb-03 1.1 02-Sep-03 04-Feb-04 05-Jul-04 04-Nov-04 1.2 2.0 3.0 4.0 Table 151. Device Functional Change History Functional Change PWM Block After Date Code 0242 An 8-bit, Programmable PWM 4 channel and the associated registers are added. When DDC is disabled, the data space FF00h-FFFFh assigned to DDC SRAM is available for external data mapping. The SWENB Bit definition in the DDCON Register is modified. 1. USB Reset Function 2. 3. Option to block USB generated reset from resetting the MCU/PSD modules. Allow USB Reset Flag (RSTF) to interrupt MCU. Add RSTE and RSTFIE Bits to the UIEN Interrupt Enable Register. Date Code 0242 and before Only PWM0-PWM3 channels are available. DDC SRAM Mapping Data space FF00h-FFFFh is dedicated to DDC SRAM. USB-generated reset always resets both, the USB and the MCU/PSD modules. Note: Date Code is the 6th to the 9th digit of the Trace Code on top of the device. 169/170 uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 170/170 |
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