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| PowerPC 403GCX 32-Bit RISC Embedded Controller Features * PowerPC RISC CPU and instruction set architecture * Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices * 16KB instruction cache and 8KB writeback data cache, two-way set-associative * Memory management unit -64-entry, fully associative TLB array -Variable page size (1KB-16MB) -Flexible TLB management * Individually programmable on-chip controllers for: -Four DMA channels -DRAM, SRAM, and ROM banks -External interrupts * DRAM controller supports EDO DRAM * Flexible interface to external bus masters Overview The PowerPC 403GCX 32-bit RISC embedded controller offers high performance and functional integration with low power consumption. The 403GCX RISC CPU executes at sustained speeds approaching one cycle per instruction. On-chip caches and integrated DRAM and SRAM control functions reduce chip count and design complexity in systems, while improving system throughput. External I/O devices or SRAM/DRAM memory banks can be directly attached to the 403GCX bus interface unit (BIU). Interfaces for up to eight memory banks and I/O devices, including a maximum of four DRAM banks, can be configured individually, allowing the BIU to manage devices or memory banks with differing control, timing, or bus width requirements. Data Sheet * CPU core can run at 2X the external bus speed Applications * Set-top boxes and network computers * Consumer electronics and video games * Telecommunications and networking * Office automation (printers, copiers, fax) Specifications * CPU core frequency of 76 MHz, I/Os to 38 MHz * Interfaces to both 3V and 5V technologies * Low-power 3.3V operation with built-in power management and stand-by mode * Low-cost 160 lead PQFP package * 0.45 m triple-level-metal CMOS Interrupt Controller JTAG Port Serial Port 4-Channel DMA Controller (Address and Control) Timers RISC Execution Unit Memory Management Unit Instruction Cache Unit Data Cache Unit On-chip Peripheral Bus Bus Interface Unit DRAM Controller I/O Controller Data Address Bus Bus DRAM Controls SRAM, ROM, I/O Controls IBM PowerPC 403GCX The 403GCX RISC controller consists of a pipelined RISC processor core and several peripheral interface units: BIU, DMA controller, asynchronous interrupt controller, serial port, and JTAG debug port. The RISC processor core includes the internal 16KB instruction cache and 8KB data cache, reducing overhead for data transfers to or from external memory. The instruction queue logic manages branch prediction, folding of branch and condition register logical instructions, and instruction prefetching to minimize pipeline stalls.The integrated memory management unit provides robust memory management and protection functions, optimized for embedded environments. the address for the data read or write to the BIU.When noncacheable operands are being transferred, data can pass directly between the EXU and the BIU, which interfaces to the external memory being accessed. Special Purpose Registers Special purpose registers are used to control debug facilities, timers, interrupts, the protection mechanism, memory cacheability, and other architected processor resources. SPRs are accessed using move to/from special purpose register (mtspr/mfspr) instructions, which move operands between GPRs and SPRs. Supervisory programs can write the appropriate SPRs to configure the operating and interface modes of the execution unit. The condition register (CR) and machine state register (MSR) are written by internal control logic with program execution status and machine state, respectively. Status of external interrupts is maintained in the external interrupt status register (EXISR). Fixedpoint arithmetic exception status is available from the exception register (XER). RISC CPU The RISC core comprises four tightly coupled functional units: the execution unit (EXU), the memory management unit (MMU), the data cache unit (DCU), and the instruction cache unit (ICU). Each cache unit consists of a data array, tag array, and control logic for cache management and addressing. The execution unit consists of general purpose registers (GPR), special purpose registers (SPR), ALU, multiplier, divider, barrel shifter, and the control logic required to manage data flow and instruction execution within the EXU. The 403GCX core can operate at either 1X or 2X the speed of the external buses, which run at the SysClk input rate. The EXU handles instruction decoding and execution, queue management, branch prediction, and branch folding. The instruction cache unit passes instructions to the queue in the EXU or, in the event of a cache miss, requests a fetch from external memory through the bus interface unit. The MMU provides translation and memory protection for instruction and data accesses, using a unified 64-entry, fully associative TLB array. Device Control Registers Device control registers (DCR) are used to manage I/O interfaces, DMA channels, SRAM and DRAM memory configurations and timing, and status/address information regarding bus errors. DCRs are accessed using move to/from device control register (mtdcr/mfdcr) instructions, which move operands between GPRs and DCRs. Instruction Set Table 1 summarizes the 403GCX instruction set by categories of operations. Most instructions execute in a single cycle, with the exceptions of load/store multiple, load/store string, multiply, and divide instructions. Bus Interface Unit The bus interface unit integrates the functional controls for data transfers and address operations other than those which the DMA controller handles. DMA transfers use the address logic in the BIU to output the memory addresses being accessed. General Purpose Registers Data transfers to and from the EXU are handled through the bank of 32 GPRs, each 32 bits wide. Load and store instructions move data operands between the GPRs and the data cache unit, except in the cases of noncacheable data or cache misses. In such cases the DCU passes 2 IBM PowerPC 403GCX Control functions for direct-connect I/O devices and for DRAM, SRAM, or ROM banks are provided by the BIU. Burst access for SRAM, ROM, and page-mode DRAM devices is supported for cache fill and flush operations. The BIU controls the transfer of data between the external bus and the instruction cache, the data cache, or registers internal to the processor core. The BIU also arbitrates among external bus master and DMA transfers, the internal buses to the cache units and the register banks, and the serial port on the on-chip peripheral bus (OPB). ble. For each SRAM/ROM bank, the bank size, bank location, number of wait states, and timings of chip selects, byte enables, and output enables are all user-programmable. Memory Management Unit The memory management unit (MMU) supports address translation and protection functions for embedded applications. When used with appropriate system level software, the MMU provides the following functions: translation of 4GB logical address space into physical addresses, independent enabling of instruction and data translation/ protection, page level cacheability and access control via the translation mechanism, software control of page replacement strategy, and additional control over protection via zones. The fully associative 64-entry TLB array handles both instruction and data accesses. The translation for any virtual address can be placed in any one of the 64 entries, allowing maximum flexibility by TLB management software. Each TLB entry contains a translation for a page that can be any one of eight sizes from 1KB to 16MB, incrementing by powers of 4. The TLB can simultaneously contain any mix of page sizes. This feature enables the use of small pages when maximum granularity is required, reducing the amount of wasted memory when compared to the more common fixed 4KB page size. Memory Addressing Regions The 403GCX can address an effective range of 4GB, mapped to 3.5GB (256MB for SRAM/ROM or other I/O, 256MB DRAM, and 3GB OPB/ reserved) of physical address space containing twenty-eight 128MB regions. Cacheability with respect to the instruction or data cache is programmed via the instruction and data cache control registers, respectively. Within the DRAM and SRAM/ROM regions, a total of eight banks of devices are supported. Each bank can be configured for 8-, 16-, or 32-bit devices. For individual DRAM banks, the number of wait states, bank size, RAS-to-CAS timing, use of an external address multiplexer (for external bus masters), and refresh rate are user-programma- Table 1. 403GCX Instructions by Category Category Data Movement Arithmetic / Logical Comparison Branch Condition Rotate/Shift Cache Control Interrupt Control Processor Management load, store add, subtract, negate, multiply, divide, and, or, xor, nand, nor, xnor, sign extension, count leading zeros compare, compare logical, compare immediate branch, branch conditional condition register logical rotate, rotate and mask, shift left, shift right invalidate, touch, zero, flush, store write to external interrupt enable bit, move to/from machine state register, return from interrupt, return from critical interrupt system call, synchronize, move to/from device control registers, move to/ from special purpose registers Base Instructions 3 IBM PowerPC 403GCX Instruction Cache Unit The instruction cache unit (ICU) is a two-way setassociative 16KB cache memory unit with enhancements to support branch prediction and folding. The ICU is organized as 512 sets of 2 lines, each line containing 16 bytes. A separate bypass path is available to handle cache-inhibited instructions and to improve performance during line fill operations. The cache can send two cached instructions per cycle to the execution unit, allowing instructions to be folded out of the queue without interrupting normal instruction flow. When a branch instruction is folded and executed in parallel with another instruction, the ICU provides two more instructions to replace both of the instructions just executed so that bandwidth is balanced between the ICU and the execution unit. the block and then wrapping around to fill the remaining fullwords at the beginning of the block. DMA Controller The four-channel DMA controller manages block data transfers in buffered, fly-by and memory-tomemory transfer modes with options for burstmode operation. In fly-by and buffered modes, the DMA controller supports transactions between memory and peripheral devices. Each DMA channel provides a control register, a source address register, a destination address register, a transfer count register, and a chained count register. Peripheral set-up cycles, wait cycles, and hold cycles can be programmed into each DMA channel control register. Each channel supports chaining operations. The DMA status register holds the status of all four channels. Data Cache Unit The data cache unit is provided to minimize the access time of frequently used data items in main store. The 8KB cache is organized as a two-way set associative cache. There are 256 sets of 2 lines, each line containing 16 bytes of data. The cache features byte-writeability to improve the performance of byte and halfword store operations. Cache operations are performed using a writeback strategy. A write-back cache only updates locations in main storage that corresponds to changed locations in the cache. Data is flushed from the cache to main storage whenever changed data needs to be removed from the cache to make room for other data. The data cache may be disabled for a 128MB memory region via control bits in the data cache control register or on a per-page basis if the MMU is enabled for data translation. A separate bypass path is available to handle cache-inhibited data operations and to improve performance during line fill operations. Cache flushing and filling are triggered by load, store, and cache control instructions executed by the processor. Cache blocks are loaded starting at the requested fullword, continuing to the end of Exception Handling Table 2 summarizes the 403GCX exception priorities, types, and classes. Exceptions are generated by interrupts from internal and external peripherals, instructions, the internal timer facility, debug events or error conditions. Six external interrupt signals are provided on the 403GCX: one critical and five general-purpose, all individually maskable. All exceptions fall into three basic classes: asynchronous imprecise exceptions, synchronous precise exceptions, and asynchronous precise exceptions. Asynchronous exceptions are caused by events external to processor execution, while synchronous exceptions are caused by instructions. Except for a system reset or machine check, all 403GCX exceptions are handled precisely. Precise handling implies that the address of the excepting instruction (synchronous exceptions other than system call) or the address of the next sequential instruction (asynchronous exceptions and system call) is passed to the exception handling routine. Precise handling also implies that all instructions prior to the excepting instruction have completed execution and have written back their results. 4 IBM PowerPC 403GCX Asynchronous imprecise exceptions include system resets and machine checks. Synchronous precise exceptions include most debug exceptions, program exceptions, data storage violations, TLB misses, system calls, and alignment error exceptions. Asynchronous precise exceptions include the critical interrupt exception, external interrupts, and internal timer facility exceptions and some debug events. Only one exception is handled at a time. If multiple exceptions occur simultaneously, they are handled in priority order. The 403GCX processes exceptions as reset, critical, or noncritical. Four exceptions are defined as critical: machine check exceptions, debug exceptions, exceptions caused by an active level on the critical interrupt pin, and the first time-out from the watchdog timer. When a noncritical exception is taken, special purpose register Save/Restore 0 (SRR0) is loaded with the address of the excepting instruction (synchronous exceptions other than system call) or the next sequential instruction to be processed (asynchronous exceptions and system call). If the 403GCX is executing a multicycle instruction (load/store multiple, load/store string, multiply or divide), the instruction is terminated and its address stored in SRR0. Save/Restore Register 1 (SRR1) is loaded with the contents of the machine state register. The MSR is then updated to reflect the new context of the machine. The new MSR contents take effect beginning with the first instruction of the exception handling routine. At the end of the exception handling routine, execution of a return from interrupt (rfi) instruction forces the contents of SRR0 and SRR1 to be loaded into the program counter and the MSR, respectively. Execution then begins at the address in the program counter. The four critical exceptions are processed in a similar manner. When a critical exception is taken, SRR2 and SRR3 hold the next sequential address to be processed when returning from the exception and the contents of the machine state register, respectively. After the critical exception handling routine, return from critical interrupt (rfci) forces the contents of SRR2 and SRR3 to be loaded into the program counter and the MSR, respectively. Timers The 403GCX contains four timer functions: a time base, a programmable interval timer (PIT), a fixed interval timer (FIT), and a watchdog timer. The time base is a 64-bit counter incremented at the timer clock rate. The timer clock may be driven by either an internal signal equal to the processor clock rate or by a separate external timer clock pin. No interrupts are generated when the time base rolls over. Table 2. 403GCX Exception Priorities, Types and Classes Priority 1 2 3 4 5 6 7 8 9 10 Exception Type System Reset Machine Check Exception Class Asynchronous imprecise Asynchronous imprecise Synchronous precise Debug (except UDE and EXC) Critical Interrupt Asynchronous precise WatchdogTimer Time-out Asynchronous precise Program Exception, Data Storage Exception,TLB Miss, and Synchronous precise System Calls Alignment Exceptions Synchronous precise External Interrupts Asynchronous precise Fixed Interval Timer Asynchronous precise Programmable Interval Timer Asynchronous precise 5 IBM PowerPC 403GCX The programmable interval timer is a 32-bit register that is decremented at the same rate as the time base is incremented. The user preloads the PIT register with a value to create the desired delay. When the register is decremented to zeros, the timer stops decrementing, a bit is set in the timer status register (TSR), and a PIT interrupt is generated. Optionally, the PIT can be programmed to reload automatically the last value written to the PIT register, after which the PIT begins decrementing again.The timer control register (TCR) contains the interrupt enable for the PIT interrupt. The fixed interval timer generates periodic interrupts based on selected bits in the time base. Users may select one of four intervals for the timer period by setting the correct bits in the TCR. When the selected bit in the time base changes from 0 to 1, a bit is set in the TSR and a FIT interrupt is generated. The FIT interrupt enable is contained in the TCR. The watchdog timer generates a periodic interrupt based on selected bits in the time base. Users may select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an intervening clear from software. If enabled, the watchdog timer generates a system reset unless an exception handler updates the watchdog timer status bit before the timer has completed two of the selected timer intervals. break and false start bit detection are also provided, as well as operating modes that allow the serial port to react to handshaking line inputs or control handshaking line outputs without software interaction. Program generation mode allows the serial port transmitter to be used for pulse width modulation with duty cycle variation controlled by frame size, baud rate, and data pattern. JTAG Port The JTAG port has been enhanced to allow it to be used as a debug port. Through the JTAG test access port, debug software on a workstation or PC can single-step the processor and interrogate internal processor state to facilitate software debugging. The standard JTAG boundary-scan register allows testing of circuitry external to the chip, primarily the board interconnect. Alternatively, the JTAG bypass register can be selected when no other test data register needs to be accessed during a board-level test operation. Real-Time Debug Port The real-time debug port supports tracing the instruction stream being executed out of the instruction cache in real time. The trace status signals provide trace information while in realtime trace debug mode. This mode does not alter the performance of the processor. P/N Code Table 3. PPC403GCX Part Number MHz 76 Part Number 403GCX-3JC76C2 Package PQFP Serial Port The 403GCX serial port is capable of supporting RS232 standard serial communication, as well as high-speed execution (bit speed at a maximum of one-sixteenth of the SysClk processor clock rate). The serial clock which drives the serial port can come from the internal SysClk or an external clock source at the external serial clock pin (maximum of one-half the SysClk rate). The 403GCX serial port contains many features found only on advanced communications controllers, including the capability of being a peripheral for DMA transfers. An internal loopback mode supports diagnostic testing without requiring external hardware. An auto echo mode is included to retransmit received bits to the external device. Auto-resynchronization after a line 6 Note: The characters following the dash indicate reliability grade (3), package type (J), revision level (C), maximum internal CPU core clock rate (76), commercial version (C), and the ratio of internal CPU core clock rate to external bus speed (2 times the maximum external bus clock rate). IBM PowerPC 403GCX Logic Symbol Signals in brackets are multiplexed. SYSCLK SERCLK DSR[CTS] DTR[RTS] RECVD XMITD Serial Port PPC403GCX RISC Controller DMAR0 * * * DMAR3[XREQ] DMAA0 DMA Controls * * * DMAA3[XACK] EOT0[TC0] * * * EOT3[TC3][XSIZE0] HOLDREQ HOLDACK BUSREQ/ [DMADXFER] TIMERCLK CINT INT0 * * * External Master SRAM Controls WBE0[A4][BE0] WBE1[A5][BE1] WBE2[A30][BE2] WBE3[A31][BE3] OE[XSIZE1][BLast] R/W CS0 Interrupts SRAM/DRAM Controls * * * INT4 READY BUSERROR ERROR RESET BOOTW TESTC/ [HOLDPRI] DRAM Controls CS3 CS4[RAS3] * * * CS7[RAS0] CAS0 * * * CAS3 AMUXCAS DRAMOE DRAMWE TS0 TS1 TS2 TS3[DP3] TS4[DP2] TS5[DP1] TS6[DP0] Trace Status JTAG TCK TMS TDI TDO HALT A6 A29 * * * Address Bus Data Bus D0 * * * D31 7 IBM PowerPC 403GCX Pin/Ball Functional Descriptions Active-low signals are shown with overbars: DMAR0. Multiplexed signals are alphabetized under the first (unmultiplexed) signal names on the same pins/balls. The logic symbol on the preceding page shows all 403GCX signals arranged by functional groups. Table 4. 403GCX Signal Descriptions Signal Name A6 Pin 92 Ball K12 I/O Type I/O Function Address Bus Bit 6. When the 403GCX is bus master, this is an address output from the 403GCX. When the 403GCX is not bus master, this is an address input from the external bus master, to determine bank register usage. Address Bus Bit 7. See description of A6. Address Bus Bit 8. See description of A6. Address Bus Bit 9. See description of A6. Address Bus Bit 10. See description of A6. Address Bus Bit 11. See description of A6. Address Bus Bit 12. When the 403GCX is bus master, this is an address output from the 403GCX. Address Bus Bit 13. See description of A12. Address Bus Bit 14. See description of A12. Address Bus Bit 15. See description of A12. Address Bus Bit 16. See description of A12. Address Bus Bit 17. See description of A12. Address Bus Bit 18. See description of A12. Address Bus Bit 19. See description of A12. Address Bus Bit 20. See description of A12. Address Bus Bit 21. See description of A12. Address Bus Bit 22. When the 403GCX is bus master, this is an address output from the 403GCX. When the 403GCX is not bus master, this is an address input from the external bus master, to determine page crossings. Address Bus Bit 23. See description of A22. Address Bus Bit 24. See description of A22. Address Bus Bit 25. See description of A22. Address Bus Bit 26. See description of A22. Address Bus Bit 27. See description of A22. Address Bus Bit 28. See description of A22. A7 A8 A9 A10 A11 A12 93 94 95 96 97 98 K11 J13 J14 J12 J11 H13 I/O I/O I/O I/O I/O O A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 99 103 104 105 106 107 108 109 110 112 H14 G14 G13 G11 F14 F12 F13 F11 E14 E13 O O O O O O O O O I/O A23 A24 A25 A26 A27 A28 113 114 115 116 117 118 E11 D14 D12 D13 C14 C12 I/O I/O I/O I/O I/O I/O 8 IBM PowerPC 403GCX Table 4. 403GCX Signal Descriptions Signal Name A29 AMuxCAS Pin 119 139 Ball C13 A8 I/O Type I/O O Function Address Bus Bit 29. See description of A22. DRAM External Address Multiplexer Select. AMuxCAS controls the select logic on an external multiplexer. If AMuxCAS is low, the multiplexer should select the row address for the DRAM and when AMuxCAS is 1, the multiplexer should select the column address. Boot-up ROM Width Select. BootW is sampled while the Reset pin is active and again after Reset becomes inactive to determine the width of the boot-up ROM. If this pin is tied to logic 0 when sampled on reset, an 8-bit boot width is assumed. If BootW is tied to 1, a 32bit boot width is assumed. For 16-bit boot widths, this pin should be tied to the RESET pin. Bus Error Input. A logic 0 input to the BusError pin by an external device signals to the 403GCX that an error occurred on the bus transaction. BusError is only sampled during the data transfer cycle or the last wait cycle of the transfer. Bus Request. While HoldAck is active, BusReq is active when the 403GCX has a bus operation pending and needs to regain control of the bus. DMA Data Transfer. When HoldAck is not active, DMADXFER indicates a valid data transfer cycle. For DMA use, DMADXFER controls burst-mode fly-by DMA transfers between memory and peripherals. DMADXFER is not meaningful unless a DMA Acknowledge signal (DMAA0:3) is active. For transfer rates slower than one transfer per cycle, DMADXFER is active for one cycle when one transfer is complete and the next one starts. For transfer rates of one transfer per cycle, DMADXFER remains active throughout the transfer. DRAM Column Address Select 0. CAS0 is used with byte 0 of all DRAM banks. DRAM Column Address Select 1. CAS1 is used with byte 1 of all DRAM banks. DRAM Column Address Select 2. CAS2 is used with byte 2 of all DRAM banks. DRAM Column Address Select 3. CAS3 is used with byte 3 of all DRAM banks. Critical Interrupt. To initiate a critical interrupt, the user must maintain a logic 0 on the CINT pin for a minimum of one SysClk clock cycle followed by a logic 1 on the CINT pin for at least one SysClk cycle. SRAM Chip Select 0. Bank register 0 controls an SRAM bank, CS0 is the chip select for that bank. SRAM Chip Select 1. See description of CS0 but controls bank 1. BootW 11 E1 I BusError 12 E3 I 135 BusReq/ DMADXFER A9 O CAS0 CAS1 CAS2 CAS3 CINT 142 143 144 145 36 C8 A7 B7 D7 L2 O O O O I CS0 CS1 155 154 C4 A4 O O 9 IBM PowerPC 403GCX Table 4. 403GCX Signal Descriptions Signal Name CS2 CS3 CS4/RAS3 Pin 153 152 151 Ball D5 B5 C5 I/O Type O O O Function SRAM Chip Select 2. See description of CS0 but controls bank 2. SRAM Chip Select 3. See description of CS0 but controls bank 3. Chip Select 4/ DRAM Row Address Select 3. When bank register 4 is configured to control an SRAM bank, CS4/RAS3 functions as a chip select. When bank register 4 is configured to control a DRAM bank, CS4/RAS3 is the row address select for that bank. Chip Select 5/ DRAM Row Address Select 2. See description of CS4/RAS3 but controls bank 5. Chip Select 6/ DRAM Row Address Select 1. See description of CS4/RAS3 but controls bank 6. Chip Select 7/ DRAM Row Address Select 0. See description of CS4/RAS3 but controls bank 7. Data bus bit 0 (most significant bit). Data bus bit 1. Data bus bit 2. Data bus bit 3. Data bus bit 4. Data bus bit 5. Data bus bit 6. Data bus bit 7. Data bus bit 8. Data bus bit 9. Data bus bit 10. Data bus bit 11. Data bus bit 12. Data bus bit 13. Data bus bit 14. Data bus bit 15. Data bus bit 16. Data bus bit 17. Data bus bit 18. Data bus bit 19. Data bus bit 20. Data bus bit 21. CS5/RAS2 CS6/RAS1 CS7/RAS0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 148 147 146 42 43 44 45 46 47 48 51 52 53 54 55 56 57 58 62 63 64 65 66 67 68 B6 C6 A6 N2 P2 N3 P3 N4 M4 P4 P5 M5 L5 N6 P6 M6 L6 N7 M7 P8 N8 L8 P9 M9 N9 O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 10 IBM PowerPC 403GCX Table 4. 403GCX Signal Descriptions Signal Name D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DMAA0 DMAA1 DMAA2 DMAA3/ XACK Pin 71 72 73 74 75 76 77 78 79 82 156 157 158 159 Ball I/O Type Data bus bit 22. Data bus bit 23. Data bus bit 24. Data bus bit 25. Data bus bit 26. Data bus bit 27. Data bus bit 28. Data bus bit 29. Data bus bit 30. Data bus bit 31. DMA Channel 0 Acknowledge. DMAA0 has an active level when a transaction is taking place between the 403GCX and a peripheral. DMA Channel 1 Acknowledge. See description of DMAA0. DMA Channel 2 Acknowledge. See description of DMAA0. DMA Channel 3 Acknowledge / External Master Transfer Acknowledge. When the 403GCX is bus master, this signal is DMAA3; see description of DMAA0. When the 403GCX is not the bus master, this signal is XACK, an output from the 403GCX which has an active level when data is valid during an external bus master transaction. DMA Channel 0 Request. External devices request a DMA transfer on channel 0 by putting a logic 0 on DMAR0. DMA Channel 1 Request. See description of DMAR0. DMA Channel 2 Request. See description of DMAR0. DMA Channel 3 Request. When the 403GCX is the bus master, external devices request a DMA transfer on channel 3 by putting a logic 0 on DMAR3. See description of DMAR0. When the 403GCX is not the bus master, DMAR3 is used as the XREQ input. The external bus master places a logic 0 on XREQ to initiate a transfer to the DRAM controlled by the 403GCX DRAM controller. DRAM Output Enable. DRAMOE has an active level when either the 403GCX or an external bus master is reading from a DRAM bank. This signal enables the selected DRAM bank to drive the data bus. DRAM Write Enable. DRAMWE has an active level when either the 403GCX or an external bus master is writing to a DRAM bank. Function M10 I/O N10 L10 P11 I/O I/O I/O M11 I/O N11 P12 I/O I/O M12 I/O N12 N13 B4 A3 C3 B3 I/O I/O O O O O DMAR0 DMAR1 DMAR2 DMAR3/ XREQ 2 3 4 5 B2 B1 C2 C1 I I I I DRAMOE 137 D9 O DRAMWE 138 B8 O 11 IBM PowerPC 403GCX Table 4. 403GCX Signal Descriptions Signal Name DSR/CTS Pin 28 Ball J2 I I/O Type Function Data Set Ready / Clear to Send. The function of this pin as either DSR or CTS is selectable via the Serial Port Configuration bit in the IOCR. Data Terminal Ready / Request to Send. The function of this pin as either DTR or RTS is selectable via the Serial Port Configuration bit in the IOCR. End of Transfer 0 / Terminal Count 0. The function of the EOT0/TC0 is controlled via the EOT/TC bit in the DMA Channel 0 Control Register. When EOT0/TC0 is configured as an End of Transfer pin, external users may stop a DMA transfer by placing a logic 0 on this input pin. When configured as a Terminal Count pin, the 403GCX signals the completion of a DMA transfer by placing a logic 0 on this pin. End of Transfer 1 / Terminal Count 1. See description of EOT0/TC0. End of Transfer 2 / Terminal Count 2. See description of EOT0/TC0. End of Transfer 3 / Terminal Count 3 / External Master Transfer Size 0. When the 403GCX is bus master, this pin has the same function as EOT0/TC0. When the 403GCX is not bus master, EOT3/TC3/XSize0 is used as one of two external transfer size input bits, XSize0:1. System Error. Error goes to a logic 1 whenever a machine check error is detected in the 403GCX. The Error pin then remains a logic 1 until the machine check error is cleared in the Exception Syndrome Register and/or Bus Error Syndrome Register. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. DTR/RTS 88 L14 O EOT0/TC0 128 A11 I/O EOT1/TC1 EOT2/TC2 EOT3/TC3/ XSize0 131 132 133 A10 C10 D10 I/O I/O I/O Error 136 C9 O 1 10 15 29 30 GND 41 50 59 60 70 81 G7 E2 F1 J4 K1 H7 N5 P7 L7 P10 H8 12 IBM PowerPC 403GCX Table 4. 403GCX Signal Descriptions Signal Name Pin 90 101 102 GND 111 121 130 141 150 Halt HoldAck 9 134 Ball K13 G12 H12 E12 G8 B10 C7 A5 D4 B9 I O I/O Type Function Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Ground. All ground pins must be used. Halt from external debugger, active low. Hold Acknowledge. HoldAck outputs a logic 1 when the 403GCX relinquishes its external buses to an external bus master. HoldAck outputs a logic 0 when the 403GCX regains control of the bus. Hold Request. External bus masters can request the 403GCX bus by placing a logic1 on this pin. The external bus master relinquishes the bus to the 403GCX by deasserting HoldReq. Interrupt 0. INT0 is an interrupt input to the 403GCX and users may program the pin to be either edge-triggered or level-triggered and may also program the polarity to be active high or active low. The IOCR contains the bits necessary to program the trigger type and polarity. Interrupt 1. See description of INT0. Interrupt 2. See description of INT0. Interrupt 3. See description of INT0. Interrupt 4. See description of INT0. Reserved for manufacturing test. Tied high for normal operation. Output Enable / External Master Transfer Size 1. When the 403GCX is bus master, OE enables the selected SRAMs to drive the data bus. The timing parameters of OE relative to the chip select, CS, are programmable via bits in the 403GCX bank registers. When the 403GCX is not bus master, OE/XSize1 is used as one of two external transfer size input bits, XSize0:1. In Byte Enable mode, Burst Last (BLast) goes active to indicate the last transfer of a memory access, whether burst or nonburst. Ready. Ready is used to insert externally generated (device-paced) wait states into bus transactions. The Ready pin is enabled via the Ready Enable bit in 403GCX bank registers. Serial Port Receive Data. HoldReq 14 F2 I INT0 31 K3 I INT1 INT2 INT3 INT4 IVR OE/XSize1/ BLast 32 33 34 35 39 126 K2 K4 L1 L3 M2 B11 I I I I I O/I/O Ready 13 E4 I RecvD 27 J3 I 13 IBM PowerPC 403GCX Table 4. 403GCX Signal Descriptions Signal Name Reset Pin 91 Ball K14 I/O Type I/O Function Reset. A logic 0 input placed on this pin for one SysClk cycle causes the 403GCX to begin a system reset. When a system reset is invoked, the Reset pin becomes a logic 0 output for 2048 SysClk cycles. Read / Write. When the 403GCX is bus master, R/W is an output which is high when data is read from memory and low when data is written to memory. When the 403GCX is not bus master, R/W is an input from the external bus master which indicates the direction of data transfer. Serial Port Clock. Through the Serial Port Clock Source bit in the Input/Output Configuration register (IOCR), users may choose the serial port clock source from either the input on the SerClk pin or processor SysClk. The maximum allowable input frequency into SerClk is half the SysClk frequency. SysClk is the processor system clock input. The 403GCX can also be programmed to operate at a 2X internal clock rate while the external bus interface runs at the SysClk input rate. JTAG Test Clock Input. TCK is the clock source for the 403GCX test access port (TAP). The maximum clock rate into the TCK pin is one half of the processor SysClk clock rate. Test Data In. The TDI is used to input serial data into the TAP. When the TAP enables the use of the TDI pin, the TDI pin is sampled on the rising edge of TCK and this data is input to the selected TAP shift register. Test Data Output. TDO is used to transmit data from the 403GCX TAP. Data from the selected TAP shift register is shifted out on TDO. Reserved for manufacturing test. Tied low for normal operation. Reserved for manufacturing test. Tied high for normal operation. TestC. Reserved for manufacturing test during the reset interval. While Reset is active, this signal should be tied low for normal operation. HoldReq Priority. When Reset is not active, this signal is sampled to determine the priority of the external bus master signal HoldReq. If HoldPri = 0 then the HoldReq signal is considered high priority, otherwise HoldReq is considered low priority. Reserved for manufacturing test. Tied low for normal operation. Timer Facility Clock. Through the Timer Clock Source bit in the Input/Output Configuration register (IOCR), users may choose the clock source for the Timer facility from either the input on the TimerClk pin or processor CoreClk. The maximum input frequency into TimerClk is half the CoreClk frequency. R/W 127 C11 I/O SerClk 26 J1 I SysClk 22 G3 I TCK 6 D2 I TDI 8 D1 I TDO TestA TestB TestC/HoldPri 16 23 24 37 F3 H1 H2 M1 O I I I TestD TimerClk 38 25 M3 H4 I I 14 IBM PowerPC 403GCX Table 4. 403GCX Signal Descriptions Signal Name TMS Pin 7 Ball D3 I I/O Type Function Test Mode Select. The TMS pin is sampled by the TAP on the rising edge of TCK. The TAP state machine uses the TMS pin to determine the mode in which the TAP operates. Trace Status 0. Trace Status 1. Trace Status 2. Trace Status 3 / Data Parity 3. When parity checking and generation are enabled, this signal represents odd parity for read/write operations using byte 3 (D24:31) of the data bus. The Parity Error status bit is set in the BESR when a parity error is detected. Trace Status 4 / Data Parity 2 for byte 2 (D16:23). See TS3/DP3 description above. Trace Status 5 / Data Parity 1 for byte 1 (D8:15). See TS3/DP3 description above. Trace Status 6 / Data Parity 0 for byte 0 (D0:7). See TS3/DP3 description above. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. Power. All power pins must be connected to 3.3V supply. TS0 TS1 TS2 TS3/DP3 17 18 19 86 F4 G2 G1 L13 O O O O/I/O TS4/DP2 TS5/DP1 TS6/DP0 85 84 83 20 21 40 49 61 69 M14 O/I/O M13 O/I/O N14 G4 H3 N1 L4 M8 L9 P13 L11 H11 B14 D11 D8 D6 A2 O/I/O VDD 80 89 100 120 129 140 149 160 15 IBM PowerPC 403GCX Table 4. 403GCX Signal Descriptions Signal Name WBE0/A4/ BE0 Pin 122 Ball B13 I/O Type O/I/O Function Write Byte Enable 0 / Address Bus Bit 4 / Byte Enable 0. When the 403GCX is bus master, the write byte enable outputs, WBE0:3, select the active byte(s) in a memory write access to SRAM. The byte enables can also be programmed as read/write byte enables, depending on the mode set in the IOCR. Note 5 on page 35 summarizes the functional and timing differences in these signals when programmed as read/write byte enables. For 8-bit memory regions, WBE2 and WBE3 become address bits 30 and 31 and WBE0 is the byte-enable line. For 16-bit memory regions, WBE2 and WBE3 become address bits 30 and 31 and WBE0 and WBE1 are the high byte and low byte enables, respectively. For 32-bit memory regions, WBE0:3 are byte enables for bytes 0-3 on the data bus, respectively. When the 403GCX is not bus master, WBE0:1 are used as the A4:5 inputs (for bank register selection) and WBE2:3 are used as the A30:31 inputs (for byte selection and page crossing detection). Write Byte Enable 1 / Address Bus Bit 5 / Byte Enable 1. See description of WBE0 / A4 above. Write Byte Enable 2 / Address Bus Bit 30 / Byte Enable 2. See description of WBE0 / A4 above. Write Byte Enable 3 / Address Bus Bit 31 / Byte Enable 3. See description of WBE0 / A4 above. Serial port transmit data. WBE1/A5/ BE1 WBE2/A30/ BE2 WBE3/A31/ BE3 XmitD 123 124 125 87 A13 B12 A12 L12 O/I/O O/I/O O/I/O O 16 IBM PowerPC 403GCX Table 5. PQFP Package Signals Ordered by Pin Number Pin 1 2 3 4 5 6 7 8 9 Signal Name GND DMAR0 DMAR1 DMAR2 DMAR3/XREQ TCK TMS TDI Halt Pin Signal Name Pin Signal Name Pin 33 INT2 34 INT3 35 INT4 36 CINT 38 TestD 39 IVR 40 VDD 41 GND 42 D0 43 D1 44 D2 45 D3 46 D4 47 D5 48 D6 49 VDD 50 GND 51 D7 52 D8 53 D9 54 D10 55 D11 56 D12 57 D13 58 D14 59 GND 60 GND 61 VDD 62 D15 63 D16 64 D17 65 D18 66 D19 67 D20 68 D21 70 GND 71 D22 72 D23 73 D24 74 D25 75 D26 76 D27 77 D28 78 D29 79 D30 80 VDD 81 GND 82 D31 83 TS6/DP0 84 TS5/DP1 85 TS4/DP2 86 TS3/DP3 87 XmitD 88 DTR/RTS 89 VDD 90 GND 91 Reset 92 A6 93 A7 94 A8 95 A9 96 A10 97 98 99 Signal Name A11 A12 A13 Pin Signal Name 129 VDD 130 GND 131 EOT1/TC1 132 EOT2/TC2 133 EOT3/TC3/XSize0 134 HoldAck 135 BusReq/ DMADXFER 136 Error 137 DRAMOE 138 DRAMWE 139 AMuxCAS 140 VDD 141 GND 142 CAS0 143 CAS1 144 CAS2 145 CAS3 146 CS7/RAS0 147 CS6/RAS1 148 CS5/RAS2 149 VDD 150 GND 151 CS4/RAS3 152 CS3 153 CS2 154 CS1 155 CS0 37 TestC/HoldPri 69 VDD 100 VDD 101 GND 102 GND 103 A14 104 A15 105 A16 106 A17 107 A18 108 A19 109 A20 110 A21 111 GND 112 A22 113 A23 114 A24 115 A25 116 A26 117 A27 118 A28 119 A29 120 VDD 121 GND 122 WBE0/A4/BE0 123 WBE1/A5/BE1 10 GND 11 BootW 12 BusError 13 Ready 14 HoldReq 15 GND 16 TDO 17 TS0 18 TS1 19 TS2 20 VDD 21 VDD 22 SysClk 23 TestA 24 TestB 25 TimerClk 26 SerClk 27 RecvD 28 DSR/CTS 29 GND 30 GND 31 INT0 32 INT1 124 WBE2/A30/BE2 156 DMAA0 125 WBE3/A31/BE3 157 DMAA1 126 OE/XSize1/ BLast 127 R/W 128 EOT0/TC0 158 DMAA2 159 DMAA3/XACK 160 VDD 17 IBM PowerPC 403GCX PQFP Mechanical Drawing (Top View) 120 81 See detail 80 121 mm Dimensions: 31.2 0.25 1.228 0.01 inches Note: English dimensions are for reference only. 28 0.2 1.102 0.008 Index Mark 160 41 1 40 3.95 Max 0.155 0.25 Min 0.01 0.015 0.05 0.006 0.002 0.65 Basic 0.0256 0.3 0.1 0.012 0.004 0.8 0.15 0.032 0.006 0 - 7 18 IBM PowerPC 403GCX Package Thermal Specifications The 403GCX is designed to operate within the case temperature range from -40C to 120C. Thermal resistance values are shown in Table 6: Table 6. Thermal Resistance (C/Watt) Airflow-ft/min (m/sec) Parameter 0 (0) 2 37.2 100 (0.51) 2 31.6 200 (1.02) 2 29.8 JC Junction to case CA Case to ambient PQFP (no heatsink) Notes: 1. Case temperature TmC is measured at top center of case surface with device soldered to circuit board. 2. TmA = TmC - Px CA, where TmA is ambient temperature. 3. TmCMax = TmJMax - PxJC, where TmJMax is maximum junction temperature and P is power consumption. 4. The above assumes that the chip is mounted on a card with at least one signal and two power planes. Electrical Specifications Absolute Maximum Ratings The absolute maximum ratings in Table 7 below are stress ratings only. Operation at or beyond these maximum ratings may cause permanent damage to the device. Table 7. 403GCX Maximum Ratings Parameter Supply voltage with respect to GND Voltage on other pins with respect to GND Case temperature under bias Storage temperature Maximum Rating -0.5V to +3.8V -0.5V to +5.5V -40C to +120C -65C to +150C 19 IBM PowerPC 403GCX Operating Conditions The 403GCX can interface to either 3V or 5V technologies. The range for supply voltages is specified for five-percent margins relative to a nominal 3.3V power supply. Device operation beyond the conditions specified in Table 8 is not recommended. Extended operation beyond the recommended conditions may affect device reliability: Table 8. Operating Conditions Symbol VDD FC TmC Supply voltage: 403GCX-3JC76 Clock 403GCX-3JC76 frequency1: 24 -40 38 85 MHz C Parameter Min 3.14 Max 3.47 Unit V Case temperature under bias: 403GCX-3JC76 Note: These frequencies do not account for TCS. See Table 11. Power Considerations Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. Typical power dissipation is 0.49 W at 38/76 MHz, with an average 50pF capacitive load. Derating curves are provided in the section, "Output Derating for Capacitance and Voltage," on page 29. Recommended Connections Power and ground pins should all be connected to separate power and ground planes in the circuit board to which the 403GCX is mounted. Unused input pins must be tied inactive, either high or low. The IVR pin should be tied to VDD for normal operation. 20 IBM PowerPC 403GCX DC Specifications Table 9. 403GCX DC Characteristics Symbol VIL VILC VIH VIHC VOL VOH IOH IOL ILI ILO ICC Parameter Input low voltage (except for SysClk) Input low voltage for SysClk Input high voltage (except for SysClk) Input high voltage for SysClk Output low voltage Output high voltage Output high current Output low current Input leakage current3 Output leakage current Supply current (ICC Max at FCore of 76MHz) 2.4 Min GND - 0.1 GND - 0.1 2.0 2.0 Max 0.8 0.8 5.1 5.1 0.4 VDD 2 4 150 10 305 Units V V V V V V mA mA A A mA Notes: 1. The 403GCX drives its outputs to the level of VDD and, when not driving, the 403GCX outputs can be pulled up to 5V by other devices in a system. 2. ICC Max is measured at worst-case recommended operating conditions for temperature, frequency and voltage as specified in Table 8 on page 20, and a capacitive load of 50 pF. 3. The Input leakage current is dependent on the applied. See "Input Leakage Current," on page 32 for details. . Table 10. 403GCX I/O Capacitance Symbol CIN CINC COUT CI/O Parameter Input capacitance (except for SysClk) Input capacitance for SysClk Output capacitance1 Min Max 5 15 7 8 Units pF pF pF pF I/O pin capacitance Note: 1. COut is specified as the load capacitance of a floating output in high impedance. 21 IBM PowerPC 403GCX AC Specifications Clock timing and switching characteristics are specified in accordance with recommended operating conditions in Table 8 on page 20. AC specifications are characterized at VDD = 3.14V and TJ = 85C with the 50pF test load shown in the figure at right. Derating of outputs for capacitive loading is shown in the figure "Output Derating for Capacitance and Voltage," on page 29. Output Pin CL CL = 50 pf for all signals SysClk Timing TCR TCF 2.0V 1.5V 0.8V TCH TC TCL Table 11. 403GCX System Clock Timing 38 MHz Symbol FC TC TCS TCH TCL TCR TCF Parameter Min SysClk clock input frequency1 SysClk clock period1 Clock edge stability2 11 11 0.5 0.5 2.5 2.5 24 27.8 Max 38 41.7 0.2 MHz ns ns ns ns ns ns Units Clock input high time Clock input low time Clock input rise time3 Clock input fall time3 Notes: 1. These values do not include the allowable tolerance for clock edge instability represented by TCS. 2. Cycle-to-cycle jitter allowed between any two edges. 3. Rise and fall times measured between 0.8V and 2.0V. 22 IBM PowerPC 403GCX Serial Clock Timing Characteristics Table 12. 403GCX Serial Clock Timings Symbol FSC TSC TSCH TSCL Parameter SerClk input frequency SerClk period SerClk input high time SerClk input low time 2TC TC TC Min Max 0.5 FC Units MHz ns ns ns Timer Clock Timing Characteristics Table 13. 403GCX Timer Clock Timings IOCR[2xC] = 1 CoreClk Doubled Mode Min FTC TTC TTCH TTCL TimerClk input frequency TimerClk period TimerClk input high time TimerClk input low time TC 0.5 TC 0.5 TC Max FC 2 TC TC TC IOCR[2xC] = 0 CoreClk Non-Doubled Mode Min Max 0.5 FC MHz ns ns ns Symbol Parameter Units Table 14. 403GCX Serial Port Output Timings 38 MHz Symbol TOH, TOV Parameter TOHMin Output hold, output valid TOHSP1, TOVSP1 TOHSP2, TOVSP2 DTR/RTS XmitD Units TOVMax 12 10 ns Note: 1. Output times are measured with a standard 50 pF capacitive load, unless otherwise noted. 23 IBM PowerPC 403GCX Input Setup and Hold Waveform SysClk 1.5V+ TIS MIN TIH MIN Inputs 1.5V + VALID TISCAS TIHCAS MIN TISEDO MIN Data Bus D0:31 (Inputs) MIN 1.5V + VALID VALID TISCAS MIN VALID TIHCAS MIN TIHEDO MIN CAS0:3 Outputs 1.5V+ TCAS2CLK MIN TCAS2CLK MIN Notes: 1. The 403GCX may be programmed to latch data from the data bus with respect to SysClk, or with respect to CAS. When IOCR[DRC] = 1, the 403GCX is programmed to latch data on the rise of CAS. When IOCR[EDO] = 1, the 403GCX is programmed to latch data on either the fall of CAS or the fall of the internal duty cycle corrected SysClk, depending on the parameters set in the bank register and the type of transfer. When neither of these special modes are set, the 403GCX will latch data on the rise of SysClk. Note that it is invalid to concurrently set IOCR[DRC] = 1 and IOCR[EDO] = 1. 2. TCAS2CLK 13.5 ns. When IOCR[DRC] = 1 or IOCR[EDO] = 1, the capacitive load on the CAS outputs must not delay the CAS transition such that the period from the CAS data latching edge to the next SysClk rising edge becomes less than 13.5 ns. The maximum value of CAS capacitive loading can be determined by using the output time for CAS from Table 17 on page 27, and applying the appropriate derating factor for your application. See the figure, "Output Derating for Capacitance and Voltage," on page 29. 24 IBM PowerPC 403GCX All TIS and TIH timings in Table 15 are specified with respect to the rise of the external SysClk signal. Internal system clocks are duty-cycle corrected so the falling edge of the external SysClk signal may not be the same as the falling edge of the internally corrected system clock. Table 15. 403GCX Synchronous Input Timings 38 MHz Symbol TIS Input setup: TIS1 TIS2 TIS3 TISEDO TISCAS TIS4 TIS5 TIS6 TIS7 TIS8 TIS9 TIS10 Input hold: TIH1 TIH2 TIH3 TIHEDO TIHCAS TIH4 TIH5 TIH6 TIH7 TIH8 TIH9 TIH10 Input rise/fall time Parameter Min A4:11,A22:31 BusError D0:31 (to SysClk)3 D0:31 (to SysClk)4,5 D0:31 (to CAS)5 HoldPri HoldReq R/W Ready Ready(SOR mode) XReq XSize0:1 A4:11,A22:31 BusError D0:31 (after SysClk)3 D0:31 (after SysClk)4,5 D0:31 (after CAS)5 HoldPri HoldReq R/W Ready Ready(SOR mode) XReq XSize0:1 Max Units 3 5 4 16.2 3 3 3 3 5 10 4 3 2 2 3 -10.2 3 2 2 2 2 2 2 2 0.5 2.5 ns TIH ns TR,TF ns Notes: 1. Parity setup and hold times are the same as for the data bus. 2. For detailed EDO DRAM timing waveforms, refer to "EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer Read," on page 42 and "EDO DRAM 3-1-1-1 Burst Read Followed by Single Transfer Read," on page 44. 3. Data bus input setup and hold times TIS3 and TIH3 are the specifications to use for all modes except DRAM Read on CAS and EDO DRAM read modes (controlled via IOCR[DRC] and IOCR[EDO], respectively). 4. In EDO mode, the data bus input setup and hold times with respect to SysClk. Use the following equations to determine the minimum input setup and hold times for this signal: TISEDOMin = Tc/2 + 3; TIHEDOMin = -Tc/2 + 3. Valid for Tc greater than 25ns and less than 41.7 ns. 5. Guaranteed by design and not tested. 25 IBM PowerPC 403GCX Table 16. 403GCX Asynchronous Input Timings 38 MHz Symbol TIS Input setup time TIS11 TIS12 TIS13 TIS14 TIS15 TIS16 TIS17 Input hold time TIH11 TIH12 TIH13 TIH14 TIH15 TIH16 TIH17 Parameter Min CINT DMAR0:3 EOT0:3 HALT INT0:4 Reset Ready Units Max 3 3 3 3 4 8 5 TC TC TC TC TC Note 1,2 TC ns TIH CINT DMAR0:3 EOT0:3 HALT INT0:4 Reset Ready Notes: 1. During a system-initiated reset, Reset must be taken low for a minimum of 2048 SysClk cycles. 2. The BootW input has a maximum rise time requirement of 10 ns when it is tied to Reset. 3. Input hold times are measured at 3.47V and TJ = 0C. Output Delay and Float Timing Waveform 1.5V SysClk TOV Max TOH Min Outputs 1.5V Valid TOF Min Max Outputs 1.5V 26 IBM PowerPC 403GCX All TOH and TOV timings in Table 17 are specified with respect to the rise of the SysClk input signal. Internal system clocks are duty-cycle corrected so the falling edge of the external SysClk signal may not be the same as the falling edge of the internally corrected system clock. TOHxr/TOVxr specifications are for signals which transition relative to the rising edge of SysClk, while TOHxf/TOVxf apply to falling edge transitions. Refer to the appropriate timing diagram to determine the appropriate clock edge for signal transitions. Table 17. 403GCX Synchronous Output Timings Symbol Parameter Output hold, output TOH1r, TOV1r TOH1f, TOV1f TOH2, TOV2 TOH3, TOV3 TOH4r, TOV4r TOH4f, TOV4f TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9r, TOV9r TOH9f, TOV9f TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14r, TOV14r TOH14f, TOV14f TOH15, TOV15 TOH16, TOV16 TOH17, TOV17 TOH18, TOV18 TOH19, TOV19 TOH20, TOV20 TOH21, TOV21 TOH22, TOV22 Output float time TOF1 TOF4 TOF5 TOF6 TOF9 TOF10 TOF13 TOF14 TOF16 TOF17 TOF20 valid A6:31 A6:312,3,8 AMuxCAS BusReq CAS0:38 CAS0:32,3 CS0:7 D0:31 DMAA0:3 DMADXFER DRAMOE DRAMOE2,3,8 DRAMWE Error HoldAck OE RAS0:3(turn-off)8 RAS0:3(turn-on)3 RAS0:3(Early, turn-on)4 38 MHz TOHMin 3 16.2 3 3 3 16.2 3 3 3 3 3 16.2 3 3 3 3 3 16.2 10 2 3 3 4 3 3 4 Min 2 3 3 3 3 3 3 3 2 3 3 TOVMax 10 23.2 9 9 9 22.3 9 12 9 10 9 23.2 9 10 9 10 9 23.2 16.9 10 9 10 13 9 10 14 Max 8 10 10 10 9 9 9 10 9 9 9 Units TOH, TOV ns Reset R/W TC0:3 Parity(DMA)5,8 WBE0:3[BE0:3] XAck BLast8 A6:31 CAS0:3 CS0:7 TOF D0:31 DRAMOE DRAMWE OE RAS0:3 Reset R/W WBE0:3[BE0:3] ns 27 IBM PowerPC 403GCX Notes: 1. For all output timing, TOH and TOV are relative to the rising edge of SysClk. 2. For detailed EDO DRAM timing waveforms, refer to "EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer Read," on page 42 and "EDO DRAM 3-1-1-1 Burst Read Followed by Single Transfer Read," on page 44. 3. The Address bus, RAS, CAS and DRAMOE output timings (with respect to the falling edge of the internal duty cycle corrected SysClk) vary with the 403GCX operating frequency. Use the following equations to determine the worst-case output delay and hold times for these signals: TOVfMax = Tc/2 + TOVrMax; TOHfMin = Tc/2 + TOHrMin, where TOVrMax and TOHrMin correspond to the specifications for the speed grade of the part. Valid for Tc greater than 25 ns and less than 41.7 ns. 4. In early RAS mode, the RAS output delay varies with the 403GCX operating frequency. Use the following equation to determine the worst-case output delay for this signal: TOV15Max = Tc/4 + TOH15Min, where TOH15Min corresponds to the specification for the speed grade of the part. TOHMin remains unchanged. Valid for Tc greater than 25 ns and less than 41.7 ns. 5. Parity timings are for DMA buffered mode. For normal memory accesses, use the data bus timings for parity. 6. Output times are measured with a standard 50 pF capacitive load, unless otherwise noted. Output hold times are measured as TOVmin at 3.47V and Tj=0C. 7. All output hold and float times are guaranteed by design and not tested. 8. Noted output valid times guaranteed by design and not tested. Table 18. 403GCX DRAM Interface Timing Relationships Symbol Parameter Row Address Setup Time to RAS: BRn[ERM] = 0 BRn[ERM] = 1 Row Address Hold Time: BRn[ERM] = 0 BRn[ERM] = 1 Column Address Setup Time to CAS Column Address Hold Time Available CAS Access Time: 2-1-1-1 access 3-2-2-2 access 3-1-1-1 access CAS Precharge Time Write Data Setup Time to CAS RAS Precharge Time: BRn[ERM] = 0 and BRn[PCC] = 0 BRn[ERM] = 0 and BRn[PCC] = 1 BRn[ERM] = 1 and BRn[PCC] = 0 BRn[ERM] = 1 and BRn[PCC] = 1 RAS Active During Refresh: BR[RAR] = 0 BR[RAR] = 1 38 MHz Min Units TASR 0.5TC -4.0 0.25TC -2.5 0.5TC -1.5 0.67TC -0.5 0.5TC -4.0 0.5TC -2.0 0.5TC -2.5 1.5TC -2.5 0.5TC -2.5 0.5TC -2.5 0.5TC -4.0 1.5TC -2.5 2.5TC -2.5 1.25TC -1.0 2.25TC -1.0 1.5TC -1.5 2.5TC -1.5 ns TRAH TASC TCAH ns ns ns TCAS ns TCP TDS ns ns TRP ns TRAS ns Note: 1. Relationships are guaranteed by design and are not tested. Relationships also assume 50 pF capacitive loading on interface signals. 2. For detailed DRAM interface timing waveforms, refer to "DRAM Interface Timing Diagram," on page 29. 28 IBM PowerPC 403GCX DRAM Interface Timing Diagram ADDRESS TRAS TRP TASR TRAH TASC TCAH RAS 1.5V TCAS TCP CAS TDS WRITE DATA Output Derating for Capacitance and Voltage Output Propagation Delay Derating Derating Equations for Output Delays: 1. tpLH(CL, V) = tpLHC + tpLHV 2. tpHL(CL, V) = tpHLC + tpHLV 3. tpZL5V(CL, V) = tpZLC + tpHLV +20 Note: Test Conditions Vt = 1.5V at TJ = 85C tpZLC = 0.14 CL - 1.2ns (from 5.5V) Output Delay (ns) +10 tpHLC = 0.06 CL - 2.3ns tpLHC = 0.04 CL - 1.9ns 0 -10 0 50 100 150 CL (pF) 29 IBM PowerPC 403GCX Output Propagation Delay Derating vs Output Voltage Level +6 Note: Test condition TJ = 85C tpHLV (CL = 100 pF) tpLHV (CL = 100 pF) +4 Output Delay (ns) tpHLV (CL = 50pF) tpLHV (CL = 50pF) +2 tpHLV (CL = 25 pF) tpLHV (CL = 25 pF) 0 0 1.5 VOut (V) 3 Output Rise and Fall Time Derating Output Transition Time Derating Note: Test Conditions Vt = 0.8V to 2V at TJ = 85C +6 tprC Output Transition (ns) +4 Derating Equations for Output Rise and Fall Times: 4. tR(CL) = 2ns + tprC 5. tF(CL) = 2.5ns + tpfC tpfC +2 0 -2 0 50 100 150 CL (pF) 30 IBM PowerPC 403GCX Output Voltage vs Output Current 3.5 0.6 VOL Max (V) 0.3 0 0 1 2 3 4 VOH Min (V) 3 2.5 2 0 1 2 3 IOL (mA) Note: Test conditions 3.14V at TJ = 85C IOH (mA) Supply Current vs Operating Frequency Test Conditions: 3.47V at TJ = 85C (Worst Case) 320 mA ICC (mA) 260 mA 200 mA 103 mA 127 mA 155 mA Test Conditions: 3.3V at TJ = 55C (Typical) 0 0 FC (MHz) 25 33 40 31 IBM PowerPC 403GCX Input Leakage Current +200 +100 Leakage Current (a) 0 -100 -200 0 0.5 1.0 1.5 Input Voltage (v) See Note 3 in "403GCX DC Characteristics," on page 21. 2.0 2.5 3.0 32 IBM PowerPC 403GCX Reset and HoldAck The following table summarizes the states of signals on output pins when Reset or HoldAck is active. Table 19. Signal States During Reset or Hold Acknowledge Signal Names A6:29 AMuxCAS BusReq CAS0:3 CS0:3 CS4:7/RAS3:0 D0:31 DMAA0:3 XAck DRAMOE DRAMWE Error HoldAck OE Reset R/W TC0:2 TC3 TDO TS0:2 TS3:6[DP3:0] WBE0:3[BE0:3] XmitD State When Reset Active Floating Inactive (low) Inactive (low) Inactive (high) Floating Floating Floating Inactive (high) Inactive (high) Inactive (high) Inactive (high) Inactive (low) Inactive (low) Floating Floating unless initiating system reset Floating Floating (set to input) Floating (set to input) Floating Inactive (low) Floating Floating Inactive (high) State When HoldAck Active Floating (set to input mode) Operable (see note 1) Operable (see note 1) Operable (see notes 1 and 2) Floating CS floating, RAS operable (notes 1 and 2) Floating (external master drives bus) Inactive (high) Operable (see note 1) Operable (see notes 1 and 2) Operable (see notes 1 and 2) Operable (see note 1) Active Floating (input for XSize1) Floating unless initiating system reset Floating (set to input) Inactive (high) Floating (input for XSize0) Operable (see note 1) Operable (see note 1) Operable (see note 1)[floating when parity mode is enabled] Operable (inputs for A4:5, A30:31) Operable (see note 1) Note: 1. Signal may be active while HoldAck is asserted, depending on the operation being performed by the 403GCX. 2. Signal may be placed in high impedance, depending on DRAM 3-state control setting in IOCR. Bus Waveforms The waveforms in this section represent external bus operations, including SRAM and DRAM accesses, DMA transfers, and external master operations. Write Byte Enable Encoding The 403GCX provides four write byte enable signals (WBE0:3) to support 8-, 16-, and 32-bit devices, as shown in Table 20. For an eight-bit memory region, WBE2:3 are encoded as A30:31 and WBE0 is the byte-enable line. For a 16-bit region, WBE0 is the high-byte enable, WBE1 is the low-byte enable and WBE2:3 are encoded as A30:31. For a 32-bit region, address bits 6:29 select the word address and WBE0:3 select data bytes 0:3, respectively. 33 IBM PowerPC 403GCX Table 20. Write Byte Enable Encoding Transfer Size Byte 8-Bit Bus Width Byte Byte Byte Transfer Size Half-word Half-word 16-Bit Bus Width Byte Byte Byte Byte Transfer Size Word Half-word 32-Bit Bus Width Half-word Byte Byte Byte Byte Address 0 1 2 3 Address 0 2 0 1 2 3 Address 0 0 2 0 1 2 3 WBE0 = WE 0 0 0 0 WBE0 = BHE 0 0 0 1 0 1 WBE0 0 0 1 0 1 1 1 WBE1 = 1 1 1 1 1 WBE1 = BLE 0 0 1 0 1 0 WBE1 0 0 1 1 0 1 1 WBE2 = A30 0 0 1 1 WBE2 = A30 0 1 0 0 1 1 WBE2 0 1 0 1 1 0 1 WBE3 = A31 0 1 0 1 WBE3 =A31 0 0 0 1 0 1 WBE3 0 1 0 1 1 1 0 Address Bus Multiplexing To support DRAM memories with differing configurations and bus widths, the 403GCX provides an internally multiplexed address bus controlled by the BIU. Table 21 shows the multiplexed address outputs referenced by waveforms later in this section. Table 21. Multiplexed Address Outputs Address Pins Addr Bits Out in RAS Cycle Addr Bits Out in CAS Cycle A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 a6 xx a7 a6 a8 a7 a9 a10 a11 a12 a13 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a8 a9 a10 a11 a12 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 When the 403GCX is bus master and there are no bus operations in progress, the states of the address bus outputs are determined by the setting of IOCR[ATC]. If this bit is set to zero, the address bus will be placed in high impedance. If this bit is set to one, the last address held in the BIU address register will be driven out on the address bus until bus operations resume. 34 IBM PowerPC 403GCX SRAM Read-Write-Read with Zero Wait and One Hold 1 SysClk A6:29,1 WBE2[A30], WBE3[A31] R/W 2 3 4 5 6 7 8 Read Address Write Address Read Address CSx OE4 BLast5 WBE0:32,4 BE0:35 Valid - BE Valid - BE Valid - BE D0:31 Data In Data Out Data In BusError Error? Error? Error? Bank Register Bit Settings SLF Bit 13 0 or 1 Burst Mode Bit 14 0 Bus Width Bits 15:16 xx Ready Enable Bit 17 0 Wait States Bits 18:23 00 0000 CSon Bit 24 0 OEon Bit 25 0 WEon Bit 26 0 WEoff Bit 27 0 Hold Bits 28:30 001 Notes: 1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. See Table 20 on page 34 for WBE signal definitions based on bus width. 3. Byte Enable Mode IOCR[BEM] = 1. WBE0:3/BE0:3 are byte enables and BLast is the signal which appears on the multiplexed OE[XSize1][BLast] output. 4. When in Byte Enable Mode IOCR[BEM] = 1, the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8. 5. Not Byte Enable Mode IOCR[BEM] = 0. WBE0:3/BE0:3 are write byte enables and OE is the signal which appears on the multiplexed OE[XSize1][BLast] output. 35 IBM PowerPC 403GCX SRAM, ROM, or I/O Write Request with Wait and Hold 1 SysClk A6:29,1 WBE2[A30], WBE3[A31] R/W CSon=0 CSon=1 2 3 4 5 6 7 8 Address Valid CSx5 OE4,5 CSon=0 WEon=0 CSon=1,0 WEon=0,1 CSon=1 WEon=1 WEoff=1 WEoff=0 WBE0:32,3,5 CSon=0 OEon=0 CSon=1,0 OEon=0,1 CSon=1 OEon=1 D0:31 Wait + 1 Cycle Data Out Hold BusError Error? Bank Register Bit Settings SLF Bit 13 0 or 1 Burst Mode Bit 14 0 Bus Width Bits 15:16 xx Ready Enable Bit 17 0 Wait States Bits 18:23 00 0011 CSon Bit 24 0 or 1 OEon Bit 25 0 or 1 WEon Bit 26 0 or 1 WEoff Bit 27 0 or 1 Hold Bits 28:30 001 Notes: 1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. See Table 20 for WBE signal definitions based on bus width. 3. WBE signals can be read/write byte enables based on the setting of IOCR[BEM]. See waveform and note 3 on page 35. 4. When in Byte Enable Mode IOCR[BEM] = 1, the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8. 5. Wait must be programmed to a value (CSon + WEon + WEoff) and (CSon + OEon + WEoff). If Wait > (CSon + WEon) and > (CSon + OEon), then all signals retain the values shown in cycle 4 until the Wait time expires. 6. If Hold is programmed > 001, all signals retain the values shown in cycle 6 until the Hold timer expires. 36 IBM PowerPC 403GCX SRAM, ROM, or I/O Read Request, Wait Extended with Ready 1 SysClk A6:29,1 WBE2[A30], WBE3[A31] R/W CSon=0 CSon=1 2 3 4 5 6 7 8 Address Valid CSx5 CSon=0 OEon=0 CSon=0,1 OEon=1,0 CSon=1 OEon=1 OE4,5 WBE0:32,3 Sample Data D0:31 Wait Data In Not Ready Not Ready Sample Ready Ready Hold Ready7 BusError Error? Bank Register Bit Settings SLF Bit 13 0 or 1 Burst Mode Bit 14 0 Bus Width Bits 15:16 xx Ready Enable Bit 17 1 Wait States Bits 18:23 00 0010 CSon Bit 24 0 or 1 OEon Bit 25 0 or 1 WEon Bit 26 0 or 1 WEoff Bit 27 x Hold Bits 28:30 001 Notes: 1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. See Table 20 on page 34 for WBE signal definitions based on bus width. 3. WBE signals can be read/write byte enables based on the setting of IOCR[BEM]. See waveform and note 3 on page 35. 4. When in Byte Enable Mode IOCR[BEM] = 1, the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8. 5. Wait must be programmed to a value (CSon + OEon). If Wait > (CSon + OEon), then all signals will retain the values shown in cycle 4 until the Wait timer expires. 6. If Hold is programmed > 001, all output signals retain the values shown in cycle 7 until the Hold timer expires. 7. If Wait = 00 0000, the Ready input is ignored and single-cycle transfers occur. If Wait > 00 0000, Ready is sampled starting after the Wait cycles have expired. 8. IOCR[SOR] = 0. 37 IBM PowerPC 403GCX SRAM Read Extended with Ready (Asynchronous Ready Mode) Cycle SysClk A6:291 WBE2/A30 WBE3/A31 R/W CSon=0 CSon=1 Wait=000010 Sample Ready Hold=01 1 2 3 4 5 6 7 8 9 Valid CSx CSon=0 OEon=0 CSon=1, OEon=0 or CSon=0, OEon=1 OE2 BLAST3 WBE0:32 BE0:33 D0:D31 4 CSon=0 OEon=0 CSon=1, OEon=0 or CSon=0, OEon=1 Latch Data Data In READY Bank Register Settings SLF Bit 13 x Burst Mode Bit 14 o Bus Width Bits 15:16 xx Ready Enable Bit 17 1 Wait States Bits 18:23 000010 CSon Bit 24 0 or 1 OEon Bit 25 0 or 1 WEon Bit 26 x WEoff Bit 27 0 Hold Bits 28:30 001 Notes: 1. WBE2:3 are address bits A30:31 if the bus width is programmed as byte or halfword. 2. Not Byte Enable Mode (IOCR[BEM] = 0). WBE0:3/BE0:3 are write byte enables and OE/BLAST is OE. 3. Byte Enable Mode (IOCR[BEM] = 1). WBE0:3/BE0:3 are byte enables and OE/BLAST is BLAST 4. Arrows indicate when READY is sampled. 5. IOCR[ARE] is set. 38 IBM PowerPC 403GCX SRAM, ROM or I/O Burst Read with Wait and Hold 1 SysClk A6:29,1 WBE2[A30], WBE3[A31] R/W CSon=0 CSon=1 2 3 4 5 6 7 8 Address1 Addr2 Addr3 Address4 CSx5 CSon=0 OEon=0 CSon=0,1 OEon=1,0 OE4,5 BLast4 WBE0:32,3 BE0:33 D0:31 BusError Valid BE BE BE Valid BE D1 D2 D3 D4 Error? Wait + 1 Cycles5 Error? Burst + 1 Cycles Error? Burst + 1 Cycles Error? Burst + 1 Cycles Hold 6 Bank Register Bit Settings SLF Bit 13 0 or 1 Burst Mode Bit 14 1 Bus Width Bits 15:16 xx Ready Enable Bit 17 0 Wait States Burst Wait CSon Bit 24 0 or 1 OEon Bit 25 0 or 1 WEon Bit 26 x WEoff Bit 27 x Hold Bits 28:30 001 Bits 18:21 Bits 22:23 0001 00 Notes: 1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. See Table 20 on page 34 for WBE signal definitions based on bus width. 3. WBE signals can be read/write byte enables based on the setting of IOCR[BEM]. 4. When in Byte Enable Mode (IOCR[BEM] = 1), the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8. 5. Wait must be programmed to a value (CSon + OEon). If Wait > (CSon + OEon), then all signals will retain the values shown in cycle 3 until the Wait timer expires. 6. If Hold is programmed > 001, all output signals retain the values shown in cycle 7 until the Hold timer expires. 7. Data parity is only checked when IOCR[RDM] = 11 and BRHx[PCE] is set. 39 IBM PowerPC 403GCX SRAM, ROM or I/O Burst Write with Wait, Burst Wait, and Hold 1 SysClk A6:29,1 WBE2[A30], WBE3[A31] R/W CSon=0 CSon=1 2 3 4 5 6 7 8 9 10 11 12 13 14 Address1 Addr2 Addr3 Address4 CSx5 OE4,5 BLast4 CSon=0 CSon=1,0 CSon=1 WEon=0 WEon=0,1 WEon=1 WEoff=1 WEoff=1 WEoff=1 WEoff=1 WEoff=0 WBE0:32,3 BE0:33 Valid BE CSon=0 CSon=1,0 CSon=1 OEon=0 OEon=0,1 OEon=1 BE BE Valid BE D0:31 BusError Data1 Data2 Data3 Data4 Error ? Error ? Error ? Error ? Wait + 1 Cycles Burst + 1 Cycles Burst + 1 Cycles Burst + 1 Cycles Hold Bank Register Bit Settings SLF Bit 13 0 or 1 Burst Mode Bit 14 1 Bus Width Bits 15:16 xx Ready Enable Bit 17 0 Wait States Burst Wait CSon Bit 24 0 or 1 OEon Bit 25 0 or 1 WEon Bit 26 0 or 1 WEoff Bit 27 0 or 1 Hold Bits 28:30 001 Bits 18:21 Bits 22:23 0100 01 Notes: 1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. See Table 20 on page 34 for WBE signal definitions based on bus width. 3. WBE signals can be read/write byte enables based on the setting of a control bit in the IOCR. 4. When in Byte Enable Mode (IOCR bit 20 = 0), the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8. 5. Wait must be programmed to a value (CSon + WEon + WEoff) and (CSon + OEon + WEoff). If Wait > (CSon + WEon) and > (CSon + OEon), then all signals retain the values shown in cycle 3 until the Wait timer expires. 6. If Hold is programmed > 001, all output signals retain the values shown in cycle 12 until the Hold timer expires. 7. Data parity is only generated when IOCR[RDM] = 11. 40 IBM PowerPC 403GCX DRAM 2-1-1-1 Page Mode Read 1 SysClk A11:29, WBE2[A30], WBE3[A31] RAS CAS CAS CAS CAS Pre-Charge 2 3 4 5 6 7 8 Row Column1 Column2 Column3 Column4 AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE Note 8 Data1 Data2 Data3 Data4 Note 7 D0:31 BusError Error ? Error ? Error ? Error ? Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh CAS Mode Bit 18 0 Bit 19 0 Page Mode First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 0 or 1 0 xx x Bit 20 Bits 21:22 Bits 23:24 1 00 00 Notes: 1. For burst access, the addresses represented by Columns 1 to 4 does not necessarily indicate that they are in incremental address order. Typically, burst access is target word first. 2. If internal mux mode is used, address bits A11:29 represent address bits described in Table 21 on page 34. 3. During internal mux mode access, A6:10 retain their unmultiplexed values. 4. If external mux mode is used, A11:29 are unaffected and do not change between CAS and RAS cycles. 5. If bus width is programmed as byte or half-word, WBE2:3 represent address bits A30:31 regardless of mux mode. 6. WBE0:1 are always ones during DRAM transfers. 7. Data is latched on the rising edge of SysClk when IOCR[DRC] = 0 (default setting). 8. Data is latched later (on the rising edge of CAS) if IOCR[DRC] = 1. 41 IBM PowerPC 403GCX EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer Read Cycle SysClk A6:291 WBE2/A30 WBE3/A31 AMuxCAS Row Addr Col 1 Col 2 Col 3 Col 4 Row Addr Column Addr 1 2 RAS 3 CAS0 4 CAS1 5 CAS2 6 CAS3 7 Pre-Charge 8 9 10 RAS 11 CAS0 12 Pre-Chg 13 R/W RAS CAS DramOE DramWE D0:31, DP0:3 Note 2 D0 D1 D2 D3 D4 BusError Error? ? ? ? ? Error? Bank Register Bit Settings SLF ERM Bus Width Ext RAS-to- Refresh Page Mux CAS Mode Mode Bit 18 0 Bit 19 0 First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 1 Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 x 0 10 0 Bit 20 Bits 21:22 Bits 23:24 1 00 00 Notes: 1. IOCR[EDO] is set and IOCR[DRC] is cleared. 2. Data is latched with respect to the fall of the internal system clock (duty-cycle corrected). 3. Data parity, if enabled, matches the timing of data bus transfers. 42 IBM PowerPC 403GCX DRAM 3-2-2-2 Page Mode Write 1 SysClk RAS CAS CAS CAS CAS CAS CAS CAS CAS Pre-Chg 2 3 4 5 6 7 8 9 10 11 12 A11:29 Row Column1 Column2 Column3 Column4 AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE Data1 Data2 Data3 Data4 D0:31 BusError Error? Error? Error? Error? Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh CAS Mode Bit 18 0 Bit 19 0 Page Mode First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 0 or 1 0 xx x Bit 20 Bits 21:22 Bits 23:24 1 01 01 Notes: 1. For burst access, the addresses represented by Columns 1 to 4 do not necessarily indicate that they are in incremental address order. Typically, burst access is target word first. 2. If internal mux mode is used, address bits A11:29 represent address bits described in Table 21 on page 34. 3. During internal mux mode access, A6:10 retain their unmultiplexed values. 4. If external mux mode is used, A11:29 are unaffected and do not change between CAS and RAS cycles. 5. If bus width is programmed as byte or half-word, WBE2:3 represent address bits A30:31 regardless of mux mode. 6. WBE0:1 are always ones during DRAM transfers. 7. DRAM read on CAS, IOCR[DRC], and EDO DRAM, IOCR[EDO], modes do not affect writes. 43 IBM PowerPC 403GCX EDO DRAM 3-1-1-1 Burst Read Followed by Single Transfer Read Cycle SysClk A6:291 WBE2/A30 WBE3/A31 AMuxCAS Row Addr Col 1 Col 2 Col 3 Col 4 Row Addr Column Addr 1 2 RAS 3 CAS0 4 CAS0 5 CAS1 6 CAS2 7 CAS3 8 Pre-Chg 9 10 11 12 13 14 15 16 RAS CAS CAS Pre-Chg R/W RAS CAS DramOE DramWE D0:31 Latch data with fall of CAS D0 D1 D2 D3 D4 Note 2 ? ? ? ? Error? BusError Error? Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh CAS Mode Bit 18 0 Bit 19 0 Page Mode First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 x 0/1 10 0 Bit 20 Bits 21:22 Bits 23:24 1 01 00 Notes: 1. IOCR[EDO] is set and IOCR[DRC] is cleared. 2. Data is latched with respect to the fall of the internal system clock (duty-cycle corrected). 3. Data parity, if enabled, matches the timing of data bus transfers. 44 IBM PowerPC 403GCX DRAM Read-Write-Read, One Wait 1 SysClk RAS CAS CAS PreCharge RAS CAS PreCAS Charge RAS Column2 CAS CAS PreCharge 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11:29 Row1 Column1 Row2 Row3 Column3 AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 Data1 Data2 Data3 BusError Error ? Error ? Error ? Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh CAS Mode Bit 18 0 Bit 19 0 Page Mode First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 0 or 1 0 xx x Bit 20 Bits 21:22 Bits 23:24 0 01 xx Notes: 1. If internal mux mode is used, address bits A11:29 represent address bits described in Table 21 on page 34. 2. During internal mux mode access, A6:10 retain their unmultiplexed values. 3. If external mux mode is used, A11:29 are unaffected and do not change between CAS and RAS cycles. 4. If bus width is programmed as byte or half-word, WBE2:3 represent address bits A30:31 regardless of mux mode. 5. WBE0:1 are always ones during DRAM transfers. 45 IBM PowerPC 403GCX DRAM Three-state - Refresh request before and after HoldAck Cycle SysClk A6:29 WBE2/A30 WBE3/A31 HoldReq HoldAck RAS0:3 CAS0:3 DramWE, DramOE, R/W, OE/XSize1, EOT3/TC3/XSize0, WBE0:3 Bank 4 refresh request gets in just before HoldAck External master has control of bus; refreshes held off until out of HoldAck Bank 5 refresh counter expired while in HoldAck. Refresh of bank as soon as out of HoldAck F F E F F D F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 F F 0 F Bank Register Bit Settings SLF x ERM x Bus Ext Width Mux 10 0 RAS-to- Refresh CAS Mode x 0 Page Mode x First Burst Access Access x x Prechg Refresh Refresh Cycles RAS Rate x 0 xxxx Note: 1. IOCR[EDT] is set. 46 IBM PowerPC 403GCX DMA Buffered Single Transfer from Peripheral to 3-Cycle DRAM 1 SysClk Sync Sync BIU Req DMA Ack RAS CAS CAS Pre-Chg 2 3 4 5 6 7 8 9 10 11 12 DMAR DMAA A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 OE WBE0:3 Data Data Row Column Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh CAS Mode Bit 18 0 Bit 19 0 Page Mode First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 0 or 1 0 10 0 Bit 20 Bits 21:22 Bits 23:24 0 01 xx DMA Control Register Bit Settings Transfer Direction Transfer Width Transfer Mode PeripheralSetup Peripheral Wait Peripheral Hold Bit 2 1 Bits 4:5 10 Bits 9:10 00 Bits 11:12 00 Bits 13:18 00 0000 Bits 19-21 000 Notes: 1. DMAR must be inactive inactive at the start of cycle 9 to guarantee a single transfer. 2. This waveform assumes that the internal address mux is used. 3. CAS0 is used for byte accesses, CAS0:1 for halfwords, and CAS0:3 for fullwords. 47 IBM PowerPC 403GCX DMA Fly-By Single Transfer, Write to 3-Cycle DRAM 1 SysClk Sync Sync BIU Req RAS CAS CAS Pre-Chg 2 3 4 5 6 7 8 9 10 11 12 DMAR S=0 S=1 S=2 (S = peripheral setup time) DMAA DMADXFER A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 Data Row Column Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh Page CAS Mode Mode Bit 18 0 Bit 19 0 First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 0 or 1 0 10 0 Bit 20 Bits 21:22 Bits 23:24 0 01 xx DMA Control Register Bit Settings Transfer Direction Transfer Width Transfer Mode PeripheralSetup Peripheral Wait Peripheral Hold Bit 2 Bits 4:5 Bits 9:10 Bits 11:12 Bits 13:18 Bits 19-21 xxx 1 10 01 Note 3 xx xxxx Notes: 1. DMAR must be inactive in cycle 7 (last DMAA cycle) to guarantee a single transfer. 2. Peripheral data bus width must match DRAM bus width. 3. See diagram for settings. 4. This waveform assumes that the internal address mux is used. 5. CAS0 is used for byte accesses, CAS0:1 for halfwords, and CAS0:3 for fullwords. 48 IBM PowerPC 403GCX DMA Fly-By Continuous Burst to 3-Cycle DRAM 1 SysClk Sync Sync 2 3 BIU Req 4 RAS 5 CAS 6 CAS 7 CAS 8 CAS 9 CAS 10 CAS 11 Pre-Chg 12 DMAR DMAA DMADXFER A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 1 S=0 2 S=1 3 (S = peripheral setup time) 1 1 1 2 2 3 3 Row Column1 Column2 Column3 Data1 Data2 Data3 Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh Page CAS Mode Mode Bit 18 0 Bit 19 0 First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 0 or 1 0 10 0 Bit 20 Bits 21:22 Bits 23:24 1 01 01 DMA Control Register Bit Settings Transfer Direction Bit 2 1 Transfer Width Bits 4:5 10 Transfer Mode Bits 9:10 01 Peripheral Setup Bits 11:12 Note 3 Peripheral Wait Bits 13:18 xx xxxx Peripheral Hold Bits 19-21 xxx Burst Mode Bit 25 1 Notes: 1. DMAR must be inactive at the end of cycle 10 (last DMAA cycle) to guarantee three transfers. 2. Peripheral data bus width must match DRAM bus width. 3. See diagram for settings. 4. This waveform assumes that the internal address mux is used. 5. CAS0 is used for byte accesses, CAS0:1 for halfwords, and CAS0:3 for fullwords. 6. Numbers (1,2,3,...) in the DMAR signal represent when DMAR is sampled and accepted. Numbers (1,2,3,...) in the DMAA signal represent the transfers associated with the accepted DMAR. 49 IBM PowerPC 403GCX External Master Nonburst DRAM Read with HoldReq/HoldAck 1 SysClk Ext Bus Master XReq BSel RAS CAS CAS PreCharge 2 3 4 5 6 7 8 9 10 11 12 HoldReq HoldAck XReq1 R/W XSize0:11 XAck1 A4:312 403 Master Valid Address - Ext Master HiZ 403 Address 10 D0:31 DRAM Control 403 Master DRAM drives bus HiZ 403 Data AMuxCAS RASx CAS0:3 DRAMOE DRAMWE Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh CAS Mode Bit 18 0 Bit 19 0 Page Mode First Access Burst Access Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 0 or 1 0 10 1 Bit 20 Bits 21:22 Bits 23:24 0 01 xx Notes: 1. XReq, XSize0, XSize1, and XAck are multiplexed with DMAR3, EOT3/TC3, OE, and DMAA3, respectively. 2. A4, A5, A30, and A31 are multiplexed with WBE0, WBE1, WBE2, and WBE3, respectively. 50 IBM PowerPC 403GCX External Master DRAM Burst Write, 3-2-2-2 Page Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SysClk Ext Bus Master PreXReq BSel RAS CAS CAS CAS CAS CAS CAS CAS CAS Chg HoldReq HoldAck XReq3 R/W XSize0:11,2,3 XAck A4:314 D0:31 DRAM Control Valid Address1 - Ext Master 11 11 11 Address2 Address3 Address4 Valid Data1 - Ext Master Data2 Data3 Data4 AMuxCAS RASx CAS0:3 DRAMOE DRAMWE Bank Register Bit Settings SLF ERM Bus Width Ext Mux RAS-to- Refresh CAS Mode Bit 18 0 Bit 19 0 Page Mode First Access Burst Access Bits 23:24 01 Prechg Refresh Refresh Cycles RAS Rate Bit 25 0 Bit 26 x Bits 27:30 xxxx Bit 13 Bit 14 Bits 15:16 Bit 17 0 or 1 0 10 1 Bit 20 Bits 21:22 1 01 Notes: 1. XReq, XSize0, XSize1, and XAck are multiplexed with DMAR3, EOT3/TC3, OE, and DMAA3, respectively. 2. XSize0:1 = 11 indicates a burst transfer at the width of the DRAM device. 3. The burst is terminated in cycle 12 by deasserting the XReq input signal. A burst may also be terminated by deasserting either XSize0 or XSize1. 4. A4, A5, A30, and A31 are multiplexed with WBE0, WBE1, WBE2, and WBE3, respectively. 51 IBM PowerPC 403GCX Ordering Information This section provides the part numbering nomenclature for the 403GCX. For availability, contact your local IBM sales office. Table 22. PPC403GCX Part Number IBM Part Number 06K6173 OEMLS Part Number IBM25403GCX-3JC76C2 Processor Bus Frequency 76 MHz Package PQFP Revision Level C IBM Part Number Key for 403GCX IBM25403GCX-3JC76C2 403 Family Grade: 3 = 100 FITS 2 = 25 FITS Package: J - PQFP B - PBGA Clock Doubler Commercial Revision Level CPU speed: 50, 66, 80 52 IBM PowerPC 403GCX 53 (c) Copyright IBM Corporation 1996,2000. All rights reserved. Printed in the USA on recycled paper. 8-00 IBM Microelectronics, PowerPC, PowerPC Architecture, and 403GCX are trademarks, IBM and the IBM logo are registered trademarks of IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility of liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. IBM Microelectronics Division 1580 Route 52, Bldg. 502 Hopewell Junction, NY 12533-6531 Tel: (800) PowerPC SC09-3033-SP 08.16.00 |
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