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| ASAHI KASEI [AK5355] Low Power 16bit ADC FEATURES The AK5355 is a low voltage 16bit A/D converter for digital audio systems. The AK5355 also includes an Input Gain Amplifier, making it suitable for microphone applications or low-input signal levels. The analog signal input of the AK5355 is single-ended, eliminating the need for external filters. The AK5355 is housed in a space-saving 16-pin TSSOP package. FEATURES 1. Resolution: 16bits 2. Recording Functions * Gain Amplifier (0dB / +15dB) * Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz) 3. ADC Characteristics * Single-ended Input * Input Level: 1.8Vpp@VA=3.0V (= 0.6 x VA) * S/(N+D): 85dB * DR, S/N: 91dB 4. Master Clock: 256fs/384fs/512fs 5. Audio Data Format: MSB First, 2's compliment * 16bit MSB justified or I2S 8. Power Supply * VA, VD: 2.1 3.6V (typ. 3.0V) 9. Power Supply Current: 5mA 10. Ta = -40 85C 11. Package: 16pin TSSOP SEL DIF AK5355 LIN ADC RIN HPF Audio I/F Controller LRCK BCLK SDTO VD VCOM VA VSS Clock Divider PDN MCLK MS0113-E-00 -1- 2001/08 ASAHI KASEI [AK5355] Ordering Guide AK5355VT AKD5355 -40 +85C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK5355 Pin Layout VCOM RIN LIN VSS VA VD SEL NC 1 2 3 4 5 6 7 8 16 15 14 TST1 NC DIF PDN BCLK MCLK LRCK SDTO Top View 13 12 11 10 9 PIN/FUNCTION Function ADC Common Voltage Output Pin Rch Input Pin Lch Input Pin Ground Pin Analog Power Supply Pin, +3.0V Digital Power Supply Pin, +3.0V Input Gain Select Pin 7 SEL I "L": 0dB, "H": +15dB 8 NC NC Pin (No internal bonding) 9 SDTO O Audio Serial Data Output Pin 10 LRCK I Input/Output Channel Clock Pin 11 MCLK I Master Clock Input Pin 12 BCLK I Audio Serial Data Clock Pin Reset & Power Down Pin 13 PDN I "L" : Reset & Power down, "H" : Normal operation Audio Data Format Select Pin 14 DIF I "L": MSB justified, "H": I2S 15 NC NC Pin (No internal bonding) TEST pin (Pull-down Pin) 16 TST1 I This pin should be left floating or connected to VSS Note: All digital input pins should not be left floating. No. 1 2 3 4 5 6 Pin Name VCOM RIN LIN VSS VA VD I/O O I I - MS0113-E-00 -2- 2001/08 ASAHI KASEI [AK5355] ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 1) Parameter Power Supply Analog Digital Input Current (Any Pin Except Supplies) Analog Input Voltage (LIN, RIN pins) Digital Input Voltage Ambient Temperature (power applied) Storage Temperature Note 1. All voltages with respect to ground. Symbol VA VD IIN VINA VIND Ta Tstg Min -0.3 -0.3 -0.3 -0.3 -40 -65 max 4.6 4.6 10 VA+0.3 VD+0.3 85 150 Units V V mA V V C C WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Power Supply Analog (VA pin) Digital (VD pin) Note 1. All voltages with respect to ground. Symbol VA VD min 2.1 2.1 typ 3.0 3.0 max 3.6 VA Units V V WARNING: AKM assumes no responsibility for the usage beyond the conditions in this data sheet. MS0113-E-00 -3- 2001/08 ASAHI KASEI [AK5355] ANALOG CHARACTERISTICS (Ta=25C; VA, VD=3.0V; fs=44.1kHz; Signal Frequency=1kHz; Measurement frequency=10Hz 20kHz; unless otherwise specified) Parameter min typ max Resolution 16 Input PGA Characteristics (IPGA): Gain = 0dB 1.65 1.8 1.95 Input Voltage (Note 2) Gain = +15dB 0.29 0.32 0.35 Gain = 0dB 27 40 Input Impedance Gain = +15dB 20 30 ADC Analog Input Characteristics: (Note 3) Gain = 0dB 75 85 S/(N+D) (-0.5dBFS Output) Gain = +15dB 70 80 Gain = 0dB 84 91 D-Range (-60dBFS Output, A-weight) Gain = +15dB 76 84 Gain = 0dB 84 91 S/N (A-weight) Gain = +15dB 76 84 Gain = 0dB 90 100 Interchannel Isolation Gain = +15dB 80 90 Gain = 0dB 0.2 0.5 Interchannel Gain Mismatch Gain = +15dB 0.2 1.0 Power Supplies Units bits Vpp Vpp k k dB dB dB dB dB dB dB dB dB dB Power Supply Current: VA+VD Normal Operation (PDN="H") 5 7.5 mA Power Down (PDN="L") (Note 4) 10 100 A Note 2. Analog input voltage (full-scale voltage) scales with VA. Gain = 0dB; 0.6 x VA Gain = +15dB; 0.107 x VA Note 3. ADC measurements are input from LIN/RIN and routed through input gain amplifier. The internal HPF cancels the offset of input gain amplifier and ADC. Note 4. In case of power-down mode, all digital input pins including clocks pins (MCLK, BCLK and LRCK) are held at VD or VSS. PDN pin is held at VSS. MS0113-E-00 -4- 2001/08 ASAHI KASEI [AK5355] FILTER CHARACTERISTICS (Ta=25C; VA, VD=2.1 3.6V; fs=44.1kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): PB 0 17.4 kHz Passband (Note 5) 0.1dB 20.0 kHz -1.0dB 21.1 kHz -3.0dB Stopband (Note 5) SB 27.0 kHz Passband Ripple PR dB 0.1 Stopband Attenuation SA 65 dB Group Delay (Note 6) GD 17.0 1/fs Group Delay Distortion 0 GD s ADC Digital Filter (HPF): Frequency Response (Note 5) -3dB FR 3.4 Hz -0.5dB 10 Hz -0.1dB 22 Hz Note 5. The passband and stopband frequencies scale with fs (sampling frequency). For examples, PB=0.454 x fs(@ADC: -1.0dB). Note 6. The calculated delay time caused by digital filtering. This time is from the input of an analog signal to setting the 16bit data of both channels to the output register of the ADC and includes the group delay of the HPF. DC CHARACTERISTICS (Ta=25C; VA, VD=2.1 3.6V) Parameter Symbol High-Level Input Voltage (Except for TST1 pin) VIH Low-Level Input Voltage (Except for TST1 pin) VIL VOH High-Level Output Voltage (Iout=-80A) VOL Low-Level Output Voltage (Iout=80A) Input Leakage Current (Note 7) Iin Note 7. TST1 pin is pulled-down internally (typ. 100k) min 75%VD VD-0.4 typ max 25%VD 0.4 10 Units V V V V A MS0113-E-00 -5- 2001/08 ASAHI KASEI [AK5355] SWITCHING CHARACTERISTICS (Ta=25C; VA, VD=2.1 3.6V; CL=20pF) Parameter Symbol min Control Clock Frequency Master Clock (MCLK) 256fs: Frequency 2.048 fCLK Pulse Width Low 28 tCLKL Pulse Width High 28 tCLKH 384fs: Frequency 3.072 fCLK Pulse Width Low 23 tCLKL Pulse Width High 23 tCLKH 512fs: Frequency 4.096 fCLK Pulse Width Low 16 tCLKL Pulse Width High 16 tCLKH Channel Clock (LRCK) Frequency 8 fs Duty Cycle 45 duty Audio Interface Timing BCLK Period 312.5 tBLK BCLK Pulse Width Low 130 tBLKL Pulse Width High 130 tBLKH -tBLKH+50 tBLR BCLK "" to LRCK tDLR LRCK Edge to SDTO (MSB) tDSS BCLK "" to SDTO Reset / Initializing Timing 150 PDN Pulse Width tPW PDN "" to SDTO (Note 8) tPWV Note 8. This is the number of LRCK rising after the PDN pin is pulled high. typ max Units 11.2896 12.8 16.9344 19.2 22.5792 25.6 44.1 50 55 MHz ns ns MHz ns ns MHz ns ns kHz % ns ns ns ns ns ns ns 1/fs tBLKL-50 80 80 4128 MS0113-E-00 -6- 2001/08 ASAHI KASEI [AK5355] Timing Diagram 1/fCLK MCLK tCLKH 1/fs LRCK tBLK BCLK tBLKH tBLKL VIH VIL VIH VIL tCLKL VIH VIL Figure 1. Clock Timing LRCK tBLR BCLK tDLR SDTO tDSS D15 (MSB) Figure 2. Audio Data Input/Output Timing (Audio I/F = No.0) tPW PDN tPWV SDTO Figure 3. Reset Timing VIL VIH VIL VIH VIL 50%VD 50%VD MS0113-E-00 -7- 2001/08 ASAHI KASEI [AK5355] OPERATION OVERVIEW System Clock The clocks required to operate are MCLK (256fs/384fs/512fs), LRCK (fs) and BCLK (32fs). The master clock (MCLK) should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be input as 256fs, 384fs or 512fs. When the 384fs or 512fs is input, the internal master clock is divided into 2/3 or 1/2 automatically. *fs is sampling frequency. All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these clocks are not provided, the AK5355 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK5355 should be placed in powerdown mode. Audio Data I/F Format The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes, MSBfirst and 2's compliment. The data format is set using the DIF pin. No. 0 1 DIF pin L H SDTO (ADC) LRCK 16bit MSB justified Lch: "H", Rch: "L" I2S Compatible Lch: "L", Rch: "H" Table 1. Audio Data Format BCLK 32fs 32fs Figure Figure 4 Figure 5 LRCK 0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1 BCLK(32fs) SDTO(o) 0 15 14 13 1 2 3 8 7 14 6 15 5 16 4 17 3 18 2 1 31 0 0 15 14 13 1 2 3 8 7 14 6 15 5 16 4 17 3 18 2 1 31 0 0 15 1 BCLK(64fs) SDTO(o) 15 14 13 13 2 1 0 15 14 13 1 2 1 0 15 15:MSB, 0:LSB Lch Data Rch Data Figure 4. Audio Data Timing (No.0) LRCK 0 1 2 3 4 9 10 11 12 13 14 15 0 1 2 3 4 9 10 11 12 13 14 15 0 1 BCLK(32fs) SDTO(o) 0 0 1 15 2 14 13 3 4 7 14 7 15 6 16 5 17 4 18 3 2 31 1 0 0 1 15 14 13 2 3 4 7 14 7 15 6 16 5 17 4 18 3 2 31 1 0 0 1 BCLK(64fs) SDTO(o) 15 14 13 2 1 0 15 14 13 2 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 5. Audio Data Timing (No. 1) MS0113-E-00 -82001/08 ASAHI KASEI [AK5355] Digital High Pass Filter The AK5355 has a Digital High Pass Filter (HPF) to cancel DC-offset in both the ADC and input gain amplifier. The cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This cut-off frequency scales with the sampling frequency (fs). Input Gain Amplifier The AK5355 includes an input gain amplifier. The gain can be changed to 0dB or +15dB by using the SEL pin. Input impedance is 40k typically. SEL pin Gain L 0dB H +15dB Table 2. Input Gain Amplifier Power down The AK5355 is placed in the power-down mode by bringing PDN "L". The digital filter is also reset at the same time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down mode. The output data SDTO becomes available after 4128 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2's complement "0". The ADC outputs settle to the data corresponding to the input signals at the end of initialization (Settling time equals the group delay time approximately). 4128/fs(93.6ms@fs=44.1kHz) PDN Internal State A/D In (Analog) A/D Out (Digital) Clock In MCLK,LRCK,BCLK Normal Operation GD (1) Power-down Initialize Normal Operation GD Idle Noise (2) "0"data "0"data Idle Noise (3) Notes: (1) Digital output corresponding to the analog input is delayed by the Group Delay amount (GD). (2) A/D output is "0" data in the power-down state. (3) When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5355 should be placed in the powerdown state. Figure 6. Power-down/up sequence example System Reset The AK5355 should be reset once by bringing PDN "L" upon power-up. The AK5355 is powered up and the internal timing starts clocking by LRCK "" after exiting reset and power down state by MCLK. The AK5355 is in the power-down mode until MCLK and LRCK are input. MS0113-E-00 -9- 2001/08 ASAHI KASEI [AK5355] SYSTEM DESIGN Figure 7 shows the system connection diagram. An evaluation board [AKD5355] is available which demonstrates the application circuit, optimum layout, power supply arrangements and measurement results. 2.2 + 0.1 Rch In Lch In + + 1 2 3 VCOM RIN LIN VSS VA VD SEL NC TST1 16 NC 15 DIF 14 Mode Setting Reset Analog Supply 2.1 3.6V Digital Supply 2.1 3.6V 10 + 0.1 4 5 6 Top View PDN 13 BCLK 12 MCLK 11 LRCK 10 SDTO 9 10 + 0.1 Controller 7 8 Analog Ground System Ground Figure 7. System Connection Diagram Example MS0113-E-00 - 10 - 2001/08 ASAHI KASEI [AK5355] MIC Device Connection Example Figure 8 shows the connection example of MIC Device. In this case, a mono microphone is connected to LIN pin the AK5355. Unused RIN pin can be open. The power supply for the microphone is provided via 4.4k (2.2k + 2.2k) from analog power supply. The power supply noise provided to the microphone should be care because the microphone gain is usually high, around 40dB. In Figure 8, 1st order LPF by 2.2k and 10F is inserted between the power supply and the microphone. The AK5355 has a gain of +15dB in analog stage. However, as the usual application needs a gain of around 40dB or 50dB, the shortage of gain, 25dB or 35dB, should be covered by digital processing like DSP. The total S/N in each gain level is shown in Table 3 Analog Gain +15dB +15dB +15dB Digital Gain 0dB +25dB +35dB Table 3. S/N of each gain level S/N 83dB 58dB 48dB MIC 2.2k 2.2k 0.1 2.2 + 0.1 10 + 1 2 3 VCOM RIN LIN VSS VA VD SEL NC TST1 16 NC 15 DIF 14 Mode Setting Reset Analog Supply 2.1 3.6V Digital Supply 2.1 3.6V 10 + 0.1 4 5 6 Top View PDN 13 BCLK 12 MCLK 11 LRCK 10 SDTO 9 10 + 0.1 Controller 7 8 Analog Ground System Ground Figure 8. MIC Device Connection Example MS0113-E-00 - 11 - 2001/08 ASAHI KASEI [AK5355] 1. Grounding and Power Supply Decoupling The AK5355 requires careful attention to power supply and grounding arrangements. VA is usually supplied from the analog supply in the system. VD is a power supply pin to interface with the external ICs and is supplied from the digital supply in the system. VSS of the AK5355 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5355 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference The input to VA Voltage sets the analog input range. A 0.1F ceramic capacitor and a 10F electrolytic capacitor are normally connected to VA and VSS pins. VCOM is a signal ground of this chip. An electrolytic 2.2F in parallel with a 0.1F ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clock, should be kept away from the VA, VD and VCOM pins in order to avoid unwanted coupling into the AK5355. 3. Analog Inputs The analog inputs are single-ended and the input resistance is 40k (typ). The input signal range scales with nominally (0.6 x VA) Vpp (typ) @ GAIN = 0dB centered around the internal common voltage (typ. 0.45 x VA). Usually, the input signal cuts DC with a capacitor. The cut-off frequency is fc=(1/2RC). The ADC output data format is 2's complement. The DC offset including the ADC's own DC offset is removed by the internal HPF (fc=3.4Hz@fs=44.1kHz). MS0113-E-00 - 12 - 2001/08 ASAHI KASEI [AK5355] PACKAGE 16pin TSSOP (Unit: mm) *5.00.1 1.050.05 16 9 *4.40.1 A 6.40.2 0.170.05 Detail A 0.10.1 0-10 0.50.2 0.10 Epoxy Cu Solder (Pb free) plate 2001/08 - 13 - 1 0.220.1 8 0.65 0.13 M Seating Plane NOTE: Dimension "*" does not include mold flash. Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0113-E-00 ASAHI KASEI [AK5355] MARKING AKM 5355VT XXYYY 1) Pin #1 indication 2) Date Code : XXYYY (5 digits) XX : Lot# YYY : Date Code 3) Marketing Code : 5355VT 4) Asahi Kasei Logo IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0113-E-00 - 14 - 2001/08 |
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