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EP9302 Data Sheet
FEATURES
* 200-MHz ARM920T Processor * 16-kbyte Instruction Cache * 16-kbyte Data Cache * * * Linux(R), Microsoft(R) Windows(R) CE-enabled MMU 100-MHz System Bus
High-speed ARM9 System-on-chip Processor with MaverickCrunch
* 6-channel Serial Audio Interface (I2S) * 2-channel, Low-cost Serial Audio Interface (AC'97) Internal Peripherals * 12 Direct Memory Access (DMA) Channels * Real-time Clock with Software Trim * Dual PLL controls all clock domains. * Watchdog Timer * Two General-purpose 16-bit Timers * One General-purpose 32-bit Timer * One 40-bit Debug Timer * Interrupt Controller * Boot ROM Package * 208-pin LQFP
MaverickCrunchTM Math Engine * Floating point, Integer and Signal Processing Instructions * Optimized for digital music compression and decompression algorithms. * Hardware interlocks allow in-line coding. MaverickKeyTM IDs * 32-bit unique ID can be used for DRM-compliant, 128-bit random ID. Integrated Peripheral Interfaces * 16-bit SDRAM Interface (up to 4 banks) * 16-bit SRAM / FLASH / ROM * Serial EEPROM Interface * 1/10/100 Mbps Ethernet MAC * Two UARTs * Two-port USB 2.0 Full-speed Host (OHCI) (12 Mbits per second) * IrDA Interface * ADC * Serial Peripheral Interface (SPI) Port
*
*
*
*
COMMUNICATIONS PORTS
Serial Audio Interface
Peripheral Bus
USER INTERFACE
MaverickCrunch
(2) UARTs w/ IrDA 12 Channel DMA
TM
Clocks & Timers
ARM920T D-Cache 16KB I-Cache 16KB
Interrupts & GPIO
MaverickKeyTM (2) USB Hosts Processor Bus Ethernet MAC Boot ROM
MMU
Bus Bridge
SRAM & Flash I/F
Unified SDRAM I/F
MEMORY AND STORAGE (c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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OVERVIEW
The EP9302 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: * * * * * * * * * * * * * * * Industrial controls Digital media servers Integrated home media gateways Digital audio jukeboxes Streaming audio players Set-top boxes Point-of-sale terminals Thin clients Biometric security systems GPS & fleet management systems Educational toys Industrial computers Industrial hand-held devices Voting machines Medical equipment
The ARM920T microprocessor core with separate 16 kbyte, 64-way set-associative instruction and data caches is augmented by the MaverickCrunchTM coprocessor enabling faster than real-time compression of audio CDs. The MaverickKeyTM unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. A high-performance 1/10/100 Mbps Ethernet media access controller (EMAC) is included along with external interfaces to SPI, AC'97, and I2S audio. A two-port USB 2.0 Full-speed Host (OHCI) (12 Mbits per second), two UARTs, and a analog voltage measurement analog-todigital converter (ADC) are included as well. The EP9302 is a high-performance, low-power RISCbased, single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1.8 V supply, while the I/O operates at 3.3 V with power usage between 100 mW and 750 mW (dependent on speed).
The EP9302 is one of a series of ARM920T-based devices. Other members of the family have different peripheral sets, coprocessors and package configurations.
Table A. Change History
Revision
PP1 PP2 PP3
Date
June 2004 July 2004 March 2005 Initial Release. Update AC data. Add ADC data.
Changes
Update electrical specs with most-current characterization data.
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Table of Contents
Processor Core - ARM920T ......................................................................................... 6 MaverickCrunchTM Math Engine .................................................................................. 6 MaverickKeyTM Unique ID ............................................................................................ 6 General Purpose Memory Interface (SDRAM, SRAM, ROM, Flash) ........................... 6 Ethernet Media Access Controller (MAC) .................................................................... 7 Serial Interfaces (SPI, I2S, and AC '97) ....................................................................... 7 12-bit Analog-to-digital Converter (ADC) ..................................................................... 7 Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 8 Dual-port USB Host ..................................................................................................... 8 Two-wire Interface ........................................................................................................ 8 Real-Time Clock with Software Trim ............................................................................ 8 PLL and Clocking ......................................................................................................... 9 Timers .......................................................................................................................... 9 Interrupt Controller ....................................................................................................... 9 Dual LED Drivers ......................................................................................................... 9 General Purpose Input/Output (GPIO) ......................................................................... 9 Reset and Power Management ................................................................................. 10 Hardware Debug Interface ......................................................................................... 10 12-Channel DMA Controller ....................................................................................... 10 Internal Boot ROM ..................................................................................................... 10
Electrical Specifications ................................................................................. 11
Absolute Maximum Ratings ........................................................................................11 Recommended Operating Conditions .......................................................................11 DC Characteristics ..................................................................................................... 12
Timings .............................................................................................................13
Memory Interface ....................................................................................................... 14 Ethernet MAC Interface ............................................................................................ 27 Audio Interface ........................................................................................................... 29 AC'97 ........................................................................................................................ 33 ADC ........................................................................................................................... 34 JTAG .......................................................................................................................... 35
208 Pin LQFP Package Outline .....................................................................36
208 Pin LQFP Pinout ................................................................................................. 37
Acronyms and Abbreviations ........................................................................41 Units of Measurement .....................................................................................41 Ordering Information ......................................................................................42
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List of Figures
Figure 1. Timing Diagram Drawing Key ................................................................................. 13 Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 14 Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 15 Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 16 Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 17 Figure 6. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement .................... 18 Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement .................... 19 Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement .................. 20 Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement .................. 21 Figure 10. Static Memory Burst Read Cycle Timing Measurement ....................................... 22 Figure 11. Static Memory Burst Write Cycle Timing Measurement ....................................... 23 Figure 12. Static Memory Single Read Wait Cycle Timing Measurement ............................. 24 Figure 13. Static Memory Single Write Wait Cycle Timing Measurement .............................. 25 Figure 14. Static Memory Turnaround Cycle Timing Measurement ....................................... 26 Figure 15. Ethernet MAC Timing Measurement ..................................................................... 28 Figure 16. TI Single Transfer Timing Measurement ............................................................... 30 Figure 17. Microwire Frame Format, Single Transfer ............................................................ 30 Figure 18. SPI Format with SPH=1 Timing Measurement ..................................................... 31 Figure 19. Inter-IC Sound (I2S) Timing Measurement ........................................................... 32 Figure 20. AC `97 Configuration Timing Measurement .......................................................... 33 Figure 21. ADC Transfer Function ......................................................................................... 34 Figure 22. JTAG Timing Measurement .................................................................................. 35
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List of Tables
Table A. Change History .......................................................................................................... 2 Table B. General Purpose Memory Interface Pin Assignments .............................................. 6 Table C. Ethernet Media Access Controller Pin Assignments ................................................. 7 Table D. Audio Interfaces Pin Assignment .............................................................................. 7 Table E. 12-bit Analog-to-Digital Converter Pin Assignments ................................................. 7 Table F. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 8 Table G. Dual Port USB Host Pin Assignments ....................................................................... 8 Table H. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 8 Table I. Real-Time Clock with Pin Assignments ..................................................................... 8 Table J. PLL and Clocking Pin Assignments .......................................................................... 9 Table K. Interrupt Controller Pin Assignment .......................................................................... 9 Table L. Dual LED Pin Assignments ....................................................................................... 9 Table M.General Purpose Input/Output Pin Assignment ........................................................ 9 Table N. Reset and Power Management Pin Assignments ................................................... 10 Table O. Hardware Debug Interface ...................................................................................... 10 Table P. Pin List in Numerical Order by Pin Number ............................................................. 37 Table Q. Pin Descriptions ..................................................................................................... 39 Table R. Pin Multiplex Usage Information .............................................................................. 40
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Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with separate 16-kbyte instruction and data caches with an 8word line length but a unified memory. The processor utilizes a five-stage pipeline consisting of fetch, decode, execute, memory, and write stages. Key features include: * * * * * * * * ARM (32-bit) and Thumb (16-bit compressed) instruction sets 32-bit Advanced Micro-Controller Bus Architecture (AMBA) 16 kbyte Instruction Cache with lockdown 16 kbyte Data Cache (programmable write-through or write-back) with lockdown MMU for Linux(R), Microsoft(R) Windows(R) CE and other operating systems Translation Look Aside Buffers with 64 Data and 64 Instruction Entries Programmable Page Sizes of 1 Mbyte, 64 kbyte, 4 kbyte, and 1 kbyte Independent lockdown of TLB Entries
provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID are programmed into the EP9302 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9302 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today's Internet appliances.
General Purpose Memory Interface (SDRAM, SRAM, ROM, Flash)
The EP9302 features a unified memory address model where all memory devices are accessed over a common address/data bus. Memory accesses are performed via the Processor bus. The SRAM memory controller supports 8 and 16-bit devices and accommodates an internal boot ROM concurrently with 16-bit SDRAM memory. * * * 1 to 4 banks of 16-bit ,100-MHz SDRAM Address and data bus shared between SDRAM, SRAM, ROM, and FLASH memory NOR FLASH memory supported
Table B. General Purpose Memory Interface Pin Assignments
MaverickCrunchTM Math Engine
The MaverickCrunch Engine is a mixed-mode coprocessor designed primarily to accelerate the math processing required to rapidly encode digital audio formats. It accelerates single and double precision integer and floating point operations plus an integer multiply-accumulate (MAC) instruction that is considerably faster than the ARM920T's native MAC instruction. The ARM920T coprocessor interface is utilized thereby sharing its memory interface and instruction stream. Hardware forwarding and interlock allows the ARM to handle looping and addressing while MaverickCrunch handles computation. Features include: * * * * * * * * IEEE-754 single and double precision floating point 32 / 64-bit integer Add / multiply / compare Integer MAC 32-bit input with 72-bit accumulate Integer Shifts Floating point to/from integer conversion Sixteen 64-bit register files Four 72-bit accumulators
Pin Mnemonic
SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn CSn[7:6] and CSn[3:0] AD[25:0] DA[15:0] DQMn[1:0] WRn RDn WAITn
Pin Description
SDRAM Clock SDRAM Clock Enable SDRAM Chip Selects 3-0 SDRAM RAS SDRAM CAS SDRAM Write Enable Chip Selects 7, 6, 3, 2, 1, 0 Address Bus 25-0 Data Bus 15-0 SDRAM Output Enables / Data Masks SRAM Write Strobe SRAM Read / OE Strobe SRAM Wait Input
MaverickKeyTM Unique ID
MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs
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Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC 802.3 topology for a single shared medium with several stations. Multiple MII-compliant PHYs are supported. Features include: * * Supports 1/10/100 Mbps transfer rates for home / small-business / large-business applications Interfaces to an off-chip PHY through industrystandard Media-independent Interface (MII)
Table C. Ethernet Media Access Controller Pin Assignments
Table D. Audio Interfaces Pin Assignment
Pin Name
SCLK1 SFRM1
Normal Mode Pin Description
SPI Bit Clock
I2S on SSP Mode Pin Description
I2S Serial Clock
I2S on AC'97 Mode Pin Description
SPI Bit Clock SPI Frame Clock SPI Serial Input SPI Serial Output
SPI Frame Clock I2S Frame Clock I2S Serial Input I2S Serial Output (No I2S Master Clock)
SSPRX1 SPI Serial Input SSPTX1 SPI Serial Output
Pin Mnemonic
MDC MDIO RXCLK MIIRXD[3:0] RXDVAL RXERR TXCLK MIITXD[3:0] TXEN TXERR CRS CLD
Pin Description
Management Data Clock Management Data I / O Receive Clock Receive Data Receive Data Valid Receive Data Error Transmit Clock Transmit Data Transmit Enable Transmit Error Carrier Sense Collision Detect
ARSTn
AC'97 Reset
AC'97 Reset AC'97 Bit Clock AC'97 Frame Clock AC'97 Serial Input
I2S Master Clock I2S Serial Clock I2S Frame Clock I2S Serial Input
ABITCLK AC'97 Bit Clock ASYNC ASDI ASDO AC'97 Frame Clock AC'97 Serial Input AC'97 Serial Output
AC'97 Serial Output I2S Serial Output
12-bit Analog-to-digital Converter (ADC)
The ADC block consists of a 12-bit analog-to-digital converter with a analog input multiplexer. The multiplexer can select to measure battery voltage and other miscellaneous voltages on the external measurement pins. Features include: * * * 5 external pins for ADC measurement Measurement pin input range: 0 to 3.3 V. ADC-conversion-complete interrupt signal
Serial Interfaces (SPI, I2S, and AC '97)
The Serial Peripheral Interface (SPI) port can be configured as a master or a slave, supporting the National Semiconductor(R), Motorola(R), and Texas Instruments(R) signaling protocols. The AC'97 port supports multiple codecs for multichannel audio output with a single stereo input. The I2S port supports stereo 24-bit audio. These ports are multiplexed so that the I2S port will take over either the AC'97 pins or the SPI pins. * * * Normal Mode: One SPI Port and one AC'97 Port I2S on SSP Mode: One AC'97 Port and one I2S Port I2S on AC'97 Mode: One SPI Port and one I2S Port
Note: I2S may not be output on AC'97 and SSP ports at the same time.
Table E. 12-bit Analog-to-Digital Converter Pin Assignments
Pin Mnemonic
ADC[0] (Ym, pin 135) ADC[1] (sXp, pin 134) ADC[2] (sXm, pin 133) ADC[3] (sYp, pin 132) ADC[4] (sYm, pin 131)
Pin Description
External Analog Measurement Input External Analog Measurement Input External Analog Measurement Input External Analog Measurement Input External Analog Measurement Input
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Universal Asynchronous Receiver/Transmitters (UARTs)
Two 16550-compatible UARTs are supplied. One provides asynchronous HDLC (High-level Data Link Control) protocol support for full duplex transmit and receive. The HDLC receiver handles framing, address matching, CRC checking, control-octet transparency, and optionally passes the CRC to the host at the end of the packet. The HDLC transmitter handles framing, CRC generation, and control-octet transparency. The host must assemble the frame in memory before transmission. The HDLC receiver and transmitter use the UART FIFOs to buffer the data streams. The second UART provides IrDA(R) compatibility. * UART1 supports modem bit rates up to 115.2 kbps, supports HDLC and includes a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Interrupts are generated on Rx, Tx and modem status change. UART2 contains an IrDA encoder operating at either the slow (up to 115 kbps), medium (0.576 or 1.152 Mbps), or fast (4 Mbps) IR data rates. It also has a 16 byte FIFO for receive and a 16 byte FIFO for transmit.
Table F. Universal Asynchronous Receiver/Transmitters Pin Assignments
Supports both low-speed (1.5 Mbps) and full-speed (12 Mbps) USB device connections * Root HUB integrated with 2 downstream USB ports * Transceiver buffers integrated, over-current protection on ports * Supports power management * Operates as a master on the bus The Open HCI host controller initializes the master DMA transfer with the AHB bus: * * * * Fetches endpoint descriptors and transfer descriptors Accesses endpoint data from system memory Accesses the HC communication area Writes status and retire transfer descriptor
Table G. Dual Port USB Host Pin Assignments
*
Pin Mnemonic
USBp[2,0] USBm[2,0] Note:
Pin Name - Description
USB Positive signals USB Negative Signals
*
USBm[1] and USBp[1] are not bonded out.
Two-wire Interface
The two-wire interface provides communication and control for synchronous-serial-driven devices.
Table H. Two-Wire Port with EEPROM Support Pin Assignments
Pin Mnemonic
TXD0 RXD0 CTSn DSRn / DCDn DTRn RTSn EGPIO[0] / RI TXD1 / SIROUT RXD1 / SIRIN
Pin Name - Description
UART1 Transmit UART1 Receive UART1 Clear To Send / Transmit Enable UART1 Data Set Ready / Data Carrier Detect UART1 Data Terminal Ready UART1 Ready To Send UART1 Ring Indicator UART2 Transmit / IrDA Output UART2 Receive / IrDA Input
Pin Mnemonic
EECLK EEDATA
Pin Name - Description
Two-wire Interface Clock Two-Wire Interface Data
Alternative Usage
General Purpose I/O General Purpose I/O
Real-Time Clock with Software Trim
The software trim feature on the real time clock (RTC) provides software controlled digital compensation of the 32.768 KHz input clock. This compensation is accurate to 1.24 sec/month.
Note: A real time clock must be connected to RTCXTALI or the EP9302 device will not boot.
Dual-port USB Host
The USB Open Host Controller Interface (Open HCI) provides full-speed serial communications ports at a baud rate of 12 Mbits/sec. Up to 127 USB devices (printer, mouse, camera, keyboard, etc.) and USB hubs can be connected to the USB host in the USB "tieredstar" topology. This includes the following feature: * *
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Table I. Real-Time Clock with Pin Assignments
Pin Mnemonic
RTCXTALI RTCXTALO
Pin Name - Description
Real-Time Clock Oscillator Input Real-Time Clock Oscillator Output
Compliance with the USB 2.0 specification Compliance with the Open HCI Rev 1.0 specification (c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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PLL and Clocking
The Processor and the Peripheral Clocks operate from a single 14.7456 MHz crystal. The Real Time Clock operates from a 32.768 KHz external oscillator.
Table J. PLL and Clocking Pin Assignments
*
Software supported priority mask for all FIQs and IRQs
Table K. External Interrupt Controller Pin Assignment
Pin Mnemonic
INT[3] and INT[1:0] Note:
Pin Name - Description
External Interrupts 2, 1, 0
INT[2] is not bonded out.
Pin Mnemonic
XTALI XTALO VDD_PLL GND_PLL
Pin Name - Description
Main Oscillator Input Main Oscillator Output Main Oscillator Power Main Oscillator Ground
Dual LED Drivers
Two pins are assigned specifically to drive external LEDs.
Table L. Dual LED Pin Assignments
Timers
The Watchdog Timer ensures proper operation by requiring periodic attention to prevent a reset-on-timeout. Two 16-bit timers operate as free running down-counters or as periodic timers for fixed interval interrupts and have a range of 0.03 ms to 4.27 seconds. One 32-bit timer, plus a 6-bit prescale counter, has a range of 0.03 s to 73.3 hours. One 40-bit debug timer, plus 6-bit prescale counter, has a range of 1.0 s to 12.7 days.
Pin Mnemonic
GRLED REDLED
Pin Name Description
Green LED Red LED
Alternative Usage
General Purpose I/O General Purpose I/O
General Purpose Input/Output (GPIO)
The 16 EGPIO and the 3 FGPIO pins may each be configured individually as an output, an input, or an interrupt input. There are 10 pins that may alternatively be used as input, output, or open-drain pins, but do not support interrupts. These pins are: * Ethernet MDIO * Both LED Outputs * EEPROM Clock and Data * HGPIO[5:2] * CGPIO[0] 6 pins may alternatively be used as inputs only: * CTSn, DSRn / DCDn * 3 Interrupt Lines 2 pins may alternatively be used as outputs only: * RTSn * ARSTn
Table M. General Purpose Input/Output Pin Assignment
Interrupt Controller
The interrupt controller allows up to 54 interrupts to generate an Interrupt Request (IRQ) or Fast Interrupt Request (FIQ) signal to the processor core. Thirty-two hardware priority assignments are provided for assisting IRQ vectoring, and two levels are provided for FIQ vectoring. This allows time critical interrupts to be processed in the shortest time possible. Internal interrupts may be programmed as active high or active low level sensitive inputs. GPIO pins programmed as interrupts may be programmed as active high level sensitive, active low level sensitive, rising edge triggered, falling edge triggered, or combined rising/falling edge triggered. * * * * Supports 54 interrupts from a variety of sources (such as UARTs, GPIO and ADC) Routes interrupt sources to either the ARM920T's IRQ or FIQ (Fast IRQ) inputs Three dedicated off-chip interrupt lines operate as active high level sensitive interrupts Any of the 19 GPIO lines maybe configured to generate interrupts
Pin Mnemonic
EGPIO[15:0] FGPIO[3:1]
Pin Name - Description
Expanded General Purpose Input / Output Pins with Interrupts Expanded General Purpose Input / Output Pins with Interrupts
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Reset and Power Management
The chip may be reset through the PRSTn pin or through the open drain common reset pin, RSTOn. Clocks are managed on a peripheral-by-peripheral basis and may be turned off to conserve power. The processor clock is dynamically adjustable from 0 to 200 MHz (184 MHz for industrial conditions).
Table N. Reset and Power Management Pin Assignments
12-Channel DMA Controller
The DMA module contains 12 separate DMA channels. Ten of these may be used for peripheral-to-memory or memory-to-peripheral access. Two of these are dedicated to memory-to-memory transfers. Each DMA channel is connected to the 16-bit DMA request bus. The request bus is a collection of requests, Serial Audio and UARTs. Each DMA channel can be used independently or dedicated to any request signal. For each DMA channel, source and destination addressing can be independently programmed to increment, decrement, or stay at the same value. All DMA addresses are physical, not virtual addresses.
Pin Mnemonic
PRSTn RSTOn
Pin Name - Description
Power On Reset User Reset In/Out - Open Drain - Preserves Real Time Clock value
Internal Boot ROM
The Internal 16-kbyte ROM allows booting from FLASH memory, SPI or UART. Consult the EP9301 User's Guide for operational details.
Hardware Debug Interface
The JTAG interface allows use of ARM's Multi-ICE or other in-circuit emulators.
Table O. Hardware Debug Interface
Pin Mnemonic
TCK TDI TDO TMS TRSTn
Pin Name - Description
JTAG Clock JTAG Data In JTAG Data Out JTAG Test Mode Select JTAG Port Reset
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Electrical Specifications
Absolute Maximum Ratings
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter Symbol
RVDD CVDD VDD_PLL VDD_ADC (Note 1)
Min
-
Max
3.96 2.16 2.16 3.96 2 10 50 RVDD+0.3 +125
Unit
V V V V W mA mA V C
Power Supplies
Total Power Dissipation Input Current per Pin, DC (Except supply pins) Output current per pin, DC Digital Input voltage Storage temperature
(Note 2)
-0.3 -40
Note:
1. Includes all power generated by AC and/or DC output loading. 2. The power supply pins are at maximum values listed in "Recommended Operating Conditions", below. 3. At ambient temperatures above 70 C, total power dissipation must be limited to less than 2.5 Watts.
WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Recommended Operating Conditions
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter Symbol
RVDD CVDD VDD_PLL VDD_ADC TA TA FCLK FCLK HCLK HCLK
Min
3.0 1.65 1.65 3.0 0 -40 -
Typ
3.3 1.80 1.80 3.3 +25 +25 -
Max
3.6 1.94 1.94 3.6 +70 +85 200 184 100 92
Unit
V V V V C C MHz MHz MHz MHz
Power Supplies
Operating Ambient Temperature - Commercial Operating Ambient Temperature - Industrial Processor Clock Speed - Commercial Processor Clock Speed - Industrial System Clock Speed - Commercial System Clock Speed - Industrial
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
DC Characteristics
(TA = 0 to 70 C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V; All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)
Parameter
High level output voltage Low level output voltage High level input voltage Low level input voltage High level leakage current Low level leakage current Vin = 3.3 V Vin = 0 Iout = -4 mA Iout = 4 mA (Note 5) (Note 5) (Note 5) (Note 5) (Note 4)
Symbol
Voh Vol Vih Vil Iih Iil
Min
0.85 x RVDD 0.65 x RVDD -0.3 -
Max
0.15 x RVDD VDD + 0.3 0.35 x RVDD 10 -10
Unit
V V V V A A
Parameter Power Supply Pins (Outputs Unloaded)
Power Supply Current: Low-Power Mode Supply Current CVDD / VDD_PLL Total RVDD CVDD / VDD_PLL Total RVDD
Min
Typ
Max
Unit
-
180 45 2 1.0
230 80 3.5 2
mA mA mA mA
Note:
4. For open drain pins, high level output voltage is dependent on the external load. 5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table Q on page 39). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not driven and programmed as an input, it should be tied to power or ground through its own resistor.
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Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
Clock
High to Low
High/Low to High
Bus Change
Bus Valid
Undefined/Invalid
Valid Bus to Tristate
Bus/Signal Omission
Figure 1. Timing Diagram Drawing Key
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. * TA = 0 to 70 C * CVDD = VDD_PLL = 1.8V * RVDD = 3.3 V * All grounds = 0 V * Logic 0 = 0 V, Logic 1 = 3.3 V * Output loading = 50 pF * Timing reference levels = 1.5 V * The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between 33 MHz and 100 MHz (92 MHz for industrial conditions).
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Memory Interface
Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes.
Parameter
SDCLK high time SDCLK low time SDCLK rise/fall time Signal delay from SDCLK rising edge time Signal hold from SDCLK rising edge time DQMn delay from SDCLK rising edge time DQMn hold from SDCLK rising edge time DA valid setup to SDCLK rising edge time DA valid hold from SDCLK rising edge time
Symbol
tclk_high tclk_low tclkrf td th tDQd tDQh tDAs tDAh
Min
1 1 2 3
Typ
(tHCLK) / 2 (tHCLK) / 2 2 -
Max
4 8 8 -
Unit
ns ns ns ns ns ns ns ns ns
SDRAM Load Mode Register Cycle
tclkrf SDCLK
tclk_low
tclk_high
td SDCSn
th
RASn
CASn
SDWEn
DQMn
AD
OP-Code
DA
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
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SDRAM Burst Read Cycle
tclk_low SDCLK
tclk_high
tclkrf td SDCSn th
RASn
CASn
SDWEn DQMn
CL = 2
tDQd
tDQh
tDQh DQMn
CL = 3
AD td tDAs DA
CL = 2 n
tDAh
n+1 n+2 n+3
tDAs DA
CL = 3 n
tDAh
n+1 n+2 n+3
Figure 3. SDRAM Burst Read Cycle Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
SDRAM Burst Write Cycle
tclk_low SDCLK
tclk_high
tclkrf td SDCSn th th
RASn
CASn
SDWEn
DQMn
AD
DA
n
n +1
n+2
n+3
Figure 4. SDRAM Burst Write Cycle Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
SDRAM Auto Refresh Cycle
tclk_low SDCLK
tclk_high
tclkrf td SDCSn 7 b d e th
RASn
CASn
SDWEn
Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access Figure 5. SDRAM Auto Refresh Cycle Timing Measurement
DS653PP3
(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory 32-bit Read on 8-bit External Bus
Parameter
AD setup to CSn assert time CSn assert to Address transition time Address assert time AD transition to CSn deassert time AD hold from CSn deassert time RDn assert time CSn to RDn delay time CSn assert to DQMn assert delay time DA setup to AD transition time DA setup to RDn deassert time DA hold from AD transition time DA hold from RDn deassert time
Symbol
tADs tAD1 tAD2 tAD3 tADh tRDpwL tRDd tDQMd tDAs1 tDAs2 tDAh1 tDAh2
Min
tHCLK tHCLK 15 tHCLK + 12 0 0
Typ
-
Max
3 1 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
tHCLK x (WST1 + 1) tHCLK x (WST1 + 1) tHCLK x (WST1 + 2) tHCLK x (4 x WST1 + 5) -
tADs AD
tAD1
tAD2
tAD2
tAD3
tADh
CSn
WRn RDn
tRDd tDQMd
tRDd
DQMn tDAh1 DA tDAs1 WAIT tDAs1 tDAs1 tDAs2 tDAh1
1 tDAh1
tDAh2
Figure 6. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement
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DS653PP3
EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory 32-bit Write on 8-bit External Bus
Parameter
AD setup to WRn assert time WRn/DQMn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time WRn deassert time CSn to DQMn assert delay time DQMn assert time DQMn deassert time WRn / DQMn deassert to DA transition time WRn / DQMn assert to DA valid time
Symbol
tADs tADd tADh tCSh tWRd tWRpwL tWRpwH tDQMd tDQMpwL tDQMpwH tDAh tDAV
Min
tHCLK - 3 tHCLK x 2 7 tHCLK -
Typ
tHCLK x (WST1 + 1) tHCLK x 2 tHCLK x (WST1 + 1) -
Max
tHCLK + 6 2 (tHCLK x 2) + 14 1 (tHCLK x 2) + 7 8
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
-
tADs AD
tADd
tADd
tADd
tADh
CSn tWRd WRn tWRpwH RDn tDQMd DQMn tDQMpwH tDAV DA tDAh WAIT
Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement
tWRpwL
tWRpwL tWRpwH
tWRpwL tWRpwH
tCSh
tDQMpwL
tDQMpwL tDQMpwH tDAV
tDQMpwL tDQMpwH tDAV tDAV
tDAh
tDAh
tDAh
DS653PP3
(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory 32-bit Read on 16-bit External Bus
Parameter
AD setup to CSn assert time CSn assert to AD transition time AD transition to CSn deassert time AD hold from CSn deassert time RDn assert time CSn to RDn delay time CSn assert to DQMn assert delay time DA setup to AD transition time DA to RDn deassert time DA hold from AD transition time DA hold from RDn deassert time
Symbol
tADs tADd1 tADd2 tADh tRDpwL tRDd tDQMd tDAs1 tDAs2 tDAh1 tDAh2
Min
tHCLK tHCLK 15 tHCLK + 12 0 0
Typ
tHCLK x (WST1 + 1) tHCLK x (WST1 + 2) tHCLK x ((2 x WST1) + 3) -
Max
3 1 -
Unit
ns ns ns ns ns ns ns ns ns ns ns
tADs AD
tADd1
tADd2
tADh
CSn
WRn RDn
tRDd
tRDpwl
tRDh
DQMn
tDQMd
tDQMh
tDAs1 DA
tDAh1
tDAs2
tDAh2
WAIT
Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement
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(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory 32-bit Write on 16-bit External Bus
Parameter
AD setup to WRn assert time WRn/DQMn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time WRn deassert time CSn to DQMn assert delay time DQMn assert time DQMn deassert time WRn / DQMn deassert to DA transition time WRn / DQMn assert to DA valid time
Symbol
tADs tADd tADh tCSh tWRd tWRpwL tWRpwH tDQMd tDQMpwL tDQMpwH tDAh1 tDAV
Min
tHCLK - 3 tHCLK x 2 7 tHCLK -
Typ
tHCLK x (WST1 + 1) tHCLK x (WST1 + 1) -
Max
tHCLK + 6 2 (tHCLK x 2) + 14 1 (tHCLK x 2) + 7 8
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
tADs AD
tADd
tADh
CSn tWRd WRn tWRpwL tWRpwH tWRpwL tCSh
RDn tDQMd DQMn tDAV DA tDQpwL tDQpwH tDAh tDAV tDAh tDQpwL
WAIT
Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement
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(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Burst Read Cycle
Parameter
CSn assert to Address 1 transition time Address assert time AD transition to CSn deassert time AD hold from CSn deassert time CSn to RDn delay time CSn to DQMn assert delay time DA setup to AD transition time DA setup to CSn deassert time DA hold from AD transition time DA hold from RDn deassert time Note:
Symbol
tADd1 tADd2 tADd3 tADh tRDd tDQMd tDAs1 tDAs2 tDAh1 tDAh2
Min
tHCLK 15 tHCLK + 12 0 0
Typ
tHCLK x (WST1 + 1) tHCLK x (WST2 + 1) tHCLK x (WST1 + 2) -
Max
3 1 -
Unit
ns ns ns ns ns ns ns ns ns ns
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
tADs AD
tADd1
tADd2
tADd2
tADd3
tADh
CSn
WRn tRDd RDn tDQMd
DQMn
tDAh1 DA tDAs1 WAIT tDAs1
tDAh1
tDAh1
tDAh2
tDAs1
tDAs2
Figure 10. Static Memory Burst Read Cycle Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Burst Write Cycle
Parameter
AD setup to WRn assert time AD hold from WRn deassert time WRN/DQMn deassert to AD transition time CSn hold from WRn deassert time CSn to WRn assert delay time CSn to DQMn assert delay time DQMn assert time DQMn deassert time WRn assert time WRn deassert time WRn/DQMn deassert to DA transition time WRn/DQMn assert to DA valid time Note:
Symbol
tADs tADh tADd tCSh tWRd tDQMd tDQpwL tDQpwH tWRpwL tWRpwH tDAh tDAv
Min
tHCLK - 3 tHCLK x 2
Typ
Max
Unit
ns ns
tHCLK + 6 7 2 1 tHCLK x (WST1 + 1) (tHCLK x 2) + 14 tHCLK x (WST1 + 11) (tHCLK x 2) + 7 tHCLK 8
ns ns ns ns ns ns ns ns ns ns
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
tADs
tADd
tADh
AD
CSn
tWRpwL tCSh tWRpwH
WRn
tWRd
RD
tDQMd tDQpwL tDQpwH tDAv tDAh
DQMn
DA
WAIT
Figure 11. Static Memory Burst Write Cycle Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Single Read Wait Cycle
Parameter
CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time
Symbol
tWAITd tWAITpw tCSnd
Min
tHCLK x 2 tHCLK x 3
Typ
-
Max
tHCLK x (WST1-2) tHCLK x 510 tHCLK x 5
Unit
ns ns ns
AD
CSn
WRn
RDn DQMn
DA
WAIT
tWAITd
tWAITpw
tCSnd
Figure 12. Static Memory Single Read Wait Cycle Timing Measurement
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(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Single Write Wait Cycle
Parameter
WAIT to WRn deassert delay time CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time
Symbol
tWRd tWAITd tWAITpw tCSnd
Min
tHCLK x 2 tHCLK x 2 tHCLK x 3
Typ
-
Max
tHCLK x 4 tHCLK x (WST1-2) tHCLK x 510 tHCLK x 5
Unit
ns ns ns ns
AD
CSn tWRd WRn
RDn DQMn
DA tWAITd WAIT tCSnd
tWAITpw
Figure 13. Static Memory Single Write Wait Cycle Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Turnaround Cycle
Parameter
CSnX deassert to CSnY assert time
Symbol
tBTcyc
Min
-
Typ
tHCLK x (IDCY+1)
Max
-
Unit
ns
Notes: 1. X and Y represent any two chip select numbers. 2. IDCY occurs on read-to-write and write-to-read. 3. IDCY is honored when going from a asynchronous device (CSx) to a synchronous device (/SDCSy).
tBTcyc AD
CSnX
CSnY
WRn
RDn
DQMn
DA
WAIT
Figure 14. Static Memory Turnaround Cycle Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Ethernet MAC Interface
Min Parameter Symbol 10 Mbit mode
140 140 0 140 140 10 10 160 160 10 10 -
Typ 10 Mbit mode
400 200 200 10 400 200 200 400 -
Max 10 Mbit mode
260 260 25 5 260 260 5 5 300
100 Mbit mode
14 14 0 14 14 10 10 160 160 10 10 -
100 Mbit mode
40 20 20 10 40 20 20 400 -
100 Mbit mode
26 26 25 5 26 26 5 5 300
Unit
TXCLK cycle time TXCLK high time TXCLK low time TXCLK to signal transition delay time TXCLK rise/fall time RXCLK cycle time RXCLK high time RXCLK low time RXDVAL / RXERR setup time RXDVAL / RXERR hold time RXCLK rise/fall time MDC cycle time MDC high time MDC low time MDC rise/fall time MDIO setup time (STA sourced) MDIO hold time (STA sourced) MDC to MDIO signal transition delay time (PHY sourced)
tTX_per tTX_high tTX_low tTXd tTXrf tRX_per tRX_high tRX_low tRXs tRXh tRXrf tMDC_per tMDC_high tMDC_low tMDCrf tMDIOs tMDIOh tMDIOd
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium. PHY - Ethernet physical layer interface.
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
tTX_high TXCLK TXD[3:0]/ TXEN/ TXERR tTXd tTX_per
tTX_low
tRX_low RXCLK RXD[3:0]/ RXDVAL/ RXERR tRXh tRXs tRX_per
tRX_high
MDC MDIO (Sourced by STA) tMDC_high tMDC_low tMDIOs tMDIOh
tMDC_per
MDC MDIO (Sourced by PHY)
tMDIOd
Figure 15. Ethernet MAC Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Audio Interface
The following table contains the values for the timings of each of the SPI modes.
Parameter
SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time Data from master valid delay time Data from master setup time Data from master hold time Data from slave setup time Data from slave hold time
Symbol
tclk_per tclk_high tclk_low tclkrf tDMd tDMs tDMh tDSs tDSh
Min
1 20 40 20 40
Typ
tspix_clk (tspix_clk) / 2 (tspix_clk) / 2 -
Max
8 3 -
Unit
ns ns ns ns ns ns ns ns ns
Note:
The tspix_clk is programmable by the user.
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Texas Instruments' Synchronous Serial Format
tclk_per tclk_high SCLK tclk_low SFRM SSPTXD/ SSPRXD tclkrf
MSB 4 to 16 bits
LSB
Figure 16. TI Single Transfer Timing Measurement
Microwire
tclk_high tclk_per tclkrf
SCLK
tclk_low
SFRM
SSPTXD
MSB
LSB
8-bit control SSPRXD
0 MSB LSB
4 to 16 bits output data
Figure 17. Microwire Frame Format, Single Transfer
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Motorola SPI
tclk_per tclk_high SCLK (SPO=0) tclk_low SCLK (SPO=1) tDMs SSPTXD (master) tDMd tDSs SSPRXD (slave) SFRM MSB tDSh LSB MSB tDMh LSB tclkrf
Figure 18. SPI Format with SPH=1 Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Inter-IC Sound - I2S
Parameter
SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time SCLK to LRCLK assert delay time Hold between SCLK assert then LRCLK deassert or Hold between LRCLK deassert then SCLK assert SDI to SCLK deassert setup time SDI from SCLK deassert hold time SCLK assert to SDO delay time SDO from SCLK assert hold time Note: ti2s_clk is programmable by the user.
Symbol
tclk_per tclk_high tclk_low tclkrf tLRd tLRh tSDIs tSDIh tSDOd tSDOh
Min
1 0 12 0 1
Typ
ti2s_clk (ti2s_clk) / 2 (ti2s_clk) / 2 4 -
Max
8 3 9 -
Unit
ns ns ns ns ns ns ns ns ns ns
tclk_per tclk_high SCLK tLRd LRCLK tSDIs SDI tSDOd SDO tSDOh tSDIh tLRh tclk_low tclkrf
Figure 19. Inter-IC Sound (I2S) Timing Measurement
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(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
AC'97
Parameter
ABITCLK input cycle time ABITCLK input high time ABITCLK input low time ABITCLK input rise/fall time ASDI setup to ABITCLK falling ASDI hold after ABITCLK falling ASDI input rise/fall time ABITCLK rising to ASDO / ASYNC valid, CL = 55 pF ASYNC / ASDO rise/fall time, CL = 55 pF
Symbol
tclk_per tclk_high tclk_low tclkrf ts th trfin tco trfout
Min
36 36 2 10 10 2 2 2
Typ
81.4 -
Max
45 45 6 6 15 6
Unit
ns ns ns ns ns ns ns ns ns
tclk_high tclk_per ABITCLK tclkrf tclkrf
tclk_low
th ts
trfin
ASDI
ASDO trfout tco ASYNC trfout
Figure 20. AC `97 Configuration Timing Measurement
tco tco trfout
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
ADC
Parameter
Resolution Integral non-linearity Offset error Full scale error Maximum sample rate Channel switch settling time Noise (RMS) - typical Note: ADIV = 0 ADIV = 1 ADIV = 0 ADIV = 1
Comment
No missing codes Range of 0 to 3.3 V
Value
50K counts (approximate) 0.01% 15 0.2% 3750 925 500 2 120
Units
mV
Samples per second Samples per second s ms V
ADIV refers to bit 16 in the KeyTchClkDiv register. ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4. ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.
61A8
0000 FFFF
9E58 0 Vref/2 Vref
A/D Converter Transfer Function (approximately 25,000 counts)
Figure 21. ADC Transfer Function
Using the ADC: This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay between each successful conversion and the issue of the next conversion command, or else the returned value of successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion. Note that reading TSXYResult during a conversion will not affect the result of the ongoing process. The following is a recommended procedure for safely polling the ADC from software: 1. Read the TSXYResult register into a local variable to initiate a conversion. 2. If the value of bit 31 of the local variable is '0' then repeat step 1. 3. Delay long enough to meet the maximum sample rate as shown above. 4. Mask the local variable with 0xFFFF to remove extraneous data. 5. If signed mode is used, do a sign extend of the lower halfword. 6. Return the sampled value.
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(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
JTAG
Parameter
TCK clock period TCK clock high time TCK clock low time TMS / TDI to clock rising setup time Clock rising to TMS / TDI hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance
Symbol
tclk_per tclk_high tclk_low tJPs tJPh tJPco tJPzx tJPxz
Min
100 50 50 20 45 -
Max
30 30 30
Units
ns ns ns ns ns ns ns ns
TMS
TDI tclk_per tclk_high TCK tJPzx TDO tJPco tJPxz tclk_low tJPs tJPh
Figure 22. JTAG Timing Measurement
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
208 Pin LQFP Package Outline
2.19 208-Pin LQFP (28 x 28 x 1.40-mm Body)
29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011)
27.80 (1.094) 28.20 (1.110)
29.60 (1.165) 30.40 (1.197)
0.50 (0.0197) BSC
Pin 1 Indicator
Pin 208 Pin 1
0.45 (0.018) 0.75 (0.030)
1.35 (0.053) 1.45 (0.057)
1.00 (0.039) BSC
0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 1.60 (0.063) 0.05 (0.002) 0.15 (0.006)
0 MIN 7 MAX
NOTES: 1) Dimensions are in millimeters, and controlling dimension is millimeter. 2) Package body dimensions do not include mold protrusion, which is 0.25 mm (0.010 in). 3) Pin 1 identification may be either ink dot or dimple. 4) Package top dimensions can be smaller than bottom dimensions by 0.20 mm (0.008 in). 5) The `lead width with plating' dimension does not include a total allowable dambar protrusion of 0.08 mm (at maximum material condition). 6) Ejector pin marks in molding are present on every package. 7) Drawing above does not reflect exact package pin count.
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(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
208 Pin LQFP Pinout
The following table shows the 208 pin LQFP pinout. * VDD_core is CVDD. * VDD_ring is RVDD. * NC means that the pin is not connected.
Pin List
The following Low-Profile Quad Flat Pack (LQFP) pin assignment table is sorted in order of pin.
Table P. Pin List in Numerical Order by Pin Number
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Pin Name
CSn[7] CSn[6] CSn[3] CSn[2] CSn[1] AD[25] vdd_ring gnd_ring AD[24] SDCLK AD[23] vdd_core gnd_core SDWEn SDCSn[3] SDCSn[2] SDCSn[1] SDCSn[0] vdd_ring gnd_ring RASn CASn DQMn[1] DQMn[0] AD[22] AD[21] vdd_ring gnd_ring DA[15] AD[7] DA[14] AD[6] DA[13] vdd_core gnd_core
Pin Number
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Pin Name
AD[5] DA[12] AD[4] DA[11] AD[3] vdd_ring gnd_ring DA[10] AD[2] DA[9] AD[1] DA[8] AD[0] vdd_ring gnd_ring NC NC vdd_ring gnd_ring AD[15] DA[7] vdd_core gnd_core AD[14] DA[6] AD[13] DA[5] AD[12] DA[4] AD[11] vdd_ring gnd_ring DA[3] AD[10] DA[2]
Pin Number
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
Pin Name
AD[9] DA[1] AD[8] DA[0] DSRn DTRn TCK TDI TDO TMS vdd_ring gnd_ring BOOT[1] BOOT[0] gnd_ring NC EECLK EEDAT ASYNC vdd_core gnd_core ASDO SCLK1 SFRM1 SSPRX1 SSPTX1 GRLED RDLED vdd_ring gnd_ring INT[3] INT[1] INT[0] RTSn USBm[0]
Pin Number
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
Pin Name
USBp[0] ABITCLK CTSn RXD[0] RXD[1] vdd_ring gnd_ring TXD[0] TXD[1] CGPIO[0] gnd_core PLL_GND XTALI XTALO PLL_VDD vdd_core gnd_ring vdd_ring RSTOn PRSTn CSn[0] gnd_core vdd_core gnd_ring vdd_ring ADC[4] ADC[3] ADC[2] ADC[1] ADC[0] ADC_VDD RTCXTALI RTCXTALO ADC_GND EGPIO[11]
Pin Number
141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
Pin Name
EGPIO[10] EGPIO[9] EGPIO[8] EGPIO[7] EGPIO[6] EGPIO[5] EGPIO[4] EGPIO[3] gnd_ring vdd_ring EGPIO[2] EGPIO[1] EGPIO[0] ARSTn TRSTn ASDI USBm[2] USBp[2] WAITn EGPIO[15] gnd_ring vdd_ring EGPIO[14] EGPIO[13] EGPIO[12] gnd_core vdd_core FGPIO[3] FGPIO[2] FGPIO[1] gnd_ring vdd_ring CLD CRS TXERR
Pin Number
176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Pin Name
TXEN MIITXD[0] MIITXD[1] MIITXD[2] MIITXD[3] TXCLK RXERR RXDVAL MIIRXD[0] MIIRXD[1] MIIRXD[2] gnd_ring vdd_ring MIIRXD[3] RXCLK MDIO MDC RDn WRn AD[16] AD[17] gnd_core vdd_core HGPIO[2] HGPIO[3] HGPIO[4] HGPIO[5] gnd_ring vdd_ring AD[18] AD[19] AD[20] SDCLKEN
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(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
The following section focuses on the EP9302 pin signals from two viewpoints - the pin usage and pad characteristics, and the pin multiplexing usage. The first table (Table Q) is a summary of all the EP9302 pin signals. The second table (Table R) illustrates the pin signal multiplexing and configuration options. Table Q is a summary of the EP9302 pin signals, which illustrates the pad type and pad pull type (if any). The symbols used in the table are defined as follows. (Note: A blank box means Not Applicable (NA) or, for Pull Type, No Pull (NP).)
Under the Pad Type column: * A - Analog pad * P - Power pad * G - Ground pad * I - Pin is an input only * I/O - Pin is input/output * 4mA - Pin is a 4mA output driver * 8mA - Pin is an 8mA output driver * 12mA - Pin is an 12mA output driver See the text description for additional information about bi-directional pins. Under the Pull Type Column: * * PU - Resistor is a pull up to the RVDD supply PD - Resistor is a pull down to the RGND supply
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(c)Copyright 2005 Cirrus Logic (All Rights Reserved)
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
.
Table Q. Pin Descriptions
Pin Name Block Pad Type I I 4ma I I I A A P G A A 4ma 4ma I 8ma 8ma 4ma 4ma 8ma 8ma 8ma 4ma 8ma 8ma 8ma A P G A A 4ma I I I 4ma 4ma 4ma I PU PU PU PU PU PU PU PU PD PD PD Pull Type PD PD JTAG clock in JTAG data in JTAG data out JTAG test mode select JTAG reset Boot mode select in Main oscillator input Main oscillator output Main oscillator power, 1.8V Main oscillator ground RTC oscillator input RTC oscillator output SRAM Write strobe out SRAM Read / OE strobe out SRAM Wait in Shared Address bus out Shared Data bus in/out Chip select out Chip select out Shared data mask out SDRAM clock out SDRAM clock enable out SDRAM chip selects out SDRAM RAS out SDRAM CAS out SDRAM write enable out External Analog Measurement Input ADC power, 3.3V ADC ground USB positive signals USB negative signals Transmit out Receive in Clear to send / transmit enable Data set ready / Data Carrier Detect Data Terminal Ready output Ready to send Transmit / IrDA output Receive / IrDA input Description Pin Name
Table Q. Pin Descriptions (Continued)
Block Pad Type 4ma 4ma I I I I I I 4ma 4ma I I 12ma 12ma 4ma 4ma 8ma 8ma I 8ma 8ma 8ma 8ma I 8ma I I 4ma 4ma I/O, 4ma I/O, 8ma I/O, 8ma I/O, 8ma P P G G PU PU PU PU PD PU PD PD PD PU PU PD PD PD PU PU PD PD PD PD PU PD PD PD PD PU Pull Type Description
TCK TDI TDO TMS TRSTn BOOT[1:0] XTALI XTALO VDD_PLL GND_PLL RTCXTALI RTCXTALO WRn RDn WAITn AD[25:0] DA[15:0] CSn[3:0] CSn[7:6] DQMn[1:0] SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn ADC[4:0] VDD_ADC GND_ADC USBp[2, 0] USBm[2, 0] TXD0 RXD0 CTSn DSRn DTRn RTSn TXD1 RXD1
JTAG JTAG JTAG JTAG JTAG System PLL PLL PLL PLL RTC RTC EBUS EBUS EBUS EBUS EBUS EBUS EBUS EBUS SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM ADC ADC ADC USB USB UART1 UART1 UART1 UART1 UART1 UART1 UART2 UART2
MDC MDIO RXCLK MIIRXD[3:0] RXDVAL RXERR TXCLK MIITXD[3:0] TXEN TXERR CRS CLD GRLED RDLED EECLK EEDAT ABITCLK ASYNC ASDI ASDO ARSTn SCLK1 SFRM1 SSPRX1 SSPTX1 INT[3], INT[1:0] PRSTn RSTOn SLA[1:0] EGPIO[15:0] FGPIO[3:1] HGPIO[5:2] CGPIO[0] CVDD RVDD CGND RGND
EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC LED LED EEPROM EEPROM AC97 AC97 AC97 AC97 AC97 SPI1 SPI1 SPI1 SPI1 INT Syscon Syscon EEPROM GPIO GPIO GPIO GPIO Power Power Ground Ground
Management data clock Management data input/output Receive clock in Receive data in Receive data valid Receive data error Transmit clock in Transmit data out Transmit enable Transmit error Carrier sense Collision detect Green LED Red LED EEPROM / Two-wire Interface clock EEPROM / Two-wire Interface data AC97 bit clock AC97 frame sync AC97 Primary input AC97 output AC97 reset SPI bit clock SPI Frame Clock SPI input SPI output External interrupts Power on reset User Reset in out - open drain Flash programming voltage control Enhanced GPIO GPIO on Port F GPIO on Port H GPIO on Port C Digital power, 1.8V Digital power, 3.3V Digital ground Digital ground
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Table R illustrates the pin signal multiplexing and configuration options.
Table R. Pin Multiplex Usage Information
Physical Pin Name
EGPIO[0] EGPIO[1] EGPIO[3] EGPIO[4] EGPIO[5] EGPIO[6] EGPIO[7] EGPIO[8] EGPIO[9] EGPIO[10] EGPIO[11] EGPIO[12] EGPIO[13] EGPIO[14] EGPIO[15] ABITCLK ASYNC ASDO ASDI ARSTn SCLK1 SFRM1 SSPTX1 SSPRX1
Description
Ring Indicator Input 1Hz clock monitor HDLC Clock I2S Transmit Data 1 I2S Receive Data 1 I2S Transmit Data 2 DMA Request 0 DMA Acknowledge 0 DMA EOT 0 DMA Request 1 DMA Acknowledge 1 DMA EOT 1 I2S Receive Data 2 PWM1 Output Device active / present I2S Serial clock I2S Frame Clock I2S Transmit Data 0 I2S Receive Data 0 I2S Master clock I2S Serial clock I2S Frame Clock I2S Transmit Data 0 I2S Receive Data 0
Multiplex signal name
RI CLK1HZ HDLCCLK1 SDO1 SDI1 SDO2 DREQ0 DACK0 DEOT0 DREQ1 DACK1 DEOT1 SDI2 PWMOUT1 DASP SCLK LRCK SDO0 SDI0 MCLK SCLK LRCK SDO0 SDI0
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DS653PP3
EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Acronyms and Abbreviations
The following tables list abbreviations and acronyms used in this data sheet.
Term
ADC ALT AMBA ATAPI CODEC CRC DAC DMA EBUS
Term
OHCI PHY
Definition
Open Host Controller Interface Ethernet PHYsical layer interface Programmed I/O Reduced Instruction Set Computer Secure Digital Music Initiative Synchronous Dynamic RAM Serial Peripheral Interface Static Random Access Memory Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium Thin Film Transistor Translation Lookaside Buffer Universal Serial Bus
Definition
PIO Analog-to-Digital Converter RISC Alternative SDMI Advanced Micro-controller Bus Architecture SDRAM ATA Packet Interface SPI COder / DECoder SRAM Cyclic Redundancy Check Digital-to-Analog Converter Direct-Memory Access TFT External Memory Bus TLB STA
EEPROM Electronically Erasable Programmable Read Only Memory USB EMAC FIFO FIQ FLASH GPIO HDLC I/F I2 S IC ICE IDE IEEE IrDA IRQ ISO JTAG LFSR MII MMU Ethernet Media Access Controller First In / First Out Fast Interrupt Request Flash memory General Purpose I/O High-level Data Link Control Interface Inter-IC Sound kHz Integrated Circuit In-Circuit Emulator Integrated Drive Electronics Institute of Electronics and Electrical Engineers Infrared Data Association Standard Interrupt Request International Standards Organization Joint Test Action Group Linear Feedback Shift Register Media-independent Interface Memory Management Unit Mbps MHz A s mA ms mW ns pF V W kiloHertz = 1000 Hz Megabits per second MegaHertz = 1,000 KiloHertz microAmpere = 10-6 Ampere microsecond = 1,000 nanoseconds = 10-6 seconds milliAmpere = 10-3 Ampere millisecond = 1,000 microseconds = 10-3 seconds milliWatt = 10-3 Watts nanosecond = 10-9 seconds picoFarad = 10-12 Farads Volt Watt
Units of Measurement
Symbol Unit of Measure
degree Celsius Hertz = cycle per second kilobits per second kilobyte
C
Hz kbps kbyte
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EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch
Ordering Information
The order numbers for the device are: EP9302-CQ EP9302-CQZ EP9302-IQ EP9302-IQZ 0C to +70C 0C to +70C -40C to +85C -40C to +85C 208-pin LQFP 208-pin LQFP 208-pin LQFP 208-pin LQFP
Lead Free Lead Free
EP9302 -- CQZ
Lead Material: Z = Lead Free Part Number Product Line: Embedded Processor Package Type: Q = 208 pin, Low Profile Quad Flat Pack (28 mm x 28 mm) Temperature Range: C = Commercial E = Extended Operating Version I = Industrial Operating Version
Note:
Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation. Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola and SPI are registered trademarks of Motorola, Inc. LINUX is a registered trademark of Linus Torvalds.
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