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IS61LV2568
FEATURES
256K x 8 HIGH-SPEED CMOS STATIC RAM
High-speed access times: 8, 10, 12 and 15 ns High-preformance, lower-power CMOS process Multiple center power and ground pins for greater noise immunity Easy memory expansion with CE and OE options CE power-down CMOS power: 540 mW @ 10 ns 36 mW standby mode TTL compatible inputs and outputs Single 3.3V + 10% power supply Packages available: 36-pin 400mil SOJ 44-pin TSOP-2
262,144-word by 8-bit COMS static RAM. The IS61LV2568 is fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher preformance and low power consumotion devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 36 mW (max.) with CMOS input levels. The IS61LV2568 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV2568 is available in 36-pin, 400mil SOJ and 44-pin TSOP-2 package.
DESCRIPTION The 1+51 IS61LV2568 is a very high-speed, low power,
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K X 8 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE OE WE CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution, Inc.
Integrated Circuit Solution, Inc.
SR026-0C
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IS61LV2568
PIN CONFIGURATION
36-Pin SOJ
A4 A3 A2 A1 A0 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A5 A6 A7 A8 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A9 A10 A11 A12 NC NC
PIN CONFIGURATION
44-Pin TSOP-2
NC NC A4 A3 A2 A1 A0 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A17 A16 A15 A14 A13 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC NC NC A5 A6 A7 A8 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A9 A10 A11 A12 NC NC NC NC
PIN DESCRIPTIONS
A0-A17 CE OE WE I/O0-I/O7 Vcc GND NC Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output Power Ground No Connection
TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB, ISB ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM TBIAS TSTG PD IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value Unit 0.5 to +4.6 V 0.5 to Vcc + 0.5 V 10 to +85 C 45 to +90 65 to +150 C 1 W 20 mA
Com. Ind.
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Integrated Circuit Solution, Inc.
SR026-0C
IS61LV2568
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C 40C to +85C VCC 3.3V + 10% 3.3V + 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VCC = Min., IOH = 4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 2.0 0.3 1 5 1 5 Max. 0.4 VCC + 0.3 0.8 1 5 1 5 Unit V V V V A A
Notes: 1. VIL (min.) = 0.3V (DC); VIL (min.) = 2.0V (pulse width 2.0 ns). VIH (max.) = VCC + 0.3V (DC); VIH (max.) = Vcc + 2.0V (pulse width 2.0 ns). 2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Sym. ICC ISB Parameter Test Conditions Com. Ind. Com. Ind. Com. Ind. -8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max. Unit
Vcc Dynamic Operating VCC = Max., CE = VIL Supply Current IOUT = 0 mA, f = fMAX TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE VIH, f = 0

170 180 30 40 10 15

150 160 30 40 10 15

140 150 30 40 10 15

130 140 30 40 10 15
mA mA
ISB
CMOS Standby VCC = Max., Current (CMOS Inputs) CE VCC 0.2V, VIN > VCC 0.2V, or VIN 0.2V, f = 0
mA
Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V.
Integrated Circuit Solution, Inc.
SR026-0C
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IS61LV2568
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time
Min. Max.
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Unit
tRC tAA tOHA tACE tDOE tHZOE tLZCE
8 3 0 0 3 0
8 8 3 3 3
10 3 0 0 3 0
10 10 4 4 4
12 3 0 0 3 0
12 12 5 5 5
15 3 0 0 3 0
15 15 6 6 6
ns ns ns ns ns ns ns ns ns
tLZOE OE to Low-Z Output
OE to High-Z Output CE to Low-Z Output
tHZCE CE to High-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
Notes: 1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
319 3.3V
3.3V 319
OUTPUT 30 pF Including jig and scope 353
OUTPUT 5 pF Including jig and scope 353
Figure 1. 4
Figure 2. Integrated Circuit Solution, Inc.
SR026-0C
IS61LV2568
AC WAVEFORMS READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
OE
t OHA
t DOE
CE
t HZOE
t LZOE t ACE t LZCE t HZCE
DATA VALID
DOUT
HIGH-Z
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Circuit Solution, Inc.
SR026-0C
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IS61LV2568
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time
"
Min.
-8 ns
Max.
Min.
-10 ns
Max.
Min.
-12 ns
Max.
Min.
-15 ns
Max.
Unit
tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE
!
8 7 7 0 0 7 4.5 0 0
3
10 8 8 0 0 8 5 0 0
4
12 9 9 0 0 9 6 0 0
5
15 10 10 0 0 10 7 0 0
6
ns ns ns ns ns ns ns ns ns ns
WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low-Z Output
tHZWE! WE LOW to High-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 4.Tested with OE Hith.
AC WAVEFORMS WRITE CYCLE NO. 1 (1,2 )(CE Controlled, OE is HIGH or LOW)
t WC
ADDRESS
VALID ADDRESS
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t HZWE t LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t SD
DIN
t HD
DATAIN VALID
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Integrated Circuit Solution, Inc.
SR026-0C
IS61LV2568
WRITE CYCLE NO. 2(WE Controlled, OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW t PWE1
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE CE
LOW
t HA
LOW
t AW t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH.
Integrated Circuit Solution, Inc.
SR026-0C
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IS61LV2568
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 8 10 12 15 Order Part No. IS61LV2568-8T IS61LV2568-8K IS61LV2568-10T IS61LV2568-10K IS61LV2568-12T IS61LV2568-12K IS61LV2568-15T IS61LV2568-15K Package 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ
ORDERING INFORMATION Industrial Range: 40C to +85C
Speed (ns) 8 10 12 15 Order Part No. IS61LV2568-8TI IS61LV2568-8KI IS61LV2568-10TI IS61LV2568-10KI IS61LV2568-12TI IS61LV2568-12KI IS61LV2568-15TI IS61LV2568-15KI Package 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000
Integrated Circuit Solution, Inc.
BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
8 Integrated Circuit Solution, Inc.
SR026-0C

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