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TOSHIBA
TLCS-90 Series CMOS 8-Bit Microcontrollers TMP90P802AP/TMP90P802AM
1. Outline and Characteristics The TMP90P802A is a system evaluation LSI having a built in One-Time PROM for TMP90C802A.
TMP90P802A
A programming and verification for internal PROM is achieved by using a general EPROM programmer with an adapter socket. The function of this device is exactly same as the TMP90C802A by programming to the internal PROM. The following are the memory map of TMP91C640 and TMP90C840A.
Parts No.
TMP90P802AP TMP90P802AM
ROM
OTP 8192 x 8bit
RAM
256 x 8bit
Package
40-DIP 40-DIP
Adapter Socket No.
BM1158 BM1159
The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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Figure 1. TMP90C802A Block Diagram
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2. Pin Assignment and Functions
The assignment of input/output pins, their names and functions are described below.
2.1 Pin Assignment Figure 2.1 (1) shows pin assignment of the TMP90P802A.
Figure 2.1 (1). Pin Assignment
Figure 2.1 (2) shows pin assignment of the TMP90P802A.
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2.2 Pin Names and Functions The TMP90P802A has MCU mode and PROM mode. (1) MCU Mode (The TMP90P802A and the TMP90C802A are pin compatible).
Table 2.2 Pin Names and Functions
Pin Name
P00 ~ P07 /D0 ~ D7 P10 ~ P17 /A0 ~ A7 P20 ~ P27 /A8 ~ A 15 P31 /RxD P32 /TxD /RTS /SCLK P33 /TxD P35 /RD P36 /WR P37 /WAIT
No. of pins
8
I/O 3 states
I/O
Function
Port 0: 8-bit I/O port that allows selection of input/output on byte basis Data Bus: Also functions as 8-bit bidirectional data bus for external memory Port 1: 8-bit I/O port that allows selection on byte basis Addrress Bus: The lower 8 bits address bus for external memory Port 2: 8-bit I/O port that allows selection on byte basis Addrress Bus: The uppper 8 bits address bus for external memory Port 31: 1-bit input port Receives serial data Port 32: 1-bit output port
3 states
I/O
8
Output
I/O
8
Output
Input
1
1
Output
Serial clock output
1
Output
Port 33: 1-bit output port Transmits serial data Port 35: 1-bit output port Read: Generates strobe signal for reading external memory Port 36: 1-bit output port Writes: Generates strobe signal for writing external memory Port 37: 1-bit input port Wait: Input pin for connecting slow speed memory or peripheral LSI Port 80: 1-bit input port
1
Output
1
Output
1
Input
P80 /INTO
1
Input
Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable)
Port 81: 1-bit input port P81 /INT1 /TI4 Interrupt request pin 1: Interrupt request pin (Rising/falling edge is programmable) 1 Input Timer input 4: Counter/capture trigger signal for Timer 4 Non-maskable interrupt request pin: Falling edge interrupt request pin NMI CLK EA RESET X1/X2 VCC VSS (GND) 1 1 1 1 2 1 1 Input Output Input Input Input/ Output - - Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is Pulled up internally during resetting. Connects with VCC pin . Reset: Initializes the TMP90P802A (Built-in pull-up resistor) Pin for quartz crystal or ceramic resonator (1 ~ 12.5MHz) Power supply (+5V) Ground (0V)
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2) PROM Mode Table 2.2.2
Pin Function Name
A7 ~ A0 A12 ~ A8 A15 ~ A13 D7 ~ D0 OE CE VPP VCC VSS
No. of pins
8 5 3 8 1 1 1 1 1
I/O
Input Input Input I/0 Input Input Power Supply Power Supply Power Supply Address Input Be fixed to "L" level. Data Input/Output Output Enable Input Chip Enable Input
Function
Pin Name (MCU mode)
P17 ~ P10 P24 ~ P20 P27 ~ P25 P07 ~ P00 P35 P36 EA
12.5V/5V (Programming Power Supply) 5V 0V
Pin Name
P31 P32 ~ P34 P37 P80 , P81 NMI RESET CLK X1 X2
No. of pins
1 3 1 2 1 1 1 1 1
I/O
Input Output Input Input Input Input Input Input Output Be fixed level. Open Be fixed level. Be fixed to "H" level. Be fixed to level. Be fixed to "L" level. Be fixed to "L" level. Resonator connection pin
Pin Setting
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3. Operation
The TMP90P802A is the OTP version of the TMP90C802A that is replaced an internal ROM from Mask ROM to EPROM. The function of TMP90P802A is exactly same as that of TMP90C840A. Refer to the TMP90C802A except the functions which are not described this section. The following is an explanation of the hardware configuration and operation in the relation to the TMP90P802A. The TMP90P802A has an MCU mode and a PROM mode.
3.1 MCU Mode (1) Mode Setting and Function The MCU mode is set by opening the CLK pin (Output status). In the MCU mode, the operation is the same as that of TMP90C802A. (2) Memory Map Figure 3.1 shows the memory map of TMP90P802A, and the accessing area by the respective addressing mode.
Figure 3.1. TMP90P802A Memory Map
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3.2 PROM Mode (1) Mode Setting and Function PROM mode is set by setting the RESET and CLK pins to the "L" level. The programming and verification for the internal PROM is achieved by using a general PROM programmer with the adaptor socket. The device selection (ROM Type) should be "27256" with following conditions. size : 256Kbit (32K x 8-bit) VPP: 12.5V TPW: 1ms Figure 3.2 shows the setting of pins in PROM mode.
Figure 3.2. PROM Mode Pin Setting
(2)
Programming Flow Chart The programming mode is set by applying 12.5V (programming voltage) to the VPP pin when the following pins are set as follows, (Vcc : 6.0V) *These conditions can be (RESET : "L" level) obtained by using adaptor (CLK : "L" level) socket. After the address and data have been fixed, a data on the Data Bus is programmed when the CE pin is set to "Low" (1ms plus is required). General Programming procedure of an EPROM programmer is as follows,
* Write a data to a specified address for 1ms. * Verify the data. If the read-out data does not match the expected data, another writing is performed until the correct data is written (Max. 25 times). After the correct data is written, an additional writing is performed by using three times longer programming pulse width (1ms x programming times), or using three times more programming pulse number. Then, verify the data and increment the address. The verification for all data is done under the condition of Vpp = Vcc = 5V after all data were written. Figure 3.3 shows the programming flow chart.
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Figure 3.3. Flow Chart (3) The Mode Bit and the Security Bit The TMP90P802A has the Security Bit in PROM cell. If the Sercuity Bit is programmed to "0", the content of the PROM is disable to read in PROM mode. How to Program the Security Bit. 1) Connect A15 pins to VCC. [Otherwise connect them to GND to program PROM] 2) Set programming address to 0000H. 3) To program the Security Bit, set D0 to "0". 4) Set D2 ~ D7 to "1" respectively. The following table shows the 8-bit data to program The Security Bit. Table 3.1 Data to Program
Bit to Program
The Security Bit PROM (0000H ~ 1FFFH)
D0 ~ D7
FEH -
A0 ~ A12
All "0" -
A13, A14, A15
A13, A14 = "0" A15 = "1" All "0"
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4. Electrical Characteristics
TMP90P802AP/TMP90P802AM 4.1 Absolute Maximum Ratings
Symbol
VCC VIN PD TSOLDER TSTG TOPR Supply voltage Input voltage Power dissipation (Ta = 85C) Soldering temperature (10s) Storage temperature Operating temperature
Parameter
Rating
-0.5 ~ + 7 -0.5 ~ VCC + 0.5 F 500 N 600 260 -65 ~ 150 -40 ~ 85
Unit
V V mW C C C
4.2 DC Characteristics
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) TA = -20 ~ 70 (1 ~ 16MHz) Symbol
VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH4 VOL VOH VOH1 VOH2 IDAR ILI ILO Input Low Voltage (P0) P1, P2, P3, P8 RESET, INT0, NMI EA X1 Input Low Voltage (D0 ~ D7) P1, P2, P3, P8 RESET, INT0, NMI X1 Output Low Voltage Output High Voltage Darlington Drive Current (8 I/O pins) Input Leakage Current Output Leakage Current Operating Current (RUN) Idle 1 Idle 2 STOP (TA = -20 ~ 70C) STOP (TA = 0 ~ 50C) VSTOP RRST CIO VTH Power Down Voltage (@STOP) RESET Pull Up Register Pin Capacitance Schmitt width RESET, NMI, INT0
Parameter
Min
-0.3 -0.3 -0.3 -0.3 -0.3 2.2 0.7VCC 0.75VCC 0.8VCC - 2.4 0.75VCC 0.9VCC -1.0 0.02 (Typ) 0.05 (Typ) 17 (Typ) 1.5 (Typ) 6 (Typ) 0.2 (Typ) 2 RAM BACK UP 50 - 0.4
Max
0.8 0.3VCC 0.25VCC 0.3 0.2VCC VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.45 -
Unit
V V V V V V V V V V V V V mA A A mA mA mA A A K K pF V
Test Conditions
- - - - - - - - - IOL = 1.6mA IOH = -400A IOH = -100A IOH = -20A VEXT = 1.5V REXT = 1.1k 0.0 Vin VCC 0.2 Vin VCC - 0.2 tosc = 10MHz (25% Up @ 12.5MHz) 0.2 Vin VCC - 0.2 VIL2 = 0.2VCC, VIH2 = 0.8VCC - testfreq = 1MHz -
-3.5 5 10 30 5 15 50 10 6 150 10 1.0 (Typ)
ICC
Note: IDAR is guaranteed for a total of up to 8 optional ports.
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4.3 AC Characteristics
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70C (1 ~ 16MHz) Variable Symbol
tOSC tCYC tWL tWH tAC tRR tCA tAD tRD tHR tWW tDW tWD tCWA tAWA tWAS tWAH tRV tCPW tPRC tCPR tCHCL tCLC tCLHA tACL tCLD OSC. Period = x CLK Period CLK Low width CLK High width Address Setup to RD, WR RD Low width Address Hold Time After RD, WR Address to Valid Data In RD to Valid Data In Input Data Hold After RD WR Low width Data Setup to WR Data Hold After WR RD, WR to Valid WAIT Address to Valid WAIT WAIT Setup to CLK WAIT Hold After CLK RD/WR Recovery Time CLK to Port Data Output Port Data Setup to CLK Port Data Hold After CLK RD/WR Hold After CLK RD/WR Setup to CLK Address Hold After CLK Address Setup to CLK Data Setup to CLK
10MHz Clock Max
1000 4x - - - - -
12.5MHz Clock Unit Min
80 320 120 120 35 160 10 - - 0 160 110 20 - - 70 0 85 - 200 100 20 70 40 120 30
Parameter Min
80 4x 2x - 40 2x - 40 x - 45 2.5x - 40 0.5x - 30 - - 0 2.5x - 40 2x - 50 20 - - 70 0 1.5x - 35 - 200 100 x - 60 1.5x - 50 1.5x - 80 2.5x - 80 x - 50
Min
100 400 160 160 55 210 20 - - 0 210 150 20 - - 70 0 115 - 200 100 40 100 70 170 50
Max
- - - - - - - 255 170 - - - 90 50 120 - - - 300 - - - - - - -
Max
- - - - - - - 185 120 - - - 90 20 70 - - - 260 - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3.5x - 95 2.5x - 80 - - - 90 1.5x - 100 2.5x - 130 - - - x + 200 - - - - - - -
* AC output level High 2.2V/Low 0.8V * AC input level High 2.4V/Low 0.45V (D0 - D7) High 0.8VCC/Low 0.2VCC (excluding D0 - D7)
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4.4 Zero - Cross Characteristics
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) TA = -20 ~ 70C (1 ~ 12.5MHz) Symbol
VZX AZX FZX
Parameter
Zero-cross detection input Zero-cross accuracy Zero-cross detection input frequency
Condition
AC coupling C = 0.1F 50/60Hz sine wave -
Min
1 - 0.04
Max
1.8 135 1
Unit
VAC p - p mV KHz
4.5 Serial Channel Timing - I/O Interface Mode
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70C (1 ~ 12.5MHz) Variable Symbol
tSCY tOSS tOHS tHSR tSRD
10MHz Clock Max
- - - -
12.5MHz Clock Unit Min
640 330 40 0 -
Parameter Min
Serial Port Clock Cycle Time Output Data Setup SCLK Rising Edge Output Data Hold After SCLK Rising Edge Input Data Hold After SCLK Rising Edge SCLK Rising Edge to Input DATA Valid 8x 6x - 150 2x - 120 0 -
Min
800 450 80 0 -
Max
- - - - 450
Max
- - - - 330 ns ns ns ns ns
6x - 150
4.6 8-bit Event Counter
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70C (1 ~ 12.5MHz) Variable Symbol
tVCK tVCKL tVCKH TI4 clock cycle TI4 Low clock pulse width TI4 High clock pulse width
10MHz Clock Max
- - -
12.5MHz Clock Unit Min
740 360 360
Parameter Min
8x + 100 4x + 40 4x + 40
Min
900 440 440
Max
- - -
Max
- - - ns ns ns
4.7 Interrupt Operation
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70C (1 ~ 12.5MHz) Variable Symbol Parameter Min
NMI, INT0 Low level pulse width tINTAL NMI, INT0 High level pulse width 4x - 400 - 320 - ns
10MHz Clock Max Min Max
12.5MHz Clock Unit Min Max
tINTAH
4x
-
400
-
320
-
ns
INT1, INT2 Low level pulse width tINTBL INT1, INT2 High level pulse width tINTBH 8x + 100 - 900 - 740 - ns 8x + 100 - 900 - 740 - ns
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4.8 Read Operation (PROM Mode) DC Characteristic, AC Characterisc
TA = -40 ~ 85C Vcc = 5V 10% Symbol
VPP VIH1 VIL1 tACC
Parameter
VPP Read Voltage Input High Voltage (A0 ~ A15, CE, OE) Input Low Voltage (A ~ A15, CE, OE) Address to Output Delay
Condition
- - - CL = 50pf
Min
4.5 0.7 x VCC -0.3 2.25TCYC +
Max
5.5 Vcc + 0.3 0.3 x VCC
Unit
V V V ns
TCYC = 400ns (10MHz Clock) = 200ns
4.9 Programming Operation (PROM Mode) DC Characteristic, AC Characteristic
TA = 25 5C Vcc = 6V 0.25V Symbol
VPP VIH VIL VIH1 VIL1 ICC IPP
Parameter
Programming Voltage Input High Voltage (D0 ~ D7) Input Low Voltage (D0 ~ D7) Input High Voltage (A0 ~ A15, CE, OE) Input Low Voltage (A0 ~ A15, CE, OE) VCC Supply Current VPP Supply Current CE Programming Pulse Width
Condition
- - - - - tOSC = 10MHz VPP = 13.00V CL = 50PF
Min
12.25 0.2VCC + 1.1 -0.3 0.7VCC -0.3 - - 0.95
Typ
12.50
Max
12.75 VCC + 0.3 0.2VCC - 0.1 VCC + 0.3 0.3VCC 50 50 1.05
Unit
V V V V V mA mA ms
tPW
1.00
4.10 I/O Interface Mode Timing
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4.11 Timing Chart
4.12 Read Operation Timing Chart (PROM Mode)
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4.13 Programming Operation Timing Chart (PROM Mode)
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