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| User's Manual PD789104A, 789114A, 789124A, 789134A Subseries 8-bit Single-chip Microcontrollers PD789101A PD789102A PD789104A PD789111A PD789112A PD789114A PD78F9116A PD789101A(A) PD789102A(A) PD789104A(A) PD789111A(A) PD789112A(A) PD789114A(A) PD789121A PD789122A PD789124A PD789131A PD789132A PD789134A PD78F9136A PD789121A(A) PD789122A(A) PD789124A(A) PD789131A(A) PD789132A(A) PD789134A(A) Document No. U14643EJ1V0UM00 (1st edition) Date Published June 2000 NS CP(K) (c) Printed in Japan 2000 [MEMO] 2 User's Manual U14643EJ1V0UM00 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun-Microsystems, Inc. OSF/Motif is a trademark of Open Software Foundation, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. TRON is an abbreviation of The Realtime Operating System Nucleus. ITRON is an abbreviation of Industrial TRON. User's Manual U14643EJ1V0UM00 3 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. Licence not needed: PD78F9116A, 78F9136A The customer must judge the need for license: PD789101A, 789102A, 789104A, 789101A(A), 789102A(A), 789104A(A) PD789111A, 789112A, 789114A, 789111A(A), 789112A(A), 789114A(A) PD789121A, 789122A, 789124A, 789121A(A), 789122A(A), 789124A(A) PD789131A, 789132A, 789134A, 789131A(A), 789132A(A), 789134A(A) * The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 4 User's Manual U14643EJ1V0UM00 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 User's Manual U14643EJ1V0UM00 5 [MEMO] 6 User's Manual U14643EJ1V0UM00 INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of the PD789104A, 789114A, 789124A, 789134A Subseries and to design and develop application systems and programs using these microcontrollers. The target devices are shown as follows: * PD789104A Subseries: PD789101A, 789102A, 789104A, PD789101A(A), 789102A(A), 789104A(A) * PD789114A Subseries: PD789111A, 789112A, 789114A, 78F9116A, PD789111A(A), 789112A(A), 789114A(A) * PD789124A Subseries: PD789121A, 789122A, 789124A, PD789121A(A), 789122A(A), 789124A(A) * PD789134A Subseries: PD789131A, 789132A, 789134A, 78F9136A, PD789131A(A), 789132A(A), 789134A(A) The PD789104A/114A/124A/134A Subseries is a generic term for all the target devices in this manual. The oscillation frequency of the system clock is regarded as fX for ceramic/crystal oscillation (PD789104A and 789114A Subseries), and regarded as fCC for an RC oscillation (PD789124A and 789134A Subseries). Purpose This manual is intended for users to understand the functions described in the organization below. Organization The PD789104A, 789114A, 789124A, 789134A Subseries User's Manual is divided into two parts: this manual and instructions (common to the 78K/0S Series). PD789104A,789114A,789124A, 789134A Subseries User's Manual (This manual) * Pin functions * Internal block functions * Interrupt * Other internal peripheral functions 78K/0S Series User's Manual Instructions * CPU function * Instruction set * Instruction description User's Manual U14643EJ1V0UM00 7 How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. For users who use this document as the manual for the PD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A), 789114A(A), 789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A), and 789134A(A) The only differences between standard products and (A) products are the quality grades and the electrical specifications. (refer to 1.9 Differences between Standard Quality Grade Products and (A) Products and 2.9 Differences between Standard Quality Grade Products and (A) Products). For the (a) products, read the part numbers in the following manner. PD789101A PD789101A(A) PD789102A PD789102A(A) PD789104A PD789104A(A) PD789111A PD789111A(A) PD789112A PD789112A(A) PD789114A PD789114A(A) PD789121A PD789121A(A) PD789122A PD789122A(A) PD789124A PD789124A(A) PD789131A PD789131A(A) PD789132A PD789132A(A) PD789134A PD789134A(A) To understand the overall functions in general Read this manual in the order of the CONTENTS. How to interpret register formats The name V a bit whose number is encircled is reserved for the assembler and is defined for the C compiler by the header file sfrbit.h. To learn the detailed functions of a register whose register name is known Refer to APPENDIX C REGISTER INDEX. To learn the details of the instruction functions of the 78K/0S Series Refer to 78K/0S Series User's Manual Instructions (U11047E). To know the electrical specifications of the PD789104A/114A/124A/134A Subseries Refer to separately available Data Sheet. Caution The application examples in this manual are created for "Standard" quality grade products for general electric equipment. When using the application examples in this manual for purposes which require "Special" quality grades, thoroughly examine the quality grade of each part and circuit actually used. Conventions Data significance: Note: Caution: Remark: Higher digits on the left and lower digits on the right Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Decimal ... xxxx Hexadecimal ... xxxxH Active low representation: xxx (overscore over pin or signal name) Numerical representation: Binary ... xxxx or xxxxB 8 User's Manual U14643EJ1V0UM00 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. English Japanese U14590J PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A), 112A(A),114A(A) Data Sheet U14590E PD789121A,122A,124A,131A,132A,134A,121A(A),122A(A),124A(A),131A(A), 132A(A),134A(A) Data Sheet U14678E U14678J PD78F9116A Data Sheet PD78F9136A Data Sheet PD789104A,789114A,789124A,789134A Subseries User's Manual 78K/0S Series User's Manual Instruction 78K/0, 78K/0S Series Application Note Flash Memory Write U14667E U14690E This manual U11047E U14458E U14667J U14690J U14643J U11047J U14458J Documents Related to Development Tools (User's Manuals) Document Name Document No. English RA78K0S Assembler Package Operation Assembly Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K0S System Simulator WindowsTM Based Reference External components user open interface specification Reference U11622E U11599E U11623E U11816E U11817E U11489E U10092E U12901E U13549E U14363E Japanese U11622J U11599J U11623J U11816J U11817J U11489J U10092J U12901J U13549J U14363J SM78K Series System Simulator ID78K0S-NS Integrated Debugger Windows Based IE-78K0S-NS In-Circuit Emulator IE-789136-NS-EM1 Emulation Board Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U14643EJ1V0UM00 9 Document Related to Embedded Software (User's Manual) Document Name Document No. English 78K/0S Series OS MX78K0S Basics U12938E Japanese U12938J Other Documents Document Name Document No. English SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party X13769X C10535E C11531E C10983E C11892E C10535J C11531J C10983J C11892J U11416J Japanese Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 10 User's Manual U14643EJ1V0UM00 CONTENTS CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) ................................................... 1.1 Features ............................................................................................................................... 1.2 Applications ........................................................................................................................ 1.3 Ordering Information ......................................................................................................... 1.4 Quality Grade ...................................................................................................................... 1.5 Pin Configuration (Top View) ........................................................................................... 1.6 78K/0S Series Lineup ........................................................................................................ 1.7 Block Diagram .................................................................................................................... 1.8 Outline of Functions .......................................................................................................... 1.9 Differences between Standard Quality Grade Products and (A) Products ............... CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) ................................................... 2.1 Features ............................................................................................................................... 2.2 Applications ........................................................................................................................ 2.3 Ordering Information ......................................................................................................... 2.4 Quality Grade ...................................................................................................................... 2.5 Pin Configuration (Top View) ........................................................................................... 2.6 78K/0S Series Lineup ........................................................................................................ 2.7 Block Diagram .................................................................................................................... 2.8 Outline of Functions .......................................................................................................... 2.9 Differences between Standard Quality Grade Products and (A) Products ............... CHAPTER 3 PIN FUNCTIONS ......................................................................................................... 3.1 Pin Function List ................................................................................................................ 3.2 Description of Pin Functions ........................................................................................... 3.2.1 P00 to P03 (Port 0) .................................................................................................................. 3.2.2 P10, P11 (Port 1) ...................................................................................................................... 3.2.3 P20 to P25 (Port 2) .................................................................................................................. 3.2.4 P50 to P53 (Port 5) .................................................................................................................. 3.2.5 P60 to P63 (Port 6) .................................................................................................................. 3.2.6 RESET ...................................................................................................................................... 3.2.7 X1, X2 (PD789104A, 789114A Subseries) ........................................................................... 3.2.8 CL1, CL2 (PD789124A, 789134A Subseries) ....................................................................... 3.2.9 AVDD ............................................................................................................................................................................................................... 3.2.10 AVSS ............................................................................................................................................................................................................. 3.2.11 VDD ................................................................................................................................................................................................................ 3.2.12 VSS ................................................................................................................................................................................................................ 3.2.13 VPP (PD78F9116A, 78F9136A only) .................................................................................... 3.2.14 IC0 (pin No.20) (mask ROM version only) ............................................................................ 3.2.15 IC0 (pins No.10 and No.21) ................................................................................................... 23 23 23 24 24 25 26 28 29 30 31 31 31 32 32 33 34 36 37 38 39 39 41 41 41 41 42 42 42 42 42 42 42 42 42 43 43 43 3.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ............. CHAPTER 4 CPU ARCHITECTURE ................................................................................................ 4.1 Memory Space .................................................................................................................... 4.1.1 Internal program memory space .............................................................................................. 44 47 47 51 User's Manual U14643EJ1V0UM00 11 4.1.2 Internal data memory (internal high-speed RAM) space ........................................................ 4.1.3 Special function register (SFR) area ....................................................................................... 4.1.4 Data memory addressing ......................................................................................................... 52 52 52 4.2 Processor Registers .......................................................................................................... 4.2.1 Control registers ....................................................................................................................... 4.2.2 General registers ...................................................................................................................... 4.2.3 Special function registers (SFRs) ............................................................................................ 56 56 59 60 4.3 Instruction Address Addressing ...................................................................................... 4.3.1 Relative addressing .................................................................................................................. 4.3.2 Immediate addressing .............................................................................................................. 4.3.3 Table indirect addressing ......................................................................................................... 4.3.4 Register addressing ................................................................................................................. 63 63 64 65 65 4.4 Operand Address Addressing .......................................................................................... 4.4.1 Direct addressing ..................................................................................................................... 4.4.2 Short direct addressing ............................................................................................................ 4.4.3 Special function register (SFR) addressing ............................................................................ 4.4.4 Register addressing ................................................................................................................. 4.4.5 Register indirect addressing .................................................................................................... 4.4.6 Based addressing ..................................................................................................................... 4.4.7 Stack addressing ...................................................................................................................... 66 66 67 68 69 70 71 71 CHAPTER 5 PORT FUNCTIONS ..................................................................................................... 5.1 Functions of Ports ............................................................................................................. 5.2 Port Configuration ............................................................................................................. 5.2.1 Port 0 ........................................................................................................................................ 5.2.2 Port 1 ........................................................................................................................................ 5.2.3 Port 2 ........................................................................................................................................ 5.2.4 Port 5 ........................................................................................................................................ 5.2.5 Port 6 ........................................................................................................................................ 73 73 75 75 76 77 81 82 5.3 Port Function Control Registers ...................................................................................... 5.4 Operation of Port Functions ............................................................................................. 5.4.1 Writing to I/O port ..................................................................................................................... 5.4.2 Reading from I/O port .............................................................................................................. 5.4.3 Arithmetic operation of I/O port ................................................................................................ 83 85 85 85 86 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) ............................... 6.1 Function of Clock Generator ............................................................................................ 6.2 Configuration of Clock Generator ................................................................................... 6.3 Register Controlling Clock Generator ............................................................................ 6.4 System Clock Oscillator .................................................................................................... 6.4.1 System clock oscillator ............................................................................................................. 6.4.2 Divider ....................................................................................................................................... 87 87 87 88 89 89 92 6.5 Operation of Clock Generator .......................................................................................... 6.6 Changing Setting of CPU Clock ....................................................................................... 6.6.1 Time required for switching CPU clock ................................................................................... 6.6.2 Switching CPU clock ................................................................................................................ 92 93 93 93 12 User's Manual U14643EJ1V0UM00 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) ............................... 7.1 Function of Clock Generator ............................................................................................ 7.2 Configuration of Clock Generator ................................................................................... 7.3 Register Controlling Clock Generator ............................................................................ 7.4 System Clock Oscillator .................................................................................................... 7.4.1 System clock oscillator ............................................................................................................. 7.4.2 Divider ....................................................................................................................................... 95 95 95 96 97 97 100 7.5 Operation of Clock Generator .......................................................................................... 100 7.6 Changing Setting of CPU Clock ....................................................................................... 101 7.6.1 Time required for switching CPU clock ................................................................................... 7.6.2 Switching CPU clock ................................................................................................................ 101 101 CHAPTER 8 16-BIT TIMER 20 .......................................................................................................... 8.1 16-Bit Timer 20 Functions ................................................................................................. 8.2 16-Bit Timer 20 Configuration .......................................................................................... 8.3 Registers Controlling 16-Bit Timer 20............................................................................. 8.4 16-Bit Timer 20 Operation ................................................................................................. 8.4.1 Operation as timer interrupt ..................................................................................................... 8.4.2 Operation as timer output ........................................................................................................ 8.4.3 Capture operation ..................................................................................................................... 8.4.4 16-bit timer counter 20 readout ............................................................................................... 103 103 104 106 109 109 111 112 113 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 .......................................................................... 9.1 Functions of 8-Bit Timer/Event Counter 80 .................................................................... 9.2 8-Bit Timer/Event Counter 80 Configuration .................................................................. 9.3 8-Bit Timer/Event Counter 80 Control Registers ........................................................... 9.4 Operation of 8-Bit Timer/Event Counter 80 .................................................................... 9.4.1 Operation as interval timer ....................................................................................................... 9.4.2 Operation as external event counter ....................................................................................... 9.4.3 Operation as square wave output ........................................................................................... 9.4.4 Operation as PWM output ........................................................................................................ 115 115 116 118 120 120 122 123 125 9.5 Notes on Using 8-Bit Timer/Event Counter 80 ............................................................... 127 CHAPTER 10 WATCHDOG TIMER .................................................................................................. 10.1 Functions of Watchdog Timer ........................................................................................ 10.2 Configuration of Watchdog Timer ................................................................................. 10.3 Watchdog Timer Control Register ................................................................................. 10.4 Operation of Watchdog Timer ........................................................................................ 10.4.1 Operation as watchdog timer ................................................................................................. 10.4.2 Operation as interval timer .................................................................................................... 129 129 130 131 133 133 134 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) .......................... 11.1 8-Bit A/D Converter Functions ....................................................................................... 11.2 8-Bit A/D Converter Configuration ................................................................................. 11.3 Registers Controlling 8-Bit A/D Converter ................................................................... 11.4 8-Bit A/D Converter Operation ....................................................................................... 11.4.1 Basic operation of 8-bit A/D converter ................................................................................... 135 135 135 138 140 140 User's Manual U14643EJ1V0UM00 13 11.4.2 Input voltage and conversion result ....................................................................................... 11.4.3 Operation mode of 8-bit A/D converter .................................................................................. 141 143 11.5 Cautions Related to 8-Bit A/D Converter ...................................................................... 144 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) ........................ 12.1 10-Bit A/D Converter Functions ..................................................................................... 12.2 10-Bit A/D Converter Configuration .............................................................................. 12.3 Registers Controlling 10-Bit A/D Converter ................................................................. 12.4 10-Bit A/D Converter Operation ..................................................................................... 12.4.1 Basic operation of 10-bit A/D converter ................................................................................ 12.4.2 Input voltage and conversion result ...................................................................................... 12.4.3 Operation mode of 10-bit A/D converter ............................................................................... 149 149 149 152 154 154 155 157 12.5 Cautions Related to 10-Bit A/D Converter .................................................................... 158 CHAPTER 13 SERIAL INTERFACE 20 ........................................................................................... 13.1 Functions of Serial Interface 20 ..................................................................................... 13.2 Serial Interface 20 Configuration ................................................................................... 13.3 Serial Interface 20 Control Registers ............................................................................. 13.4 Serial Interface 20 Operation ......................................................................................... 13.4.1 Operation stop mode .............................................................................................................. 13.4.2 Asynchronous serial interface (UART) mode ........................................................................ 13.4.3 3-wire serial I/O mode ............................................................................................................ 163 163 163 167 174 174 176 189 CHAPTER 14 MULTIPLIER .............................................................................................................. 14.1 Multiplier Function ........................................................................................................... 14.2 Multiplier Configuration .................................................................................................. 14.3 Multiplier Control Register ............................................................................................. 14.4 Multiplier Operation ......................................................................................................... CHAPTER 15 INTERRUPT FUNCTIONS ........................................................................................ 15.1 Interrupt Function Types................................................................................................. 15.2 Interrupt Sources and Configuration ............................................................................ 15.3 Interrupt Function Control Registers ............................................................................ 15.4 Interrupt Processing Operation ..................................................................................... 15.4.1 Non-maskable interrupt request acknowledgement operation ............................................. 15.4.2 Maskable interrupt request acknowledgement operation ..................................................... 15.4.3 Multiple interrupt processing .................................................................................................. 15.4.4 Interrupt request reserve ....................................................................................................... 199 199 199 201 202 203 203 203 206 211 211 213 215 217 CHAPTER 16 STANDBY FUNCTION .............................................................................................. 219 16.1 Standby Function and Configuration ............................................................................ 219 16.1.1 Standby function ..................................................................................................................... 16.1.2 Standby function control register (PD789104A, 789114A Subseries) ............................... 16.2.1 HALT mode ............................................................................................................................. 16.2.2 STOP mode ............................................................................................................................ 219 220 221 224 16.2 Operation of Standby Function...................................................................................... 221 CHAPTER 17 RESET FUNCTION ................................................................................................... 227 14 User's Manual U14643EJ1V0UM00 CHAPTER 18 PD78F9116A, 78F9136A ........................................................................................ 231 18.1 Flash Memory Programming .......................................................................................... 232 18.1.1 Selecting communication mode ............................................................................................. 18.1.2 Function of flash memory programming ................................................................................ 18.1.3 Flashpro III connection example ........................................................................................... 18.1.4 Example of settings for Flashpro III (PG-FP3) ....................................................................... 232 233 233 237 CHAPTER 19 MASK OPTION (MASK ROM VERSION) ................................................................ 239 CHAPTER 20 INSTRUCTION SET .................................................................................................. 241 20.1 Operation ........................................................................................................................... 241 20.1.1 Operand identifiers and description methods ....................................................................... 20.1.2 Description of "operation" column ......................................................................................... 20.1.3 Description of "flag operation" column .................................................................................. 241 242 242 20.2 Operation List ................................................................................................................... 243 20.3 Instructions Listed by Addressing Type ....................................................................... 248 APPENDIX A DEVELOPMENT TOOLS ........................................................................................... A.1 Language Processing Software ...................................................................................... A.2 Flash Memory Writing Tools ............................................................................................ A.3 Debugging Tools................................................................................................................ A.3.1 Hardware .................................................................................................................................. A.3.2 Software ................................................................................................................................... 251 253 254 254 254 255 APPENDIX B EMBEDDED SOFTWARE ......................................................................................... 257 APPENDIX C REGISTER INDEX ...................................................................................................... 259 C.1 Register Name Index (Alphabetic Order) ....................................................................... 259 C.2 Register Symbol Index (Alphabetic Order) .................................................................... 261 User's Manual U14643EJ1V0UM00 15 [MEMO] 16 User's Manual U14643EJ1V0UM00 LIST OF FIGURES (1/4) Figure No. 3-1. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 4-10. 4-11. 4-12. 4-13. 4-14. 5-1. 5-2. 5-3. 5-4. 5-5. 5-6. 5-7. 5-8. 5-9. 5-10. 5-11. 5-12. 6-1. 6-2. 6-3. 6-4. 6-5. 7-1. 7-2. 7-3. 7-4. 7-5. Title Pin Input/Output Circuits .................................................................................................................... Memory Map (PD789101A, 789111A, 789121A, 789131A) ........................................................... Memory Map (PD789102A, 789112A, 789122A, 789132A) ........................................................... Memory Map (PD789104A, 789114A, 789124A, 789134A) ........................................................... Memory Map (PD78F9116A, 78F9136A) ......................................................................................... Data Memory Addressing (PD789101A, 789111A, 789121A, 789131A) ....................................... Data Memory Addressing (PD789102A, 789112A, 789122A, 789132A) ....................................... Data Memory Addressing (PD789104A, 789114A, 789124A, 789134A) ....................................... Data Memory Addressing (PD78F9116A, 78F9136A) .................................................................... Program Counter Configuration ......................................................................................................... Program Status Word Configuration .................................................................................................. Stack Pointer Configuration ................................................................................................................ Data to be Saved to Stack Memory ................................................................................................... Data to be Restored from Stack Memory .......................................................................................... General Register Configuration .......................................................................................................... Port Types ........................................................................................................................................... Block Diagram of P00 to P03 ............................................................................................................. Block Diagram of P10 and P11 .......................................................................................................... Block Diagram of P20 ......................................................................................................................... Block Diagram of P21 ......................................................................................................................... Block Diagram of P22, P23, and P25 ................................................................................................ Block Diagram of P24 ......................................................................................................................... Block Diagram of P50 to P53 ............................................................................................................. Block Diagram of P60 to P63 ............................................................................................................. Port Mode Register Format ................................................................................................................ Pull-Up Resistor Option Register 0 Format ....................................................................................... Pull-Up Resistor Option Register B2 Format ..................................................................................... Block Diagram of Clock Generator .................................................................................................... Processor Clock Control Register Format ......................................................................................... External Circuit of System Clock Oscillator ....................................................................................... Examples of Incorrect Resonator Connection ................................................................................... Switching CPU Clock .......................................................................................................................... Block Diagram of Clock Generator .................................................................................................... Processor Clock Control Register Format ......................................................................................... External Circuit of System Clock Oscillator ....................................................................................... Examples of Incorrect Resonator Connection ................................................................................... Switching CPU Clock .......................................................................................................................... Page 45 47 48 49 50 52 53 54 55 56 56 58 58 58 59 73 75 76 77 78 79 80 81 82 84 84 84 87 88 89 90 93 95 96 97 98 101 User's Manual U14643EJ1V0UM00 17 LIST OF FIGURES (2/4) Figure No. 8-1. 8-2. 8-3. 8-4. 8-5. 8-6. 8-7. 8-8. 8-9. 8-10. 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 10-1 10-2 10-3 11-1. 11-2. 11-3. 11-4. 11-5. 11-6. 11-7. 11-8. 11-9. 11-10. 11-11. 11-12. 12-1. 12-2. 12-3. 12-4. 12-5. Title Block Diagram of 16-Bit Timer 20 ...................................................................................................... 16-Bit Timer Mode Control Register 20 Format ................................................................................ Port Mode Register 2 Format ............................................................................................................. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation ........................... Timing of Timer Interrupt Operation ................................................................................................... Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation .............................. Timer Output Timing ........................................................................................................................... Settings of 16-Bit Timer Mode Control Register 20 at Capture Operation ...................................... Capture Operation Timing (Both Edges of CPT20 Pin Are Specified) ............................................. 16-Bit Timer Counter 20 Readout Timing .......................................................................................... Block Diagram of 8-Bit Timer/Event Counter 80 ............................................................................... 8-Bit Timer Mode Control Register 80 Format .................................................................................. Port Mode Register 2 Format ............................................................................................................. Interval Timer Operation Timing ......................................................................................................... External Event Counter Operation Timing (with Rising Edge Specified) ......................................... Square Wave Output Timing .............................................................................................................. PWM Output Timing ............................................................................................................................ Start Timing of 8-Bit Timer Counter ................................................................................................... External Event Counter Operation Timing ......................................................................................... Block Diagram of Watchdog Timer ..................................................................................................... Timer Clock Select Register 2 Format ............................................................................................... Format of Watchdog Timer Mode Register ........................................................................................ Block Diagram of 8-Bit A/D Converter ............................................................................................... Format of A/D Converter Mode Register 0 ........................................................................................ Format of Analog Input Channel Specification Register 0 ................................................................ Basic Operation of 8-Bit A/D Converter ............................................................................................. Relationships between Analog Input Voltage and A/D Conversion Result ...................................... Software-Started A/D Conversion ...................................................................................................... How to Reduce Current Consumption in Standby Mode .................................................................. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ...................... Conversion Result Readout Timing (When Conversion Result Is Normal Value) ........................... Analog Input Pin Treatment ................................................................................................................ A/D Conversion End Interrupt Request Generation Timing .............................................................. AVDD Pin Treatment ............................................................................................................................ Block Diagram of 10-Bit A/D Converter ............................................................................................. Format of A/D Converter Mode Register 0 ........................................................................................ Format of Analog Input Channel Specification Register 0 ................................................................ Basic Operation of 10-Bit A/D Converter ........................................................................................... Relationships between Analog Input Voltage and A/D Conversion Result ...................................... Page 104 107 108 109 110 111 111 112 112 113 117 118 119 121 122 124 126 127 127 130 131 132 136 138 139 141 142 143 144 145 145 146 147 147 150 152 153 155 156 18 User's Manual U14643EJ1V0UM00 LIST OF FIGURES (3/4) Figure No. 12-6. 12-7. 12-8. 12-9. 12-10. 12-11. 12-12. 13-1. 13-2. 13-3. 13-4. 13-5. 13-6. 13-7. 13-8. 13-9. 13-10. 13-11. 14-1. 14-2. 14-3. 15-1. 15-2. 15-3. 15-4. 15-5. 15-6. 15-7. 15-8. 15-9. 15-10. 15-11. 15-12. 16-1. 16-2. 16-3. 16-4. 16-5. Title Software-Started A/D Conversion ...................................................................................................... How to Reduce Current Consumption in Standby Mode .................................................................. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ...................... Conversion Result Readout Timing (When Conversion Result Is Normal Value) ........................... Analog Input Pin Treatment ................................................................................................................ A/D Conversion End Interrupt Request Generation Timing .............................................................. AVDD Pin Treatment ............................................................................................................................ Serial Interface 20 Block Diagram ..................................................................................................... Baud Rate Generator Block Diagram ................................................................................................ Serial Operating Mode Register 20 Format ....................................................................................... Asynchronous Serial Interface Mode Register 20 Format ................................................................ Asynchronous Serial Interface Status Register 20 Format ............................................................... Baud Rate Generator Control Register 20 Format ........................................................................... Asynchronous Serial Interface Transmit/Receive Data Format ........................................................ Asynchronous Serial Interface Transmission Completion Interrupt Timing ..................................... Asynchronous Serial Interface Reception Completion Interrupt Timing ........................................... Receive Error Timing .......................................................................................................................... 3-Wire Serial I/O Mode Timing ........................................................................................................... Block Diagram of Multiplier ................................................................................................................ Multiplier Control Register 0 Format .................................................................................................. Multiplier Operation Timing ................................................................................................................. Basic Configuration of Interrupt Function .......................................................................................... Interrupt Request Flag Register Format ............................................................................................ Interrupt Mask Flag Register Format ................................................................................................. External Interrupt Mode Register 0 Format ....................................................................................... Program Status Word Configuration .................................................................................................. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement ....................... Timing of Non-Maskable Interrupt Request Acknowledgement ........................................................ Acknowledging Non-Maskable Interrupt Request ............................................................................. Interrupt Acknowledgement Program Algorithm ................................................................................ Interrupt Request Acknowledgement Timing (Example of MOV A,r) ................................................ Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Generated at the Last Clock During Instruction Execution) ....... Example of Multiple Interrupts ........................................................................................................... Oscillation Stabilization Time Select Register Format ...................................................................... Releasing HALT Mode by Interrupt .................................................................................................... Releasing HALT Mode by RESET Input ............................................................................................ Releasing STOP Mode by Interrupt ................................................................................................... Releasing STOP Mode by RESET Input ........................................................................................... Page 157 158 159 159 160 161 161 164 165 167 168 170 171 183 185 186 187 192 200 201 202 205 207 208 209 210 212 212 212 214 215 215 216 220 222 223 225 226 User's Manual U14643EJ1V0UM00 19 LIST OF FIGURES (4/4) Figure No. 17-1. 17-2. 17-3. 17-4. 18-1. 18-2. 18-3. 18-4. 18-5. 18-6. 18-7. A-1. Title Block Diagram of Reset Function ...................................................................................................... Reset Timing by RESET Input ........................................................................................................... Reset Timing by Overflow in Watchdog Timer .................................................................................. Reset Timing by RESET Input in STOP Mode .................................................................................. Communication Mode Selection Format ............................................................................................ Flashpro III Connection in 3-Wire Serial I/O Mode ........................................................................... Flashpro III Connection in UART Mode ............................................................................................. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used) .............................................. Flashpro III Connection in 3-Wire Serial I/O Mode ........................................................................... Flashpro III Connection in UART Mode ............................................................................................. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used) .............................................. Development Tool Configuration ........................................................................................................ Page 227 228 228 228 232 233 234 234 235 235 236 252 20 User's Manual U14643EJ1V0UM00 LIST OF TABLES (1/2) Table No. 1-1. 2-1. 3-1. 4-1. 4-2. 4-3. 5-1. 5-2. 5-3. 6-1. 6-2. 7-1. 7-2. 8-1. 8-2. 8-3. 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 10-1. 10-2. 10-3. 10-4. 10-5. 11-1. 12-1. Title Differences between Standard Quality Grade Products and (A) Products ...................................... Differences between Standard Quality Grade Products and (A) Products ...................................... Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins ...................... Internal ROM Capacity ....................................................................................................................... Vector Table ......................................................................................................................................... Special Function Register List ............................................................................................................ Port Functions ..................................................................................................................................... Configuration of Port ........................................................................................................................... Port Mode Register and Output Latch Settings When Using Alternate Functions .......................... Configuration of Clock Generator ...................................................................................................... Maximum Time Required for Switching CPU Clock .......................................................................... Configuration of Clock Generator ...................................................................................................... Maximum Time Required for Switching CPU Clock .......................................................................... Configuration of 16-Bit Timer 20 ........................................................................................................ Interval Time of 16-Bit Timer 20 ......................................................................................................... Settings of Capture Edge ................................................................................................................... Interval Time of 8-Bit Timer/Event Counter 80 .................................................................................. Square Wave Output Range of 8-Bit Timer/Event Counter 80 ......................................................... 8-Bit Timer/Event Counter 80 Configuration ...................................................................................... Interval Time of 8-Bit Timer/Event Counter 80 (At fX = 5.0-MHz Operation) ................................... Interval Time of 8-Bit Timer/Event Counter 80 (At fCC = 4.0-MHz Operation) ................................. Square Wave Output Range of 8-Bit Timer/Event Counter 80 (At fX = 5.0-MHz Operation) .......... Square Wave Output Range of 8-Bit Timer/Event Counter 80 (At fCC = 4.0-MHz Operation) ........ Runaway Detection Time of Watchdog Timer ................................................................................... Interval Time ........................................................................................................................................ Configuration of Watchdog Timer ....................................................................................................... Runaway Detection Time of Watchdog Timer ................................................................................... Interval Time of Interval Timer ............................................................................................................ Configuration of 8-Bit A/D Converter ................................................................................................. Configuration of 10-Bit A/D Converter ............................................................................................... Page 30 38 44 51 51 61 74 75 83 87 93 95 101 104 109 112 115 115 116 120 120 123 123 129 129 130 133 134 135 149 User's Manual U14643EJ1V0UM00 21 LIST OF TABLES (2/2) Table No. 13-1. 13-2. 13-3. 13-4. 13-5. 13-6. 13-7. 15-1. 15-2. 15-3. 16-1. 16-2. 16-3. 16-4. Title Serial Interface 20 Configuration ....................................................................................................... Serial Interface 20 Operating Mode Settings .................................................................................... Example of Relationships between System Clock and Baud Rate .................................................. Relationship between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) .......................................................................................................... Example of Relationship between System Clock and Baud Rate .................................................... Relationship between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ................................................................................ Receive Error Causes ......................................................................................................................... Interrupt Source List ........................................................................................................................... Flags Corresponding to Interrupt Request Signal ............................................................................. Time from Generation of Maskable Interrupt Request to Processing .............................................. HALT Mode Operating Status ............................................................................................................ Operation after Release of HALT Mode ............................................................................................. STOP Mode Operating Status ............................................................................................................ Operation after Release of STOP Mode ............................................................................................ Page 163 169 172 173 181 182 187 204 206 213 221 223 224 226 17-1. 18-1. 18-2. 18-3. 18-4. Hardware Status after Reset .............................................................................................................. Differences between Flash Memory and Mask ROM Versions ........................................................ Communication Mode ......................................................................................................................... Functions of Flash Memory Programming ......................................................................................... Example of Settings for PG-FP3 ........................................................................................................ 229 231 232 233 237 19-1. 20-1. Selection of Mask Option for Pins ...................................................................................................... Operand Identifiers and Description Methods ................................................................................... 239 241 22 User's Manual U14643EJ1V0UM00 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.1 Features ROM and RAM capacities Item Part Number Program Memory Data Memory (Internal High-Speed RAM) 256 bytes PD789101A, 789111A PD789102A, 789112A PD789104A, 789114A PD78F9116A ROM 2 Kbytes 4 Kbytes 8 Kbytes Flash memory 16 Kbytes System clock: Crystal/ceramic oscillation Two minimum instruction execution times selectable: high speed (0.4 s) and low speed (1.6 s) (system clock: 5.0 MHz) 20 I/O ports Serial interface: 1 channel 3-wire serial I/O mode/UART mode selectable 8-bit resolution A/D converter: 4 channels (PD789104A Subseries) 10-bit resolution A/D converter: 4 channels (PD789114A Subseries) 3 timers * 16-bit timer: * 8-bit timer/event counter: * Watchdog timer: Vectored interrupt source: 10 Supply voltage: VDD = 1.8 to 5.5 V Operating ambient temperature: TA = -40 to +85C 1 channel 1 channel 1 channel Multiplier: 8 bits x 8 bits = 16 bits 1.2 Applications Vacuum cleaners, washing machines, refrigerators, battery chargers, etc. User's Manual U14643EJ1V0UM00 23 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.3 Ordering Information Part Number Package 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Flash memory Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM PD789101AMC-xxx-5A4 PD789102AMC-xxx-5A4 PD789104AMC-xxx-5A4 PD789111AMC-xxx-5A4 PD789112AMC-xxx-5A4 PD789114AMC-xxx-5A4 PD78F9116AMC-5A4 PD789101AMC(A)-xxx-5A4 PD789102AMC(A)-xxx-5A4 PD789104AMC(A)-xxx-5A4 PD789111AMC(A)-xxx-5A4 PD789112AMC(A)-xxx-5A4 PD789114AMC(A)-xxx-5A4 Remark xxx indicates ROM code suffix. 1.4 Quality Grade Part Number Package 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) Quality Grade Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special PD789101AMC-xxx-5A4 PD789102AMC-xxx-5A4 PD789104AMC-xxx-5A4 PD789111AMC-xxx-5A4 PD789112AMC-xxx-5A4 PD789114AMC-xxx-5A4 PD78F9116AMC-5A4 PD789101AMC(A)-xxx-5A4 PD789102AMC(A)-xxx-5A4 PD789104AMC(A)-xxx-5A4 PD789111AMC(A)-xxx-5A4 PD789112AMC(A)-xxx-5A4 PD789114AMC(A)-xxx-5A4 Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 24 User's Manual U14643EJ1V0UM00 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.5 Pin Configuration (Top View) * 30-pin plastic SSOP (7.62 mm (300) ) PD789101AMC-xxx-5A4 PD789111AMC-xxx-5A4 PD78F9116AMC-5A4 PD789102AMC-xxx-5A4 PD789112AMC-xxx-5A4 PD789104AMC-xxx-5A4 PD789114AMC-xxx-5A4 PD789101AMC(A)-xxx-5A4 PD789102AMC(A)-xxx-5A4 PD789104AMC(A)-xxx-5A4 PD789111AMC(A)-xxx-5A4 PD789112AMC(A)-xxx-5A4 PD789114AMC(A)-xxx-5A4 P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 AVDD P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 AVSS IC0 P50 P51 P52 P53 P00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P22/SI20/RXD20 P21/SO20/TXD20 P20/SCK20/ASCK20 P11 P10 VDD VSS X1 X2 IC0 IC0 (VPP) RESET P03 P02 P01 Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin. 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin. Remark Pin connection in parentheses is intended for the PD78F9116A. ANI0 to ANI3: ASCK20: AVDD: AVSS: CPT20: IC0: Analog Input Asynchronous Serial Input Analog Power Supply Analog Ground Capture Trigger Input Internally Connected RxD20: SCK20: SI20: SO20: SS20: Receive Data Serial Clock Serial Input Serial Output Chip Select Input INTP0 to INTP2: Interrupt from Peripherals P00 to P03: Port 0 P10, P11: P20 to P25: P50 to P53: P60 to P63: RESET: Port 1 Port 2 Port 5 Port 6 Reset TI80: Timer Input TO20, TO80: Timer Output TxD20: VDD: VPP: VSS: X1, X2: Transmit Data Power Supply Programming Power Supply Ground Crystal 1, 2 User's Manual U14643EJ1V0UM00 25 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.6 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products under mass production Products under development Y subseries supports SMB. Small, general-purpose 44 pins 42/44 pins 28 pins PD789046 PD789026 PD789014 PD789026 with subsystem clock added PD789014 with timer reinforced and ROM and RAM expanded UART. Low-voltage (1.8-V) operation Small, general-purpose + A/D 44/48 pins 44/48 pins 44 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789217AY PD789197AY PD789177Y PD789167Y RC oscillation model of PD789197AY PD789177 with internal EEPROMTM PD789167 with improved A/D PD789104A with improved timer PD789146 with improved A/D PD789104A with EEPROM added PD789124A with improved A/D RC oscillation model of PD789104A PD789104A with improved A/D PD789026 with A/D and multiplier added For inverter control 44 pins 78K/0S series 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins PD789842 For driving LCD Internal inverter control circuit and UART PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789407A with improved A/D PD789456 with improved I/O PD789446 with improved A/D PD789426 with improved display output PD789426 with improved A/D PD789306 with A/D added RC oscillation model of PD789306 Basic subseries for driving LCD For driving Dot LCD 144 pins 88 pins PD789835 PD789830 For ASSP Segment/common output: 96 pins Segment: 40 pins, common: 16 pins 52 pins 52 pins 44 pins 44 pins 20 pins 20 pins PD789467 PD789327 PD789800 PD789840 PD789861 PD789860 PD789327 with A/D added For remote controller. Internal LCD controller/driver For PC keyboard. Internal USB function For key pad. Internal POC RC oscillation model of PD789860 For keyless entry. Internal POC and key return circuit 26 User's Manual U14643EJ1V0UM00 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) The major differences between subseries are shown below. Function Subseries Name VDD MIN Value 1.8 V ROM Capacity Timer 8-bit 1 ch 16-bit Watch WDT 1 ch 1 ch - 2 ch 3 ch - 1 ch 1 ch 1 ch 1 ch 8-bit A/D - 10-bit A/D - Serial Interface I/O Remark - PD789046 16 K Small, generalPD789026 4 K-16 K purpose PD789014 2 K-4 K PD789177 16 K-24 K Small, generalPD789167 purpose PD789156 8 K-16 K + A/D PD789146 PD789134A 2 K-8 K PD789124A PD789114A PD789104A For inverter control 1 ch (UART:1 ch) 34 pins 22 pins - 8 ch 8 ch - 4 ch - 4 ch 4 ch - 4 ch - 4 ch - - 1 ch (UART: 1 ch) 30 pins 4.0 V - 20 pins Internal EEPROM RC oscillation version - 1 ch (UART: 1 ch) 31 pins 1.8 V - 1 ch - - 4 ch PD789842 8 K-16 K 3 ch Note 1 ch 1 ch 8 ch For LCD PD789417A 12 K-24 K driving PD789407A 3 ch 1 ch 1 ch 1 ch 7 ch 7 ch - 6 ch - 6 ch - 1 ch (UART: 1 ch) 43 pins 1.8 V - PD789456 12 K-16 K PD789446 PD789436 PD789426 PD789316 8 K to 16K PD789306 For Dot LCD driving ASSP 2 ch - 6 ch - 6 ch - 30 pins 40 pins 2 ch (UART: 1 ch) 23 pins RC oscillation version - PD789835 24 K-60 K PD789830 24 K PD789467 4 K-24 K PD789327 PD789800 8 K PD789840 PD789861 4 K 6 ch 1 ch 2 ch - 1 ch - 1 ch 1 ch 2 ch - - 1 ch 27 pins 1.8 V 2.7 V 1.8 V - 1 ch (UART: 1 ch) 30 pins - 1 ch 2 ch (USB: 1 ch) 1 ch - - 18 pins 21 pins 31 pins 29 pins 14 pins 1 ch 1 ch 1 ch - Internal LCD 2 ch 1 ch - 1 ch - 4 ch 4.0 V 2.8 V 1.8 V - - - RC oscillation version, Internal EEPROM Internal EEPROM PD789860 Note 10-bit timer: 1 channel User's Manual U14643EJ1V0UM00 27 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.7 Block Diagram TI80/INTP2/P25 TO80/TO20 /INTP1/P24 8-bit TIMER/ EVENT COUNTER 80 PORT0 P00 to P03 TO20/TO80 /INTP1/P24 CPT20/INTP0 /SS20/P23 16-bit TIMER 20 PORT1 P10, P11 PORT2 WATCHDOG TIMER 78K/0S CPU CORE SCK20/ASCK20 /P20 SO20/TxD20/P21 SI20/RxD20/P22 SS20/INTP0 /CPT20/P23 RAM ANI0/P60 to ANI3/P63 AVDD AVSS A/D CONVERTER SYSTEM CONTROL SERIAL INTERFACE 20 PORT6 ROM (FLASH MEMORY) PORT5 P20 to P25 P50 to P53 P60 to P63 RESET X1 X2 INTERRUPT CONTROL VDD VSS IC0 (VPP) INTP0/CPT20 /P23/SS20 INTP1/TO80 /TO20/P24 INTP2/TI80/P25 Remarks 1. The size of the internal ROM varies depending on the product. 2. Items in parentheses apply to the PD78F9116A. 28 User's Manual U14643EJ1V0UM00 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.8 Outline of Functions Item PD789101A PD789111A Mask ROM PD789102A PD789112A PD789104A PD789114A PD78F9116A Flash memory Maks ROM Internal memory ROM High-speed RAM System clock Minimum instruction execution time General registers Instruction set 2 Kbytes 256 bytes 4 Kbytes 8 Kbytes 16 Kbytes Crystal/ceramic oscillation 0.4/1.6 s (@5.0-MHz operation with system clock) 8 bits x 8 registers * 16-bit operations * Bit manipulations (such as set, reset, and test) 8 bits x 8 bits = 16 bits Total: * CMOS input: * CMOS I/O: * N-ch open-drain (12-V withstand voltage): 20 4 12 4 Multiplier I/O ports A/D converter 8-bit resolution x 4 channels (PD789104A Subseries) 10-bit resolution x 4 channels (PD789114A Subseries) 3-wire serial I/O mode/UART mode selectable: 1 channel 16-bit timer: 8-bit timer/event counter: Watchdog timer: One output Maskable Non-maskable Internal: 6, External: 3 Internal: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C 30-pin plastic SSOP (7.62 mm (300) ) 1 channel 1 channel 1 channel Serial interface Timer Timer outputs Vectored interrupt Power supply voltage Operating ambient temperature Packages An outline of the timers is shown below. 16-Bit Timer 20 Operating Interval timer Mode External event timer Function Timer output PWM output Square wave output Capture Interrupt source -- -- 1 output -- -- 1 input 1 8-Bit Timer/Event Counter 80 1 channel 1 channel 1 output 1 output 1 output -- 1 Watchdog Timer 1 channelNote -- -- -- -- -- 1 Note Since the watchdog timer provides the watchdog timer function and interval timer function, select the one out of two functions. User's Manual U14643EJ1V0UM00 29 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.9 Differences between Standard quality Grade Products and (A) Products Table 1-1 shows the differences between the standard quality grade products (PD789101A, 789102A, 789104A, 789111A, 789112A, 789114A) and (A) products (PD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A), 789114A(A)). Table 1-1. Differences between Standard Quality Grade Products and (A) Products Part Number Item Quality grade Electrical Specifications Standard Refer to separate Data Sheets Special Standard Quality Grade Products (A) Products 30 User's Manual U14643EJ1V0UM00 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.1 Features ROM and RAM capacities Item Part Number Program Memory Data Memory (Internal High-Speed RAM) 256 bytes PD789121A, 789131A PD789122A, 789132A PD789124A, 789134A PD78F9136A ROM 2 Kbytes 4 Kbytes 8 Kbytes Flash memory 16 Kbytes System clock: RC oscillation Two minimum instruction execution times selectable: high speed (0.5 s) and low speed (2.0 s) (system clock: 4.0 MHz) 20 I/O ports Serial interface: 1 channel 3-wire serial I/O mode/UART mode selectable 8-bit resolution A/D converter: 4 channels (PD789124A Subseries) 10-bit resolution A/D converter: 4 channels (PD789134A Subseries) 3 timers * 16-bit timer: * 8-bit timer/event counter: * Watchdog timer: Vectored interrupt source: 10 Supply voltage: VDD = 1.8 to 5.5 V Operating ambient temperature: TA = -40 to +85C 1 channel 1 channel 1 channel Multiplier: 8 bits x 8 bits = 16 bits 2.2 Applications Vacuum cleaners, washing machines, refrigerators, battery chargers, etc. User's Manual U14643EJ1V0UM00 31 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.3 Ordering Information Part Number Package 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Flash memory Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM PD789121AMC-xxx-5A4 PD789122AMC-xxx-5A4 PD789124AMC-xxx-5A4 PD789131AMC-xxx-5A4 PD789132AMC-xxx-5A4 PD789134AMC-xxx-5A4 PD78F9136AMC-5A4 PD789121AMC(A)-xxx-5A4 PD789122AMC(A)-xxx-5A4 PD789124AMC(A)-xxx-5A4 PD789131AMC(A)-xxx-5A4 PD789132AMC(A)-xxx-5A4 PD789134AMC(A)-xxx-5A4 Remark xxx indicates ROM code suffix. 2.4 Quality Grade Part Number Package 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) 30-pin plastic SSOP (7.62 mm (300) ) Quality Grade Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special PD789121AMC-xxx-5A4 PD789122AMC-xxx-5A4 PD789124AMC-xxx-5A4 PD789131AMC-xxx-5A4 PD789132AMC-xxx-5A4 PD789134AMC-xxx-5A4 PD78F9136AMC-5A4 PD789121AMC(A)-xxx-5A4 PD789122AMC(A)-xxx-5A4 PD789124AMC(A)-xxx-5A4 PD789131AMC(A)-xxx-5A4 PD789132AMC(A)-xxx-5A4 PD789134AMC(A)-xxx-5A4 Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 32 User's Manual U14643EJ1V0UM00 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.5 Pin Configuration (Top View) * 30-pin plastic SSOP (7.62 mm (300) ) PD789121AMC-xxx-5A4 PD789131AMC-xxx-5A4 PD78F9136AMC-5A4 PD789122AMC-xxx-5A4 PD789132AMC-xxx-5A4 PD789124AMC-xxx-5A4 PD789134AMC-xxx-5A4 PD789121AMC(A)-xxx-5A4 PD789122AMC(A)-xxx-5A4 PD789124AMC(A)-xxx-5A4 PD789131AMC(A)-xxx-5A4 PD789132AMC(A)-xxx-5A4 PD789134AMC(A)-xxx-5A4 P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 AVDD P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 AVSS IC0 P50 P51 P52 P53 P00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P22/SI20/RXD20 P21/SO20/TXD20 P20/SCK20/ASCK20 P11 P10 VDD VSS CL1 CL2 IC0 IC0 (VPP) RESET P03 P02 P01 Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin. 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin. Remark Pin connection in parentheses is intended for the PD78F9136A. ANI0 to ANI3: ASCK20: AVDD: AVSS: CL1, CL2: CPT20: IC0: INTP0 to INTP2: P00 to P03: P10, P11: P20 to P25: P50 to P53: P60 to P63: Analog Input Asynchronous Serial Input Analog Power Supply Analog Ground RC oscillator Capture Trigger Input Internally Connected Interrupt from Peripherals Port 0 Port 1 Port 2 Port 5 Port 6 RESET: RxD20: SCK20: SI20: SO20: SS20: TI80: TO20, TO80: TxD20: VDD: VPP: VSS: Reset Receive Data Serial Clock Serial Input Serial Output Chip Select Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground User's Manual U14643EJ1V0UM00 33 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.6 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products under mass production Products under development Y subseries supports SMB. Small, general-purpose 44 pins 42/44 pins 28 pins PD789046 PD789026 PD789014 PD789026 with subsystem clock added PD789014 with timer reinforced and ROM and RAM expanded UART. Low-voltage (1.8-V) operation Small, general-purpose + A/D 44/48 pins 44/48 pins 44 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789217AY PD789197AY PD789177Y PD789167Y RC oscillation model of PD789197AY PD789177 with internal EEPROMTM PD789167 with improved A/D PD789104A with improved timer PD789146 with improved A/D PD789104A with EEPROM added PD789124A with improved A/D RC oscillation model of PD789104A PD789104A with improved A/D PD789026 with A/D and multiplier added For inverter control 44 pins 78K/0S series 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins PD789842 For driving LCD Internal inverter control circuit and UART PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789407A with improved A/D PD789456 with improved I/O PD789446 with improved A/D PD789426 with improved display output PD789426 with improved A/D PD789306 with A/D added RC oscillation model of PD789306 Basic subseries for driving LCD For driving Dot LCD 144 pins 88 pins PD789835 PD789830 For ASSP Segment/common output: 96 pins Segment: 40 pins, common: 16 pins 52 pins 52 pins 44 pins 44 pins 20 pins 20 pins PD789467 PD789327 PD789800 PD789840 PD789861 PD789860 PD789327 with A/D added For remote controller. Internal LCD controller/driver For PC keyboard. Internal USB function For key pad. Internal POC RC oscillation model of PD789860 For keyless entry. Internal POC and key return circuit 34 User's Manual U14643EJ1V0UM00 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) The major differences between subseries are shown below. Function Subseries Name VDD MIN Value 1.8 V ROM Capacity Timer 8-bit 1 ch 16-bit Watch WDT 1 ch 1 ch - 2 ch 3 ch - 1 ch 1 ch 1 ch 1 ch 8-bit A/D - 10-bit A/D - Serial Interface I/O Remark - PD789046 16 K Small, generalPD789026 4 K-16 K purpose PD789014 2 K-4 K PD789177 16 K-24 K Small, generalPD789167 purpose PD789156 8 K-16 K + A/D PD789146 PD789134A 2 K-8 K PD789124A PD789114A PD789104A For inverter control 1 ch (UART:1 ch) 34 pins 22 pins - 8 ch 8 ch - 4 ch - 4 ch 4 ch - 4 ch - 4 ch - - 1 ch (UART: 1 ch) 30 pins 4.0 V - 20 pins Internal EEPROM RC oscillation version - 1 ch (UART: 1 ch) 31 pins 1.8 V - 1 ch - - 4 ch PD789842 8 K-16 K 3 ch Note 1 ch 1 ch 8 ch For LCD PD789417A 12 K-24 K driving PD789407A 3 ch 1 ch 1 ch 1 ch 7 ch 7 ch - 6 ch - 6 ch - 1 ch (UART: 1 ch) 43 pins 1.8 V - PD789456 12 K-16 K PD789446 PD789436 PD789426 PD789316 8 K to 16K PD789306 For Dot LCD driving ASSP 2 ch - 6 ch - 6 ch - 30 pins 40 pins 2 ch (UART: 1 ch) 23 pins RC oscillation version - PD789835 24 K-60 K PD789830 24 K PD789467 4 K-24 K PD789327 PD789800 8 K PD789840 PD789861 4 K 6 ch 1 ch 2 ch - 1 ch - 1 ch 1 ch 2 ch - - 1 ch 27 pins 1.8 V 2.7 V 1.8 V - 1 ch (UART: 1 ch) 30 pins - 1 ch 2 ch (USB: 1 ch) 1 ch - - 18 pins 21 pins 31 pins 29 pins 14 pins 1 ch 1 ch 1 ch - Internal LCD 2 ch 1 ch - 1 ch - 4 ch 4.0 V 2.8 V 1.8 V - - - RC oscillation version, Internal EEPROM Internal EEPROM PD789860 Note 10-bit timer: 1 channel User's Manual U14643EJ1V0UM00 35 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.7 Block Diagram TI80/INTP2/P25 TO80/TO20 /INTP1/P24 8-bit TIMER/ EVENT COUNTER 80 PORT0 P00 to P03 TO20/TO80 /INTP1/P24 CPT20/INTP0 /SS20/P23 16-bit TIMER 20 PORT1 P10, P11 PORT2 WATCHDOG TIMER 78K/0S CPU CORE SCK20/ASCK20 /P20 SO20/TxD20/P21 SI20/RxD20/P22 SS20/INTP0 /CPT20/P23 RAM ANI0/P60 to ANI3/P63 AVDD AVSS A/D CONVERTER SYSTEM CONTROL SERIAL INTERFACE 20 PORT6 ROM (FLASH MEMORY) PORT5 P20 to P25 P50 to P53 P60 to P63 RESET CL1 CL2 INTERRUPT CONTROL VDD VSS IC0 (VPP) INTP0/CPT20 /P23/SS20 INTP1/TO80 /TO20/P24 INTP2/TI80/P25 Remarks 1. The size of the internal ROM varies depending on the product. 2. Items in parentheses apply to the PD78F9136A. 36 User's Manual U14643EJ1V0UM00 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.8 Outline of Functions Item PD789121A PD789131A Mask ROM 2 Kbytes PD789122A PD789132A PD789124A PD789134A PD78F9136A Flash memory Internal memory ROM 4 Kbytes 8 Kbytes 16 Kbytes High-speed RAM System clock Minimum instruction execution time General registers Instruction set 256 bytes Crystal/ceramic oscillation 0.5/2.0 s (@4.0-MHz operation with system clock) 8 bits x 8 registers * 16-bit operations * Bit manipulations (such as set, reset, and test) 8 bits x 8 bits = 16 bits Total: * CMOS input: * CMOS I/O: 20 4 12 Multiplier I/O ports * N-ch open-drain (12-V withstand voltage ): 4 A/D converter 8-bit resolution x 4 channels (PD789124A Subseries) 10-bit resolution x 4 channels (PD789134A Subseries) 3-wire serial I/O mode/UART mode selectable: 1 channel 16-bit timer: 8-bit timer/event counter: Watchdog timer: One output Maskable Non-maskable Power supply voltage Operating ambient temperature Packages Internal: 6, External: 3 Internal: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C 30-pin plastic SSOP (7.62 mm (300) ) 1 channel 1 channel 1 channel Serial interface Timer Timer outputs Vectored interrupt An outline of the timers is shown below. 16-Bit Timer 20 Operating Interval timer Mode External event timer Function Timer output PWM output Square wave output Capture Interrupt source -- -- 1 output -- -- 1 input 1 8-Bit Timer/Event Counter 80 1 channel 1 channel 1 output 1 output 1 output -- 1 Watchdog Timer 1 channelNote -- -- -- -- -- 1 Note Since the watchdog timer provides the watchdog timer function and interval timer function, select the one out of two functions. User's Manual U14643EJ1V0UM00 37 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.9 Differences between Standard quality Grade Products and (A) Products Table 2-1 shows the differences between the standard quality grade products (PD789121A, 789122A, 789124A, 789131A, 789132A, 789134A) and (A) products (PD789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A)). Table 2-1. Differences between Standard Quality Grade Products and (A) Products Part Number Item Quality grade Electrical Specifications Standard Refer to separate Data Sheets Special Standard Quality Grade Products (A) Products 38 User's Manual U14643EJ1V0UM00 CHAPTER 3 PIN FUNCTIONS 3.1 Pin Function List (1) Port pins Pin Name P00 to P03 Input/Output Input/output Function Port 0 4-bit input/output port Input/output can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). Port 1 2-bit input/output port Input/output can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). Port 2 6-bit input/output port Input/output can be specified in 1-bit units An on-chip pull-up resistor can be specified by means of pull-up resistor option register B2 (PUB2) After Reset Input Alternate Function -- P10, P11 Input/output Input -- P20 P21 P22 P23 P24 P25 P50 to P53 Input/output Input SCK20/ASCK20 SO20/TxD20 SI20/RxD20 INTP0/CPT20/SS20 INTP1/TO80/TO20 INTP2/TI80 Input/output Port 5 4-bit N-channel open-drain input/output port Input/output can be specified in 1-bit units For a mask ROM version, an on-chip pull-up resistor can be specified by the mask option. Port 6 4-bit input port Input -- P60 to P63 Input Input ANI0 to ANI3 User's Manual U14643EJ1V0UM00 39 CHAPTER 3 PIN FUNCTIONS (2) Non-port pins Pin Name INTP0 INTP1 INTP2 SI20 SO20 SCK20 ASCK20 SS20 RxD20 TxD20 TI80 TO80 TO20 CPT20 ANI0 to ANI3 AVSS AVDD X1 X2 CL1 CL2 RESET VDD VSS IC0 VPP Input -- -- -- -- Input -- Input -- Input Output Input/output Input Input Input Output Input Output Output Input Input -- -- Input/Output Input Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. Serial data input to serial interface Serial data output from serial interface Serial clock input/output for serial interface Serial clock input to asynchronous serial interface Chip select input to serial interface Serial data input to asynchronous serial interface Serial data output from asynchronous serial interface External count clock input to 8-bit timer (TM80) 8-bit timer (TM80) output 16-bit timer (TM20) output Capture edge input A/D converter analog input A/D converter ground potential A/D converter analog power supply Connecting crystal resonator for system clock oscillation (PD789104A, 789114A Subseries) Connecting resistor (R) and capacitor (C) for system clock oscillation (PD789124A and 789134A Subseries) System reset input Positive power supply Ground potential Internally connected. Directly connect to the VSS pin. Sets flash memory programming mode. Applies high voltage when a program is written or verified. Connect directly to VSS in normal operation mode. Input Input Input Input Input Input Input Input Input Input Input Input -- -- -- -- -- -- Input -- -- -- -- After Reset Input Alternate Function P23/CPT20/SS20 P24/TO80/TO20 P25/TI80 P22/RxD20 P21/TxD20 P20/ASCK20 P20/SCK20 P23/CPT20/INTP0 P22/SI20 P21/SO20 P25/INTP2 P24/INTP1/TO20 P24/INTP1/TO80 P23/INTP0/SS20 P60 to P63 -- -- -- -- -- -- -- -- -- -- -- 40 User's Manual U14643EJ1V0UM00 CHAPTER 3 PIN FUNCTIONS 3.2 Description of Pin Functions 3.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). 3.2.2 P10, P11 (Port 1) These pins constitute a 2-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode register 1 (PM1). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). 3.2.3 P20 to P25 (Port 2) These pins constitute a 6-bit I/O port. In addition, they function as timer input/outputs, external interrupt inputs, and serial interface data and clock input/outputs. Port 2 can be specified in the following operation modes in 1-bit units. (1) Port mode In this mode, P20 to P25 function as a 6-bit I/O port. Port 2 can be specified as input or output mode in 1bit units by using port mode register 2 (PM2). Use of an on-chip pull-up resistor can be specified in 1-bit units by using pull-up resistor option register B2 (PUB2), regardless of the setting of port mode register 2 (PM2). (2) Control mode In this mode, P20 to P25 function as the timer input/output, the external interrupt input, and the clock input/ output of the serial interface and the data input/output. (a) TI80 This is the external clock input pin for 8-bit timer/event counter 80. (b) TO20, TO80 TO20 is the output pin of the 16-bit timer. TO80 is the output pin of the 8-bit timer. (c) CPT20 This is the input pin of the capture edge. (d) INTP0 to INTP2 These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both rising and falling edges) can be specified. (e) SI20, SO20 These are the serial data I/O pins of the serial interface. (f) SCK20 These are the serial clock I/O pins of the serial interface. (g) SS20 This is the chip select input pin of the serial interface. User's Manual U14643EJ1V0UM00 41 CHAPTER 3 PIN FUNCTIONS (h) RxD20, TxD20 These are the serial data I/O pins of the asynchronous serial interface. (i) ASCK20 This is the serial clock input pin of the asynchronous serial interface. Caution When using these pins as serial interface pins, the input/output mode and output latch must be set according to the functions to be used. For the details of the setting, refer to Table 13-2 Serial Interface 20 Operating Mode Settings. 3.2.4 P50 to P53 (Port 5) This is a 4-bit N-ch open-drain I/O port. Port 5 can be specified in input or output mode in 1-bit units by using port mode register 5 (TM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by the mask option. 3.2.5 P60 to P63 (Port 6) This is a 4-bit input-only port. In addition to general-purpose input ports, these pins function as the A/D converter input pins. (1) Port mode In the port mode, port 6 functions as a 4-bit input-only port. (2) Control mode In the control mode, the pins of port 6 can be used as A/D converter analog inputs (ANI0 to ANI3). 3.2.6 RESET This pin inputs an active-low system reset signal. 3.2.7 X1, X2 (PD789104A, 789114A Subseries) These pins are used to connect a crystal resonator for system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 3.2.8 CL1, CL2 (PD789124A, 789134A Subseries) Resistor (R) and capacitor (C) connect pins for system clock oscillation. 3.2.9 AVDD Analog power supply pin of the A/D converter. Always use the same potential as that of the VDD pin even when the A/D converter is not used. 3.2.10 AVSS This is a ground potential pin of the A/D converter. Always use the same potential as that of the VSS pin even when the A/D converter is not used. 3.2.11 VDD Positive power supply pin 3.2.12 VSS Ground pin 42 User's Manual U14643EJ1V0UM00 CHAPTER 3 PIN FUNCTIONS 3.2.13 VPP (PD78F9116A, 78F9136A only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Directly connect this pin to VSS in the normal operation mode. 3.2.14 IC0 (pin No.20) (mask ROM version only) The IC0 (Internally Connected) pin (No. 20) (refer to 1.5 Pin Configuration (Top View), 2.5 Pin Configuration (Top View)) is used to set the PD789104A/114A/124A/134A subseries in the test mode before shipment. In the normal operation mode, connect this pin directly to the VSS pin with as short a wiring length as possible. If a potential difference is generated between the IC0 pin and VSS pin due to a long wiring length between the IC0 pin and VSS pin or external noise superimposed on the IC0 pin, the user program may not run correctly. Connect the IC0 pin directly to the VSS pin. VSS IC0 (pin No.20) Keep short 3.2.15 IC0 (pins No.10 and No.21) The IC0 pins (No.10 and No.21) (refer to 1.5 Pin Configuration (Top View), 2.5 Pin Configuration (Top View) are internally connected. Connect the IC0 pins directly to VSS. User's Manual U14643EJ1V0UM00 43 CHAPTER 3 PIN FUNCTIONS 3.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins The input/output circuit type for each pin and the recommended connection of pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins Pin Name P00 to P03 P10, P11 P20/SCK20/ASCK20 P21/SO20/TxD20 P22/SI20/RxD20 P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 P50 to P53 (Mask ROM version) P50 to P53 (PD78F9116A, 78F9136A) P60/ANI0 to P63/ANI3 AVDD AVSS RESET IC0 2 -- Input -- Connect directly to VSS. 13-V 13-W Input: Independently connect these pins to VSS via a resistor. Output: Leave open Input: Independently connect these pins to VDD via a resistor. Output: Leave open 8-A Input/Output Circuit Type 5-A Input/Output Input/output Recommended Connection of Unused Pins Input: Independently connect these pins to VDD or VSS via a resistor. Output: Leave open 9-C -- Input -- Connect to VDD or VSS. Connect to VDD. Connect to VSS. -- 44 User's Manual U14643EJ1V0UM00 CHAPTER 3 PIN FUNCTIONS Figure 3-1. Pin Input/Output Circuits Type 2 Type 9-C IN IN P-ch N-ch AVSS Comparator + - VREF (Threshold voltage) Schmitt-triggered input with hysteresis characteristics Input enable Type 5-A VDD Type 13-V Pull-up enable VDD Data P-ch P-ch Output data Output disable N-ch IN/OUT VSS IN/OUT Input enable Middle-voltage input buffer Output disable N-ch VSS Input enable Type 8-A VDD Type 13-W VDD Pull-up enable VDD Data P-ch IN/OUT Output disable N-ch VSS Middle-voltage input buffer Input enable Output data Output disable N-ch P-ch Pull-up resistor (mask option) IN/OUT VSS User's Manual U14643EJ1V0UM00 45 [MEMO] 46 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE 4.1 Memory Space The PD789104A/114A/124A/134A Subseries can access 64 Kbytes of memory space. Figures 4-1 through 44 show the memory maps. Figure 4-1. Memory Map (PD789101A, 789111A, 789121A, 789131A) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Data memory space 0800H 07FFH Reserved 07FFH Program area Program memory space Internal ROM 2,048 x 8 bits 0080H 007FH 0040H 003FH 0016H 0015H CALLT table area Program area Vector table area 0000H 0000H User's Manual U14643EJ1V0UM00 47 CHAPTER 4 CPU ARCHITECTURE Figure 4-2. Memory Map (PD789102A, 789112A, 789122A, 789132A) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Data memory space 1000H 0FFFH Reserved 0FFFH Program area Program memory space Internal ROM 4,096 x 8 bits 0080H 007FH 0040H 003FH 0016H 0015H CALLT table area Program area Vector table area 0000H 0000H 48 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE Figure 4-3. Memory Map (PD789104A, 789114A, 789124A, 789134A) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Data memory space 2000H 1FFFH Reserved 1FFFH Program area Program memory space Internal ROM 8,192 x 8 bits 0080H 007FH 0040H 003FH 0016H 0015H CALLT table area Program area Vector table area 0000H 0000H User's Manual U14643EJ1V0UM00 49 CHAPTER 4 CPU ARCHITECTURE Figure 4-4. Memory Map (PD78F9116A, 78F9136A) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Data memory space 4000H 3FFFH Reserved 3FFFH Program area Program memory space Flash memory 16,384 x 8 bits 0080H 007FH 0040H 003FH 0016H 0015H CALLT table area Program area Vector table area 0000H 0000H 50 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE 4.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD789104A/114A/124A/134A Subseries provides the following internal ROMs (or flash memory) containing the following capacities. Table 4-1. Internal ROM Capacity Part Number Structure Internal ROM Capacity 2,048 x 8 bits 4,096 x 8 bits 8,192 x 8 bits Flash memory 16,384 x 8 bits PD789101A, 789111A, 789121A, 789131A PD789102A, 789112A, 789122A, 789132A PD789104A, 789114A, 789124A, 789134A PD78F9116A, 78F9136A Mask ROM The following areas are allocated to the internal program memory space: (1) Vector table area A 22-byte area of addresses 0000H to 0015H is reserved as a vector table area. This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 4-2. Vector Table Vector Table Address 0000H 0004H 0006H 0008H 000AH Interrupt Request RESET input INTWDT INTP0 INTP1 INTP2 Vector Table Address 000CH 000EH 0010H 0012H 0014H Interrupt Request INTSR20/INTCSI20 INTST20 INTTM80 INTTM20 INTAD0 (2) CALLT instruction table area In a 64-byte area of addresses 0040H to 007FH, the subroutine entry address of a 1-byte call instruction (CALLT) can be stored. User's Manual U14643EJ1V0UM00 51 CHAPTER 4 CPU ARCHITECTURE 4.1.2 Internal data memory (internal high-speed RAM) space The PD789104A/114A/124A/134A Subseries provides a 256-byte internal high-speed RAM. The internal high-speed RAM can also be used as a stack memory. 4.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (refer to Table 4-3). 4.1.4 Data memory addressing The PD789104A/114A/124A/134A Subseries provides a variety of addressing modes which take account of memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FEFFH), particular addressing modes are possible to meet the functions of the special function registers (SFRs) and general registers. Figures 4-5 through 4-8 show the data memory addressing modes. Figure 4-5. Data Memory Addressing (PD789101A, 789111A, 789121A, 789131A) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 0800H 07FFH Internal ROM 2,048 x 8 bits 0000H 52 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE Figure 4-6. Data Memory Addressing (PD789102A, 789112A, 789122A, 789132A) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 1000H 0FFFH Internal ROM 4,096 x 8 bits 0000H User's Manual U14643EJ1V0UM00 53 CHAPTER 4 CPU ARCHITECTURE Figure 4-7. Data Memory Addressing (PD789104A, 789114A, 789124A, 789134A) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 2000H 1FFFH Internal ROM 8,192 x 8 bits 0000H 54 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE Figure 4-8. Data Memory Addressing (PD78F9116A, 78F9136A) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 4000H 3FFFH Flash memory 16,384 x 8 bits 0000H User's Manual U14643EJ1V0UM00 55 CHAPTER 4 CPU ARCHITECTURE 4.2 Processor Registers The PD789104A/114A/124A/134A Subseries provides the following on-chip processor registers: 4.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents is set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 4-9. Program Counter Configuration 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 4-10. Program Status Word Configuration 7 PSW IE Z 0 AC 0 0 1 0 CY 56 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of CPU. When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgement is controlled with an interrupt mask flag for various interrupt sources. This flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to (1). It is reset (0) in all other cases. (d) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. User's Manual U14643EJ1V0UM00 57 CHAPTER 4 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 4-11. Stack Pointer Configuration 15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 4-12 and 4-13. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution. Figure 4-12. Data to be Saved to Stack Memory PUSH rp instruction CALL, CALLT instructions SP SP _ 3 SP _ 3 PC7 to PC0 PC15 to PC8 SP _ 2 SP _ 1 SP Interrupt SP SP _ 2 SP _ 2 SP _ 1 SP Register pair lower Register pair higher SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 PSW Figure 4-13. Data to be Restored from Stack Memory POP rp instruction RET instruction RETI instruction SP SP + 1 SP SP + 2 Register pair lower Register pair higher SP SP SP + 1 SP + 2 PC7 to PC0 PC15 to PC8 SP SP + 1 SP + 2 SP SP + 3 PC7 to PC0 PC15 to PC8 PSW 58 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE 4.2.2 General registers The general registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and in addition, two 8-bit registers in pairs can be used as a 16bit register (AX, BC, DE, and HL). They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 4-14. General Register Configuration (a) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Functional names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 0 7 0 User's Manual U14643EJ1V0UM00 59 CHAPTER 4 CPU ARCHITECTURE 4.2.3 Special function registers (SFRs) Unlike general registers, special function registers have their own functions and are allocated to the 256-byte area FF00H to FFFFH. Special function registers can be manipulated, like general registers, with operation, transfer, and bit manipulation instructions. The bit units in which one register can be manipulated (1, 8, and 16) differ depending on the special function register type. Each bit unit for manipulation can be specified as follows. * 1-bit manipulation A symbol reserved by assembler is described as the operand (sfr.bit) of a 1-bit manipulation instruction. This manipulation can also be specified with an address. * 8-bit manipulation A symbol reserved by assembler is described as the operand (sfr) of an 8-bit manipulation instruction. This manipulation can also be specified with an address. * 16-bit manipulation A symbol reserved by assembler is described as the operand of a 16-bit manipulation instruction. When specifying an address, describe an even address. Table 4-3 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol Indicates the addresses of the implemented special function registers. The symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file called "sfrbit.h" of the C compiler. Therefore, these symbols can be used as instruction operands if assembler or integrated debugger is used. * R/W Indicates whether the special function register in question can be read or written. R/W: R: W: Read/write Read only Write only * Bit units for manipulation Indicates the bit units (1, 8, and 16) in which the special function register in question can be manipulated. * After reset Indicates the status of the special function register when the RESET signal is input. 60 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE Table 4-3. Special Function Register List (1/2) Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit FF00H FF01H FF02H FF05H FF06H FF10H FF11H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF20H FF21H FF22H FF25H FF32H FF42H FF48H FF50H FF51H FF53H Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 5 Pull-up resistor option register B2 Time clock select register 2 16-bit timer mode control register 20 8-bit compare register 80 8-bit timer counter 80 8-bit timer mode control register 80 16-bit capture register 20 16-bit timer counter 20 16-bit compare register 20 CR20L CR20 CR20H TM20L TM20 TM20H TCP20L TCP20 TCP20H PM0 PM1 PM2 PM5 PUB2 TCL2 TMC20 CR80 TM80 TMC80 W R R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- Undefined 00H 00H FFH -- Note 1 Note 2 Undefined R -- Note 1 Note 2 0000H W -- Note 1 Note 2 FFFFH A/D conversion result register Note 3 After Reset 8 bits Note 1 16 bits -- -- -- -- -- Note 2 Port 0 Port 1 Port 2 Port 5 Port 6 16-bit multiplication result storage register 0 P0 P1 P2 P5 P6 MUL0L MUL0 MUL0H ADCR0 R/W 00H R -- Undefined -- Note 2 Notes 1. Although these registers are usually accessed in 16-bit units, they can also be accessed in 8-bit units. Access these registers in 8-bit units by means of direct addressing. 2. These registers can be accessed in 16-bit units only by means of short direct addressing. 3. When this register is used as an 8-bit A/D converter (PD789104A and 789124A Subseries), it can be accessed only in 8-bit units. At this time, the register address is FF15H. When this register is used as a 10-bit A/D converter (PD789114A and 789134A Subseries), it can be accessed only in 16-bit units. When using the PD78F9116A as the flash memory version of the PD789101A, 789102A, or 789104A, or when using the PD78F9136A as the flash memory version of the PD789121A, 789122A, or 789124A, this register can be accessed in 8-bit units. However, only the object file assembled with the PD789101A, 789102A, or 789104A, or object file assembled with the PD789121A, 789122A, or 789124A can be used. User's Manual U14643EJ1V0UM00 61 CHAPTER 4 CPU ARCHITECTURE Table 4-3. Special Function Register List (2/2) Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit FF70H FF71H FF72H FF73H FF74H Asynchronous serial interface mode register 20 ASIM20 R/W R R/W -- W R R/W -- -- W R/W -- -- 8 bits 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 04H 02H 00H FFH 00H Undefined FFH Undefined 00H 00H After Reset Asynchronous serial interface status register 20 ASIS20 Serial operating mode register 20 Baud rate generator control register 20 Transmit shift register 20 Receive buffer register 20 CSIM20 BRGC20 TXS20 SIO20 RXB20 ADM0 ADS0 MRA0 MRB0 MULC0 IF0 IF1 MK0 MK1 INTM0 PU0 WDTM Note FF80H FF84H FFD0H FFD1H FFD2H FFE0H FFE1H FFE4H FFE5H FFECH FFF7H FFF9H FFFAH FFFBH A/D converter mode register 0 Analog input channel specification register 0 Multiplication data register A0 Multiplication data register B0 Multiplier control register 0 Interrupt request flag register 0 Interrupt request flag register 1 Interrupt mask flag register 0 Interrupt mask flag register 1 External interrupt mode register 0 Pull-up resistor option register 0 Watchdog timer mode register Oscillation stabilization time select register Processor clock control register OSTS PCC Note PD789104A, 789114A Subseries only 62 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE 4.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (For details of each instruction, refer to 78K/0S Series User's Manual Instruction (U11047E)). 4.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the "BR $addr16" instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 8 7 S jdisp8 15 PC When S = 0, indicates all bits "0". When S = 1, indicates all bits "1". 6 0 ... PC is the start address of the next instruction of a BR instruction. 0 0 User's Manual U14643EJ1V0UM00 63 CHAPTER 4 CPU ARCHITECTURE 4.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the "CALL !addr16 and BR !addr16" instructions are executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces. [Illustration] In case of CALL !addr16, BR !addr16 instruction 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 64 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE 4.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces. [Illustration] 7 Instruction code 1 6 1 5 ta4-0 1 0 1 15 Effective address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective address + 1 High Addr. 15 PC 8 7 0 4.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the "BR AX" instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 User's Manual U14643EJ1V0UM00 65 CHAPTER 4 CPU ARCHITECTURE 4.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 4.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 OP code addr16 (low) addr16 (high) 0 Memory 66 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE 4.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal highspeed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of all SFR areas. In this area, ports which are frequently accessed in a program and a compare register of the timer/event counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to [Illustration]. [Operand format] Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only) [Description example] MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 OP code saddr-offset 0 Short direct memory 15 Effective address 1 1 1 1 1 1 1 8 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. User's Manual U14643EJ1V0UM00 67 CHAPTER 4 CPU ARCHITECTURE 4.4.3 Special function register (SFR) addressing [Function] Memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier sfr Special function register name Description [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 OP code sfr-offset 0 SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0 68 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE 4.4.4 Register addressing [Function] General registers are accessed as operands. The general register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier r rp X, A, C, B, E, D, L, H AX, BC, DE, HL Description `r' and `rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specify code INCW DE; When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code User's Manual U14643EJ1V0UM00 69 CHAPTER 4 CPU ARCHITECTURE 4.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier -- [DE], [HL] Description [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 DE D 87 E 7 0 0 Memory address specified by register pair DE The contents of addressed memory are transferred 7 A 0 70 User's Manual U14643EJ1V0UM00 CHAPTER 4 CPU ARCHITECTURE 4.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier -- [HL+byte] Description [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 4.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only. [Description example] In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 User's Manual U14643EJ1V0UM00 71 [MEMO] 72 User's Manual U14643EJ1V0UM00 CHAPTER 5 PORT FUNCTIONS 5.1 Functions of Ports The PD789104A/114A/124A/134A Subseries provides the ports shown in Figure 5-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port function. For more information on these additional functions, refer to CHAPTER 3 PIN FUNCTIONS. Figure 5-1. Port Types P50 Port 5 P53 P03 P00 Port 0 P60 Port 6 P63 P10 P11 Port 1 P20 Port 2 P25 User's Manual U14643EJ1V0UM00 73 CHAPTER 5 PORT FUNCTIONS Table 5-1. Port Functions Pin Name P00 to P03 Input/Output Input/output Function Port 0 4-bit I/O port Input/output can be specified in 1-bit units When used as input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). Port 1 2-bit I/O port Input/output can be specified in 1-bit units When used as input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). Port 2 6-bit I/O port Input/output can be specified in 1-bit units An on-chip pull-up resistor can be specified by means of pull-up resistor option register B2 (PUB2). After Reset Input Alternate Function -- P10, P11 Input/output Input -- P20 P21 P22 P23 P24 P25 P50 to P53 Input/output Input ASCK20/SCK20 TxD20/SO20 RxD20/SI20 INTP0/CPT20/SS20 INTP1/TO80/TO20 INTP2/TI80 Input/output Port 5 4-bit N-ch open-drain I/O port Input/output can be specified in 1-bit units An on-chip pull-up resistor can be specified for mask ROM versions by the mask option. Port 6 4-bit input-only port Input -- P60 to 63 Input Input ANI0 to ANI3 74 User's Manual U14643EJ1V0UM00 CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration A port consists of the following hardware. Table 5-2. Configuration of Port Parameter Control register Port mode register (PMm: m = 0 to 2, 5) Pull-up resistor option register 0 (PU0) Pull-up option register B2 (PUB2) Total: 20 (input: 7, input/output: 16) * Mask ROM versions Total: 16 (software control: 12, mask option specification: 4) * Flash memory versions Total: 12 (software control only) Configuration Port Pull-up resistor 5.2.1 Port 0 This is a 4-bit I/O port with output latches. Port 0 can be specified as input or output mode in 1-bit units by using port mode register 0 (PM0). When pins P00 to P03 are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull-up resistor option register 0 (PU0). RESET input sets port 0 to input mode. Figure 5-2 shows the block diagram of port 0. Figure 5-2. Block Diagram of P00 to P03 VDD WRPU0 PU00 RD P-ch Internal bus WRPORT Output latch (P00 to P03) WRPM Selector P00 to P03 PM00 to PM03 PU0: PM: RD: WR: Pull-up resistor option register 0 Port mode register Port 0 read signal Port 0 write signal User's Manual U14643EJ1V0UM00 75 CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 This is a 2-bit I/O port with output latches. Port 1 can be specified as input or output mode in 1-bit units by using port mode register 1 (PM1). When pins P10 and P11 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (PU0). RESET input sets port 1 to input mode. Figure 5-3 shows the block diagram of port 1. Figure 5-3. Block Diagram of P10 and P11 VDD WRPU0 PU01 RD P-ch Internal bus WRPORT Output latch (P10, P11) WRPM Selector P10, P11 PM10, PM11 PU0: PM: RD: WR: Pull-up resistor option register 0 Port mode register Port 1 read signal Port 1 write signal 76 User's Manual U14643EJ1V0UM00 CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 This is a 6-bit I/O port with output latches. Port 2 can be specified as input or output mode in 1-bit units by using port mode register 2 (PM2). Use of on-chip pull-up resistors can be specified for pins P20 to P25 in 1-bit units by using pull-up resistor option register B2 (PUB2). The port is also used as a serial interface I/O, clock I/O, timer I/O, and external i;Derrupt input. RESET input sets port 2 to input mode. Figures 5-4 through 5-7 show block diagrams of port 2. Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set according to the function to be used. For how to set the latches, see Table 13-2 Serial Interface 20 Operating Mode Settings. Figure 5-4. Block Diagram of P20 VDD WRPUB2 PUB20 P-ch Alternate function RD Selector Internal bus WRPORT Output latch (P20) WRPM P20/ASCK20/ SCK20 PM20 Alternate function PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User's Manual U14643EJ1V0UM00 77 CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P21 VDD WRPUB2 PUB21 P-ch RD Selector Internal bus WRPORT Output latch (P21) WRPM P21/TxD20/ SO20 PM21 Alternate function Serial output enable signal PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal 78 User's Manual U14643EJ1V0UM00 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P22, P23, and P25 VDD WRPUB2 PUB22, PUB23, PUB25 P-ch Alternate function RD Internal bus WRPORT Output latch (P22, P23, P25) WRPM PM22, PM23, PM25 Selector P22/RxD20/SI20 P23/INTP0/CPT20/ SS20 P25/INTP2/TI80 PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User's Manual U14643EJ1V0UM00 79 CHAPTER 5 PORT FUNCTIONS Figure 5-7. Block Diagram of P24 VDD WRPUB2 PUB24 P-ch Alternate function RD Selector P24/INTP1/ TO80/TO20 Internal bus WRPORT Output latch (P24) WRPM PM24 Alternate function Alternate function PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal 80 User's Manual U14643EJ1V0UM00 CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 5 This is a 4-bit N-ch open-drain I/O port with output latches. Port 5 can be specified as input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be specified by the mask option. RESET input sets port 5 to input mode. Figure 5-8 shows a block diagram of port 5. Figure 5-8. Block Diagram of P50 to P53 RD VDD Selector Mask option resistor Mask ROM version only. For flash memory version, a pull-up resistor is not incorporated. Internal bus WRPORT Output latch (P50 to P53) N-ch P50 to P53 WRPM PM50 to PM53 PM: RD: WR: Port mode register Port 5 read signal Port 5 write signal Caution When using port 5 of PD78F9116A and 78F9136A as an input port, be sure to observe the restrictions listed below. <1> When VDD = 1.8 to 5.5 V Use within the range of TA = 25 to 85C <2> When TA = -40 to +85C Use within the range of VDD = 2.7 to 5.5 V <3> When TA = -40 to +85C and VDD = 1.8 to 5.5 V Issue three consecutive read instructions when reading port 5. If the above restrictions are not observed, the input value may be read incorrectly. Note, however, that these resrictions do not apply when port 5 pins are used as output pins, or when the product is other than PD78F9116A or 78F9136A. User's Manual U14643EJ1V0UM00 81 CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 6 This is a 4-bit input port. The port is also used as an analog input to the A/D converter. RESET input sets port 6 to input mode. Figure 5-9 shows a block diagram of port 6. Figure 5-9. Block Diagram of P60 to P63 RD Internal bus + A/D converter - P60/ANI0 to P63/ANI3 VREF 82 User's Manual U14643EJ1V0UM00 CHAPTER 5 PORT FUNCTIONS 5.3 Port Function Control Registers The following three types of registers control the ports. * Port mode registers (PM0 to PM2, PM5) * Pull-up resistor option register 0 (PU0) * Pull-up resistor option register B2 (PUB2) (1) Port mode registers (PM0 to PM2, PM5) These registers are used to set port input/output in 1-bit units. Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch according to Table 5-3. Caution As port 2 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. Table 5-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Pin Name Alternate Function Name P23 INTP0 CPT20 P24 INTP1 TO80 TO20 P25 INTP2 TI80 Input/Output Input Input Input Output Output Input Input 1 1 1 0 0 1 1 x x x 0 0 x x PMxx Pxx Caution When Port 2 is used for serial interface pin, the I/O latch or output latch must be set according to its function. For the setting method, refer to Table 13-2 Serial Interface 20 Operating Mode Settings. Remark x: PMxx: Pxx: don't care Port mode register Port output latch User's Manual U14643EJ1V0UM00 83 CHAPTER 5 PORT FUNCTIONS Figure 5-10. Port Mode Register Format Symbol PM0 7 1 6 1 5 1 4 1 3 2 1 0 Address FF20H After reset FFH R/W R/W PM03 PM02 PM01 PM00 PM1 1 1 1 1 1 1 PM11 PM10 FF21H FFH R/W PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM5 1 1 1 1 PM53 PM52 PM51 PM50 FF25H FFH R/W PMmn 0 1 Pmn pin input/output mode selection (m = 0 to 2, 5, n = 0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) (2) Pull-up resistor option register 0 (PU0) The pull-up resistor option register (PU0) sets whether to use on-chip pull-up resistors at each port or not. At a port where use of on-chip pull-up resistors has been specified by PU0, the pull-up resistors can be internally used only for the bits set in input mode. No on-chip pull-up resistors can be used for the bits set in output mode, in spite of setting PU0. On-chip pull-up resistors can also not be used when the pins are used as the alternate-function output pins. PU0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PU0 to 00H. Figure 5-11. Pull-Up Resistor Option Register 0 Format Symbol PU0 7 0 6 0 5 0 4 0 3 0 2 0 <1> <0> Address FFF7H After reset 00H R/W R/W PU01 PU00 PU0m 0 1 Pm on-chip pull-up resistor selection (m = 0, 1) On-chip pull-up resistor not used On-chip pull-up resistor used (3) Pull-up resistor option register B2 (PUB2) This register specifies whether an on-chip pull-up resistor is connected to each pin of port 2. The pin so specified by PUB2 is connected to on-chip pull-up resistor regardless of the setting of the port mode register. PUB2 is set with a 1-bit or 8-bit manipulation instruction. RESET input sets this register to 00H. Figure 5-12. Pull-Up Resistor Option Register B2 Format Symbol PUB2 7 0 6 0 <5> <4> <3> <2> <1> <0> Address FF32H After reset 00H R/W R/W PUB25 PUB24 PUB23 PUB22 PUB21 PUB20 PUB2n 0 1 P2n on-chip pull-up resistor selection (n = 0 to 5) On-chip pull-up resistor not used On-chip pull-up resistor used User's Manual U14643EJ1V0UM00 84 CHAPTER 5 PORT FUNCTIONS 5.4 Operation of Port Functions The operation of a port differs depending on whether the port is set in input or output mode, as described below. 5.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. The data once written to the output latch is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is OFF. The data once written to the output latch is retained until new data is written to the output latch. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 5.4.2 Reading from I/O port (1) In output mode The contents of the output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (2) In input mode The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed. Caution When using port 5 of PD78F9116A and 78F9136A as an input port, be sure to observe the restrictions listed below. <1> When VDD = 1.8 to 5.5 V Use within the range of TA = 25 to 85C <2> When TA = -40 to +85C Use within the range of VDD = 2.7 to 5.5 V <3> When TA = -40 to +85C and VDD = 1.8 to 5.5 V Issue three consecutive read instructions when reading port 5. If the above restrictions are not observed, the input value may be read incorrectly. Note, however, that these resrictions do not apply when port 5 pins are used as output pins, or when the product is other than PD78F9116A or 78F9136A. User's Manual U14643EJ1V0UM00 85 CHAPTER 5 PORT FUNCTIONS 5.4.3 Arithmetic operation of I/O port (1) In output mode An arithmetic operation can be performed with the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins. The data once written to the output latch is retained until new data is written to the output latch. (2) In input mode The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is OFF. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 86 User's Manual U14643EJ1V0UM00 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.1 Function of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock oscillator is the following type. * System clock (crystal/ceramic) oscillator This circuit oscillates at frequencies of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction. 6.2 Configuration of Clock Generator The clock generator consists of the following hardware. Table 6-1. Configuration of Clock Generator Item Control register Oscillator Processor clock control register (PCC) Crystal/ceramic oscillator Configuration Figure 6-1. Block Diagram of Clock Generator Prescaler X1 X2 System clock oscillator Clock to peripheral hardware fX Prescaler fX 22 Selector STOP Standby control circuit Wait control circuit CPU clock (fCPU) PCC1 Processor clock control register (PCC) Internal bus User's Manual U14643EJ1V0UM00 87 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.3 Register Controlling Clock Generator The clock generator is controlled by the following register: * Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC sets the CPU clock selection and the ratio of division. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 6-2. Processor Clock Control Register Format Symbol PCC 7 0 6 0 5 0 4 0 3 0 2 0 1 PCC1 0 0 Address FFFBH After reset 02H R/W R/W PCC1 0 1 fX (0.2 s) CPU clock (fCPU) selection fX/22 (0.8 s) Caution Bit 0 and bits 2 to 7 must be set to 0. Remarks 1. fX: System clock oscillation frequency 2. Values in parentheses are when operating at fX = 5.0 MHz. 3. Minimum instruction execution time: 2fCPU * When fCPU = 0.2 s: 0.4 s * When fCPU = 0.8 s: 1.6 s 88 User's Manual U14643EJ1V0UM00 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.4 System Clock Oscillator 6.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the X1 pin, and leave the X2 pin open. Figure 6-3 shows the external circuit of the system clock oscillator. Figure 6-3. External Circuit of System Clock Oscillator (a) Crystal or ceramic oscillation (b) External clock VSS X1 External clock X1 X2 Crystal or ceramic resonator Open X2 Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * * * * Keep the wiring length as short as possible. Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. Do not fetch signals from the oscillator. Figure 6-4 shows incorrect examples of resonator connection. User's Manual U14643EJ1V0UM00 89 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) Figure 6-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 2, 5, 6) VSS X1 X2 VSS X1 X2 90 User's Manual U14643EJ1V0UM00 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) Figure 6-4. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 VSS X1 X2 High current A B High current C (e) Signal is fetched VSS X1 X2 User's Manual U14643EJ1V0UM00 91 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.4.2 Divider The divider divides the output of the system clock oscillator (fX) to generate various clocks. 6.5 Operation of Clock Generator The clock generator generates the following clocks and controls the operating modes of the CPU, such as the standby mode: * System clock * CPU clock fX fCPU * Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC), as follows: (a) The slow mode 2fCPU (1.6 s: at 5.0-MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is stopped. (b) Two types of CPU clocks fCPU (0.2 s and 0.8 s: at 5.0-MHz operation) can be selected by the PCC setting. (c) Two standby modes, STOP and HALT, can be used. (d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral hardware is stopped when the system clock is stopped (except the external clock input operation). 92 User's Manual U14643EJ1V0UM00 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.6 Changing Setting of CPU Clock 6.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (refer to Table 6-2). Table 6-2. Maximum Time Required for Switching CPU Clock Set Value before Switching PCC1 Set Value after Switching PCC1 0 0 1 2 clocks PCC1 1 4 clocks Remark Two clocks are the minimum instruction execution time of the CPU clock before switching. 6.6.2 Switching CPU clock The following figure illustrates how the CPU clock switches. Figure 6-5. Switching CPU Clock VDD RESET CPU clock Slow operation Fastest operation Wait (6.55 ms: at 5.0-MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during which oscillation stabilizes (215/fX) is automatically secured. After that, the CPU starts instruction execution at the low speed of the system clock (1.6 s: at 5.0-MHz operation). <2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can be selected. User's Manual U14643EJ1V0UM00 93 [MEMO] 94 User's Manual U14643EJ1V0UM00 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.1 Function of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock oscillator consists of the following type. * System clock (RC) oscillator This circuit oscillates at frequencies of 2.0 to 4.0 MHz. Oscillation can be stopped by executing the STOP instruction. 7.2 Configuration of Clock Generator The clock generator consists of the following hardware. Table 7-1. Configuration of Clock Generator Item Control register Oscillator Processor clock control register (PCC) RC oscillator Configuration Figure 7-1. Block Diagram of Clock Generator Prescaler CL1 CL2 System clock oscillator Clock to peripheral hardware fCC Prescaler fCC 22 Selector STOP Standby control circuit Wait control circuit CPU clock (fCPU) PCC1 Processor clock control register (PCC) Internal bus User's Manual U14643EJ1V0UM00 95 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.3 Register Controlling Clock Generator The clock generator is controlled by the following register: * Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC sets the CPU clock selection and the ratio of division. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the PCC to 02H. Figure 7-2. Processor Clock Control Register Format Symbol PCC 7 0 6 0 5 0 4 0 3 0 2 0 1 PCC1 0 0 Address FFFBH After reset 02H R/W R/W PCC1 0 1 fCC (0.25 s) (1.0 s) CPU clock (fCPU) selection fCC/22 Caution Bit 0 and bits 2 to 7 must be set to 0. Remarks 1. fCC: System clock oscillation frequency 2. Values in parentheses are when operating at fX = 4.0 MHz. 3. Minimum instruction execution time: 2fCPU * When fCPU = 0.25 s: 0.5 s * When fCPU = 1.0 s: 2.0 s 96 User's Manual U14643EJ1V0UM00 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.4 System Clock Oscillator 7.4.1 System clock oscillator The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (4.0 MHz TYP.) connected across the CL1 and CL2 pins. An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the CL1 pin, and leave the CL2 pin open. Figure 7-3 shows the external circuit of the system clock oscillator. Figure 7-3. External Circuit of System Clock Oscillator (a) RC oscillation (b) External clock CL1 C R CL2 VSS External clock CL1 Open CL2 Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * * * * Keep the wiring length as short as possible. Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. Do not fetch signals from the oscillator. Figure 7-4 shows incorrect examples of resonator connection. User's Manual U14643EJ1V0UM00 97 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) Figure 7-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 2, 5, 6) CL1 CL2 VSS CL1 CL2 VSS 98 User's Manual U14643EJ1V0UM00 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) Figure 7-4. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A and B fluctuates) VDD PORTn (n = 0 to 2, 5, 6) CL1 High current CL2 VSS CL1 CL2 VSS A High current B (e) Signal is fetched CL1 CL2 VSS User's Manual U14643EJ1V0UM00 99 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.4.2 Divider The divider divides the output of the system clock oscillator (fCC) to generate various clocks. 7.5 Operation of Clock Generator The clock generator generates the following clocks and controls the operating modes of the CPU, such as the standby mode: * System clock * CPU clock fCC fCPU * Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC), as follows: (a) The slow mode 2fCPU (2.0 s: at 4.0-MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is stopped. (b) Two types of CPU clocks fCPU (0.5 s and 1.0 s: at 4.0-MHz operation) can be selected by the PCC setting. (c) Two standby modes, STOP and HALT, can be used. (d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral hardware is stopped when the system clock is stopped (except the external clock input operation). 100 User's Manual U14643EJ1V0UM00 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.6 Changing Setting of CPU Clock 7.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (refer to Table 7-2). Table 7-2. Maximum Time Required for Switching CPU Clock Set Value before Switching PCC1 Set Value after Switching PCC1 0 0 1 2 clocks PCC1 1 4 clocks Remark Two clocks are the minimum instruction execution time of the CPU clock before switching. 7.6.2 Switching CPU clock The following figure illustrates how the CPU clock switches. Figure 7-5. Switching CPU Clock VDD RESET CPU clock Slow operation Fastest operation Wait (32 s: at 4.0-MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during which oscillation stabilizes (27/fCC) is automatically secured. After that, the CPU starts instruction execution at the low speed of the system clock (2.0 s: at 4.0-MHz operation). <2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can be selected. User's Manual U14643EJ1V0UM00 101 [MEMO] 102 User's Manual U14643EJ1V0UM00 CHAPTER 8 16-BIT TIMER 20 The 16-bit timer counter references the free running counter and provides the functions such as timer interrupt and timer output. In addition, the count value can be captured by a trigger pin. 8.1 16-Bit Timer 20 Functions 16-bit timer 20 has the following functions. * Timer interrupt * Timer output * Count value capture (1) Timer interrupt An interrupt is generated when a count value and compare value matches. (2) Timer output Timer output control is possible when an count value and compare value matches. (3) Count value capture A TM20 count value is latched in synchronization with the capture trigger and retained. User's Manual U14643EJ1V0UM00 103 CHAPTER 8 16-BIT TIMER 20 8.2 16-Bit Timer 20 Configuration 16-bit timer 20 consists of the following hardware. Table 8-1. Configuration of 16-Bit Timer 20 Item Timer counter Register 16 bits x 1 (TM20) Compare register: 16 bits x 1 (CR20) Capture register: 16 bits x 1 (TCP20) 1 (TO20) 16-bit timer mode control register 20 (TMC20) Port mode register 2 (PM2) Configuration Timer output Control register Figure 8-1. Block Diagram of 16-Bit Timer 20 Internal bus 16-bit timer mode control register 20 (TMC20) TOF20 CPT201CPT200 TOC20 TCL201TCL200 TOE20 P24 output latch PM24 16-bit compare register 20 (CR20) Match F/F TOD20 16-bit timer mode control register 20 TO20/P24/ INTP1/TO80 INTTM20 Selector fCLK/2 2 16-bit timer counter 20 (TM20) OVF fCLK/26 CPT20/P23/ INTP0/SS20 Edge detection circuit 16-bit capture register 20 (TCP20) 16-bit counter read buffer Internal bus Remark fCLK: fX or fCC 104 User's Manual U14643EJ1V0UM00 CHAPTER 8 16-BIT TIMER 20 (1) 16-bit compare register 20 (CR20) This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and when they match, generates an interrupt request (INTTM20). CR20 is set with a 16-bit memory manipulation instruction. The values 0000H to FFFFH can be set. RESET input sets this register to FFFFH. Cautions 1. Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can be used. When manipulated with an 8-bit memory manipulation instruction, the accessing method should be direct addressing. 2. When rewriting CR20 during count operation, set CR20 to interrupt disable from interrupt mask flag register 0 (MK10) beforehand. Also, set the timer output data to inversion disable using 16-bit timer mode control register 20 (TMC20). When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. (2) 16-bit timer counter 20 (TM20) This is a 16-bit register that counts count pulses. TM20 is read with a 16-bit memory manipulation instruction. This register is free running during count clock input. RESET input clears this register to 0000H and after which it resumes free running. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can be used. When manipulated with an 8-bit memory manipulation instruction, the accessing method should be direct addressing. 3. When manipulated with an 8-bit memory manipulation instruction, readout should be performed in the order from lower byte to higher byte and must be in pairs. (3) 16-bit capture register 20 (TCP20) This is a 16-bit register that captures the contents of 16-bit timer counter 20 (TM20). TCP20 is set with a 16-bit memory manipulation instruction. RESET input sets this register to undefined. Caution Although this register is manipulated with a 16-bit memory manipulation instruction, an 8bit memory manipulation instruction can be used. When manipulated with an 8-bit memory manipulation instruction, the accessing method should be direct addressing. (4) 16-bit counter read buffer This buffer latches a counter value and retains the count value of 16-bit timer counter 20 (TM20). User's Manual U14643EJ1V0UM00 105 CHAPTER 8 16-BIT TIMER 20 8.3 Registers Controlling 16-Bit Timer 20 The following two types of registers control 16-bit timer 20. * 16-bit timer mode control register 20 (TMC20) * Port mode register 2 (PM2) (1) 16-bit timer mode control register 20 (TMC20) 16-bit timer mode control register 20 (TMC20) controls the setting of the counter clock, capture edge, etc. TMC20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC20 to 00H. 106 User's Manual U14643EJ1V0UM00 CHAPTER 8 16-BIT TIMER 20 Figure 8-2. 16-Bit Timer Mode Control Register 20 Format Symbol TMC20 7 <6> 5 4 3 2 1 <0> Address FF48H After reset 00H R/W R/W Note TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TOD20 0 1 Timer output of 0 Timer output of 1 Timer output data TOF20 0 1 Clear by reset and software Set by overflow of 16-bit timer Overflow flag set CPT201 CPT200 0 0 1 1 0 1 0 1 Capture operation disabled Rising edge of CPT20 Falling edge of CPT20 Both edges of CPT20 Capture edge selection TOC20 0 1 Inverse disabled Inverse enabled Timer output data inverse control TCL201 TCL200 16-bit timer counter 20 count clock selection At fX = 5.0 MHz At fCC = 4.0 MHz fCC/22 (1.0 MHz) fCC/26 (62.5 kHz) 0 0 0 1 fX/22 (1.25 MHz) fX/26 (78.1 kHz) Other than above Setting prohibited TOE20 0 1 Output disabled (port mode) Output enabled 16-bit timer 20 output control Note Bit 7 is read-only. fX: System clock oscillation frequency (ceramic/crystal oscillation) Remark fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ1V0UM00 107 CHAPTER 8 16-BIT TIMER 20 (2) Port mode register 2 (PM2) This register sets the input/output of port 2 in 1-bit units. To use the P24/TO20/INTP1/TO80 pin for timer output, set the output latch of PM24 and P24 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 8-3. Port Mode Register 2 Format Symbol PM2 7 1 6 1 5 4 3 2 1 0 Address FF22H After reset FFH R/W R/W PM25 PM24 PM23 PM22 PM21 PM20 PM24 0 1 Output mode (output buffer on) Input mode (output buffer off) P24 pin input/output mode selection 108 User's Manual U14643EJ1V0UM00 CHAPTER 8 16-BIT TIMER 20 8.4 16-Bit Timer 20 Operation 8.4.1 Operation as timer interrupt In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200. To operate the 16-bit timer 20 as a timer interrupt, the following settings are required. * Set count values to CR20 * Set 16-bit timer mode control counter 20 (TMC20) as shown in Figure 8-4. Figure 8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 - 0/1 0/1 0/1 0/1 0 0/1 0/1 Setting of count clock (see Table 8-2) Caution If both the CPT201 and CPT200 flags are set to 0, the capture edge becomes setting prohibited. When the count value of 16-bit timer counter 20 (TM20) coincides with the value set to CR20, counting of TM20 continues and an interrupt request signal (INTTM20) is generated. Table 8-3 shows the interval time, and Figure 8-5 shows the timing of the timer interrupt operation. Caution When rewriting CR20 during count operation, be sure to follow the procedure below. <1> <2> Set CR20 to interrupt disable (by setting bit 7 of interrupt mask flag register 0 (MK0) to 1). Set inversion control of timer output data to disable (TOC20 = 0) When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. Table 8-2. Interval Time of 16-Bit Timer 20 TCL201 TCL200 Count Clock At fX = 5.0 MHz 0 0 0 1 22/fX 26/fX (0.8 s) (12.8 s) At fCC = 4.0 MHz 22/fCC 26/fCC (1.0 s) (16 s) Interval Time At fX = 5.0 MHz 218/fX 222/fX (52.4 ms) (838.9 ms) At fCC = 4.0 MHz 218/fCC 222/fCC (65.5 ms) (1,048 ms) Other than above Setting prohibited Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ1V0UM00 109 CHAPTER 8 16-BIT TIMER 20 Figure 8-5. Timing of Timer Interrupt Operation t Count clock TM20 count value CR20 INTTM20 Interrupt accept TO20 TOF20 Overflow flag set Interrupt accept 0000H N 0001H N N FFFFH 0000H 0001H N N N FFFFH N Remark N = 0000H to FFFFH 110 User's Manual U14643EJ1V0UM00 CHAPTER 8 16-BIT TIMER 20 8.4.2 Operation as timer output Timer outputs are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200. To operate the 16-bit timer 20 as a timer output, the following settings are required. * Set P24 to output mode (PM24 = 0) * Set P24 output latch to 0 * Set the count value to CR20 * Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-6 Figure 8-6. Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 - 0/1 0/1 0/1 1 0 0/1 1 TO20 output enable Setting of count clock (see Table 8-2) Inverse enable of timer output data Caution If both CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation prohibited. When the count value of the 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the TO20/P24/INTP1/TO80 pin is inverted. This enables timer output. At that time, TM20 count is continued and an interrupt request signal (INTTM20) is generated. Figure 8-7 shows the timing of timer output (see Table 8-2 for the interval time of the 16-bit timer 20). Figure 8-7. Timer Output Timing t Count clock TM20 count value CR20 INTTM20 Interrupt accept TO20Note TOF20 Overflow flag set Interrupt accept 0000H N 0001H N N FFFFH 0000H 0001H N N N FFFFH N Note The TO20 initial value becomes low level during output enable (TOE20 = 1). N = 0000H to FFFFH Remark User's Manual U14643EJ1V0UM00 111 CHAPTER 8 16-BIT TIMER 20 8.4.3 Capture operation The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) in synchronization with a capture trigger. Set as shown in Figure 8-8 to allow 16-bit timer 20 to start the capture operation. Figure 8-8. Settings of 16-Bit Timer Mode Control Register 20 at Capture Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 - 0/1 0/1 0/1 0/1 0 0/1 0/1 Count clock selection Capture edge selection (see Table 8-3) 16-bit capture register 20 (TCP20) starts the capture operation after the CPT20 capture trigger edge has been detected, and latches and retains the count value of 16-bit timer counter 20. TCP20 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. Table 8-3 and Figure 8-9 show the setting contents of the capture edge and capture operation timing, respectively. Table 8-3. Settings of Capture Edge CPT201 0 0 1 1 CPT200 0 1 0 1 Capture operation prohibited CPT20 pin rising edge CPT20 pin falling edge CPT20 pin both edges Capture Edge Selection Caution Because TCP20 is rewritten when a capture trigger edge is detected during TCP20 read, disable the capture trigger detection during TCP20 read. Figure 8-9. Capture Operation Timing (Both Edges of CPT20 Pin Are Specified) Count clock TM20 Count read buffer TCP20 0000H 0000H 0001H 0001H Undefined Capture start CPT20 Capture edge detection Capture edge detection N N N M-1 M M M Capture start 112 User's Manual U14643EJ1V0UM00 CHAPTER 8 16-BIT TIMER 20 8.4.4 16-bit timer counter 20 readout The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction. TM20 readout is performed through a counter read buffer. The counter read buffer latches the TM20 count value. Buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises and the count value is retained. The counter read buffer value at the retention state can be read out as the count value. Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM20 higher byte falls. RESET input clears TM20 to 0000H and restarts free running. Figure 8-10 shows the timing of 16-bit timer counter 20 readout. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during oscillation stabilization time. 2. Although TM20 is a dedicated 16-bit transfer instruction register, an 8-bit transfer instruction can be used. Execute an 8-bit transfer instruction by direct addressing. 3. When using an 8-bit transfer instruction, execute in the order from lower byte to higher byte in pairs. If the only lower byte is read, the pending state of the counter read buffer is not canceled, and if the only higher byte is read, an undefined count value is read. Figure 8-10. 16-Bit Timer Counter 20 Readout Timing CPU clock Count clock TM20 Count read buffer TM20 read signal Read signal latch prohibited period 0000H 0000H 0001H 0001H N N N+1 User's Manual U14643EJ1V0UM00 113 [MEMO] 114 User's Manual U14643EJ1V0UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 The 8-bit timer/event counter can be used as an interval timer, external event counter, and for square wave output and PWM output of arbitrary frequency. 9.1 Functions of 8-Bit Timer/Event Counter 80 8-bit timer/event counter 80 has the following functions: * Interval timer * External event counter * Square wave output * PWM output (1) 8-bit interval timer When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time interval set in advance. Table 9-1. Interval Time of 8-Bit Timer/Event Counter 80 Minimum Interval Time At fX = 5.0 MHz 1/fX (200 ns) 23/fX At fCC = 4.0 MHz (1.6 s) Maximum Interval Time 2 /fX (51.2 s) 8 Resolution 1/fX (200 ns) 23/fX (1.6 s) 1/fCC (250 ns) 23/fCC (2.0 s) 2 /fX (409.6 s) 11 1/fCC (250 ns) 23/fCC (2.0 s) 28/fCC (64 s) 2 /fCC (512 s) 11 Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square wave output A square wave of arbitrary frequency can be output. Table 9-2. Square Wave Output Range of 8-Bit Timer/Event Counter 80 Minimum Pulse Width At fX = 5.0 MHz 1/fX (200 ns) 23/fX (1.6 s) At fCC = 4.0 MHz 1/fCC (250 ns) 23/fCC (2.0 s) Maximum Pulse Width 28/fX (51.2 s) 211/fX (409.6 s) 28/fCC (64 s) 211/fCC (512 s) Resolution 1/fX (200 ns) 23/fX (1.6 s) 1/fCC (250 ns) 23/fCC (2.0 s) Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ1V0UM00 115 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 (4) PWM output 8-bit resolution PWM output can be produced. 9.2 8-Bit Timer/Event Counter 80 Configuration 8-bit timer/event counter 80 consists of the following hardware. Table 9-3. 8-Bit Timer/Event Counter 80 Configuration Item Timer counter Register Timer output Control register 8 bits x 1 (TM80) Compare register: 8 bits x 1 (CR80) 1 (TO80) 8-bit timer mode control register 80 (TMC80) Port mode register 2 (PM2) Configuration 116 User's Manual U14643EJ1V0UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 80 Internal bus 8-bit compare register 80 (CR80) Match fCLK Selector TO20 output Note 8-bit timer counter 80 (TM80) Clear R INV Q Q OVF S INTTM80 fCLK/23 TI80/P25/ INTP2 TO80/P24/ INTP1/TO20 TCE80 PWME80 TCL801 TCL800 TOE80 8-bit timer mode control register 80 (TMC80) Internal bus P24 output latch PM24 Note Refer to block diagram of 16-bit timer 20 fCLK: fX or fCC Remark (1) 8-bit compare register 80 (CR80) This is an 8-bit register that compares the value set to CR80 with the 8-bit timer counter 80 (TM80) count value, and if they match, generates an interrupt request (INTTM80). CR80 is set with an 8-bit memory manipulation instruction. The values 00H to FFH can be set. RESET input makes CR80 undefined. Cautions 1. When rewriting CR80 in timer counter operation mode (i.e. PWME80 (bit 6 of 8-bit timer mode control register 80 (TMC80) is set to 0), be sure to stop the timer operation before hand. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. Do not set CR80 to 00H in the PWM output mode (when PWME80 = 1); otherwise, PWM may not be output normally. (2) 8-bit timer counter 80 (TM80) This is an 8-bit register to count count pulses. TM80 is read with an 8-bit memory manipulation instruction. RESET input clears TM80 to 00H. User's Manual U14643EJ1V0UM00 117 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.3 8-Bit Timer/Event Counter 80 Control Registers The following two types of registers are used to control the 8-bit timer/event counter 80. * 8-bit timer mode control register 80 (TMC80) * Port mode register 2 (PM2) (1) 8-bit timer mode control register 80 (TMC80) This register enables/stops operation of 8-bit timer counter 80 (TM80), sets the counter clock of TM80, and controls the operation of the output control circuit of 8-bit timer/event counter 80. TMC80 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC80 to 00H. Figure 9-2. 8-Bit Timer Mode Control Register 80 Format Symbol TMC80 <7> <6> 5 0 4 0 3 0 2 1 <0> Address FF53H After reset 00H R/W R/W TCE80 PWME80 TCL801TCL800 TOE80 TCE80 0 1 8-bit timer counter 80 operation control Operation stop (TM80 cleared to 0) Operation enable PWME80 0 1 Timer counter operating mode PWM output operating mode Operation mode selection TCL801TCL800 8-bit timer counter 80 count clock selection At fX = 5.0-MHz operation At fCC = 4.0-MHz operation fCC (4.0 MHz) fCC/23 (500 kHz) 0 0 1 1 0 1 0 1 fX (5.0 MHz) (625 kHz) fX/23 Rising edge of TI80 Falling edge of TI80 TOE80 0 1 Output disable (port mode) Output enable 8-bit timer/event counter 80 output control Caution Be sure to set TMC80 after stopping timer operation. Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 118 User's Manual U14643EJ1V0UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 (2) Port mode register 2 (PM2) This register sets port 2 to input/output in 1-bit units. When using the P24/TO80/INTP1/TO20 pin for timer output, set the output latch of PM24 and P24 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 9-3. Port Mode Register 2 Format Symbol PM2 7 1 6 1 5 4 3 2 1 0 Address FF22H After reset FFH R/W R/W PM25 PM24 PM23 PM22 PM21 PM20 PM2n 0 1 P2n pin input/output mode selection (n = 0 to 5) Output mode (output buffer ON) Input mode (output buffer OFF) User's Manual U14643EJ1V0UM00 119 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.4 Operation of 8-Bit Timer/Event Counter 80 9.4.1 Operation as interval timer The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare register 80 (CR80) in advance. To operate the 8-bit timer/event counter as an interval timer, the following settings are required. <1> <2> <3> <4> Set 8-bit timer counter 80 (TM80) to operation disable (by setting TCE80 (bit 7 of 8-bit timer mode control register 80 (TMC80)) to 0). Set the count clock of the 8-bit timer/event counter 80 (see Tables 9-4 and 9-5) Set the count value to CR80 Set TM80 to operation enable (TCE80 = 1) When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, the value of TM80 is cleared to 0 and TM80 continue counting. At the same time, an interrupt request signal (INTTM80) is generated. Tables 9-4 and 9-5 show the interval time, and Figure 9-4 shows the timing of interval timer operation. Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. Therefore, always follow the above procedure when operating the 8-bit timer/event counter as an interval timer. Table 9-4. Interval Time of 8-Bit Timer/Event Counter 80 (At fX = 5.0-MHz Operation) TCL801 TCL800 0 0 1 1 0 1 0 1 Minimum Interval Time 1/fX (200 ns) 23/fX (1.6 s) TI80 input cycle TI80 input cycle Maximum Interval Time 28/fX (51.2 s) 211/fX (409.6 s) 28 x TI80 input cycle 28 x TI80 input cycle Resolution 1/fX (200 ns) 23/fX (1.6 s) TI80 input edge cycle TI80 input edge cycle Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 9-5. Interval Time of 8-Bit Timer/Event Counter 80 (At fCC = 4.0-MHz Operation) TCL801 TCL800 0 0 1 1 0 1 0 1 Minimum Interval Time 1/fCC (250 ns) 2 /fCC (2.0 s) 3 Maximum Interval Time 2 /fCC (64 s) 8 Resolution 1/fCC (250 ns) 23/fCC (2.0 s) TI80 input edge cycle TI80 input edge cycle 2 /fCC (512 s) 11 TI80 input cycle TI80 input cycle 28 x TI80 input cycle 2 x TI80 input cycle 8 Remark fCC: System clock oscillation frequency (RC oscillation) 120 User's Manual U14643EJ1V0UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 Figure 9-4. Interval Timer Operation Timing t Count clock TM80 count value 00H 01H N 00H Clear 01H N 00H Clear 01H N CR80 N N N N TCE80 Count start INTTM80 Interrupt accept TO80 Interrupt accept Interval time Interval time Interval time Remark Interval time = (N + 1) x t : N = 00H to FFH User's Manual U14643EJ1V0UM00 121 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI80/P25/INTP2 pin by using 8-bit timer counter 80 (TM80). To operate the 8-bit timer/event counter 80 as an external event counter, the following settings are required. <1> <2> <3> <4> <5> Set P25 to input mode (PM25 = 1) Set 8-bit timer counter 80 (TM80) to operation disable (by setting TCE80 (bit 7 of 8-bit timer mode control register 80 (TMC80)) to 0). Specify the rising/falling edges of TI80 (see Tables 9-4 and 9-5), and set TO80 to output disable (i.e. set TOE80 (bit 0 of TMC80) to 0) and PWM output to disable (i.e. set PWME80 (bit 6 of TMC80) to 0). Set the count value to CR80. Set TM80 to operation enable (TCE80 = 1) Each time the valid edge specified by bit 1 (TCL800) of TMC80 is input, the value of 8-bit timer counter 80 (TM80) is incremented. When the count value of TM80 matches the value set to CR80, the value of TM80 is cleared to 0 and TM80 continues counting. At the same time, an interrupt request signal (INTTM80) is generated. Figure 9-5 shows the timing of the external event counter operation (with rising edge specified). Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. Therefore, always follow the above procedure when operating the 8-bit timer/event counter as an interval timer. Figure 9-5. External Event Counter Operation Timing (with Rising Edge Specified) TI80 pin input TM80 count value 00H 01H 02H 03H 04H 05H N-1 N 00H 01H 02H 03H CR80 N TCE80 INTTM80 Remark N = 00H to FFH 122 User's Manual U14643EJ1V0UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.4.3 Operation as square wave output The 8-bit timer/event counter can generate output square waves of a given frequency at intervals specified by the count value set to the 8-bit compare register 80 (CR80) in advance. To operate the 8-bit timer/event counter 80 for square wave output, the following settings are required. <1> <2> <3> <4> <5> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0. Set 8-bit timer counter 80 (TM80) to operation disable (TCE80 = 0). Set the count clock of the 8-bit timer/event counter 80 (see Tables 9-4 and 9-5), TO80 to output enable (TOE80 = 1), and PWM output to disable (PWME80 = 0). Set the count value to CR80. Set TM80 to operation enable (TCE80 = 1). When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, the TO80/P24/INTP1/TO20 pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, the TM80 value is cleared to 0 and TM80 continues counting. At the same time, an interrupt request signal (INTTM80) is generated. Square wave output is cleared (0) when bit 7 (TCE80) in TMC80 is set to 0. Table 9-6 shows square wave output range, and Figure 9-6 shows timing of square wave output. Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. Therefore, always follow the above procedure when operating the 8-bit timer/event counter as an interval timer. Table 9-6. Square Wave Output Range of 8-Bit Timer/Event Counter 80 (At fX = 5.0-MHz Operation) TCL801 TCL800 0 0 0 1 Minimum Pulse Width 1/fX (200 ns) 2 /fX (1.6 s) 3 Maximum Pulse Width 2 /fX (51.2 s) 8 Resolution 1/fX (200 ns) 23/fX (1.6 s) 2 /fX (409.6 s) 11 Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 9-7. Square Wave Output Range of 8-Bit Timer/Event Counter 80 (At fCC = 4.0-MHz Operation) TCL801 TCL800 0 0 0 1 Minimum Pulse Width 1/fCC (250 ns) 23/fCC (2.0 s) Maximum Pulse Width 28/fCC (64 s) 211/fCC (512 s) Resolution 1/fCC (250 ns) 23/fCC (2.0 s) Remark fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ1V0UM00 123 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 Figure 9-6. Square Wave Output Timing Count clock TM80 count value 00H 01H N 00H Clear 01H N 00H Clear 01H N CR80 N N N N TCE80 Count start INTTM80 Interrupt accept TO80Note Interrupt accept Note The initial value of TO80 during output enable (TOE80 = 1) becomes low level. 124 User's Manual U14643EJ1V0UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.4.4 Operation as PWM output PWM output enables interrupt generation repeatedly at intervals specified by the count value set to 8-bit compare register 80 (CR80) in advance. To use 8-bit timer/counter 80 for PWM output, the following settings are required. <1> <2> <3> <4> <5> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0. Set 8-bit timer counter 80 (TM80) to operation disable (TCE80 = 0). Set the count clock of the 8-bit timer/event counter 80 (see Tables 9-4 and 9-5), TO80 to output enable (TOE80 = 1), and PWM output to enable (PWME80 = 1). Set the count value to CR80 Set TM80 to operation enable (TCE80 = 1) When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, TM80 continues counting, and an interrupt request signal (INTTM80) is generated. Cautions 1. When CR80 is rewritten during timer operation, a high level may be output for the next one cycle (refer to 9.5 (2) Setting of 8-bit compare register 80). 2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. Therefore, always follow the above procedure when operating 8-bit compare register 80 as a PWM output. User's Manual U14643EJ1V0UM00 125 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 Figure 9-7. PWM Output Timing Count clock TM80 00H 01H *** M *** FFH 00H 01H 02H *** M M+1 M+2 *** FFH 00H 01H *** M *** *** CR80 M TCE80 OVF INTTM80 TO80Note M = 01H to FFH Note The initial value of TO80 upon output enable (TOE80 = 1) is low level. Caution Do not set CR80 to 00H in the PWM output mode; otherwise PWM may not be output normally. 126 User's Manual U14643EJ1V0UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.5 Notes on Using 8-Bit Timer/Event Counter 80 (1) Error on starting timer An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated. This is because 8-bit timer counter 80 (TM80) is started in asynchronization with the count pulse. Figure 9-8. Start Timing of 8-Bit Timer Counter Count pulse TM80 count value 00H 01H 02H 03H 04H Timer start (2) Setting of 8-bit compare register 80 8-bit compare register 80 (CR80) can be set to 00H. Therefore, one pulse can be counted when the 8-bit timer/event counter operates as an event counter. Figure 9-9. External Event Counter Operation Timing Tl80 input CR80 00H TM80 count value 00H 00H 00H 00H Interrupt request flag Cautions 1. When rewriting CR80 in timer counter operation mode (i.e. PWME80 (bit 6 of 8-bit timer mode control register 80 (TMC80) is set to 0), be sure to stop the timer operation before hand. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. User's Manual U14643EJ1V0UM00 127 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 2. When rewriting CR80 in PWM output operation mode (PWME80 = 1), a high level may be output for the next one cycle (count pulse x 256). This phenomenon occurs if a value smaller than the value of TM80 is written to CR80. Count clock TM80 CR80 TCE80 OVF Match Signal TO80 M = 02H-FFH Rewriting to CR80 M01H 00H 01H ... M M ... FFH 00H 01H 02H ... FFH 00H 01H ... ... 01H 3. Do not set CR80 to 00H in the PWM output mode (when PWME80 = 1); otherwise, PWM may not be output normally. 128 User's Manual U14643EJ1V0UM00 CHAPTER 10 WATCHDOG TIMER The watchdog timer can generate non-maskable interrupts, maskable interrupts and RESET with arbitrary preset intervals. 10.1 Functions of Watchdog Timer The watchdog timer has the following functions: * Watchdog timer * Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect program runaway. When a runaway is detected, a non-maskable interrupt or the RESET signal can be generated. Table 10-1. Runaway Detection Time of Watchdog Timer Runaway Detection Time 211 x 1/fW 213 x 1/fW 215 x 1/fW 2 17 x 1/fW At fX = 5.0-MHz Operation At fCC = 4.0-MHz Operation 410 s 1.64 ms 6.55 ms 26.2 ms 512 s 2.05 ms 8.19 ms 32.8 ms fW: fX or fCC fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) (2) Interval timer The interval timer generates an interrupt at a given interval set in advance. Table 10-2. Interval Time Interval Time 2 2 2 2 11 13 15 17 At fX = 5.0-MHz Operation At fCC = 4.0-MHz Operation 410 s 1.64 ms 6.55 ms 26.2 ms 512 s 2.05 ms 8.19 ms 32.8 ms x 1/fW x 1/fW x 1/fW x 1/fW fW: fX or fCC fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ1V0UM00 129 CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware: Table 10-3. Configuration of Watchdog Timer Item Control register Configuration Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 10-1. Block Diagram of Watchdog Timer Internal bus fW 24 fW 26 Prescaler fW 28 fW 210 TMMK4 TMIF4 INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request Selector 7-bit counter Clear Control circuit 3 TCL22 TCL21 TCL20 Timer clock select register 2 (TCL2) RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus Remark fW: fX or fCC 130 User's Manual U14643EJ1V0UM00 CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Control Register The following two types of registers are used to control the watchdog timer. * Timer clock select register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input clears TCL2 to 00H. Figure 10-2. Timer Clock Select Register 2 Format Symbol TCL2 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FF42H After reset 00H R/W R/W TCL22 TCL21 TCL20 TCL22 TCL21 TCL20 Watchdog timer count clock selection Interval time At fX = 5.0-MHz operation At fCC = 4.0-MHz operation At fX = 5.0-MHz operation At fCC = 4.0-MHz operation 0 0 1 1 0 1 0 1 0 0 0 0 fX/24 (312.5 kHz) fX/26 (78.1 kHz) fX/28 (19.5 kHz) fX/210 (4.88 kHz) Setting prohibited fCC/24 (250 KHZ) fCC/26 (62.5 KHZ) fCC/28 (15.6 KHZ) fCC/210 (3.91 KHZ) 211/fX (410 s) 213/fX (1.64 ms) 215/fX (6.55 ms) 217/fX (26.2 ms) 211/fCC (512 s) 213/fCC (2.05 ms) 215/fCC (8.19 ms) 217/fCC (32.8 ms) Other than above Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ1V0UM00 131 CHAPTER 10 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 10-3. Format of Watchdog Timer Mode Register Symbol WDTM <7> RUN 6 0 5 0 4 3 2 0 1 0 0 0 Address FFF9H After reset 00H R/W R/W WDTM4 WDTM3 RUN 0 1 Stops counting Selects operation of watchdog timerNote 1 Clears counter and starts counting WDTM4 WDTM3 0 0 1 1 0 1 0 1 Operation stop Selects operation mode of watchdog timerNote 2 Interval timer mode (overflow and maskable interrupt occur)Note 3 Watchdog timer mode 1 (overflow and non-maskable interrupt occur) Watchdog timer mode 2 (overflow occurs and reset operation started) Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software. 3. The watchdog timer starts operations as an interval timer when RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by timer clock select register 2 (TCL2). 2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of interrupt request flag 0) has been set to 0. When watchdog timer mode 1 or 2 is selected under the condition where TMIF4 is 1, a non-maskable interrupt occurs at the completion of rewriting. 132 User's Manual U14643EJ1V0UM00 CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Operation as watchdog timer The watchdog timer operates to detect a runaway when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the runaway detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (WDTM3) of WDTM. The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction. Caution The actual runaway detection time may be up to 0.8% shorter than the set time. Table 10-4. Runaway Detection Time of Watchdog Timer TCL22 0 0 1 1 TCL21 0 1 0 1 TCL20 0 0 0 0 Runaway Detection Time 211 x 1/fW 213 x 1/fW 215 x 1/fW 217 x 1/fW At fX = 5.0-MHz Operation At fCC = 4.0-MHz Operation 410 s 1.64 ms 6.55 ms 26.2 ms 512 s 2.05 ms 8.19 ms 32.8 ms fW: fX or fCC fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ1V0UM00 133 CHAPTER 10 WATCHDOG TIMER 10.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of watchdog timer mode register (WDTM) are set to 1, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value set in advance. Select a count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1. In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts. The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the RESET signal is input. 2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the set time. Table 10-5. Interval Time of Interval Timer TCL22 0 0 1 1 TCL21 0 1 0 1 TCL20 0 0 0 0 2 2 2 2 11 13 15 17 Interval Time x 1/fW x 1/fW x 1/fW x 1/fW At fX = 5.0-MHz Operation At fCC = 4.0-MHz Operation 410 s 1.64 ms 6.55 ms 26.2 ms 512 s 2.05 ms 8.19 ms 32.8 ms fW: fX or fCC fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 134 User's Manual U14643EJ1V0UM00 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.1 8-Bit A/D Converter Functions The 8-bit A/D converter is an 8-bit resolution converter to convert analog input to digital signals. This converter can control up to four channels of analog inputs (ANI0 to ANI3). A/D conversion can only be started by software. One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time an A/D session is completed. 11.2 8-Bit A/D Converter Configuration The 8-bit A/D converter consists of the following hardware. Table 11-1. Configuration of 8-Bit A/D Converter Item Analog input Register 4 channels (ANI0 to ANI3) Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) Control register A/D converter mode register 0 (ADM0) Analog input channel specification register 0 (ADS0) Configuration User's Manual U14643EJ1V0UM00 135 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) Figure 11-1. Block Diagram of 8-Bit A/D Converter AVDD P-ch Sample and hold circuit ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 Selector Tap selector Voltage comparator AVSS AVSS Successive approximation register (AR) Control circuit INTAD0 2 ADS01 ADS00 Analog input channel specification register 0 (ADS0) ADCS0 FR02 FR01 FR00 A/D conversion result register 0 (ADCR0) A/D converter mode register 0 (ADM0) Internal bus (1) Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB). Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0). (2) A/D conversion result register 0 (ADCR0) ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received from the successive approximation register is loaded into ADCR0, which is an 8-bit register that holds the result of A/D conversion. ADCR0 can be read with an 8-bit memory manipulation instruction. RESET input makes this register undefined. (3) Sample and hold circuit The sample and hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. (4) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. 136 User's Manual U14643EJ1V0UM00 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) (5) Series resistor string The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against which analog inputs are compared. (6) ANI0 to ANI3 pins Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the analog signals for A/D conversion. Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage greater than AVDD or less than AVSS (even if within the absolute maximum rating) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. Furthermore, the conversion values for the other channels may also be affected. (7) AVSS pin The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as the VSS pin, even while the A/D converter is not being used. (8) AVDD pin The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same potential as the VDD pin, even while the A/D converter is not being used. User's Manual U14643EJ1V0UM00 137 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.3 Registers Controlling 8-Bit A/D Converter The following two registers are used to control the 8-bit A/D converter. * A/D converter mode register 0 (ADM0) * Analog input channel specification register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADM0 to 00H. Figure 11-2. Format of A/D Converter Mode Register 0 Symbol <7> ADM0 ADCS0 6 0 5 4 3 2 0 1 0 0 0 Address FF80H After reset 00H R/W R/W FR02 FR01 FR00 ADCS0 0 1 Conversion disabled Conversion enabled A/D conversion control FR02 FR01 FR00 A/D conversion time selectionNote 1 At fX = 5.0-MHz operation At fCC = 4.0-MHz operation 144/fCC (36 s) 120/fCC (30 s) 96/fCC 72/fCC Note 2) Note 2 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 144/fX 120/fX 96/fX 72/fX 60/fX 48/fX (28.8 s) (24 s) (19.2 s) (14.4 s) (Setting prohibited (Setting prohibited (24 s) (18 s) (15 s) (Setting prohibitedNote 2) 60/fCC 48/fCC ) Other than above Setting prohibited Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least 14 s. 2. These bit combinations must not be used, as the A/D conversion time will fall below 14 s. Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined. 2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to 11.5 (5) Timing when A/D conversion result become undefined). Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 138 User's Manual U14643EJ1V0UM00 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) (2) Analog input channel specification register 0 (ADS0) The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H. Figure 11-3. Format of Analog Input Channel Specification Register 0 Symbol ADS0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF84H After reset 00H R/W R/W ADS01 ADS00 ADS01 ADS00 0 0 1 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 Analog input channel specification User's Manual U14643EJ1V0UM00 139 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.4 8-Bit A/D Converter Operation 11.4.1 Basic operation of 8-bit A/D converter <1> Select a channel for A/D conversion, using Analog input channel specification register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample and hold circuit. <3> After sampling continues for a certain period of time, the sample and hold circuit is put on hold to keep the input analog voltage until A/D conversion is completed. <4> Bit 7 of the successive approximation A/D conversion register (SAR) is set. The series resistor string voltage tap at the tap selector is set to half of AVDD. <5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. If the analog input voltage is higher than half of AVDD, the MSB of the SAR is left set. If it is lower than half of AVDD, the MSB is reset. <6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows: * Bit 7 = 1: Three quarters of AVDD * Bit 7 = 0: One quarter of AVDD The tap voltage is compared with the analog input voltage. Bit 6 is set or reset according to the result of comparison. * Analog input voltage tap voltage: Bit 6 = 1 * Analog input voltage < tap voltage: Bit 6 = 0 <7> Comparison is repeated until bit 0 of the SAR is reached. <8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate an A/D conversion end interrupt request (INTAD0). Cautions 1. The first A/D conversion value immediately after starting the A/D conversion operation may be undefined. 2. When in standby mode, the A/D converter stops operation. 140 User's Manual U14643EJ1V0UM00 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) Figure 11-4. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined 80H C0H or 40H Conversion result ADCR0 Conversion result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or Analog input channel specification register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled. In this case, if ADCS0 is set (1), A/D conversion is restarted from the beginning. RESET input makes the A/D conversion result register 0 (ADCR0) undefined. 11.4.2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion result (A/D conversion result register 0 (ADCR0)) are represented by: ADCR0 = INT ( or (ADCR0 - 0.5) x INT( ): VIN: AVDD: AVDD 256 VIN < (ADCR0 + 0.5) x AVDD 256 VIN AVDD x 256 + 0.5) Function that returns the integer part of a parenthesized value Analog input voltage A/D converter supply voltage ADCR0: Value in the A/D conversion result register 0 (ADCR0) Figure 11-5 shows the relationships between the analog input voltage and the A/D conversion result. User's Manual U14643EJ1V0UM00 141 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) Figure 11-5. Relationships between Analog Input Voltage and A/D Conversion Result 255 254 253 A/D conversion result (ADCR0) 3 2 1 0 1 1 3 2 5 3 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 1 Input voltage/AVDD 142 User's Manual U14643EJ1V0UM00 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.4.3 Operation mode of 8-bit A/D converter The 8-bit A/D converter is initially in the select mode. In this mode, Analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI3 for A/D conversion. A/D conversion can only be started by software, that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. * Software-started A/D conversion Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied to the analog input pin specified in Analog input channel specification register 0 (ADS0). Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the ongoing session of A/D conversion is discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written to the ADM0 again during A/D conversion, A/D conversion is completely stopped. Figure 11-6. Software-Started A/D Conversion Rewriting ADM0 ADCS0 = 1 Rewriting ADM0 ADCS0 = 1 ADCS0 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion is discontinued; no conversion result is preserved. Stop ADCR0 ANIn ANIn ANIm INTAD0 Remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3 User's Manual U14643EJ1V0UM00 143 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.5 Cautions Related to 8-Bit A/D Converter (1) Current consumption in the standby mode When the A/D converter enters the standby mode, it stops its operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption. Figure 11-7 shows how to reduce the current consumption in the standby mode. Figure 11-7. How to Reduce Current Consumption in Standby Mode AVDD P-ch ADCS0 Series resistor string AVSS (2) Input range for the ANI0 to ANI3 pins Be sure to keep the input voltage at ANI0 to ANI3 within its rating. If a voltage not lower than AVDD or not higher than AVSS (even within the absolute maximum rating) is input to a conversion channel, the conversion output of the channel becomes undefined. It may affect the conversion output of the other channels. (3) Conflict <1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading from ADCR0 Reading from ADCR0 takes precedence. After reading, the new conversion result is written to the ADCR0. <2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0 (ADM0) or Analog input channel specification register 0 (ADS0) Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion end interrupt request signal (INTAD0) is generated. 144 User's Manual U14643EJ1V0UM00 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) (4) Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D converter operation may be undefined. Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as annulling the first conversion result. (5) Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict, the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D converter operation has stopped, be sure to have done so by the time the next conversion result is complete. The conversion result readout timing is shown in Figures 11-8 and 11-9. Figure 11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) A/D conversion end A/D conversion end ADCR0 INTAD0 ADCS0 Normal conversion result Undefined value Normal conversion result read out A/D operation stopped Undefined value read out Figure 11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) A/D conversion end ADCR0 INTAD0 ADCS0 Normal conversion result A/D operation stopped Normal conversion result read out User's Manual U14643EJ1V0UM00 145 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) (6) Noise prevention To maintain a resolution of 8 bits, watch for noise to the AVDD and ANI0 to ANI3 pins. The higher the output impedance of the analog input source is, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 11-8. Figure 11-10. Analog Input Pin Treatment If noise not lower than AVDD or not higher than AVSS is likely to come to the AVDD pin, clamp the voltage at the pin by attaching a diode with a small VF (0.3 V or lower). VDD AVDD C = 100 to 1000 pF AVSS VSS (7) ANI0 to ANI3 The analog input pins (ANI0 to ANI3) are alternate-function pins. They are used also as port pins (P60 to P63). If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports; otherwise the conversion resolution may become lower. If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse to pins adjacent to the analog input pins during A/D conversion. (8) Interrupt request flag (ADIF0) Changing the content of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed, even when A/D conversion has not been completed for the new analog input. In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand. 146 User's Manual U14643EJ1V0UM00 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) Figure 11-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 (to begin conversion for ANIn) Rewriting to ADM0 (to begin conversion for ANIm) ADIF0 has been set, but conversion for ANIm has not been completed. A/D conversion ANIn ANIn ANIm ANIm ADCR0 ANIn ANIn ANIm ANIm INTAD0 Remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3 (9) AVDD pin The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3 input circuit. Therefore, if the application is designed to be switched to backup power, the AVDD pin must be supplied with the same voltage level as for the VDD pin, as shown in Figure 11-12. Figure 11-12. AVDD Pin Treatment VDD Main power source AVDD Backup capacitor VSS AVSS (10) Input impedance of the AVDD pin A series resistor string of several 10 k is connected across the AVDD and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher reference voltage error. User's Manual U14643EJ1V0UM00 147 [MEMO] 148 User's Manual U14643EJ1V0UM00 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter to convert an analog input to digital signals. This converter can control up to four channels of analog inputs (ANI0 to ANI3). A/D conversion can only be started by software. One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time an A/D session is completed. 12.2 10-Bit A/D Converter Configuration The A/D converter consists of the following hardware. Table 12-1. Configuration of 10-Bit A/D Converter Item Analog input Register 4 channels (ANI0 to ANI3) Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) Control register A/D converter mode register 0 (ADM0) Analog input channel specification register 0 (ADS0) Configuration User's Manual U14643EJ1V0UM00 149 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) Figure 12-1. Block Diagram of 10-Bit A/D Converter AVDD P-ch Sample and hold circuit ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 Selector Tap selector Voltage comparator AVSS AVSS Successive approximation register (SAR) Control circuit INTAD0 2 ADS01 ADS00 Analog input channel specification register 0 (ADS0) ADCS0 FR02 FR01 FR00 A/D conversion result register 0 (ADCR0) A/D converter mode register 0 (ADM0) Internal bus (1) Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB). Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0). (2) A/D conversion result register 0 (ADCR0) ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received from the successive approximation register is loaded into ADCR0, which is a 10-bit register the holds the result of A/D conversion. ADCR0 can be read with an 8-bit memory manipulation instruction. RESET input makes this register undefined. Caution When using the PD78F9116A as a flash memory version of the PD789101A, 789102A, or 789104A, or the PD78F9136A as a flash memory version of the PD789121A, 789122A, or 789124A, an 8-bit access can be made by ADCR0. However, it is performed only with the object file assembled by the PD789101A, 789102A, or 789104A, or by the PD789121A, 789122A, or 789124A, respectively. 150 User's Manual U14643EJ1V0UM00 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) (3) Sample and hold circuit The sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. (4) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. (5) Series resistor string The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against which analog inputs are compared. (6) ANI0 to ANI3 pins Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the analog signals for A/D conversion. Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage greater than AVDD or less than AVSS (even if within the absolute maximum rating) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. Furthermore, the conversion values for the other channels may also be affected. (7) AVSS pin The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as the VSS pin, even while the A/D converter is not being used. (8) AVDD pin The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same potential as the VDD pin, even while the A/D converter is not being used. User's Manual U14643EJ1V0UM00 151 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.3 Registers Controlling 10-Bit A/D Converter The following two registers are used to control the 10-bit A/D converter. * A/D converter mode register 0 (ADM0) * Analog input channel specification register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears the ADM0 to 00H. Figure 12-2. Format of A/D Converter Mode Register 0 Symbol <7> ADM0 ADCS0 6 0 5 4 3 2 0 1 0 0 0 Address FF80H After reset 00H R/W R/W FR02 FR01 FR00 ADCS0 0 1 Conversion disabled Conversion enabled A/D conversion control FR02 FR01 FR00 A/D conversion time selectionNote 1 At fX = 5.0-MHz operation At fCC = 4.0-MHz operation 144/fCC (36 s) 120/fCC (30 s) 96/fCC 72/fCC Note 2) Note 2 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 144/fX 120/fX 96/fX 72/fX 60/fX 48/fX (28.8 s) (24 s) (19.2 s) (14.4 s) (Setting prohibited (Setting prohibited (24 s) (18 s) (15 s) (Setting prohibitedNote 2) 60/fCC 48/fCC ) Other than above Setting prohibited Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least 14 s. 2. These bit combinations must not be used, as the A/D conversion time will fall below 14 s. Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined. 2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to 12.5 (5) Timing when A/D conversion result becomes undefined). Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 152 User's Manual U14643EJ1V0UM00 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) (2) Analog input channel specification register 0 (ADS0) The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H. Figure 12-3. Format of Analog Input Channel Specification Register 0 Symbol ADS0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF84H After reset 00H R/W R/W ADS01 ADS00 ADS01 ADS00 0 0 1 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 Analog input channel specification User's Manual U14643EJ1V0UM00 153 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.4 10-Bit A/D Converter Operation 12.4.1 Basic operation of 10-bit A/D converter <1> Select a channel for A/D conversion, using Analog input channel specification register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample and hold circuit. <3> After sampling continues for a certain period of time, the sample and hold circuit is put on hold to keep the input analog voltage until A/D conversion is completed. <4> Bit 9 of the successive approximation A/D conversion register (SAR) is set. The series resistor string voltage tap at the tap selector is set to half of AVDD. <5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. If the analog input voltage is higher than half of AVDD, the MSB of the SAR is left set. If it is lower than half of AVDD, the MSB is reset. <6> Bit 8 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows: * Bit 9 = 1: Three quarters of AVDD * Bit 9 = 0: One quarter of AVDD The tap voltage is compared with the analog input voltage. Bit 8 is set or reset according to the result of comparison. * Analog input voltage tap voltage: Bit 8 = 1 * Analog input voltage < tap voltage: Bit 8 = 0 <7> Comparison is repeated until bit 0 of the SAR is reached. <8> When comparison is completed for all of the 10 bits, a significant digital result is left in the SAR. This value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate an A/D conversion end interrupt request (INTAD0). Cautions 1. The A/D conversion value immediately after starting the A/D conversion operation may be undefined. 2. When in standby mode, the A/D converter stops operation. 154 User's Manual U14643EJ1V0UM00 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) Figure 12-4. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined Conversion result ADCR0 Conversion result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or Analog input channel specification register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if ADCS0 is set (1). RESET input makes A/D conversion result register 0 (ADCR0) undefined. 12.4.2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion result (A/D conversion result register 0 (ADCR0)) are represented by: ADCR0 = INT ( or (ADCR0 - 0.5) x INT( ): VIN: AVDD: AVDD 1,024 VIN < (ADCR0 + 0.5) x AVDD 1,024 VIN AVDD x 1,024 + 0.5) Function that returns the integer part of a parenthesized value Analog input voltage A/D converter supply voltage ADCR0: Value in A/D conversion result register 0 (ADCR0) Figure 12-5 shows the relationships between the analog input voltage and the A/D conversion result. User's Manual U14643EJ1V0UM00 155 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) Figure 12-5. Relationships between Analog Input Voltage and A/D Conversion Result 1,023 1,022 1,021 A/D conversion result (ADCR0) 3 2 1 0 1 1 3 2 5 3 2,048 1,024 2,048 1,024 2,048 1,024 2,043 1,022 2,045 1,023 2,047 2,048 1,024 2,048 1,024 2,048 1 Input voltage/AVDD 156 User's Manual U14643EJ1V0UM00 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.4.3 Operation mode of 10-bit A/D converter The 10-bit A/D converter is initially in the select mode. In this mode, Analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI3 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. * Software-started A/D conversion Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for a voltage applied to the analog input pin specified in Analog input channel specification register 0 (ADS0). Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to the ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the ongoing session of A/D conversion is discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written to ADM0 again during A/D conversion, A/D conversion is completely stopped. Figure 12-6. Software-Started A/D Conversion Rewriting ADM0 ADCS0 = 1 Rewriting ADM0 ADCS0 = 1 ADCS0 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion is discontinued; no conversion result is preserved. Stop ADCR0 ANIn ANIn ANIm INTAD0 Remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3 User's Manual U14643EJ1V0UM00 157 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.5 Cautions Related to 10-Bit A/D Converter (1) Current consumption in the standby mode When the A/D converter enters the standby mode, it stops its operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption. Figure 12-7 shows how to reduce the current consumption in the standby mode. Figure 12-7. How to Reduce Current Consumption in Standby Mode AVDD P-ch ADCS0 Series resistor string AVSS (2) Input range for the ANI0 to ANI3 pins Be sure to keep the input voltage at ANI0 to ANI3 within its rating. If a voltage not lower than AVDD or not higher than AVSS (even within the absolute maximum rating) is input a conversion channel, the conversion output of the channel becomes undefined. It may affect the conversion output of the other channels. (3) Conflict <1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading from ADCR0 Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0. <2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0 (ADM0) or Analog input channel specification register 0 (ADS0) Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion end interrupt request signal (INTAD0) is generated. 158 User's Manual U14643EJ1V0UM00 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) (4) Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D converter operation may be undefined. Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as annulling the first conversion result. (5) Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict, the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D converter operation has stopped, be sure to have done so by the time the next conversion result is complete. The conversion result readout timing is shown in Figures 12-8 and 12-9. Figure 12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) A/D conversion end A/D conversion end ADCR0 INTAD0 ADCS0 Normal conversion result Undefined value Normal conversion result read out A/D operation stopped Undefined value read out Figure 12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) A/D conversion end ADCR0 INTAD0 ADCS0 Normal conversion result A/D operation stopped Normal conversion result read out User's Manual U14643EJ1V0UM00 159 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) (6) Noise prevention To maintain a resolution of 10 bits, watch for noise to the AVDD and ANI0 to ANI3 pins. The higher the output impedance of the analog input source is, the larger the effect by noise is. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 12-10. Figure 12-10. Analog Input Pin Treatment If noise not lower than AVDD or not higher than AVSS is likely to come to the AVDD pin, clamp the voltage at the pin by attaching a diode with a small VF (0.3 V or lower). VDD AVDD C = 100 to 1000 pF AVSS VSS (7) ANI0 to ANI3 The analog input pins (ANI0 to ANI3) are alternate-function pins. They are used also as port pins (P60 to P63). If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports; otherwise, the conversion resolution may become lower. If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse to pins adjacent to the analog input pins during A/D conversion. (8) Interrupt request flag (ADIF0) Changing content of the A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed, even when A/D conversion has not been completed for the new analog input. In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand. 160 User's Manual U14643EJ1V0UM00 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) Figure 12-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 (to begin conversion for ANIn) Rewriting to ADM0 (to begin conversion for ANIm) ADIF0 has been set, but conversion for ANIm has not been completed. A/D conversion ANIn ANIn ANIm ANIm ADCR0 ANIn ANIn ANIm ANIm INTAD0 Remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3 (9) AVDD pin The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3 input circuit. Therefore, if the application is designed to be changed to backup power, the AVDD pin must be supplied with the same voltage level as for the VDD pin, as shown in Figure 12-10. Figure 12-12. AVDD Pin Treatment VDD AVDD Main power source Backup capacitor VSS AVSS (10) Input impedance of the AVDD pin A series resistor string of several 10 k is connected across the AVDD and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher reference voltage error. User's Manual U14643EJ1V0UM00 161 [MEMO] 162 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 13.1 Functions of Serial Interface 20 Serial interface 20 has the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. (2) Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex communication. Serial interface channel 0 contains a dedicated UART baud rate generator, enabling communication over a wide range of baud rates. It is also possible to define baud rates by dividing the frequency of the input clock pulse at the ASCK20 pin. It is recommended that ceramic/crystal oscillation be used for the system clock in the UART mode. Because the frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the baud rate generator, there may be problems in send/receive operations. (3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission) This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data lines (SI20 and SO20). As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time for data transmission than asynchronous serial interface mode. Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB or LSB, channel 0 can be connected to any device regardless of whether that device is designed for MSBfirst or LSB-first transmission. 3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having conventional clock synchronous serial interfaces, such as those of the 75XL, 78K, and 17K Series devices. 13.2 Serial Interface 20 Configuration Serial interface 20 consists of the following hardware. Table 13-1. Serial Interface 20 Configuration Item Register Transmit shift register 20 (TXS20) Receive shift register 20 (RXS20) Receive buffer register 20 (RXB20) Serial operating mode register 20 (CSIM20) Asynchronous serial interface mode register 20 (ASIM20) Asynchronous serial interface status register 20 (ASIS20) Baud rate generator control register 20 (BRGC20) Configuration Control register User's Manual U14643EJ1V0UM00 163 164 CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 SI20/P22/ RxD20 Port mode register (PM21) SO20/P21/ TxD20 User's Manual U14643EJ1V0UM00 Figure 13-1. Serial Interface 20 Block Diagram Internal bus Serial operation mode register 20 (CSIM20) Receive buffer register 20 (RXB20) Asynchronous serial interface status register 20 (ASIS20) PE20 FE20 OVE20 Asynchronous serial interface mode register 20 (ASIM20) TXE20 RXE20 PS201 PS200 CL20 SL20 Switching of the first bit Transmit shift register 20 (TXS20) Receive shift register 20 (RXS20) Reception shift clock Parity operation Stop bit addition 4 Parity operation Stop bit addition Reception data counter Reception enabled Reception clock Start bit detection Detection clock Reception detected Transmission and reception clock control Transmission data counter SL20, CL20, PS200, PS201 Data phase control Transmit shift clock CHAPTER 13 Selector CSIE20 DAP20 SERIAL INTERFACE 20 INTST20 INTSR20/INTCSI20 Baud rate generator note CSIE20 CSCK20 fX/2 to fX/28 4 SS20/P23/ CPT20/INTP0 SCK20/P20/ ASCK20 CSIE20 Clock phase control CSCK20 TPS203 TPS202 TPS201 TPS200 Internal clock output Baud rate generator control register 20 (BRGC20) External clock input Internal bus Note See Figure 13-2 for the configuration of the baud rate generator. Figure 13-2. Baud Rate Generator Block Diagram Reception detection clock Transmission shift clock 1/2 Transmission clock counter fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 SCK20/ASCK20/P20 Selector Reception shift clock 1/2 Selector Reception clock counter Selector CHAPTER 13 User's Manual U14643EJ1V0UM00 TXE20 RXE20 CSIE20 Reception detection 4 SERIAL INTERFACE 20 TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) Internal bus 165 CHAPTER 13 SERIAL INTERFACE 20 (1) Transmit shift register 20 (TXS20) TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bitserially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data to TXS20 triggers transmission. TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read. RESET input sets TXS20 to FFH. Caution Do not write to TXS20 during transmission. TXS20 and receive buffer register 20 (RXB20) are mapped at the same address, so that any attempt to read from TXS20 results in a value being read from RXB20. (2) Receive shift register 20 (RXS20) RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one entire byte has been received, RXS20 transfers the reception data to receive buffer register 20 (RXB20). RXS20 cannot be manipulated directly by a program. (3) Receive buffer register 20 (RXB20) RXB20 holds receive data. New receive data is transferred from receive shift register 0 (RXS20) per 1 byte of data received. When the data length is specified as seven bits, the receive data is sent to bits 0 to 6 of RXB20, in which the MSB is always fixed to 0. RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written to. RESET input makes RXB20 undefined. Caution RXB20 and transmit shift register 20 (TXS20) are mapped at the same address, so that any attempt to write to RXB20 results in a value being written to TXS20. (4) Transmission control circuit The transmission control circuit controls transmission. For example, it adds start, parity, and stop bits to the data in transmit shift register 20 (TXS20), according to the setting of asynchronous serial interface mode register 20 (ASIM20). (5) Reception control circuit The reception control circuit controls reception according to the setting of asynchronous serial interface mode register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected, asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error. 166 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 13.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following four registers. * Serial operating mode register 20 (CSIM20) * Asynchronous serial interface mode register 20 (ASIM20) * Asynchronous serial interface status register 20 (ASIS20) * Baud rate generator control register 20 (BRGC20) (1) Serial operating mode register 20 (CSIM20) CSIM20 is used to make the settings related to 3-wire serial I/O mode. CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Figure 13-3. Serial Operating Mode Register 20 Format Symbol <7> CSIM20 6 5 0 4 0 3 2 1 0 Address FF72H After reset 00H R/W R/W CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 1 Operation disabled Operation enabled 3-wire serial I/O mode operation control SSE20 0 1 SS20-pin selection Not used Used Function of the SS20/P23 pin Port function 0 1 Communication status Communication enabled Communication enabled Communication disabled DAP20 0 1 3-wire serial I/O mode data phase selection Outputs at the falling edge of SCK20. Outputs at the rising edge of SCK20. DIR20 0 1 MSB LSB First-bit specification CSCK20 0 1 3-wire serial I/O mode clock selection External clock pulse input to the SCK20 pin. Output of the dedicated baud rate generator CKP20 0 1 3-wire serial I/O mode clock phase selection Clock is low active, and SCK20 is at high level in the idle state Clock is high active, and SCK20 is at low level in the idle state Cautions 1. Bits 4 and 5 must be fixed to 0. 2. CSIM20 must be cleared to 00H, if UART mode is selected. User's Manual U14643EJ1V0UM00 167 CHAPTER 13 SERIAL INTERFACE 20 (2) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Figure 13-4. Asynchronous Serial Interface Mode Register 20 Format Symbol <7> ASIM20 <6> 5 4 3 2 SL20 1 0 0 0 Address FF70H After reset 00H R/W R/W TXE20 RXE20 PS201 PS200 CL20 TXE20 0 1 Send operation stop Send operation enable Transmit operation control RXE20 0 1 Receive operation stop Receive operation enable Receive operation control PS201 PS200 0 0 1 1 0 1 0 1 No parity Parity bit specification Always add 0 parity at transmission. Parity check is not performed at reception (No parity error is generated). Odd parity Even parity CL20 0 1 7 bits 8 bits Transmit data character length specification SL20 0 1 1 bit 2 bits Transmit data stop bit length Cautions 1. Bits 0 and 1 must be fixed to 0. 2. If 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H. 3. Switch operating modes after halting a serial transmit/receive operation. 168 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 Table 13-2. Serial Interface 20 Operating Mode Settings (1) Operation stopped mode ASIM20 CSIM20 PM22 P21 PM21 P21 PM20 P20 First Shift P22/SI20/RxD20 P21/SO20/TxD20 P20/SCK20/ Bit Clock Pin Function Pin Function ASCK20 Pin Function -- -- P22 P21 P20 TXE20 RXE20 CSIE20 DIR20 CSCK20 0 0 0 x x xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 Other than above Setting prohibited (2) 3-wire serial I/O mode ASIM20 CSIM20 PM22 P22 PM21 P21 PM20 P20 First Shift P22/SI20/RxD20 P21/SO20/TxD20 P20/SCK20/ Bit Clock Pin Function Pin Function ASCK20 Pin Function MSB External SI20Note 2 clock Internal clock LSB External clock Internal clock Setting prohibited SCK20 SCK20 (CMOS output) input SCK20 output SCK20 input SCK20 output TXE20 RXE20 CSIE20 DIR20 CSCK20 0 0 1 0 0 xNote 1 xNote 2 0 1 1 x 1 x 1 1 0 1 1 0 1 1 0 Other than above (3) Asynchronous serial interface mode ASIM20 CSIM20 PM22 P22 PM21 P21 PM20 P20 First Shift P22/SI20/RxD20 P21/SO20/TxD20 P20/SCK20/ Bit Clock Pin Function Pin Function ASCK20 Pin Function LSB External P22 clock Internal clock External RD20 clock Internal clock External clock Internal clock Setting prohibited P21 TxD20 ASCK20 (CMOS output) input P20 TXE20 RXE20 CSIE20 DIR20 CSCK20 1 0 0 0 0 xNote 1 xNote 1 0 1 1 x xNote 1 xNote 1 0 1 0 0 0 1 x xNote 1 xNote 1 1 x ASCK20 input P20 xNote 1 xNote 1 1 1 0 0 0 1 x 0 1 1 x TxD20 ASCK20 (CMOS output) input P20 xNote 1 xNote 1 Other than above Notes 1. These pins can be used for port functions. 2. When only transmission is used, these pins can be used as P22 (CMOS input/output). Remark x: don't care. User's Manual U14643EJ1V0UM00 169 CHAPTER 13 SERIAL INTERFACE 20 (3) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is used to display the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode. RESET input clears ASIS20 to 00H. Figure 13-5. Asynchronous Serial Interface Status Register 20 Format Symbol ASIS20 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FF71H After reset 00H R/W R PE20 FE20 OVE20 PE20 0 1 No parity error has occurred. Parity error flag A parity error has occurred (parity mismatch in transmission data). FE20 0 1 No framing error has occurred. Flaming error flag A framing error has occurred (no stop bit detected).Note 1 OVE20 0 1 No overrun error has occurred. Overrun error flag An overrun error has occurred.Note 2 (Before data was read from the reception buffer register, the subsequent reception sequence was completed.) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit. 2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error is generated. 170 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (4) Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Figure 13-6. Baud Rate Generator Control Register 20 Format Symbol BRGC20 7 6 5 4 3 0 2 0 1 0 0 0 Address FF73H After reset 00H R/W R/W TPS203 TPS202 TPS201 TPS200 TPS203 TPS202 TPS201 TPS200 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fX/2 (2.5 MHz) fX/22 (1.25 MHz) 3-bit counter source clock selection n 1 2 3 4 5 6 7 8 fX/23 (625 kHz) fX/24 (313 kHz) fX/25 fX/26 (156 kHz) (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) External clock pulse input at the ASCK20 pin Setting prohibited Note - Other than above Note An external clock can only be used in UART mode. Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during communication operations. 2. Be sure not to select n = 1 during operation at fX = 5.0 MHz because n = 1 exceeds the baud rate limit. 3. When the external input clock is selected, set port mode register 2 (PM2) in input mode. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. n: Value specified in TPS200 to TPS203 (1 n 8) 3. Values in parentheses apply to operation with fX = 5.0 MHz. User's Manual U14643EJ1V0UM00 171 CHAPTER 13 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK20 pin. (a) Generation of baud rate transmit/receive clock by means of system clock The transmit/receive clock is generated by scaling the system clock. The baud rate generated from the system clock is estimated by using the following expression. [Baud rate] = fX 2n + 1 x8 [Hz] fX: System clock oscillation frequency (ceramic/crystal oscillation) n: Values in Figure 13-6 specified by the setting in TPS200 to TPS203 (2 n 8) Table 13-3. Example of Relationship between System Clock and Baud Rate Baud Rate (bps) n BRGC20 Set Value Error (%) fX = 5.0 MHz 1,200 2,400 4,800 9,600 19,200 38,400 76,800 8 7 6 5 4 3 2 70H 60H 50H 40H 30H 20H 10H 1.73 fX = 4.9152 MHz 0 172 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate generated from the clock input from the ASCK20 pin is estimated by using the following expression. [Baud rate] = fASCK 16 [Hz] fASCK: Frequency of clock pulse received at the ASCK20 pin Table 13-4. Relationship between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) Baud Rate (bps) 75 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 ASCK20 Pin input Frequency (kHz) 1.2 2.4 4.8 9.6 19.2 38.4 76.8 153.6 307.2 500.0 614.4 User's Manual U14643EJ1V0UM00 173 CHAPTER 13 SERIAL INTERFACE 20 13.4 Serial Interface 20 Operation Serial interface 20 provides the following three types of modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode 13.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed, therefore, the power consumption can be reduced. The P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports. (1) Register setting Operation stop mode is set by serial operating mode register 20 (CSIM20) and asynchronous serial interface mode register 20 (ASIM20). (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Symbol <7> 6 5 0 4 0 3 2 1 0 Address FF72H After reset 00H R/W R/W CSIM20 CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 1 Operation disable Operation enable Operation control in 3-wire serial I/O mode Caution Be sure to set bits 4 and 5 to 0. 174 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol ASIM20 <7> <6> 5 4 3 2 1 0 0 0 Address FF70H After reset 00H R/W R/W TXE20 RXE20 PS201 PS200 CL20 SL20 TXE20 0 1 Transmit operation stop Transmit operation enable Transmit operation control RXE20 0 1 Receive operation stop Receive operation enable Receive operation control Caution Be sure to set bits 0 and 1 to 0. User's Manual U14643EJ1V0UM00 175 CHAPTER 13 SERIAL INTERFACE 20 13.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. This device incorporates a UART-dedicated baud rate generator that enables communication at the desired transfer rate from many options. In addition, the baud rate can also be defined by dividing the input clock to the ASCK pin. The UART-dedicated baud rate generator also can output the 31.25-kbps baud rate that complies with the MIDI standard. It is recommended that the ceramic/crystal oscillation be used for the system clock in the UART mode. Because the frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the baud rate generator, there may be problems in send/receive operations. (1) Register setting The UART mode is set by serial operating mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), and baud rate generator control register 20 (BRGC20). 176 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (a) Serial operating mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Set 00H to CSIM20 when UART mode is selected. Symbol <7> CSIM20 6 5 0 4 0 3 2 1 0 Address FF72H After reset 00H R/W R/W CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 1 Operation disabled Operation enabled 3-wire serial I/O mode operation control SSE20 0 1 SS20-pin selection Not used Used Function of the SS20/P23 pin Port function 0 1 Communication status Communication enabled Communication enabled Communication disabled DAP20 0 1 3-wire serial I/O mode data phase selection Outputs at the falling edge of SCK20. Outputs at the rising edge of SCK20. DIR20 0 1 MSB LSB First-bit specification CSCK20 0 1 3-wire serial I/O mode clock selection External clock pulse input to the SCK20 pin. Output of the dedicated baud rate generator CKP20 0 1 3-wire serial I/O mode clock phase selection Clock is low active, and SCK20 is high level in the idle state Clock is high active, and SCK20 is low level in the idle state Caution Bits 4 and 5 must be fixed to 0. User's Manual U14643EJ1V0UM00 177 CHAPTER 13 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol ASIM20 <7> <6> 5 4 3 2 1 0 0 0 Address FF70H After reset 00H R/W R/W TXE20 RXE20 PS201 PS200 CL20 SL20 TXE20 0 1 Transmit operation stop Transmit operation enable Transmit operation control RXE20 0 1 Receive operation stop Receive operation enable Receive operation control PS201 PS200 0 0 0 1 No parity Parity bit specification Always add 0 parity at transmission. Parity check is not performed at reception (No parity error is generated). Odd parity Even parity 1 1 0 1 CL20 0 1 7 bits 8 bits Character length specification SL20 0 1 1 bit 2 bits Transmit data stop bit length specification Cautions 1. Be sure to set bits 0 and 1 to 0. 2. Switch operating modes after halting the serial transmit/receive operation. 178 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS20 to 00H. Symbol ASIS20 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FF71H After reset 00H R/W R PE20 FE20 OVE20 PE20 0 1 Parity error not generated Parity error flag Parity error generated (when the parity of transmit data does not match.) FE20 0 1 Framing error not generated Flaming error flag Framing error generated (when stop bit is not detected.)Note 1 OVE20 0 1 Overrun error not generated Overrun error flag Overrun error generatedNote 2 (when the next receive operation is completed before the data is read from the receive buffer register.) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit. 2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error is generated. User's Manual U14643EJ1V0UM00 179 CHAPTER 13 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Symbol 7 6 5 4 3 0 2 0 1 0 0 0 Address FF73H After reset 00H R/W R/W BRGC20 TPS203 TPS202 TPS201 TPS200 TPS203 TPS202 TPS201 TPS200 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 fX/24 (625 kHz) (313 kHz) 3-bit counter source clock selection n 1 2 3 4 5 6 7 8 - fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 fX/28 (39.1 kHz) (19.5 kHz) Input clock from external to ASCK20 pin. Setting prohibited Other than above Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during communication operation. 2. Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds the baud rate limit. 3. When the external input clock is selected, set port mode register 2 (PM2) to input mode. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. n: Values specified by the setting in TPS200 to TPS203 (1 n 8) 3. Values in parentheses apply to operation with fX = 5.0 MHz. 180 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK20 pin. (i) Generation of baud rate transmit/receive clock by means of system clock The transmit/receive clock is generated by scaling the system clock. The baud rate generated from the system clock is estimated by using the following expression. [Baud rate] = fx 2n + 1 x 8 [Hz] fX: System clock oscillation frequency (ceramic/crystal oscillation) n: Values in the above table specified by the setting in TPS200 to TPS203 (2 n 8) Table 13-5. Example of Relationship between System Clock and Baud Rate Baud Rate (bps) n BRGC20 Set Value Error (%) fX = 5.0 MHz 1,200 2,400 4,800 9,600 19,200 38,400 76,800 8 7 6 5 4 3 2 70H 60H 50H 40H 30H 20H 10H 1.73 fX = 4.9152 MHz 0 User's Manual U14643EJ1V0UM00 181 CHAPTER 13 SERIAL INTERFACE 20 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate generated from the clock input from the ASCK20 pin is estimated by using the following expression. [Baud rate] = fASCK 16 [Hz] fASCK: Frequency of clock input to ASCK20 pin. Table 13-6. Relationship between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) Baud Rate (bps) 75 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 ASCK20 Pin input Frequency (kHz) 1.2 2.4 4.8 9.6 19.2 38.4 76.8 153.6 307.2 500.0 614.4 182 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 13-7. One data frame consists of a start bit, character bits, parity bit and stop bit(s). The specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out using asynchronous serial interface mode register 20 (ASIM20). Figure 13-7. Asynchronous Serial Interface Transmit/Receive Data Format One data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit * Start bits .................. * Character bits .......... * Parity bits ................. * Stop bits ................... 1 bit 7 bits/8 bits Even parity/odd parity/0 parity/no parity 1 bit/2 bits When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". The serial transfer rate is selected by means of ASIM20 and baud rate generator control register 20 (BRGC20). If a serial data receive error is generated, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (ASIS20). User's Manual U14643EJ1V0UM00 183 CHAPTER 13 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected. (i) Even parity * At transmission The transmission operation is controlled so that the number of bits with a value of "1" in the transmit data including parity bit may be even. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data: 1 The number of bits with a value of "1" is an even number in transmit data: 0 * At reception The number of bits with a value of "1" in the receive data including parity bit is counted, and if the number is odd, a parity error is generated. (ii) Odd parity * At transmission Conversely to even parity, the transmission operation is controlled so that the number of bits with a value of "1" in the transmit data including parity bit may be odd. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data: 0 The number of bits with a value of "1" is an even number in transmit data: 1 * At reception The number of bits with a value of "1" in the receive data including parity bit is counted, and if the number is even, a parity error is generated. (iii) 0 Parity When transmitting, the parity bit is set to "0" irrespective of the transmit data. At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective of whether the parity bit is set to "0" or "1". (iv) No parity A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error is not generated. 184 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit, parity bit and stop bit are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated. Figure 13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 STOP TxD20 (Output) START INTST20 D0 D1 D2 D6 D7 Parity (b) Stop bit length: 2 TxD20 (Output) START INTST20 D0 D1 D2 D6 D7 Parity STOP Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a transmit operation. If ASIM20 register is rewritten during transmission, subsequent transmission may not be performed (the normal state is restored by RESET input). It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set by INTST20. User's Manual U14643EJ1V0UM00 185 CHAPTER 13 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by ASIM20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. If the RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. When one frame of data has been received, the receive data in the shift register is transferred to receive buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated. If an error is generated, the receive data in which the error was generated is still transferred to RXB20, and INTSR20 is generated. If the RXE20 bit is reset (0) during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are not changed, and INTSR20 is not generated. Figure 13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing STOP RxD20 (Input) START INTSR20 D0 D1 D2 D6 D7 Parity Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If RXB20 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. 186 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in asynchronous serial interface status register 20 (ASIS20). Receive error causes are shown in Table 13-7. It is possible to determine what kind of error was generated during reception by reading the contents of ASIS20 in the reception error interrupt servicing (see Figures 13-9 and 13-10). The contents of ASIS20 are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). Table 13-7. Receive Error Causes Receive Errors Parity error Framing error Overrun error Cause Transmission-time parity specification and reception data parity do not match Stop bit not detected Reception of next data is completed before data is read from receive register buffer Figure 13-10. Receive Error Timing (a) Parity error generated STOP RxD20 (Input) START INTSR20 D0 D1 D2 D6 D7 Parity (b) Framing error or overrun error generated STOP RxD20 (Input) START INTSR20 D0 D1 D2 D6 D7 Parity Cautions 1. The contents of the ASIS20 register are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next data. To ascertain the error contents, read ASIS20 before reading RXB20. 2. Be sure to read receive buffer register 20 (RXB20) even if a receive error is generated. If RXB20 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. User's Manual U14643EJ1V0UM00 187 CHAPTER 13 SERIAL INTERFACE 20 (3) UART mode cautions (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission. (b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during reception, receive buffer register 20 (RXB20) and receive completion interrupt 20 (INTSR20) are as follows. RxD20 Pin Parity RXB20 INTSR20 <1> <3> <2> When RXE20 is set to 0 at a time indicated by <1>, RXB20 holds the previous data and does not generate INTSR20. When RXE20 is set to 0 at a time indicated by <2>, RXB20 renews the data and does not generate INTSR20. When RXE20 is set to 0 at a time indicated by <3>, RXB20 renews the data and generates INTSR20. 188 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 13.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc. that incorporate a conventional synchronous clocked serial interface, such as the 75XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input (SI20). (1) Register setting 3-wire serial I/O mode settings are performed using serial operating mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), and baud rate generator control register 20 (BRGC20). (a) Serial operating mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Symbol <7> CSIM20 6 5 0 4 0 3 2 1 0 Address FF72H After reset 00H R/W R/W CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 1 Operation disabled Operation enabled 3-wire serial I/O mode operation control SSE20 0 1 SS20-pin selection Not used Used Function of the SS20/P23 pin Port function 0 1 Communication status Communication enabled Communication enabled Communication disabled DAP20 0 1 3-wire serial I/O mode data phase selection Outputs at the falling edge of SCK20. Outputs at the rising edge of SCK20. DIR20 0 1 MSB LSB First-bit specification CSCK20 0 1 3-wire serial I/O mode clock selection External clock pulse input to the SCK20 pin. Output of the dedicated baud rate generator CKP20 0 1 3-wire serial I/O mode clock phase selection Clock is low active, and SCK20 is at high level in the idle state Clock is high active, and SCK20 is at low level in the idle state Caution Bits 4 and 5 must be fixed to 0. User's Manual U14643EJ1V0UM00 189 CHAPTER 13 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. When the 3-wire serial I/O mode is selected, 00H must be set to ASIM20. Symbol ASIM20 <7> <6> 5 4 3 2 1 0 0 0 Address FF70H After reset 00H R/W R/W TXE20 RXE20 PS201 PS200 CL20 SL20 TXE20 0 1 Transmit operation stop Transmit operation enable Transmit operation control RXE20 0 1 Receive operation stop Receive operation enable Receive operation control PS201 PS200 0 0 0 1 No parity Parity bit specification Always add 0 parity at transmission. Parity check is not performed at reception (No parity error is generated). Odd parity Even parity 1 1 0 1 CL20 0 1 7 bits 8 bits Character length specification SL20 0 1 1 bit 2 bits Transmit data stop bit length specification Cautions 1. Be sure to set bits 0 and 1 to 0. 2. Switching operation modes must be performed after the serial transmit/receive operation is halted. 190 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Symbol 7 6 5 4 3 0 2 0 1 0 0 0 Address FF73H After reset 00H R/W R/W BRGC20 TPS203 TPS202 TPS201 TPS200 TPS203 TPS202 TPS201 TPS200 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fX/2 (2.5 MHz) fX/22 fX/23 (1.25 MHz) (625 kHz) 3-bit counter source clock selection n 1 2 3 4 5 6 7 8 fX/24 (313 kHz) fX/25 (156 kHz) fX/26 fX/27 (78.1 kHz) (39.1 kHz) fX/28 (19.5 kHz) Setting prohibited Other than above Cautions 1. When writing to BRGC20 is performed during a communication operation, the baud rate generator output is disrupted and communication cannot be performed normally. Be sure not to write to BRGC20 during communication operation. 2. Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds the baud rate limit. 3. When the external input clock is selected, set port mode register 2 (PM2) in input mode. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. n: Values specified by TPS200 to TPS203 (1 n 8) 3. Values in parentheses apply to operation with fX = 5.0 MHz. If the internal clock is used as the serial clock for the 3-wire serial I/O mode, set the TPS200 to TPS203 bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula. When the serial clock is input from off-chip, setting BRGC20 is not necessary. Serial clock frequency = fx 2n + 1 [Hz] fX: System clock oscillation frequency (ceramic/crystal oscillation) n: Values in the above table specified by the setting in TPS200 to TPS203 (1 n 8) User's Manual U14643EJ1V0UM00 191 CHAPTER 13 SERIAL INTERFACE 20 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. The transmit shift register (TXS20/SIO20) and receive shift register (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20 latch and output from the SO20 pin. Also, receive data input to the SI0 pin is latched in the receive buffer register (RXB20/ SIO20) on the rise of SCK20. At the end of an 8-bit transfer, the operation of TXS20/SIO20 or RXS20 stops automatically, and the interrupt request signal (INTCSI20) is generated. Figure 13-11. 3-Wire Serial I/O Mode Timing (1/7) (i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 Note The value of the last bit previously output is output. 192 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (2/7) (ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The value of the last bit previously output is output. (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) SS20 SIO20 Write SCK20 1 2 3 4 5 6 7 8 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Hi-Z Note 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 Hi-Z INTCSI20 Notes 1. The value of the last bit previously output is output. 2. DO0 is output until SS20 rises. When SS20 is high, SO20 is in a high-impedance state. User's Manual U14643EJ1V0UM00 193 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (3/7) (iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 (v) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 SIO20 Write (master)Note SI20 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20. 194 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (4/7) (vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 SIO20 Write (master)Note 1 SI20 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Hi-Z DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2 Hi-Z INTCSI20 Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20. 2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state. (vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 User's Manual U14643EJ1V0UM00 195 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (5/7) (viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 SIO20 Write (master)Note SI20 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20. (ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1) SS20 SIO20 Write SCK20 SIO20 Write (master)Note 1 SI20 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Hi-Z DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2 Hi-Z INTCSI20 Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20. 2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state. 196 User's Manual U14643EJ1V0UM00 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (6/7) (x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SO20 Note DO7 DO6 DO5 DOI4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 Note The value of the last bit previously output is output. (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Note DO7 DO6 DO5 DOI4 DO3 DO2 DO1 DO0 INTCSI20 Note The value of the last bit previously output is output. User's Manual U14643EJ1V0UM00 197 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (7/7) (xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 1 2 3 4 5 6 7 8 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Hi-Z Note 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 Hi-Z INTCSI20 Notes 1. The value of the last bit previously output is output. 2. DO0 is output until SS20 rises. When SS20 is high, SO20 is in a high-impedance state. (3) Transfer start Serial transfer is started by setting transfer data to the transmission shift register (TXS20/SIO20) when the following two conditions are satisfied. * Serial operation mode register 20 (CSIM20) bit 7 (CSIE20) = 1 * Internal serial clock is stopped or SCK20 is a high level after 8-bit serial transfer. Caution If CSIE20 is set to "1" after data write to TXS20/SIO20, transfer does not start. A termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (INTCSI20). 198 User's Manual U14643EJ1V0UM00 CHAPTER 14 MULTIPLIER 14.1 Multiplier Function The multiplier has the following function: * Calculation of 8 bits x 8 bits = 16 bits 14.2 Multiplier Configuration (1) 16-bit multiplication result storage register 0 (MUL0) This register stores the 16-bit result of multiplication. This register holds the result of multiplication after 16 CPU clocks have elapsed. MUL0 is set with a 16-bit memory manipulation instruction. RESET input makes this register undefined. Caution Although this register is manipulated with a 16-bit memory manipulation instruction, it can be also manipulated with an 8-bit memory manipulation instruction. When using an 8-bit memory manipulation instruction, however, access the register by means of direct addressing. (2) Multiplication data registers A and B (MRA0 and MRB0) These are 8-bit multiplication data storage registers. The multiplier multiplies the values of MRA0 and MRB0. MRA0 and MRB0 are set with a 1-bit or 8-bit memory manipulation instructions. RESET input makes these registers undefined. Figure 14-1 shows the block diagram of the multiplier. User's Manual U14643EJ1V0UM00 199 CHAPTER 14 MULTIPLIER Figure 14-1. Block Diagram of Multiplier Internal bus Multiplication data register A (MRA0) Multiplication data register B (MRB0) Counter value Selector 3 3-bit counter Start Counter output CPU clock Clear 16-bit adder 16-bit multiplication result storage register 0 (Master) (MUL0) 16-bit multiplication result storage register 0 (Slave) MULST0 Multiplier control register 0 (MULC0) Internal bus Reset 200 User's Manual U14643EJ1V0UM00 CHAPTER 14 MULTIPLIER 14.3 Multiplier Control Register The multiplier is controlled by the following register: * Multiplier control register (MULC0) MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier. MULC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 14-2. Multiplier Control Register 0 Format Symbol MULC0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MULST0 Address FFD2H After reset 00H R/W R/W MULST0 0 1 Multiplier operation start control bit Stops operation after resetting counter to 0. Enables operation Operating status of multiplier Operation stops Operation in progress Caution Be sure to set bits 1 to 7 to 0. User's Manual U14643EJ1V0UM00 201 CHAPTER 14 MULTIPLIER 14.4 Multiplier Operation The multiplier of the PD789104A/114A/124A/134A Subseries can execute the calculation of 8 bits x 8 bits = 16 bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H. <1> Counting is started by setting MULST0. <2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value is incremented by one. <3> If MULST0 is cleared when the counter value is 111B, the operation is stopped. At this time, MUL0 holds the data. <4> While MULST0 is low, the counter and slave are cleared. Figure 14-3. Multiplier Operation Timing CPU clock MRA0 MRB0 MULST0 AA D3 Counter Selector output MUL0 (Master) (Slave) 000B 00AA 001B 0154 00AA 010B 0000 011B 0000 100B 0AA0 101B 0000 110B 2A80 111B 5500 000B 00AA 8C1E 0000 01FE 01FE 01FE 0C9E 0C9E 0C9E 371E 371E 0000 00AA 01FE 01FE 01FE 0C9E 202 User's Manual U14643EJ1V0UM00 CHAPTER 15 INTERRUPT FUNCTIONS 15.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. The non-maskable interrupt has one source of interrupt from the watchdog timer. (2) Maskable interrupt These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in Table 15-1. A standby release signal is generated. The maskable interrupt has three sources of external interrupts and six sources of internal interrupts. 15.2 Interrupt Sources and Configuration There are total of 10 non-maskable and maskable interrupts in the interrupt sources (see Table 15-1). User's Manual U14643EJ1V0UM00 203 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-1. Interrupt Source List Interrupt Type PriorityNote 1 Name Non-maskable -- INTWDT Interrupt Source Trigger Watchdog timer overflow (watchdog timer mode 1 selected) Watchdog timer overflow (interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH End of serial interface 20 UART reception Internal 000CH (B) Internal Internal /External Vector Basic Table Configuration Address TypeNote 2 0004H (A) Maskable 0 INTWDT (B) 1 2 3 4 INTP0 INTP1 INTP2 INTSR20 (C) INTCSI20 End of serial interface 20 3-wire transfer 5 INTST20 End of serial interface 20 UART transmission Generation of 8-bit timer/event counter 80 match signal Generation of 16-bit timer 20 match signal A/D conversion completion signal 000EH 6 INTTM80 0010H 7 INTTM20 0012H 8 INTAD0 0014H Notes 1. Priority is the priority applicable when two or more maskable interrupts are simultaneously generated. 0 is the highest priority and 8 is the lowest priority. 2. Basic configuration types A to C correspond to A to C in Figure 15-1. Remark As the interrupt source of the watchdog timer (INTWDT), either a non-maskable interrupt or a maskable interrupt (internal) can be selected. 204 User's Manual U14643EJ1V0UM00 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Interrupt request Vector table address generator Standby release signal (B) Internal maskable interrupt Internal bus MK IE Interrupt request IF Vector table address generator Standby release signal (C) External maskable interrupt Internal bus External interrupt mode register (INTM0) MK IE Interrupt request Edge detector IF Vector table address generator Standby release signal IF: IE: Interrupt request flag Interrupt enable flag MK: Interrupt mask flag User's Manual U14643EJ1V0UM00 205 CHAPTER 15 INTERRUPT FUNCTIONS 15.3 Interrupt Function Control Registers The following four registers are used to control the interrupt functions. * Interrupt request flag registers (IF0, IF1) * Interrupt mask flag registers (MK0, MK1) * External interrupt mode register (INTM0) * Program status word (PSW) Table 15-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. Table 15-2. Flags Corresponding to Interrupt Request Signal Interrupt Request Signal Name INTWDT INTP0 INTP1 INTP2 INTSR20/INTCSI20 INTST20 INTTM80 INTTM20 INTAD0 TMIF4 PIF0 PIF1 PIF2 SRIF20 STIF20 TMIF80 TMIF20 ADIF0 Interrupt Request Flag TMMK4 PMK0 PMK1 PMK2 SRMK20 STMK20 TMMK80 TMMK20 ADMK0 Interrupt Mask Flag 206 User's Manual U14643EJ1V0UM00 CHAPTER 15 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0, IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input. IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 15-2. Interrupt Request Flag Register Format Symbol <7> IF0 <6> <5> <4> <3> <2> PIF1 <1> <0> Address FFE0H After reset 00H R/W R/W TMIF20 TMIF80 STIF20 SRIF20 PIF2 PIF0 TMIF4 Symbol IF1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> ADIF0 Address FFE1H After reset 00H R/W R/W xxIFx 0 1 Interrupt request flag No interrupt request signal is generated Interrupt request signal is generated; Interrupt request state Cautions 1. TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer. If the watchdog timer mode 1 and 2 are used, set the TMIF4 flag to 0. 2. Because port 2 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. User's Manual U14643EJ1V0UM00 207 CHAPTER 15 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0, MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 15-3. Interrupt Mask Flag Register Format Symbol MK0 <7> <6> <5> <4> <3> <2> <1> <0> Address FFE4H After reset FFH R/W R/W TMMK20 TMMK80 STMK20 SRMK20 PMK2 PMK1 PMK0 TMMK4 Symbol MK1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 <0> ADMK0 Address FFE5H After reset FFH R/W R/W xxMKx 0 1 Interrupt servicing enabled Interrupt servicing disabled Interrupt servicing control Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1 and 2, its value becomes undefined. 2. Because port 2 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 208 User's Manual U14643EJ1V0UM00 CHAPTER 15 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 15-4. External Interrupt Mode Register 0 Format Symbol INTM0 7 6 5 4 3 2 1 0 0 0 Address FFECH After reset 00H R/W R/W ES21 ES20 ES11 ES10 ES01 ES00 ES21 ES20 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP2 valid edge selection ES11 ES10 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 valid edge selection ES01 ES00 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP0 valid edge selection Cautions 1. Be sure to set bits 0 and 1 to 0. 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag (xxMKx = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (xxIFx = 0), then clear the interrupt mask flag (xxMKx = 0), which will enable interrupts. User's Manual U14643EJ1V0UM00 209 CHAPTER 15 INTERRUPT FUNCTIONS (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped. This register can be read/written in 8-bit units and can carry out operations using a bit manipulation and dedicated instructions (EI, DI). When a vectored interrupt request is acknowledged, PSW is automatically saved into a stack, and the IE flag is reset to 0. It is reset from the stack by the RETI and POP PSW instructions. RESET input sets PSW to 02H. Figure 15-5. Program Status Word Configuration Symbol PSW 7 IE 6 Z 5 0 4 AC 3 0 2 0 1 1 0 CY After reset 02H Used when normal instruction is executed IE 0 1 Disable Enable Interrupt acknowledge enable/disable 210 User's Manual U14643EJ1V0UM00 CHAPTER 15 INTERRUPT FUNCTIONS 15.4 Interrupt Processing Operation 15.4.1 Non-maskable interrupt request acknowledgement operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches. Figure 15-6 shows the flowchart from non-maskable interrupt request generation to acknowledgement. Figure 15-7 shows the timing of non-maskable interrupt request acknowledgement. Figure 15-8 shows the acknowledgement operation if multiple non-maskable interrupts are generated. Caution During a non-maskable interrupt service program execution, do not input another non-maskable interrupt request; if it is input, the service program will be interrupted and the new interrupt request will be acknowledged. User's Manual U14643EJ1V0UM00 211 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement Start WDTM4 = 1 (watchdog timer mode is selected) Yes No Interval timer WDT overflows Yes WDTM3 = 0 No (non-maskable interrupt is selected) Yes Interrupt request is generated Interrupt processing is started No Reset processing WDTM: WDT: Watchdog timer mode register Watchdog timer Figure 15-7. Timing of Non-Maskable Interrupt Request Acknowledgement Save PSW and PC, and jump to interrupt processing CPU processing Instruction Instruction Interrupt processing program TMIF4 Figure 15-8. Acknowledging Non-Maskable Interrupt Request Main routine First interrupt processing NMI request (first) NMI request (second) Second interrupt processing 212 User's Manual U14643EJ1V0UM00 CHAPTER 15 INTERRUPT FUNCTIONS 15.4.2 Maskable interrupt request acknowledgement operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt processing after a maskable interrupt request has been generated is shown in Table 15-3. Refer to Figures 15-10 and 15-11 for the interrupt request acknowledgement timing. Table 15-3. Time from Generation of Maskable Interrupt Request to Processing Minimum Time 9 clocks Maximum TimeNote 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instruction. Remark 1 clock: 1 (fCPU: CPU clock) fCPU When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. A pending interrupt is acknowledged when the status where it can be acknowledged is set. Figure 15-9 shows the algorithm of acknowledging interrupt requests. When a maskable interrupt request is acknowledged, the contents of PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt processing, use the RETI instruction. User's Manual U14643EJ1V0UM00 213 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-9. Interrupt Acknowledgement Program Algorithm Start No xxIF = 1 ? Yes (Interrupt request generated) No xxMK = 0 ? Yes Interrupt request pending No IE = 1 ? Yes Vectored interrupt processing Interrupt request pending xxIF: xxMK: IE: Interrupt request flag Interrupt mask flag Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable) 214 User's Manual U14643EJ1V0UM00 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Interrupt Request Acknowledgement Timing (Example of MOV A,r) 8 clocks Clock CPU MOV A,r Save PSW and PC, jump to interrupt processing Interrupt processing program Interrupt If an interrupt request flag (xxIF) is set before an instruction clock n (n = 4 to 10) under execution becomes n- 1, the interrupt is acknowledged after the instruction under execution is complete. Figure 15-10 shows an example of the interrupt request acknowledgement timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgement processing is performed after the MOV A,r instruction is completed. Figure 15-11. Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Generated at the Last Clock During Instruction Execution) 8 clocks Clock CPU NOP MOV A,r Save PSW and PC, jump to interrupt processing Interrupt processing program Interrupt If an interrupt request flag (xxIF) is set at the last clock of the instruction, the interrupt acknowledgement processing starts after the next instruction is executed. Figure 15-11 shows an example of the interrupt acknowledgement timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is executed, and then the interrupt acknowledgement processing is performed. Caution Interrupt requests are reserved while the interrupt request flag register (IF0, IF1) or the interrupt mask flag register (MK0, MK1) is being accessed. 15.4.3 Multiple interrupt processing Multiple interrupt processing in which another interrupt is acknowledged while an interrupt is being processed can be processed by priority. When the priority is controlled by the default priority and two or more interrupts are generated at once, interrupt processing is performed according to the priority assigned to each interrupt request in advance (refer to Table 15-1). User's Manual U14643EJ1V0UM00 215 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-12. Example of Multiple Interrupts Example 1. Multiple interrupts are acknowledged Main processing INTxx processing INTyy processing EI IE = 0 EI IE = 0 INTxx INTyy RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and a multiple interrupt is generated. An EI instruction is issued before each interrupt request acknowledgement, and the interrupt request acknowledgement enable state is set. Example 2. A multiple interrupt is not generated because interrupts are not enabled Main processing INTxx processing INTyy processing EI IE = 0 INTyy RETI INTyy is kept pending INTxx IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy request is reserved and acknowledged after the INTxx processing is performed. IE = 0: Interrupt request acknowledgement disabled 216 User's Manual U14643EJ1V0UM00 CHAPTER 15 INTERRUPT FUNCTIONS 15.4.4 Interrupt request reserve Some instructions may reserve the acknowledgement of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. The following shows such instructions (interrupt request reserve instruction). * Manipulation instruction for the interrupt request flag register (IF0, IF1) * Manipulation instruction for the interrupt mask flag register (MK0, MK1) User's Manual U14643EJ1V0UM00 217 [MEMO] 218 User's Manual U14643EJ1V0UM00 CHAPTER 16 STANDBY FUNCTION 16.1 Standby Function and Configuration 16.1.1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes: (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU. The system clock oscillation circuit continues oscillating. This mode does not reduce the power consumption as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) STOP mode This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock oscillation circuit and stops the entire system. The power consumption of the CPU can be substantially reduced in this mode. The low voltage (VDD = 1.8 V) of the data memory can be retained. Therefore, this mode is useful for retaining the contents of the data memory at an extremely low current. The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillation circuit stabilizes after the STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode. In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained. Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction. User's Manual U14643EJ1V0UM00 219 CHAPTER 16 STANDBY FUNCTION 16.1.2 Standby function control register (PD789104A, 789114A Subseries) The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS)Note. OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 215/fX, instead of 217/fX. Note PD789104A and 789114A Subseries only. The PD789124A and 789134A Subseries do not provide an oscillation stabilization time select register. The oscillation stabilization time of the PD789124A and 789134A Subseries is fixed to 27/fCC. Figure 16-1. Oscillation Stabilization Time Select Register Format Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FFFAH After reset 04H R/W R/W OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 0 0 1 0 1 0 0 0 0 212/fX (819 s) 215/fX (6.55 ms) 217/fX (26.2 ms) Setting prohibited Oscillation stabilization time selection Other than above Caution The wait time after the STOP mode in a ceramic/crystal oscillator is released does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of release by RESET input or by interrupt generation. STOP mode release X1 pin voltage waveform a VSS Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. Values in parentheses apply to operation with fX = 5.0 MHz. 220 User's Manual U14643EJ1V0UM00 CHAPTER 16 STANDBY FUNCTION 16.2 Operation of Standby Function 16.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 16-1. HALT Mode Operating Status Item Clock generator HALT Mode Operating Status System clock can be oscillated. Clock supply to CPU stops. Operation stopped Retains the status before setting the HALT mode. Operable Operable Operable Operable Operation stopped Operation stopped Operable Note CPU Port (Output latch) 16-bit timer 20 8-bit timer/event counter 80 Watchdog timer Serial interface 20 A/D converter Multiplier External interrupt Note Maskable interrupt that is not masked User's Manual U14643EJ1V0UM00 221 CHAPTER 16 STANDBY FUNCTION (2) Releasing HALT mode The HALT mode can be released by the following three types of sources: (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is able to be acknowledged, vectored interrupt processing is performed. If the interrupt is disabled, the instruction at the next address is executed. Figure 16-2. Releasing HALT Mode by Interrupt HALT instruction Standby release signal Operating mode Wait HALT mode Wait Oscillation Operating mode Clock Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt processing is performed: 9 to 10 clocks * When vectored interrupt processing is not performed: 1 to 2 clocks (b) Releasing by non-maskable interrupt request The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed. 222 User's Manual U14643EJ1V0UM00 CHAPTER 16 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 16-3. Releasing HALT Mode by RESET Input HALT instruction RESET signal Operating mode Reset period Oscillation stop WaitNote HALT mode Oscillation Oscillation stabilization wait status Oscillation Operating mode Clock Note In the PD789104A and 789114A Subseries, 215/fX: 6.55 ms (at fX = 5.0-MHz operation) In the PD789124A and 789134A Subseries, 27/fCC: 32 s (at fCC = 4.0-MHz operation) Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) Table 16-2. Operation after Release of HALT Mode Releasing Source Maskable interrupt request MKxx 0 0 1 IE 0 1 x x -- Operation Executes next address instruction Executes interrupt processing Retains HALT mode Executes interrupt processing Reset processing Non-maskable interrupt request RESET input -- -- x: don't care User's Manual U14643EJ1V0UM00 223 CHAPTER 16 STANDBY FUNCTION 16.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 or CL2 pin is internally pulled up to VDD to suppress the current leakage of the oscillation circuit block. Therefore, do not use the STOP mode in a system where the external clock is used as the system clock. 2. Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation stabilization time select register (OSTS) elapses, and then an operation mode is set. The operation status in the STOP mode is shown in the following table. Table 16-3. STOP Mode Operating Status Item Clock generator CPU Port (Output latch) 16-bit timer 20 8-bit timer/event counter 80 Watchdog timer Serial interface 20 A/D converter Multiplier External interrupt STOP Mode Operating Status System clock oscillation stopped Operation stopped Retains the status before setting the STOP mode Operation stopped Operable Note 1 Operation stopped Operable Note 2 Operation stopped Operation stopped Operable Note 3 Notes 1. Operation is possible only when TI80 is selected as the count clock. 2. Operation is possible in both 3-wire serial I/O and UART modes while an external clock is being used. 3. Maskable interrupt that is not masked 224 User's Manual U14643EJ1V0UM00 CHAPTER 16 STANDBY FUNCTION (2) Releasing STOP mode The STOP mode can be released by the following two types of sources: (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is able to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time has elapsed. If the interrupt is disabled, the instruction at the next address is executed. Figure 16-4. Releasing STOP Mode by Interrupt WaitNote (set time by OSTS) STOP instruction Standby release signal Operating mode Oscillation STOP mode Oscillation stop Oscillation stabilization wait status Oscillation Operating mode Clock Note OSTS is not provided in the PD789124A and 789134A Subseries, and the wait time is fixed to 27/fCC. Remark The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. User's Manual U14643EJ1V0UM00 225 CHAPTER 16 STANDBY FUNCTION (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 16-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Operating mode Oscillation Reset period WaitNote STOP mode Oscillation stop Oscillation stabilization wait status Oscillation Operating mode Clock Note In the PD789104A and 789114A Subseries, 215/fX: 6.55 ms (at fX = 5.0-MHz operation) In the PD789124A and 789134A Subseries, 27/fCC: 32 s (at fCC = 4.0-MHz operation) Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) Table 16-4. Operation after Release of STOP Mode Releasing Source Maskable interrupt request MKxx 0 0 1 IE 0 1 x -- Operation Executes next address instruction Executes interrupt processing Retains STOP mode Reset processing RESET input -- x: don't care 226 User's Manual U14643EJ1V0UM00 CHAPTER 17 RESET FUNCTION The following two operations are available to generate reset signals. (1) (2) External reset input with RESET pin Internal reset by program runaway time detection with watchdog timer External and internal reset have no functional differences. In both cases, program execution starts at the addresses 0000H and 0001H by reset signal input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware item is set to the status shown in Table 17-1. Each pin has a high impedance during reset input or during the oscillation stabilization time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 17-2 through 174). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance. Figure 17-1. Block Diagram of Reset Function RESET Reset control circuit Reset signal Count clock Watchdog timer Stop Overflow Interrupt function User's Manual U14643EJ1V0UM00 227 CHAPTER 17 RESET FUNCTION Figure 17-2. Reset Timing by RESET Input X1, CL1 During normal operation RESET Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) Internal reset signal Delay Delay Hi-Z Port pin Figure 17-3. Reset Timing by Overflow in Watchdog Timer X1, CL1 During normal operation Overflow in watchdog timer Reset period (oscillation continues) Oscillation stabilization time wait Normal operation (reset processing) Internal reset signal Port pin Hi-Z Figure 17-4. Reset Timing by RESET Input in STOP Mode X1, CL1 STOP instruction execution Stop status (oscillation During normal operation stops) RESET Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) Internal reset signal Delay Port pin Delay Hi-Z 228 User's Manual U14643EJ1V0UM00 CHAPTER 17 RESET FUNCTION Table 17-1. Hardware Status after Reset (1/2) Hardware Program counter (PC)Note 1 Status after Reset The contents of reset vector tables (0000H and 0001H) are set. Undefined 02H Data memory General register Port (P0 to P2, P5) (Output latch) Port mode register (PM0 to PM2, PM5) Pull-up resistor option register 0 (PU0) Pull-up resistor option register B2 (PUB2) Processor clock control register (PCC) Oscillation stabilization time select register 16-bit timer 20 (OSTS)Note 3 UndefinedNote 2 UndefinedNote 2 00H FFH 00H 00H 02H 04H 0000H FFFFH 00H Undefined 00H Undefined 00H 00H 00H 00H 00H Undefined 00H 00H 00H 00H FFH Undefined Stack pointer (SP) Program status word (PSW) RAM Timer counter (TM20) Compare register (CR20) Mode control register (TMC20) Capture register (TPC20) 8-bit timer/event counter 80 Timer counter (TM80) Compare register (CR80) Mode control register (TMC80) Watchdog timer Timer clock select register (TCL2) Mode register (WDTM) A/D converter Mode register (ADM0) Input channel specification register (ADS0) Conversion result register (ADCR0) Serial interface 20 Mode register (CSIM20) Asynchronous serial interface mode register (ASIM20) Asynchronous serial interface status register (ASIS20) Baud rate generator control register (BRGC20) Transmit shift register (TXS20) Receive buffer register (RXB20) Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware remains unchanged after reset. 2. If the reset signal is input in the standby mode, the status before reset is retained even after reset. 3. PD789104A, 789114A Subseries only User's Manual U14643EJ1V0UM00 229 CHAPTER 17 RESET FUNCTION Table 17-1. Hardware Status after Reset (2/2) Hardware Multiplier 16-bit multiplication result storage register (MUL0) Data register A (MRA0) Data register B (MRB0) Control register (MULC0) Interrupt Request flag register (IF0, IF1) Mask flag register (MK0, MK1) External interrupt mode register (INTM0) Status after Reset Undefined Undefined Undefined 00H 00H FFH 00H 230 User's Manual U14643EJ1V0UM00 CHAPTER 18 PD78F9116A, 78F9136A The PD78F9116A is a version with flash memory instead of the internal ROM of the mask ROM version in the PD789104A and 789114A Subseries. The PD78F9136A is a version with flash memory instead of the internal ROM of the mask ROM version in the PD789124A and 789134A Subseries. The differences between the flash memory and the mask ROM versions are shown in Table 18-1. Table 18-1. Differences between Flash Memory and Mask ROM Versions Item Flash Memory Mask ROM PD78F9116A PD78F9136A Internal memory ROM 16 Kbytes (flash memory) 256 bytes PD789101A PD789111A PD789121A PD789131A 2 Kbytes PD789102A PD789112A PD789122A PD789132A 4 Kbytes PD789104A PD789114A PD789124A PD789134A 8 Kbytes High-speed RAM Pull-up resistor VPP pin Electrical specifications 12 (software control only) 16 (software control: 12, mask option specification: 4) Provided Not provided Refer to the individual data sheets. Cautions 1. There are differences in noise immunity and noise radiation between the flash memory versions and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions. 2. A/D conversion result register 0 (ADCR0) is manipulated by an 8-bit memory manipulation instruction or a 16-bit memory manipulation instruction, when used as an 8-bit A/D converter (PD789104A, 789124A Subseries) or 10-bit A/D converter (PD789114A, 789134A Subseries), respectively. However, if the PD78F9116A is used as the flash memory version of the PD789101A, 789102A, 789104A, ADCR0 can be manipulated by an 8-bit memory manipulation instruction, providing an object file has been assembled in the PD789101A, 789102A, 789104A. If the PD78F9136A is used as the flash memory version of the PD789121A, 789122A, 789124A, ADCR0 can be manipulated by an 8-bit memory manipulation instruction, providing an object file has been assembled in the PD789121A, 789122A, 789124A. User's Manual U14643EJ1V0UM00 231 CHAPTER 18 PD78F9116A, 78F9136A 18.1 Flash Memory Programming The on-chip program memory in the PD78F9116A, 78F9136A is flash memory. The flash memory can be written with the PD78F9116A mounted on the target system (on-board). Connect the dedicated flash programmer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and target system to write the flash memory. Remark FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd. 18.1.1 Selecting communication mode The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 18-2. To select a communication mode, the format shown in Figure 18-1 is used. Each communication mode is selected by the number of VPP pulses shown in Table 18-2. Table 18-2. Communication Mode Communication Mode 3-wire serial I/O Pins Used SCK20/ASCK20/P20 SO20/TxD20/P21 SI20/RxD20/P22 TxD20/SO20/P21 RxD20/SI20/P22 P00 (Serial clock input) P01 (Serial data output) P02 (Serial data input) 0 Number of VPP Pulses UART Pseudo 3-wire mode Note 8 12 Note Serial transfer is performed by controlling a port by software. Caution Be sure to select a communication mode based on the VPP pulse number shown in Table 18-2. Figure 18-1. Communication Mode Selection Format 10 V VPP VDD VSS 1 2 n VDD RESET VSS 232 User's Manual U14643EJ1V0UM00 CHAPTER 18 PD78F9116A, 78F9136A 18.1.2 Function of flash memory programming By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 18-3 shows the major functions of flash memory programming. Table 18-3. Functions of Flash Memory Programming Function Batch erase Batch blank check Data write Batch verify Erases all contents of memory Checks erased state of entire memory Write to flash memory based on write start address and number of data written (number of bytes) Compares all contents of memory with input data Description 18.1.3 Flashpro III connection example Connection between the Flashpro III and the PD78F9116A and 78F9136A differs depending on the communication mode (3-wire serial I/O, UART, or pseudo 3-wire mode). Figures 18-2 to 18-4 show the connection examples in the respective modes. (a) Connection between PD78F9116A and Flashpro III Figure 18-2. Flashpro III Connection in 3-Wire Serial I/O Mode PD78F9116A VPP VDD, AVDD RESET X1 SCK20 SI20 SO20 VSS, AVSS Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND Note n = 1, 2 User's Manual U14643EJ1V0UM00 233 CHAPTER 18 PD78F9116A, 78F9136A Figure 18-3. Flashpro III Connection in UART Mode Flashpro III VPPnNote VDD RESET CLK SO SI GND VPP VDD, AVDD RESET X1 RxD20 TxD20 VSS, AVSS PD78F9116A Note n = 1, 2 Figure 18-4. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used) Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND VPP PD78F9116A VDD, AVDD RESET X1 P00 (Serial clock) P02 (Serial input) P01 (Serial output) VSS, AVSS Note n = 1, 2 234 User's Manual U14643EJ1V0UM00 CHAPTER 18 PD78F9116A, 78F9136A (b) Connection between PD78F9136A and Flashpro III Figure 18-5. Flashpro III Connection in 3-Wire Serial I/O Mode Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND VPP VDD, AVDD RESET P03 SCK20 SI20 SO20 VSS, AVSS PD78F9136A Note n = 1, 2 Figure 18-6. Flashpro III Connection in UART Mode PD78F9136A VPP VDD, AVDD RESET P03 RxD20 TxD20 VSS, AVSS Flashpro III VPPnNote VDD RESET CLK SO SI GND Note n = 1, 2 User's Manual U14643EJ1V0UM00 235 CHAPTER 18 PD78F9116A, 78F9136A Figure 18-7. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used) Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND VPP VDD, AVDD RESET P03 P00 (Serial clock) P02 (Serial input) P01 (Serial output) VSS, AVSS PD78F9136A Note n = 1, 2 236 User's Manual U14643EJ1V0UM00 CHAPTER 18 PD78F9116A, 78F9136A 18.1.4 Example of settings for Flashpro III (PG-FP3) Make the following setting when writing to flash memory using Flashpro III (PG-FP3). <1> <2> <3> Load the parameter file. Select serial mode and serial clock using the type command. An example of the settings for the PG-FP3 is shown below. Table 18-4. Example of Settings for PG-FP3 Communication Mode 3-wire serial I/O COMM PORT CPU CLK Example of Setting for PG-FP3 SIO-ch0 On Target Board In Flashpro On Target Board SIO CLK In Flashpro SIO CLK UART COMM PORT CPU CLK On Target Board UART BPS Pseudo 3-wire COMM PORT CPU CLK 4.1943 MHz 1.0 MHz 4.0 MHz 1.0 MHz UART-ch0 On Target Board 4.1943 MHz 9600 bpsNote 2 Port A On Target Board In Flashpro On Target Board SIO CLK In Flashpro SIO CLK 4.1943 MHz 1.0 kHz 4.0 MHz 1.0 kHz 12 8 Number of VPP PulsesNote 1 0 Notes 1. The number of VPP pulses supplied from Flashpro III when serial communication is initialized. The pins to be used for communication are determined according to the number of these pulses. 2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. Remark COMM PORT: Selection of serial port SIO CLK: CPU CLK: Selection of serial clock frequency Selection of source of CPU clock to be input User's Manual U14643EJ1V0UM00 237 [MEMO] 238 User's Manual U14643EJ1V0UM00 CHAPTER 19 MASK OPTION (MASK ROM VERSION) Table 19-1. Selection of Mask Option for Pins Pin P50 to P53 Mask Option On-chip pull-up resistor can be specified in 1-bit units. For P50 to P53 (port 5), an on-chip pull-up resistor can be specified by the mask option. The mask option is specified in 1-bit units. Caution The flash memory versions do not provide the on-chip pull-up resistor function. User's Manual U14643EJ1V0UM00 239 [MEMO] 240 User's Manual U14643EJ1V0UM00 CHAPTER 20 INSTRUCTION SET This chapter lists the instruction set of the PD789104A/114A/124A/134A Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User's Manual Instruction (U11047E). 20.1 Operation 20.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. Each symbol has the following meaning. * #: * !: Immediate data specification Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parenthesis in the table below, R0, R1, R2, etc.) can be used for description. Table 20-1. Operand Identifiers and Description Methods Identifier r rp sfr saddr saddrp addr16 addr5 word byte bit Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbol FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even addresses only) 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) 0040H to 007FH Immediate data or labels (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Remark Refer to Table 4-3 Special Function Register List for symbols of special function registers. User's Manual U14643EJ1V0UM00 241 CHAPTER 20 INSTRUCTION SET 20.1.2 Description of "operation" column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: ( ): xH, xL: : : : : jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicating non-maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis Higher 8 bits and lower 8 bits of 16-bit register Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data Signed 8-bit data (displacement value) addr16: 16-bit immediate data or label 20.1.3 Description of "flag operation" column (Blank): Unchanged 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored 242 User's Manual U14643EJ1V0UM00 CHAPTER 20 INSTRUCTION SET 20.2 Operation List Flag Mnemonic MOV r,#byte saddr,#byte sfr,#byte A,r r,A Note 1 Note 1 Operands Byte 3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2 Clock 6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8 r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL+byte) (HL+byte) A AX Ar A (saddr) A sfr A (DE) A (HL) A (HL+byte) Operation Z AC CY A,saddr saddr,A A,sfr sfr,A A,!addr16 !addr16,A PSW,#byte A,PSW PSW,A A,[DE] [DE],A A,[HL] [HL],A A,[HL+byte] [HL+byte],A XCH A,X A,r Note 2 A,saddr A,sfr A,[DE] A,[HL] A,[HL+byte] xxx xxx Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control Register (PCC). User's Manual U14643EJ1V0UM00 243 CHAPTER 20 INSTRUCTION SET Flag Mnemonic MOVW rp,#word AX,saddrp saddrp,AX AX,rp Note rp,AX Note XCHW ADD AX,rp Note A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] ADDC A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] SUB A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] Operands Byte 3 2 2 1 1 1 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 Clock 6 6 8 4 4 8 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp A,CY A + byte (saddr),CY (saddr) + byte A,CY A + r A,CY A + (saddr) A,CY A + (addr16) A,CY A + (HL) A,CY A + (HL+byte) A,CY A+ byte + CY (saddr),CY (saddr) + byte + CY A,CY A + r + CY A,CY A + (saddr) + CY A,CY A + (addr16) + CY A,CY A + (HL) + CY A,CY A + (HL+byte) + CY A,CY A - byte (saddr), CY (saddr) - byte A,CY A - r A,CY A - (saddr) A,CY A - (addr16) A,CY A - (HL) A,CY A - (HL+byte) xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx Operation Z AC CY Note Only when rp = BC, DE, or HL. One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control Register (PCC). Remark 244 User's Manual U14643EJ1V0UM00 CHAPTER 20 INSTRUCTION SET Flag Mnemonic SUBC A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] AND A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] OR A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] XOR A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] Operands Byte 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 Clock 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 Operation Z AC CY A,CY A - byte - CY (saddr),CY (saddr) - byte - CY A,CY A - r - CY A,CY A - (saddr) - CY A,CY A - (addr16) - CY A,CY A - (HL) - CY A,CY A - (HL+byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL+byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL+byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL+byte) xxx xxx xxx xxx xxx xxx xxx x x x x x x x x x x x x x x x x x x x x x Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control Register (PCC). User's Manual U14643EJ1V0UM00 245 CHAPTER 20 INSTRUCTION SET Flag Mnemonic CMP A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] ADDW SUBW CMPW INC AX,#word AX,#word AX,#word r saddr DEC r saddr INCW DECW ROR ROL RORC ROLC SET1 rp rp A,1 A,1 A,1 A,1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit SET1 CLR1 NOT1 CY CY CY Operands Byte 2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1 3 3 2 3 2 3 3 2 3 2 1 1 1 Clock 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2 6 6 4 6 10 6 6 4 6 10 2 2 2 A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL+byte) AX,CY AX + word AX,CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY,A7 A0, Am-1 Am) x 1 (CY,A0 A7, Am+1 Am) x 1 (CY A0, A7 CY, Am-1 Am) x 1 (CY A7, A0 CY, Am+1 Am) x 1 (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY 1 0 x xxx xxx x x x x Operation Z AC CY xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xx xx xx xx Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control Register (PCC). 246 User's Manual U14643EJ1V0UM00 CHAPTER 20 INSTRUCTION SET Flag Mnemonic CALL CALLT !addr16 [addr5] Operands Byte 3 1 Clock 6 8 Operation Z AC CY (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 4 + jdisp8 if PSW.bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode RRR RRR RET RETI PUSH PSW rp POP PSW rp MOVW SP, AX AX, SP BR !addr16 $addr16 AX BC BNC BZ BNZ BT $addr16 $addr16 $saddr16 $saddr16 saddr.bit,$addr16 sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 BF saddr.bit,$addr16 sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 DBNZ B,$addr16 C,$addr16 saddr,$addr16 NOP EI DI HALT STOP 1 1 1 1 1 1 2 2 3 2 1 2 2 2 2 4 4 3 4 4 4 3 4 2 2 3 1 3 3 1 1 6 8 2 4 4 6 8 6 6 6 6 6 6 6 6 10 10 8 10 10 10 8 10 6 6 8 2 6 6 2 2 Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control Register (PCC). User's Manual U14643EJ1V0UM00 247 CHAPTER 20 INSTRUCTION SET 20.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote MOV XCHNote ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP MOV MOV DBNZ INC DEC DBNZ ROR ROL RORC ROLC A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte] $addr16 1 None [DE] [HL] [HL+byte] MOV MOV MOV Note Except r = A. 248 User's Manual U14643EJ1V0UM00 CHAPTER 20 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word 1st Operand AX ADDW SUBW CMPW MOVW MOVWNote MOVW XCHW MOVW MOVW AX rpNote saddrp SP None rp INCW DECW PUSH POP saddrp SP MOVW MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 1st Operand A.bit BT BF BT BF BT BF PSW.bit BT BF SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 None sfr.bit saddr.bit [HL].bit CY User's Manual U14643EJ1V0UM00 249 CHAPTER 20 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX 1st Operand Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ DBNZ !addr16 [addr5] $addr16 Compound Instructions (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP 250 User's Manual U14643EJ1V0UM00 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the PD789104A/114A/ 124A/134A Subseries. Figure A-1 shows the development tool configuration. * Support of the PC98-NX Series Unless otherwise specified, the PD789104A/114A/124A/134A Subseries supported by IBM PC/ATTM and compatibles can be used for the PC98-NX Series. When using the PC98-NX Series, refer to the descriptions of the IBM PC/AT and compatibles. * Windows Unless otherwise specified, "Windows" indicates the following OSs. Windows 3.1 Windows 95 Windows NTTM Ver. 4.0 User's Manual U14643EJ1V0UM00 251 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Language processing software * Assembler package * C compiler package * System simulator * Device file * C compiler source file * Integrated debugger Embedded software * OS Host machine (PC or EWS) Interface adapter Flash memory write environment In-circuit emulator Emulation board Flash memory write adapter Power supply unit Flash programmer Flash memory Emulation probe Conversion socket Target system 252 User's Manual U14643EJ1V0UM00 APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K0S Assembler package A program that converts a program written in mnemonic into object codes that can be executed by microcontrollers. In addition, automatic functions to generate symbol tables and optimize branch instructions are also provided. Used in combination with a device file (DF789136) (sold separately). Note DF789136 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S. xxxx in the part number differs depending on the host machine and operating system to be used. Remark SxxxxRA78K0S SxxxxCC78K0S SxxxxDF789136 SxxxxCC78K0S-L xxxx AA13 AB13 3P16 3K13 3K15 3R13 NEWSTM (RISC) Host Machine PC-9800 Series IBM PC/AT and compatibles HP9000 Series 700TM SPARCstationTM Japanese Japanese OS WindowsNote WindowsNote Supply Media 3.5" 2HD FD 3.5" 2HC FD DAT (DDS) 3.5" 2HC FD 1/4" CGMT 3.5" 2HC FD HP-UXTM (Rel.10.10) SunOSTM (Rel.4.1.1) SolarisTM (Rel.2.5.1) NEWS-OSTM (Rel.6.1) Note Also operates in the DOS environment User's Manual U14643EJ1V0UM00 253 APPENDIX A DEVELOPMENT TOOLS A.2 Flash Memory Writing Tools Flashpro III (Part No. FL-PR3, PG-FP3) Flash programmer FA-30MC Flash memory writing adapter Dedicated flash programmer for microcontrollers incorporating flash memory Adapter for writing to flash memory and connected to Flashpro III. * FA-30MC: for 30-pin plastic SSOP (MC-5A4 type) Remark The FL-PR3 and FA-30MC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813). A.3 Debugging Tools A.3.1 Hardware IE-78K0S-NS In-circuit emulator IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF Interface adapter IE-789136-NS-EM1 Emulation board NP-36GS Emulation probe NGS-30 Conversion socket In-circuit emulator for debugging the hardware and software of an application system using the 78K/0S Series. Supports an integrated debugger (ID78K0S-NS). Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine. Adapter for supplying power from an AC 100 to 240 V outlet. Adapter necessary when using a PC-9800 series PC (except notebook type) as the host machine of the IE-78K0S-NS (C bus supported) PC card and interface cable necessary when using a notebook PC as the host machine of the IE-78K0S-NS (PCMCIA socket supported) Interface adapter necessary when using an IBM PC/AT or compatible as the host machine of the IE-78K0S-NS (ISA bus supported) Adapter necessary when using a personal computer incorporating the PCI bus as the host machine of the IE-78K0S-NS Board for emulating the peripheral hardware inherent to the device. Used in combination with an in-circuit emulator. Probe for connecting the in-circuit emulator and target system. This is for a 30-pin plastic SSOP (MC-5A4 type). Conversion socket to connect the NP-36GS and a target system board on which a 30-pin plastic SSOP (MC-5A4 type) can be mounted. Remark The NP-36GS, and NGS-30 are products made by Naito Densei Machida Mfg. Co., Ltd. For details of these products, contact Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813). 254 User's Manual U14643EJ1V0UM00 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software ID78K0S-NS Integrated debugger (Supports in-circuit emulator IE-78K0S-NS) Control program for debugging the 78K/0S Series. This program provides a graphical user interface. It runs on Windows for personal computer users and on OSF/MotifTM for engineering work station users, and has visual designs and operationability that comply with these operating systems. In addition, it has a powerful debug function that supports C language. Therefore, trace results can be displayed at a C language level by the window integration function that links the source program, disassembled display, and memory display, to the trace result. This software also allows users to add other function extension modules such as a task debugger and system performance analyzer to improve the debug efficiency for programs using a real-time operating system. Used in combination with a device file (DF789136) (sold separately). Part number: SxxxxID78K0S-NS Remark xxxx in the part number differs depending on the host machine and operating system to be used. SxxxxID78K0S-NS xxxx AA13 AB13 Host Machine PC-9800 Series IBM PC/AT compatibles Japanese Japanese OS WindowsNote WindowsNote Supply Media 3.5" 2HD FD 3.5" 2HC FD Note Also operates in the DOS environment. SM78K0S System simulator Debugs the program at C source level or assembler level while simulating operation of the target system on the host machine. SM78K0S runs in Windows. By using SM78K0S, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used. This enhances development efficiency and improves software quality. Used in combination with a device file (DF789136) (sold separately). Part number: SxxxxSM78K0S DF789136Note Device file File containing the information inherent to the device. Used in combination with the RA78K0S, CC78K0S, and SM78K0S (all sold separately). Part number: SxxxxDF789136 Note DF789136 is a common file that can be used with the RA78K0S, CC78K0S, and SM78K0S. xxxx in the part number differs depending on the host machine and operating system to be used. Remark SxxxxSM78K0S xxxx AA13 AB13 Host Machine PC-9800 Series IBM PC/AT compatibles Japanese OS WindowsNote Supply Media 3.5" 2HD FD 3.5" 2HC FD Japanese WindowsNote Note Also operates in the DOS environment. User's Manual U14643EJ1V0UM00 255 [MEMO] 256 User's Manual U14643EJ1V0UM00 APPENDIX B EMBEDDED SOFTWARE The following embedded software products are available for efficient program development and maintenance of the PD789104A/114A/124A/134A Subseries. MX78K0S OS MX78K0S is a subset OS that is based on the ITRON specification. Supplied with the MX78K0S nucleus. The MX78K0S OS controls tasks, events, and time. In task control, the MX78K0S OS controls task execution order, and then perform the switching process to a task to be executed. Remark xxxx in the part number differ depending on the host machine and OS used. SxxxxMX78K0S xxxx AA13 AB13 BB13 Host Machine PC-9800 Series IBM PC/AT compatibles OS Japanese WindowsNote Japanese English WindowsNote Supply Media 3.5" 2HD FD 3.5" 2HD FD WindowsNote Note Can also be operated in the DOS environment. User's Manual U14643EJ1V0UM00 257 [MEMO] 258 User's Manual U14643EJ1V0UM00 APPENDIX C REGISTER INDEX C.1 Register Name Index (Alphabetic Order) 8-bit compare register 80 (CR80) ................................................................................................................ 117 8-bit timer mode control register 80 (TMC80) ............................................................................................. 118 8-bit timer counter 80 (TM80) ...................................................................................................................... 117 16-bit compare register 20 (CR20) .............................................................................................................. 106 16-bit multiplication result storage register 0 (MUL0) ................................................................................. 199 16-bit timer capture register 20 (TCP20) ..................................................................................................... 106 16-bit timer mode control register 20 (TMC20) ........................................................................................... 107 16-bit timer counter 20 (TM20) .................................................................................................................... 106 [A] Asynchronous serial interface mode register 20 (ASIM20) ............................................... 168, 175, 178, 190 Asynchronous serial interface status register 20 (ASIS20) ................................................................ 170, 179 A/D conversion result register 0 (ADCR0) ................................................................................................... 136 A/D converter mode register 0 (ADM0) ....................................................................................................... 138 Analog input channel specification register 0 (ADS0) ................................................................................ 139 [B] Baud rate generator control register 20 (BRGC20) ................................................................... 171, 180, 191 [E] External interrupt mode register 0 (INTM0) ................................................................................................. 209 [I] Interrupt mask flag register 0 (MK0) ............................................................................................................ 208 Interrupt mask flag register 1 (MK1) ............................................................................................................ 208 Interrupt request flag register 0 (IF0) ........................................................................................................... 207 Interrupt request flag register 1 (IF1) ........................................................................................................... 207 [M] Multiplication data register A0 (MRA0) ........................................................................................................ 199 Multiplication data register B0 (MRB0) ........................................................................................................ 199 Multiplier control register 0 (MULC0) ........................................................................................................... 201 [O] Oscillation stabilization time select register (OSTS) ................................................................................... 220 [P] Port 0 (P0) ....................................................................................................................................................... 75 Port 1 (P1) ....................................................................................................................................................... 76 Port 2 (P2) ....................................................................................................................................................... 77 Port 5 (P5) ....................................................................................................................................................... 81 Port 6 (P6) ....................................................................................................................................................... 82 User's Manual U14643EJ1V0UM00 259 APPENDIX C REGISTER INDEX Port mode register 0 (PM0) ............................................................................................................................ 83 Port mode register 1 (PM1) ............................................................................................................................ 83 Port mode register 2 (PM2) ........................................................................................................... 83, 109, 119 Port mode register 5 (PM5) ............................................................................................................................ 83 Processor clock control register (PCC) ................................................................................................... 88, 96 Pull-up resistor option register 0 (PU0) ......................................................................................................... 84 Pull-up resistor option register B2 (PUB2) .................................................................................................... 84 [R] Receive buffer register 20 (RXB20) ............................................................................................................. 166 [S] Serial operating mode register 20 (CSIM20) ...................................................................... 167, 174, 177, 189 [T] Timer clock select register 2 (TCL2) ............................................................................................................ 131 Transmit shift register 20 (TXS20) ............................................................................................................... 166 [W] Watchdog timer mode register (WDTM) ...................................................................................................... 132 260 User's Manual U14643EJ1V0UM00 APPENDIX C REGISTER INDEX C.2 Register Symbol Index (Alphabetic Order) [A] ADCR0: ADM0: ADS0: ASIM20: ASIS20: [B] BRGC20: Baud rate generator control register 20 ................................................................... 171, 180, 191 [C] CR20: CR80: CSIM20: [I] IF0: IF1: INTM0: [M] MK0: MK1: MRA0: MRB0: MUL0: MULC0: [O] OSTS: [P] P0: P1: P2: P5: P6: PCC: PM0: PM1: PM2: PM5: PU0: PUB2: Port 0 ............................................................................................................................................ 75 Port 1 ............................................................................................................................................ 76 Port 2 ............................................................................................................................................ 77 Port 5 ............................................................................................................................................ 81 Port 6 ............................................................................................................................................ 82 Processor clock control register ............................................................................................ 88, 96 Port mode register 0 .................................................................................................................... 83 Port mode register 1 .................................................................................................................... 83 Port mode register 2 ................................................................................................... 83, 109, 119 Port mode register 5 .................................................................................................................... 83 Pull-up resistor option register 0 ................................................................................................. 84 Pull-up resistor option register B2 ............................................................................................... 84 Oscillation stabilization time select register .............................................................................. 220 Interrupt mask flag register 0 ..................................................................................................... 208 Interrupt mask flag register 1 ..................................................................................................... 208 Multiplication data register A0 ................................................................................................... 199 Multiplication data register B0 ................................................................................................... 199 16-bit multiplication result storage register 0 ............................................................................ 199 Multiplier control register 0 ........................................................................................................ 201 Interrupt request flag register 0 ................................................................................................. 207 Interrupt request flag register 1 ................................................................................................. 207 External interrupt mode register 0 ............................................................................................. 209 16-bit compare register 20 ......................................................................................................... 106 8- bit compare register 80 .......................................................................................................... 117 Serial operating mode register 20 .................................................................... 167, 174, 177, 189 A/D conversion result register 0 ................................................................................................ 136 A/D converter mode register 0 .................................................................................................. 138 Analog input channel specification register 0 ........................................................................... 139 Asynchronous serial interface mode register 20 ............................................. 168, 175, 178, 190 Asynchronous serial interface status register 20 .............................................................. 170, 179 User's Manual U14643EJ1V0UM00 261 APPENDIX C REGISTER INDEX [R] RXB20: [T] TCL2: TCP20: TM20: TM80: TMC20: TMC80: TXS20: [W] WDTM: Watchdog timer mode register .................................................................................................. 132 Timer clock select register 2 ...................................................................................................... 131 16-bit timer capture register 20 ................................................................................................. 106 16-bit timer counter 20 ............................................................................................................... 106 8-bit timer counter 80 ................................................................................................................. 117 16-bit timer mode control register 20 ........................................................................................ 116 8-bit timer mode control register 80 .......................................................................................... 118 Transmit shift register 20 ........................................................................................................... 166 Receive buffer register 20 .......................................................................................................... 166 262 User's Manual U14643EJ1V0UM00 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6465-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: 044-548-7900 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 99.1 Excellent Good Acceptable Poor |
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