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LH531V00
FEATURES * 131,072 words x 8 bit organization * Access time: 100 ns (MAX.) * Power consumption: Operating: 275 mW (MAX.) Standby: 550 W (MAX.) * Mask-programmable OE1/OE1/DC * Fully-static operation * TTL-compatible I/O * Three-state outputs * Single +5 V power supply * Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 8 x 20 mm2 TSOP (Type I) DESCRIPTION
The LH531V00 is a 1M-bit mask-programmable ROM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology.
32-PIN DIP 32-PIN SOP OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
CMOS 1M (128K x 8) MROM
PIN CONNECTIONS
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC NC NC A14 A13 A8 A9 A11 OE A10 CE D7 D6 D5 D4 D3
531V00-1
Figure 1. Pin Connections for DIP and SOP Packages
32-PIN TSOP (Type I)
TOP VIEW
A11 A9 A8 A13 A14 NC NC VCC OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE D7 D6 D5 D4 D3 GND D2 D1 D0 A0 A1 A2 A3
531V00-2
Figure 2. Pin Connections for TSOP Package
1
LH531V00
CMOS 1M MROM
A16 A15 A14 A13
2 3 29 28 MEMORY MATRIX (131,072 x 8)
A12 4
A9 A8 A7 A6
26 27 5 6
A5 7 A4 8 A3 9 A2 10 A1 11 A0 12
ADDRESS BUFFER
A11 25 A10 23
ADDRESS DECODER
COLUMN SELECTOR
SENSE AMPLIFIER
CE 22
CE BUFFER
TIMING GENERATOR
OUTPUT BUFFER OE 24 OE1/OE1/DC 1 OE BUFFER 32 16 VCC GND NOTE: Pin numbers apply to the 32-pin DIP or SOP. 13 D0 14 D1 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7
531V00-3
Figure 3. LH531V00 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE
A0 - A16 D0 - D7 CE OE
Address input Data output Chip Enable input Output Enable input
OE1/OE1/DC VCC GND
Output Enable input Power supply (+5 V) Ground
1
NOTE: 1. Active level of OE1/OE1/DC is mask-programmable. When DC is selected out of OE1/OE1/DC, it is fixed to an active level. Then it is recommended to apply either HIGH or LOW to the DC pin.
2
CMOS 1M MROM
LH531V00
TRUTH TABLE
CE OE OE1/OE1 D0 - D7 SUPPLY CURRENT NOTE
H L L L
NOTE: 1. X = H or L
X H X L
X X L/H H/L
High-Z High-Z High-Z D0 - D7
Standby (ISB) Operating (ICC ) Operating (ICC ) Operating (ICC )
1 1 1
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Supply voltage Input voltage Output voltage Operating temperature Storage temperature
VCC VIN VOUT Topr Tstg
-0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 0 to +70 - 65 to +150
V V V C C
RECOMMENDED OPERATING CONDITIONS (TA = 0C to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage
VCC
4.5
5.0
5.5
V
DC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input `Low' voltage Input `High' voltage Output `Low' voltage Output `High' voltage Input leakage current Output leakage current
VIL V IH VOL VOH | ILI | | ILO | ICC1 ICC2 ICC3 ICC4 ISB1 ISB2 CIN COUT I OL = 2.0 mA I OH = -400 A V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 100 ns t RC = 1 s t RC = 100 ns t RC = 1 s CE = VIH CE = VCC - 0.2 V f = 1 MHz T A = 25C
-0.3 2.2 2.4
0.8 VCC + 0.3 0.4 10 10 50 45 45 40 3 100 10 10
V V V V A A mA mA mA mA mA A pF pF 1 2 3
Operating current
Standby current Input capacitance Output capacitance
NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
3
LH531V00
CMOS 1M MROM
AC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z
tRC tAA tACE tOE tOH tCHZ tOHZ
100 100 100 50 0 50 50
ns ns ns ns ns ns ns 1
NOTE: 1. This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude Input rise/fall time Input/output reference level Output load condition
0.6 V to 2.4 V 10 ns 1.5 V 1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin.
tRC
A0 - A16 tAA (NOTE) CE tACE (NOTE) OE/OE1/OE1 tOE (NOTE) tOH tOHZ tCHZ
D0 - D7
DATA VALID
NOTE: The data becomes valid after the intervals, tAA, tACE, or tOE, from address input, chip enable, and output enable, respectively have been met.
531V00-4
Figure 4. Timing Diagram
4
CMOS 1M MROM
LH531V00
PACKAGE DIAGRAMS
32DIP (DIP032-P-0600)
32 17
DETAIL
13.45 [0.530] 12.95 [0.510]
1 41.30 [1.626] 40.70 [1.602]
16 0.30 [0.012] 0.20 [0.008]
0 TO 15
4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
15.24 [0.600] TYP.
DIMENSIONS IN MM [INCHES]
32DIP
32-pin, 600-mil DIP
32SOP (SOP032-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 17
0.50 [0.020] 0.30 [0.012]
32
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 20.80 [0.819] 20.40 [0.803]
16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
32SOP
32-pin, 525-mil SOP
5
LH531V00
CMOS 1M MROM
32TSOP (Type I) (TSOP032-P-0820)
0.30 [0.012] 0.10 [0.004] 32 0.50 [0.020] TYP. 17
18.60 [0.732] 18.20 [0.717]
20.30 [0.799] 19.70 [0.776]
19.00 [0.748]
1 8.20 [0.323] 7.80 [0.307]
16 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000]
0.15 [0.006]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
32TSOP
32-pin, 8 x 20 mm2 TSOP (Type I)
ORDERING INFORMATION
LH531V00 Device Type X Package
D 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) T 32-pin, 8 x 20 mm2 TSOP (Type I) (TSOP032-P-0820) CMOS 1M (128K x 8) Mask-Programmable ROM Example: LH531V00D (CMOS 1M (128K x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP)
531V00-5
6

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