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MK3732-17
ADSL VCXO CLOCK SOURCE
Description
The MK3732-17 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive VCXO modules and oscillators. The on-chip Voltage Controlled Crystal Oscillator (VCXO) accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by +100 ppm. Using ICS' patented VCXO and analog Phase-Locked Loop (PLL) techniques, the device uses an inexpensive pullable crystal input to produce one or two output clocks. The MK3732-17 is an upgrade to the MK3732-07, and is recomended for new designs. ICS manufactures the largest variety of xDSL clock synthesizers for all applications. Consult ICS to eliminate VCXOs, crystals, and oscillators from your board.
Features
* Packaged in 16 pin (150 mil) SOIC * Replaces a VCXO and oscillator * Ideal for Asymmetrical Digital Subscriber Line
(ADSL) chipsets
* Uses an inexpensive pullable crystal * On-chip patented VCXO with pull range of 200 ppm
(+ 100 ppm) minimum
* * * * *
VCXO tuning voltage of 0 to 3.3 V 12 mA output drive capability at TTL levels Advanced, low power, sub-micron CMOS process Operating voltage of 3.3V Industrial temperature range available
Block Diagram
VDD
2
S2:S0 VIN X1 Pullable Crystal
3
CLK1 PLL/ Clock Synthesis Circuitry CLK2
X2
Voltage Controlled Crystal Oscillator
2 GND
OE
MDS 3732-17 D
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Revision 050803
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK3732-17 ADSL VCXO CLOCK SOURCE
Pin Assignment
Clock Select Table
S2 S1 S0 Input
13.248 13.248 13.248 13.248 17.664 17.664 23.552 17.664 13.248 13.248 13.248 13.248
CLK1
35.328 35.328 35.328 42.4 24.73 35.328 49.46 49.46 35.328 2.208 24.73 49.46
CLK2
29.4 47.1 40.4 35.328 35.328 OFF 35.328 35.328 Off Off 35.328 35.328
X2 X1 VD D VIN NC GND C LK1 C LK2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
S1 DC GND VDD NC S0 OE S2
0 0 0 0 0 0 1 1 1 1 1 1
0 0 0 1 1 1 0 0 0 1 1 1
0 M 1 0 M 1 0 M 1 0 M 1
16 Pin (150 m il) SO IC
0=connect directly to GND M=leave unconnected (floating) 1=connect directly to VDD
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
X2 X1 VDD VIN NC GND CLK1 CLK2 S2 OE S0 NC VDD GND DC S1
Pin Type
Input Input Power Input -Power Output Output Input Input Input -Power Power Input
Pin Description
Crystal connection. Connect to a pullable crystal. See table above. Crystal connection. Connect to a pullable crystal. See table above. Connect to +3.3V. Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency. No Connect. Okay to connect to VDD or GND (to match MK3732-07). Connect to ground. Clock output #1 per table above. Clock output #2 per table above. Select input #2. Selects outputs per table above. Internal pull-up resistor. Output enable. Tri-states outputs when low. Internal pull-up resistor. Select input #0. Selects outputs per table above. No Connect. Okay to connect to VDD or GND (to match MK3732-07). Connect to +3.3V. Connect to ground. Don't connect. Do not connect anything to this pin. Select input #1. Selects outputs per table above.
MDS 3732-17 D
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Revision 050803
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK3732-17 ADSL VCXO CLOCK SOURCE
External Component Selection
The MK3732-17 requires a minimum number of external components for proper operation.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL. To determine the value of the crystal capacitors: 1. Connect VDD of the MK3732-17 to 3.3V. Connect pin 4 of the MK3732-17 to the second power supply. Adjust the voltage on pin 4 to 0V. Measure and record the frequency of the CLK output. 2. Adjust the voltage on pin 4 to 3.3V. Measure and record the frequency of the same output. To calculate the centering error:
6 ( f 3.3V - f t arg et ) + ( f 0V - f t arg et ) Error = 10 x ----------------------------------------------------------------------------- - errorxtal ft arg et
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected between VDD and GND on pins 3 and 6, and on pins 13 and 14, as close to the MK3732-17 as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Quartz Crystal
The MK3732-17 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters must be used, and the layout guidelines discussed in the following section must be followed. The frequency of oscillation of a quartz crystal is determined by its "cut" and by the load capacitors connected to it. The MK3732-17 incorporates on-chip variable load capacitors that "pull" (change) the frequency of the crystal. The crystal specified for use with the MK3732-17 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the MK3732-17. There should be no vias between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. Please see application note MAN05 for recommended crystal parameters and suppliers.
Where: ftarget = nominal crystal frequency errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than 25 ppm, no adjustment is needed. If the centering error is more than 25ppm negative, the PC board has excessive stray capacitance and a new PCB layout should be considered to reduce stray capacitance. (Alternately, the crystal may be re-specified to a higher load capacitance. Contact ICS for details.) If the centering error is more than 25ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by:
MDS 3732-17 D
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Revision 050803
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK3732-17 ADSL VCXO CLOCK SOURCE
External Capacitor = 2 x (centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than 25ppm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3732-17. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V -40 to +85C -65 to +150C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (MK3732-17SI) Ambient Operating Temperature (MK3732-17S) Power Supply Voltage (measured in respect to GND) Reference crystal parameters
Min.
-40 0 +3.15
Typ.
Max.
+85 +70 +3.45
Units
C C V
Refer to MAN05
DC Electrical Characteristics
VDD=3.3V 5% , Ambient temperature 0 to +70C, unless stated otherwise
Parameter
Operating Voltage Output High Voltage Output Low Voltage Output High Voltage (CMOS Level) Short Circuit Current Input High Voltage, binary inputs Input High Voltage, trinary input
Symbol
VDD VOH VOL VOH IOS VIH V IH
Conditions
IOH = -12 mA IOL = 12 mA IOH = -8 mA
Min.
3.15 2.4
Typ.
3.3
Max.
3.45 0.4
Units
V V V V
VDD-0.4 50
mA V V
S2, S1, OE S0
2.0 VDD-0.5
MDS 3732-17 D
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Revision 050803
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK3732-17 ADSL VCXO CLOCK SOURCE
Parameter
Input Low Voltage, binary inputs Input Low Voltage, trinary input Operating Supply Current Input Capacitance VIN, VCXO Control Voltage Internal Pull-up Resistor
Symbol
VIL V IL IDD CIN V IA RPU
Conditions
S2, S1, OE S0 No load S2:S0, OE
Min.
Typ.
Max.
0.8 0.5
Units
V V mA pF
15 5 0 3.3 430
V k
S2:S0, OE
AC Electrical Characteristics
VDD = 3.3V 5%, Ambient Temperature 0 to +70 C, unless stated otherwise
Parameter
Input Crystal Frequency Output Clock Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Maximum Absolute Jitter Phase Noise, relative to carrier Frequency Synthesis Error VCXO Pullability VCXO Gain Note 1: Measured with a 15 pF load. Note 2: External pullable crystal must conform with those listed in application note MAN05 FP tOR tOF tD tj 0.8 to 2.0V, Note 1 2.0 to 0.8V, Note 1 At VDD/2, Note 1 Note 1, deviation from mean 10 kHz offset Both clocks 0V < VIN < 3.3V, Note 2 VIN = (VDD/2)1, Note 2 100 150 40 150 -124 0
Symbol
Conditions
Min.
Typ.
13.248
Max. Units
MHz MHz ns ns % ps dBc/Hz ppm ppm ppm/V 1.5 1.5 60
See Table on Page 2
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
120 115 105 58
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
MDS 3732-17 D
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Revision 050803
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK3732-17 ADSL VCXO CLOCK SOURCE
Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max Inches Min Max
16
E INDEX AREA
H
12 D
A A1 B C D E e H h L
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
A A1
h x 45 C
-Ce
B SEATING PLANE
.10 (.004)
L
C
Ordering Information
Part / Order Number
MK3732-17S MK3732-17STR MK3732-17SI MK3732-17SITR
Marking
MK3732-17S MK3732-17S MK3732-17SI MK3732-17SI
Shipping packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
16 pin SOIC 16 pin SOIC 16 pin SOIC 16 pin SOIC
Temperature
0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 3732-17 D
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Revision 050803
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com

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