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NT3881D
Dot Matrix LCD Controller and Driver
Features
! Internal LCD drivers 16 common signal drivers 40 segment signal drivers (can be externally extended to 400 segments using NT3882) ! Maximum display dimensions 40 characters * 2 lines or 80 characters * 1 line ! Interfaces with 4-bit or 8-bit MPU ! Versatile display functions provided on chip: Display Clear, Cursor Home, Display ON/OFF, Cursor ON/OFF, Character Blinking, Cursor Shift, and Display Shift ! Three duty factors, selected by PROGRAM: 1/8, 11/11, and 1/16 ! Displays Data RAM (DD RAM): 80 X 8 bits (displays up to 80 characters) ! Character Generator RAM (CG RAM): 64 X 8 bits for general data, 8 5 X 8 programmable dot patterns, or 4 5 X 10 programmable dot patterns ! Low voltage reset ! NOVATEK Identification code ! Bonding option for A-type and B-type waveform ! Character Generator ROM (CG ROM): 3 kinds of CG ROM sizes: 192 characters: 160 5 X 8 dot patterns 32 5 X 10 dot patterns 240 characters: 192 5 X 8 dot patterns 48 5 X 10 dot patterns 256 characters: 192 5 X 8 dot patterns 64 5 X 10 dot patterns Custom CG ROM is also available ! Built-in power-on reset function ! Logic power supply: single +5V supply ! LCD driver power supply: V1 - V5 (VDD+0.3 - VDD-13.5) ! Three oscillator operations (Freq. = 250KHz - 270KHz): * Internal oscillation * Ceramic resonator * External clock ! CMOS Process ! Available in 80-pin QFP or in CHIP FORM
General Description
The NT3881D is a dot matrix LCD controller and driver LSI that can operate with either a 4-bit or an 8-bit microprocessor (MPU). NT3881D receives control character codes from the MPU, stores them in an internal RAM (up to 80 characters), transforms each character code into a 5 X 7, 5 X 8, or 5 X 10 dot matrix character pattern, and then displays the codes on the LCD panel. The built-in Character Generator ROM consists of 256 different character patterns. The NT3881D also contains Character Generator RAM where the user can store 8 different character patterns at run time. These memory features make character display flexible. NT3881D also provides many display instructions to achieve versatile LCD display functions. The NT3881D is fabricated on a single LSI chip using the CMOS process, resulting in very low power requirements. With several NT3882 driver ICs connected to the NT3881D, up to 80 characters can be displayed.
1
V2.4
NT3881D
Pin Configuration
S E G 3 9
S E G 4 0
C O M 1 6
C O M 1 5
C O M 1 4
C O M 1 3
C O M 1 2
C O M 1 1
C O M 1 0
C O M 9
C O M 8
C O M 7
C O M 6
C O M 5
C O M 4
C O M 3
C O M 2
C O M 1
D B 7
D B 6
D B 5
D B 4
D B 3
D B 2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9
41 40 39 38 37 36 35 34
DB1 DB0 E R/W RS D M VDD CL2 CL1 V5 V4 V3 V2 V1 OSC2
UM3881DF NT3881DF
33 32 31 30 29 28 27 26 25
S E G 2 2
S E G 2 1
S E G 2 0
S E G 1 9
S E G 1 8
S E G 1 7
S E G 1 6
S E G 1 5
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
G N D
O S C 1
2
V2.4
NT3881D
Pad Configuration
S E G 2 3 80 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 O S C 2
S E G 2 4 79
S E G 2 5 78
S E G 2 6 77
S E G 2 7 76
S E G 2 8 75
S E G 2 9 74
S E G 3 0 73
S E G 3 1 72
S E G 3 2 71
S E G 3 3 70
S E G 3 4 69
S E G 3 5 68
S E G 3 6 67
S E G 3 7 66
S E G 3 8 65 64 63 62 61 60 59 58 57 56 SEG39 SEG40 COM1 6 COM1 5 COM1 4 COM1 3 COM1 2 COM1 1 COM1 0 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2
NT3881DH
55 54 53 52 51 50 49 48 47 46 45
V D D B 33 26 V 1 27 V 2 28 V 3 29 30 V 4 V 5 31 C L 1 32 C L 2 81 V D D A 34 M 35 D 36 R S 37 R / W 38 E 39 D B 0 40 D B 1
44 43 42 41
3
V2.4
NT3881D
Block Diagram
V1 V2 V3 V4 V5 VDD GND OSC1 OSC2 8 7 ADDRESS COUNTER 7 TIMING GENERATOR 7 3 INSTRUCTION REGISTER (IR) 8 INSTRUCTION DECODER M CL1 CL2
RS
7
7
R/W
7
CUR50R ADDRESS COURTER
DISPLAY DATA RAM (DD RAM) 80 X 8 BITS
16-BIT SHIFT REGISTER
16
COMMON SIGNAL DRIVER
16
COM1 | COM16
E I/O BUTTER 8 DATA REGISTER (DR) 8 CURSOR /BLINK CONTROLLER
8
7
8
DB7~DB4 4 CHARACTER GENERATOR RAM (CG RAM) 64 X 8 BITS BUSY FLAG (BF) 5 5 CHARACTER GENERATOR ROM (CG ROM)
DB3~DB0 4
40-BIT LATCH CIRCUIT
40
SEGMENT SIGNAL DRIVER
40
SEG1 | SEG40
PARALLEL-TO-SERIAL CONVERTER
40-BIT SHIFT REGISTER
D
4
V2.4
NT3881D
Pin and Pad Descriptions
Pin and Pad No. 1 - 22 24, 25 Designation SEG22 - SEG1 OSC1, OSC2 I/O O External Connection LCD panel Description Segment signal output pins Pins connected to resistor or ceramic filter for internal clock oscillation. For external clock operation, clock inputs to OSC1. P O O P Power supply NT3882 NT3882 Power supply Power supply for LCD driver Clock to latch serial data D sent to NT3882. Clock to shift serial data D VDD: +5V A-Type waveform: VDD bond to VDDA B-Type waveform: VDD bond to VDDB 23 34 GND M P O Power supply NT3882 GND: 0V Switch signal to convert LCD drive waveform to AC Character pattern data corresponding to each common signal is transmitted serially from this output. 0-Non selection, 1-selection. Register select signal 0: Instruction register (write) Busy flag, address counter (read) 1: Data register (write, read) Read/Write control signal 0: Write 1: Read Read/Write start signal Lower 4 tri-state bi-directional data bus for transmitting data between MPU and NT3881D. Not used during 4-bit operation. Higher 4 tri-state bi-directional data bus for transmitting data between MPU and NT3881D. DB7 is also used as busy flag. Common signal output pins Segment signal output pins
26 - 30 31 32 33, 81
V1 - V5 CL1 CL2 VDDB, VDDA
35
D
O
NT3882
36
RS
I
MPU
37
R/W
I
MPU
38 39 - 42
E DB0 - DB3
I I/O
MPU MPU
43 - 46
DB4 - DB7
I/O
MPU
47 - 62 63 - 80
COM1 - COM16 SEG40 - SEG23
O O
LCD panel LCD panel
5
V2.4
NT3881D
Functional Description
The NT3881D is a dot-matrix LCD controller and driver LSI. It operates with either a 4-bit or an 8-bit microprocessor (MPU). The NT3881D receives both instructions and data from the MPU. Some instructions set operation modes, such as the function mode, data entry mode, and display mode; as well as some control LCD display functions, such as clear display, restore display, shift display, and cursor. Other instructions include read and write both data and addresses. All instructions allow users convenient and powerful functions to control the LCD dot-matrix displays. Data is written into and read from the Data Display RAM (DD RAM) or the Character Generator RAM (CG RAM). As display character codes, the data stored in the DD RAM decodes a set of dot-matrix character patterns that are built into the Character Generator ROM (CG ROM). The CG ROM, with many character patterns (up to 256 patterns), defines the character pattern fonts. The NT3881D regularly scans the character patterns through the segment drivers. The CG RAM stores character pattern fonts at run time if users intend to show character patterns that are not defined in the CG ROM. This feature makes character display flexible. Other unused bytes can be used as general-purpose data storage. The LCD driver circuit consists of 16 common signal drivers and 40 segment signal drivers allowing a variety of application configurations to be implemented. Additionally, the user can extend display size by cascading the segment driver LSI NT3882. The maximum display dimensions can be either 80 characters in a 1-line display or 40 characters in a 2-line display. character patterns. Character codes from E0H to FFH are assigned to generate 5 X 10 dot character patterns, and other codes are used to generate 5x8 dot character patterns. 2. 240 Characters: The CG ROM contains 192 5 X 8 dot character patterns and 48 5 X 10 dot character patterns. An example of this type is the NT3881D-02, in which the relation between the character codes and character patterns is shown in Table 2. The character codes from 00H to 0FH are used to get character patterns from the CG RAM. Character codes from 10H to 1FH and from E0H to FFH are assigned to generate 5 X 10 dot character patterns, and other codes to generate 5 X 8 dot character patterns. No null character pattern exists in this type. Note that the underlined cursor, displayed on the 8th duty may be obscure if the 8th row of a dot character pattern is coded. We recommend that users display the cursor in the blinking mode if they code 5x8 dot character patterns is their custom CG ROM. 3. 256 Characters: The CG ROM contains 192 5 X 8 dot character patterns and 64 5 X 10 dot character patterns. No adequate example is presented here. The only difference between this type and the just mentioned second type is that the character codes from 00H to 0FH get character patterns from the CG ROM rather than from the CG RAM. These character codes are assigned to generate 5 X 10 dot character patterns. In this application, the CG RAM would be employed as a general-purpose data storage. Custom character patterns are available by maskprogramming ROM. For convenience of character pattern development, NOVATEK has developed a user-friendly editor program for the NT3881D to help determine the character patterns users prefer. By executing the program on the computer, users can easily create and modify their character patterns. By transferring the resulting files generated by the program through a modem or some other communication method, the user and NOVATEK have established a reliable, fast link for programming the CG ROM.
Character Generator ROM (CG ROM)
The character generator ROM generates LCD dot character patterns from the 8-bit character pattern codes. The NT3881D provides 3 CG ROM configurations: 1. 192 Characters: The CG ROM contains 160 5 X 8 dot character patterns and 32 5 X 10 dot character patterns. An example is the NT3881D-01, in which the relation between the character codes and character patterns is shown in Table 1. The character codes from 00H to 0FH are used to get character patterns from the CG RAM. Character codes from 10H to 1FH and from 80H to 9FH map to full
6
V2.4
NT3881D
Absolute Maximum Ratings*
Power Supply Voltage (VDD) . . . . . . . . . . -0.3V to +0.7V Power Supply Voltage(V1toV5).VDD -13.5V to VDD+0.3V Input Voltage (VI) . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Temperature (TOPR) . . . . . . . . -20C to +75C Storage Temperature (TSTG) . . . . . . . -55C to +125C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
! All voltage values are referenced to GND = 0V ! V1 to V5, must maintain VDD V1 V2 V3 V4 V5.
DC Electrical Characteristics (VDD = 5.0V, GND = VEE = 0V, TA = 25C)
Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VCOM VSEG IIL -IP Parameter "H" Level Input Voltage (1) "L" Level Input Voltage (1) "H" Level Input Voltage (2) "L" Level Input Voltage (2) "H" Level Output Voltage (1) "L" Level Output Voltage (1) "H" Level Output Voltage (2) "L" Level Output Voltage (2) Driver Voltage Descending (COM) Driver Voltage Descending (SEG) Input Leakage Current Pull-up MOS Current Min. 2.2 -0.3 VDD -1.0 GND 2.4 0.9 VDD -1 50 Typ. 125 Max. VDD 0.8 VDD 1.0 0.4 0.1 VDD 2.9 3.8 1 250 Unit V V V V V V V V V V A A IOH = -0.25mA IOL = 1.2mA IOH = -0.04mA IOL = 0.04mA ID = 0.05mA ID = 0.05mA VIN = 0 to VDD VDD = 5V RS, R/W, DB0-DB7 VDD DB0 - DB7 (TTL) Conditions Applicable Pin DB0 - DB7, RS, R/W, E
OSC1
CL1, CL2, M, D (CMOS) COM1 - 16 SEG1 - 40
IOP
Supply Current Power Supply Current
-
0.3
0.5
mA
Rf oscillation, from external clock VDD=5V, fOSC = fCP = 270KHz
7
V2.4
NT3881D
DC Electrical Character (continued)
Symbol Parameter Min. Typ. Max. Unit Conditions Applicable Pin
External Clock Operation fCP External Clock Operating Frequency External Clock Duty Cycle External Clock Rise Time External Clock Fall Time 125 270 350 KHz
tDUTY tRCP tFCP
45 0.1 0.1
50 -
55 0.5 0.5
% s s
Internal Clock Operation (RC Oscillator) fOSC Oscillator Frequency 190 270 350 KHz Rf = 91K 2%
Internal Clock Operation (Ceramic Resonator Oscillator) fOSC VLCD1 VLCD2 Oscillator Frequency LCD Driving Voltage 245 4.6 3.0 250 255 KHz V Ceramic resonator 1/5 bias 1/4bias
VDD
VDD- V5
AC Characteristics
Read Cycle Symbol tCYCE tWHE tRE, tFE (VDD = 5.0V, GND = VEE = 0V, TA = 25C) Parameter Enable Cycle Time Enable "H" Level Pulse Width Enable Rise/Fall Time Min. 500 300 60 tAS tAH tRD tDHR RS, R/W Setup Time RS, R/W Address Hold Time Read Data Output Delay Read Data Hold Time
1
Typ. -
Max. 25
Unit ns ns ns
Conditions Figure 1 Figure 1 Figure 1
100 10 20
2
-
190 -
ns ns ns ns
Figure 1 Figure 1 Figure 1 Figure 1
8
V2.4
NT3881D
AC Characteristics (continued)
Write Cycle (VDD = 5.0V, GND = VEE = 0V, TA = 25C) Symbol tCYCE tWHE tRE, tFE Parameter Enable Cycle Time Enable "H" Level Pulse Width Enable Rise/Fall Time Min. 500 300 60 tAS tAH tDS tDHR RS, R/W Setup Time RS, R/W Address Hold Time Data Output Delay Data Hold Time
1
Typ. -
Max. 25
Unit ns ns ns
Conditions Figure 2 Figure 2 Figure 2
100 10
2
-
-
ns ns ns ns
Figure 2 Figure 2 Figure 2 Figure 2
100 10
Notes: 1: 8-bit operation mode 2: 4-bit operation mode
Timing Characteristics of Interface Signals with Segment Driver LSI NT3882
(VDD = 5V, GND = VEE = 0V, TA = 25C) Symbol tCWH tCWL tSU tDH tCSU tDM Parameter Clock Pulse Width High Clock Pulse Width Low Data Setup Time Data Hold Time Clock Setup Time M Delay Time Min. 800 800 300 300 500 -1000 Typ. Max. 1000 Unit ns ns ns ns ns ns Conditions Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3
Power Supply Conditions Using Internal Reset Circuit
Symbol tRON tOFF Parameter Power Supply Rise Time Power Supply OFF Time Min. 0.1 1 Typ. Max. 10 Unit ns ms Conditions Figure 4 Figure 4
9
V2.4
NT3881D
Timing Waveforms
Read Operation
VIH1 VIL1 tAS R/W tWEM VIH1 E VIL1 tRE tRD VIH1 DB0~DB7 VIL1 tCYCE VALD DATA VIL1 VIL1 tDHR VIH1 tAH tFE VIL1 VIH1 VIL1 tAH VIH1
RS
Figure 1. Bus Read Operation Sequence (Reading out data from NT3881D to MPU) Write Operation
RS VIH1 VIL1 tAS R/W VIL1 tWEM VIH1 E VIL1 tRE tDS VIH1 DB0 ~ DB7 VALD DATA VIL1 tCYCE VIL1 tDHW VIH1 VIH1 VIL1 tAH tFE VIL1 VIL1 VIH1 VIL1 tAH
Figure 2. Bus Write Operation Sequence (Writing data from MPU to NT3881D)
10
V2.4
NT3881D
Timing Waveforms (continued)
Interface Signals with Segment Driver LSI
0.9 VDD 0.9 VDD
CLK1
CLK2 0.1 VDD
tCWH tCSU 0.9 VDD tCSU
tCWH 0.9 VDD 0.1 VDD tCWL
0.9 VDD 0.1 VDD 0.9 VDD 0.1 VDD
0.1 VDD
D
tSU
tDH
M 0.1 VDD tDM
Figure 3. Sending Data to Segment Driver LSI NT3882
Interface Signals with Segment Driver LSI (continued)
4.5V VDD 0.2V
0.1ms > tRON > 10ms
0.2V tRON tOFF > 1ms tOFF
0.2V
Figure 4. tOFF stipulates the time of power OFF for instantaneous power supply to or when power supply repeats ON and OFF.
Note 1: The NT3881D has three clock options:
A. Internal Oscillator Operation (With Ceramic Filter) Rf : 1M 10% Rd : 3.3K 5% C1 = C2 : 680pF 10%
OSC1
OSC2
CERAMIC FILTER
C1
C2
11
V2.4
NT3881D
B. Internal Oscillator (With Rf Resistor) Only Rf may be connected between OSC1 and OSC2. The wire connection Rf must be as short as possible.
OSC1 OSC2
Rf: 91kohm + 2%
C. External Clock Operation OSC1 and OSC2.
OSC1 OSC2
PULSE INPUT
Note 2 : Input/Output Terminals:
A. Input Terminal Applicable Terminal : E (No Pull Up MOS)
VDD
PMOS
NMOS
Applicable Terminals: RS, R/W (with Pull Up MOS)
VDD PULL UP MOS PMOS PMOS VDD
NMOS
12
V2.4
NT3881D
B. Output Terminal Applicable Terminals: CL1, CL2, M, D
VDD
PMOS
NMOS
C. I/O Terminal Applicable Terminals: DB0 to DB7
VDD
PULL UP MOS PMOS
VDD
PMOS VDD ENABLE PMOS
NMOS
NMOS (OUTPUT CIRCUIT) (TRISTATE)
DATA
13
V2.4
NT3881D
Table 1. Correspondence between Character Codes and Character Patterns (NOVATEK Standard NT3881D-01)
14
V2.4
NT3881D
Table 2. Correspondence between Character Codes and Character Patterns (NOVATEK Standard NT3881D-02)
15
V2.4
NT3881D
Instruction Set
Instruction RS RW DB7 DB6 Code DB5 DB4 DB3 DB2 DB1 DB0 Clear entire display area, restore display from shift, and load address counter with DD RAM address 00H. Restore display from shift and load address counter with DD RAM address 00H. Specify direction of cursor movement and display shift mode. This operation takes place after each data transfer (read/write). Specify activation of display (D) cursor (C) and blinking of character at cursor position (B). Shift display or move cursor. Set interface data length (DL), number of display line (N), and character font (F). Load the address counter with a CG RAM address. Subsequent data access is for CG RAM data. Load the address counter with a DD RAM address. Subsequent data access is for DD RAM data. Read Busy Flag (BF) and contents of Address Counter (AC). Write data to CG RAM or DD RAM. Read data from CG RAM or DD RAM. Function Execution time (max) (fOSC = 250KHz)
Display Clear
0
0
0
0
0
0
0
0
0
1
1.64ms
Display/ Cursor Home
0
0
0
0
0
0
0
0
1
*
1.64ms
Entry Mode Set
0
0
0
0
0
0
0
1
I/D
S
40s
Display ON/OFF Display/ Cursor Shift Function Set
0
0
0
0
0
0
1
D
C
B
40s
0
0
0
0
0
1
S/C
R/L
*
*
40s
0
0
0
0
1
DL
N
F
*
*
40s
RAM Address Set
0
0
0
1
ACG
40s
DD RAM Address Set Busy Flag/ Address Counter Read CG RAM/ DD RAM Data Write CG RAM/ DD RAM Data Read
0
0
1
ADD
40s
0
1
BF
AC
0s
40s
1
0
Write data
40s
1
1
Read data
Note 1: Symbol "*" signifies an insignificant bit (disregard). Note 2: Correct input value for "N" is predetermined for each model.
16
V2.4
NT3881D
Instruction Set (continued)
Instruction RS RW DB7 DB6 Code DB5 DB4 DB3 DB2 DB1 DB0 Function Execution time (max) (fOSC = 250KHz) DD RAM : Display Data RAM CG RAM : Character Generator RAM ACG : Character Generator RAM Address ADD : Display Data RAM Address AC : Address Counter
I/D = 1 : Increment S = 1 : Display Shift On D = 1 : Display On C = 1 : Cursor Display On B = 1 : Cursor Blink On S/C = 1 : Shift Display R/L = 1 : Shift Right DL = 1 : 8-Bit N = 1 : Dual Line F = 1 : 5x10 dots BF = 1 : Internal Operation BF = 0 : Ready for Instruction
I/D = 0 : Decrement
S/C R/L DL N F
= 0 : Move Cursor = 0 : Shift Left = 0 : 4-Bit = 0 : Signal Line = 0 : 5x8 dots
Note 1: Symbol "*" signifies an insignificant bit (disregard). Note 2: Correct input value for "N" is predetermined for each model.
17
V2.4
NT3881D
Interface to LCD (1) Character Font and Number of Lines
The NT3881D provides a 5 X 7 dot character font 1-line mode, a 5 X 10 dot character font 1-line mode and a 5 X 7 dot character font 2-line mode, as shown in the table below. Number of Lines 1 Character Font 5 X 7 dots + Cursor (or 5x8 dots) 5 X 10 dots + Cursor 5 X 7 dots + Cursor (or 5x8 dots) Three types of common signals are available as displayed in the table. The number of lines and the font type can be selected by the program.
Number of Common Signals 8
Duty Factor 1/8
1 2
11 16
1/11 1/16
(2) Connection to LCD
The following 4 LCD connection examples show the various combinations between characters and lines. NT3881D can directly drive the following combinations: (a) 5 X 8 Font - 8 character X 1 line (1/8 duty cycle, 1/4 bias)
LCD PANEL
COM1
COM8 SEG1
NT3881D
SEG40
18
V2.4
NT3881D
(b) 5 X 10 Font - 8 character X 1 line (1/11 duty cycle, 1/4 bias)
LCD PANEL
COM1
COM8
NT3881D
SEG1
SEG40 COM11 COM9
(c) 5 X 8 Font - 8 character X 2 lines (1/16 duty cycle, 1/5 bias)
LCD PANEL
COM1
COM8
NT3881D
SEG1
SEG40 COM16
COM9
19
V2.4
NT3881D
(d) 5 X 8 Font - 16 character X 1 line (1/16 duty cycle, 1/5 bias)
LCD PANEL
COM1
COM8 SEG1
NT3881D
SEG40 COM16
COM9
20
V2.4
NT3881D
(3) Bias Power Connection
NT3881D provides 1/4 or 1/5 bias for various duty cycle applications. The power division voltage is described in the following table. The connection of NT3881D, power supply, and resistors are also shown as follows: Power Division V1 V2 V3 V4 V5 1/8, 1/11 Duty Cycle - 1/4 Bias VDD - 1/4 VLCD VDD - 1/2 VLCD VDD - 1/2 VLCD VDD - 3/4 VLCD VDD - VLCD 1/16 Duty Cycle - 1/5 Bias VDD - 1/5 VLCD VDD - 2/5 VLCD VDD - 3/5 VLCD VDD - 4/5 VLCD VDD - VLCD
VDD VDD R V1 R V2 V2 VLCD V3 R V4 R V5 VR VEE V5 V4 V1 VDD
VDD R R
NT3881D
NT3881D
V3
R R
VLCD
R
VR VEE
Note: The resistance value depends on the LCD panel size.
21
V2.4
NT3881D
(4) LCD Waveform
A-type, 1/8 Duty Cycle, 1/4 Bias
400 CLOCKS
COM1 VDD V1 V2 (V3) V4 V5
1
2
3
4
5
8
1
2
1 FRAME A-type, 1/11 Duty Cycle, 1/4 Bias
400 CLOCKS
COM1 VDD V1 V2 (V3) V4 V5
1
2
3
4
5
11
1
2
1 FRAME A-type, 1/16 Duty Cycle, 1/5 Bias
200 CLOCKS
COM1 VDD V1 V2 (V3) V4 V5
1
2
3
4
5
16
1
2
1 FRAME
22
V2.4
NT3881D
B-type, 1/8 Duty Cycle, 1/4 Bias
400 CLOCKS COM1 VDD V1 V2 (V3) V4 V5 1 Frame 1 2 3 4 5 6 7 8 9 16 1 2
1 Frame =
1sec x 400 x 8 = 11.9ms 270K
Frame Frequency =
1 = 84.3Hz 11.9ms
B-type, 1/11 Duty Cycle, 1/4 Bias
400 CLOCKS COM1 VDD V1 V2 (V3) V4 V5 1 Frame 1 2 3 4 5 6 7 8 9 10 11 12 21 22 1 2
1Frame =
1sec x 400 x 11 = 16.3ms 270K
Frame Frequency =
1 = 61.4Hz 16.3ms
B-type, 1/16 Duty Cycle, 1/5 Bias
200 CLOCKS COM1 VDD V1 V2 V3 V4 V5 1 Frame 1 2 3 4 5 13 14 15 16 17 31 32 1 2
1Frame =
1sec x 200 x16 = 11.9ms 270K
Frame Frequency =
1 = 84.3Hz 11.9ms
23
V2.4
NT3881D
Application Circuit (for reference only)
LCD PANEL
C1 - C16
S1
-
S40 D DL1 CL2 CL1 M VDD GND V1 V2
S1
-
S40 DR2 DL2 DR1 DL1 CL2
S1
-
S40 DR2 DL2
NT3882
CL1 M
FCS SEL1 SEL2 GND VDD
NT3882
DR1 FCS SEL1 SEL2
V3
V4
V5
V6
V1
V2
V3
V4
V5
V6
CL2 CL1
NT3881D
M VDD GND
V1 V2 V3 V4 V5
VR R R R R R
C
C
C
C
C
GND or other negative voltage
24
V2.4
NT3881D
Bonding Diagram
80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65 64 63 62 61 60 59 58
NT3881DH
Y
57 56 55 54 X 53 52 51 50 49 48 47 46 45 44 43 42
3861 m
(0, 0)
33 26 27 28 29 30 31 32 81 34 35 36 37 38 39 40
41
3175 m
* Substrate Connect to VDD or keep floating * Pad window area: 120 m X 110 m
25
V2.4
NT3881D
Bonding Dimensions
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Designation SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VDDB M D RS R/W E DB0 DB1 X -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1469 -1183 -1033 -883 -733 -583 -433 -283 -133 76 268 418 568 719 870 1020 1170 Y 1743 1593 1443 1293 1143 993 843 693 543 393 243 93 -57 -207 -357 -507 -657 -807 -957 -1107 -1257 -1407 -1557 -1707 -1862 -1862 -1862 -1862 -1862 -1862 -1862 -1862 -1691 -1862 -1862 -1862 -1862 -1862 -1862 -1862 Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 Designation DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 VDDA X 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1469 1125 975 825 675 525 375 225 75 -75 -225 -375 -525 -675 -825 -975 -1125 76 Unit: m Y -1707 -1557 -1407 -1257 -1107 -957 -807 -657 -507 -357 -207 -57 93 243 393 543 693 843 993 1143 1292 1443 1593 1743 1862 1862 1862 1862 1862 1862 1862 1862 1862 1862 1862 1862 1862 1862 1862 1862 -1816
26
V2.4
NT3881D
Ordering Information
Part No. NT3881DH-01 NT3881DF-01 NT3881DH-02 NT3881DF-02 Package CHIP FORM 80L QFP/B-type waveform CHIP FORM 80L QFP/B-type waveform Remarks Refer to Table 1 Refer to Table 1 Refer to Table 2 Refer to Table 2
27
V2.4
NT3881D
Package Information QFP 80L Outline Dimensions
HD D 80 65
unit: inches/mm
1
64
24
41
25
e GD
b 40 c
HE
GE
E
GD
~ ~
A2 See Detail F Seating Plane
A
y
D
A1
L L1
Detail F
Symbol A A1 A2 b c D E e GD GE HD HE L L1 y
Dimensions in inches 0.130 Max. 0.004 Min. 0.1120.005 0.014 +0.004 -0.002 0.006 +0.004 -0.002 0.5510.005 0.7870.005 0.0310.006 0.693 NOM. 0.929 NOM. 0.7400.012 0.9760.012 0.0470.008 0.0950.008 0.006 Max. 0 ~ 12
Dimensions in mm 3.30 Max. 0.10 Min. 2.850.13 0.35 +0.10 -0.05 0.15 +0.10 -0.05 14.000.13 20.000.13 0.800.15 17.60 NOM. 23.60 NOM. 18.800.31 24.790.31 1.190.20 2.410.20 0.15 Max. 0 ~ 12
Notes: 1. Dimensions D & E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only.
28
V2.4
NT3881D
Product Spec. Change Notice
NT3881 Specification Revision History Version 2.4 2.3 2.2 2.1 2.0 1.0 Content B-type waveform modified(Page 23 , Document mistake corrected) PAD 33 VDDB,PAD 81 VDDA modified( Page 5, 24) Updated Page 16. Updated all diagrams. Modified Page1 NEW SPEC Date Apr.2002 Nov.2001 Nov.2001 Nov.1999 -
29
V2.4

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