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| USBvisionTM II ZR36504 Video & Audio Interface solution via USB Data Sheet Revision 1.00 September 1999. Zoran reserves the right to make changes without further notice to any product herein. Zoran makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Zoran assume any liability arising out of the application or use of any product or circuit, and spec ifically disclaims any and all liability, including without limitation consequential or incidental damages. Zoran products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet to support or sustain life, or for any other application in which the failure of the Zoran product could create a situation where personal injury or death may occur. November-99 Page 2 of 2 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Table of Contents: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. General Architecture............................................................................................................................. 15 Registers Bank (Control and Status) .............................................................................................. 18 Power Management .............................................................................................................................. 25 Video Input Interface ........................................................................................................................... 27 DRAM Control and Interface........................................................................................................... 42 Camera Control Serial Port ............................................................................................................... 47 External EEPROM................................................................................................................................ 55 ZR36504 USB and Status Registers ............................................................................................. 63 Programmable I/O Pins and 48MHz output pin ........................................................................ 65 Audio Channel ........................................................................................................................................ 66 Bulk Channel........................................................................................................................................... 68 Software Package ................................................................................................................................. 71 Mechanical Specification.................................................................................................................... 72 November-99 Page 3 of 3 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet ZR36504 - Full Video and Audio Interface solution for Video via USB The ZR36504 is an ideal solution for digital camera manufacturers who want to utilize the Universal Serial Bus as an interface between the camera and the computer. Using a proprietary video compression algorithm, the ZR36504 enables a throughput of up to 30f/s for CIF size images and up to 15f/s for VGA size images, utilizing only half of total available bandwidth of the USB port. An appropriate software driver in the host computer de-compresses the incoming USB data, consuming only 25% of CPU time (@ CIF 30f/s). The resulting digital image quality is almost identical to the source coming from the camera. This monolithic feature of the ZR36504 makes it ideal to be used as a one chip solution for a very low cost USB portable Video Camera. The ZR36504 can also be used to transfer video sequence from a Composite-Video source to the computer for editing (this requires an additional video decoder chip). Due to the fact that the USB bandwidth used by the ZR36504 can be adjusted (0.5-7.5 Mbit/sec), the video software application always has enough time to record the incoming compressed video data on disk and display full frame rate on screen simultaneously. The ZR36504 is compatible with the NT1003-1, but has a smaller package. It supports simultaneous Serial Digital Audio input and simultaneous external Bulk-Data input as well, and eliminates the need for an external EEPROM to set a specific manufacturer USB ID code. The ZR36504 also supports 16 Mbit DRAMs for a better quality VGA video and still capture. Features * * * * * * * * * * * * * * * * * * Up to 30 frames/sec @ CIF size (352x288 pixels) Up to 15 frames/sec @ VGA size (640x480 pixels) Connects to various YUV sources (4:4:4, 4:2:2, 16 or 8-bit bus) Selectable Raw/Compressed video out Variable Compression ratio Selectable USB bandwidth (0.5Mbps - 7.5Mbps in 0.5Mbps steps): Built-in programmable true scaler (Down Scale - horizontal and vertical) Built in Zoom and Pan capabilities Supports high resolution still image capture (640x480 pixels) Supports serial Digital Audio input (8K/16K samp/sec, 8-bit -Law / 16-bit linear) Auxiliary simultaneous external serial Bulk-data input (0 to 2Mbit/sec). Selectable Data/Clock serial protocols - ideal for camera control Low power consumption (190mW @ 3.3V) - can use USB power source Direct connection to USB port Handles device Power Management (complies with USB standard spec.) Fits Intel's MMX concept Supports most popular software applications that require digital video. Available in 100-pin PQFP and TQFP packages November-99 Page 4 of 4 (R) ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet November-99 Page 5 of 5 ZORAN Corporation Product Description USBvision II Data Decoder ZR36505 Data Sheet Refer to Fig.1 for an internal Block Diagram of the ZR36504. DRAM (4Mb, 16Mb) DIGITAL CAMERA (YUV source) M5M4V4265CTP-6,7 M5M4V4260CTP-6 M5M4V18160CTP-6 SERIAL EEPROM (optional) 24FC16-SN/P AT24C16N-2.7 ZR36504 CHIP DVI Digital Video Intrface DVS Digital Video Scaler MAU Memory Access Unit USBI Universal Serial Bus Interface USB Cable DVC Digital Video Compressor RBCS PMU Power Management Unit Register Bank Control & Status DAI Digital Audio I/F Serial Data In (0-2Mbps) CLK Clock Generator Prog. I/O SelectableSerial Protocols 12MHz X T L Camera Board Logic AUDIO CODEC (optional) OKI MSM7508B OKI MSM7716 FUJ. MB86435 Fig.1 ZR36504 Block Diagram November-99 Page 6 of 6 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet November-99 Page 7 of 7 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet The ZR36504 utilizes a single USB port to enable the host computer to access 4 different data channels simultaneously. These 4 channels are the Digital Video input (7.5Mbit/sec), Digital Audio input, Serial Bulk data input, and I/O control (internal registers, programmable I/O pins, and selectable Data/Clock serial protocols). Due to the sophisticated architecture and protocol of the USB, the software application is not required to take care of the time-sharing management of several tasks using a single serial bus; This is handled by the lower-level drivers, so that the application program can access each function of the ZR36504 independently. In normal operation, the ZR36504 will provide the system with the following services: * Compressed Video Channel: The ZR36504 connects to a Y/U/V video digital source, scales the image on the fly horizontally and vertically, compresses the data down to 0.5-7.5Mbit/sec, and sends it to the host computer via the USB port. The ZR36504 scaler supports zoom-in like effects, by applying combinations of zooming and cropping built-in functions. The unique method of compression is a special design of Zoran, to allow easy and fast de-compression in software only means. The de-compression software driver supplied with the ZR36504, will accept the compressed data and convert it back to standard video formats in less time than it takes to read raw video from any external port. Still images can be captured and sent via the USB in the best quality and resolution that the camera can provide. Sound System: Some camera applications require that a microphone sound system will be implemented inside the camera. Also, a Composite -Video to USB adapter applications requires audio recording support as well. The ZR36504 provides solution for these applications, by multiplexing a serial digital audio input with the video data that is sent via USB port. In such a system, the microphone can be located inside the camera, up to 5 meters away from the host computer. The ZR36504 does not include the audio A/D, and is designed to use an external low-cost telephony audio codec. Camera Control: Camera (or any video source) control and status monitoring can be carried out by a built-in serial interface, or direct I/O pins. The serial interface supports some commonly used serial protocols. These ports can be used by the application software to control and monitor some other remote devices as well. In a Video Conference application, this allows the local or remote user to set the focus, zoom, and other parameters of the camera, or even to switch the camera to the power-down mode. The ZR36504 also supports usage of an external capture button that is mounted on the camera board and used for capturing video frames on the host computer disk (this is application dependent; the ZR36504 only delivers the capture command signaling from button to host computer via USB). * * November-99 Page 8 of 8 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Pin Assignments (Top View) CASN WRN OEN RASN DD5 DD10 GND DD6 DD9 DD12 DD4 DD14 DD2 DD13 DD3 DD15 VDD GND DD1 DD11 DA0 DA1 DD7 DD8 DD0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DA2 DA3 VDD GND DA4 DA5 DA6 DA7 DA8 DA9 SCL/PWR0 SDA/EEPROM PWR1 RESIN GND SENS IICDT IICCK PWR_DWN SUSPND CAPTRN TEST2(VPD) VDDA USB_VP USB_VM 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12 3456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 CLK48 BCLK FS_R FS_L DAT_IN BLK_EN BLK_FULL XOUT VDDA XIN GND IO_2 IO_1 VDDA GNDA FID HSNC VSNC HVALID VCLK TEST1(MST) V7 VDD V6 V5 NT1004 USBVisionTM Video/Audio on USB 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GNDA GND VDD Y0 U3 GND U2 V0 U7 U6 U5 U4 V4 V3 V2 V1 Y2 Y1 Y6 Y5 Y4 Y3 Y7 U1 U0 PIN DESCRIPTIONS PIN NUMBER 3, 28, 53, 78 37, 42, 98 4, 15, 40, 54, 65, 79, 90 1, 36 2, 5-11 12-14,16-20 21-27, 29 SIGNAL VDD VDDA GND GNDA Y0-Y7 U0-U7 V0-V7 I/O DESCRIPTION Digital 3.3V power supply Analog 3.3V supply. 37:PLL, 42:OSC, 98:USB Digital ground connection Analog ground connection. 1:USB, 36:PLL I I I 30 November-99 TEST1(MST) I Video Luminance input from camera. The ZR36504 uses the VCLK input to sample this bus. These input pins are 5-volt tolerant with P.D Video Chroma U or U/V-components input from camera. The ZR36504 uses the VCLK input to sample this bus. These input pins are 5-volt tolerant with P.D. Video Chroma V-component input from camera. The ZR36504 uses the VCLK input to sample this bus in the 24-bit format mode. V2 -V0 inputs are also used to set the idProduct code. V7 V3 inputs are also used to set the idVendor code. These input pins are 5-volt tolerant. Should be connected to GND if not used. This pin must be connected to GND. Page 9 of 9 ZORAN Corporation 31 32 VCLK HVALID USBvision II Data Decoder I I ZR36505 Data Sheet Video Pixel-Clock input from camera. This input pin is 5-volt tolerant. Video Clock Enable input qualifier. This input pin is 5-volt tolerant. Should be connected to GND if not used. PIN DESCRIPTIONS (continued) PIN NUMBER 33 34 35 38-39 SIGNAL VSNC HSNC FID IO-1 - IO-2 I/O I I I I/O DESCRIPTION Video Vertical-Sync input signal from camera. This input pin is 5-volt tolerant. Should be connected to GND if not used. Video Horizontal-Sync input signal from camera. This input pin is 5-volt tolerant. Should be connected to GND if not used. Video Field-ID input signal from camera. This input pin is 5 -volt tolerant. Should be connected to GND if not used. General Programmable I/O pins. Each of these 2 pins has an Open Drain 5v tolerant output, and it is supposed to be connected to an external pull-up resistor. The host uses these pins as programmable output ports by writing '0' or '1'. By writing '1' and read back, the host can use these pins as input ports - as this allows any external source to force the pull-up resistor. These outputs are temporarily set to high-z while in the Suspend position. Crystal Oscillator input pin (12 MHz). Crystal frequency must have not worse than 100 PPM accurac y. Crystal Oscillator output pin (12 MHz). "Bulk-Fifo full" indication output signal. This output signal is normally '0', and is set to '1' when the ZR36504 Bulk -Fifo is full. This output is temporarily set to '0' while in the Suspend or Power-Down position. Bulk Data Enable input. When set to '1', Bulk input data from DAT_IN pin is sampled-in by falling edge of BCLK into the ZR36504 Bulk -Fifo. This input pin is 5-volt tolerant. Data Input pin for both Audio CODEC Tx chan and Bulk Data in. This input pin is 5 -volt tolerant, and requires an external pullup resistor. Audio Codec Frame-Sync pulse for Left channel. This signal triggers the beginning of a new audio sample (left chan.) . This output is temporarily set to '0' while in the Suspend or PowerDown position. Audio Codec Frame-Sync pulse for Right channel. This signal triggers the beginning of a new audio sample (right chan.) . This output is temporarily set to '0' while in the Suspend or PowerDown position. Main Clock for both Audio CODEC and Bulk Data in. This output is temporarily set to '0' while in the Suspend or PowerDown position. 48MHz Clock output for user application. This output is temporarily set to '0' while in the Suspend or Power-Down position. DRAM Data bus input/output pins. These pins have internal PullDown resistors, and are temporarily set to High -Z while in the Suspend or Power-Down position.. DRAM Column-Select control signal. This output is designed to drive 2 input pins of the external DRAM that are tied together (LCAS+UCAS). This output is temporarily set to High -Z while in the Suspend or Power-Down position. DRAM Write control signal. This output is temporarily set to High -Z while in the Suspend or Power-Down position. 41 43 44 XIN XOUT BLK_FULL I O O 45 46 47 BLK_EN DAT_IN FS_L I I O 48 FS_R O 49 50 51-52,55-64,6669 70 BCLK CLK48 DD0-DD15 CASN O O I/O O 71 WRN O November-99 Page 10 of 10 ZORAN Corporation 72 73 74-77, 80-84 85 OEN RASN DA0-DA8 DA9 USBvision II Data Decoder O O O O ZR36505 Data Sheet DRAM Read control signal. This output is temporarily set to High -Z while in the Suspend or Power-Down position. DRAM Row-Select control signa l. This output is temporarily set to High -Z while in the Suspend or Power-Down position. DRAM Row/Column Address-bus. These outputs are temporarily set to '0' while in the Suspend or Power -Down position. DRAM Row/Column MSbit of Address-bus. This outputs is used for 16M DRAMs, and temporarily set to '0' while in the Suspend or Power-Down position. November-99 Page 11 of 11 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet PIN DESCRIPTIONS (continued) PIN NUMBER 86 SIGNAL SCL/PWR0 I/O I/O DESCRIPTION Serial EEPROM clock signal, and LSbit of Device Power Code. If an EEPROM was detected, then this pin is used as the EEPROM clock output signal; otherwise its voltage (Vdd or GND) is used by the ZR36504 as the LSbit of the Device Power Code for the USB Device Descriptor. If EEPROM is detected, this pin is temporarily set to '1' while in the Suspend position. Serial EEPROM data signal, and EEPROM Detect pin. If EEPROM is used, a 10K pull-up resistor to Vdd should be connected to this pin; otherwise it should be tied to GND. During a Reset operation the ZR36504 samples the voltage level on this pin, to determine if an external EEPROM exists. This pin has an Open Drain output, and is temporarily set to high -z while in the Suspend position. MSbit of Device Power Code. The voltage level in this input (Vdd or GND) is used by the ZR36504 as the MSbit of the Device Power Code for the USB Device Descriptor. If an external EEPROM exists, this input is ignored. Power-On Reset input. This input is Schmitt-Trigger type, and it is active low. Serial control Enable Signaling. This pin has an Open Drain output, and is 5v tolerant. It should be connected to an external 3.3-10K pull-up resistor. This output is temporarily set to high -z while in the Suspend or Power-Down position. Camera-Control Data I/O (supports some commonly used serial protocols). This pin has an Open Drain output, and is 5v tolerant. It should be connected to an external 3.3-10K pull-up resistor. This output is temporarily set to high -z while in the Suspend or Power-Down position. Camera-Control Clock output (supports some commonly used serial protocols). This pin has an Open Drain output, and is 5v tolerant. It should be connected to an external 3.3-10K pull-up resistor. This output is temporarily set to high -z while in the Suspend or Power-Down position. Camera Power -Down control. This is an Open Drain 5v tolerant output. The ZR36504 uses this output to switch On/Off the camera and/or external circuit. Upon Reset operation to the ZR36504, this output is set to high-z (=Off). It is also set to high -z in the Suspend position, and remains high-z after Suspend position is over. USB Suspend mode control output. This pin is an Open Drain 5v tolerant output. A Power -On Reset or a USB-Reset clear this output to 0 volt; it is set to high -z when the ZR36504 enters the Suspend mode, and cleared back to '0' upon detection of Resume condition. Capture Command input. This input has an internal pull-up to Vdd. When forced to '0', host computer is automatically informed that a video frame capture was requested by user. This input is Schmitt-Trigger type. This pin must be connected to GND. Universal-Serial-Bus Positive data line; This line should be connected to an external pull-up resistor of 1.5K . Refer to Electrical Characteristics table for pin spec. This pin is kept high -z while in the Suspend position. Universal-Serial-Bus Negative data line. Refer to Electrical Characteristics table for pin spec. This pin is kept high-z while in the Suspend position. 87 SDA/EEPROM I/O 88 PWR1 I 89 91 RESIN SENS I O 92 IICDT I/O 93 IICCK O 94 PWR_DWN O 95 SUSPND O 96 CAPTRN I 97 99 TEST2(VPD) USB_VP I I/O 100 USB_VM I/O November-99 Page 12 of 12 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to GND) Rating Symbol DC Supply Voltage Voltage, any pin to GND DC Current Drain per Pin (Excluding Vdd, GND) Junction Temperature Range Storage Temperature Range Vdd - GND V I TJ T stg Value -0.5 to 4.0 -0.5 to Vdd+0.5 14 -40 to +125 -55 to +125 * Unit V V mA o o C C * 5.5V for 5-volt Tolerant inputs, and 6.0V for 5-volt Tolerant Open-Drain outputs ELECTRICAL CHARACTERISTICS (Vdd=3.3V, TA = 0 to 70 o C) Characteristic Symbol DC Supply Voltage (Vdd to GND) DC Supply Current (@ Vdd=3.3V) Suspend mode Current (@ Vdd=3.3V) High Level Input Voltage (other than XIN, CAPTRN, and RESIN) Min 3.0 2.0 -0.3 0.8 Vdd -0.5 -5 -10 Vdd-0.5 0 25 Typ 3.3 58 +1 5 +1 5 50 Max 3.6 73 200 Vdd+0.3 0.8 Vdd+0.3 0.2Vdd +5 16 +10 16 Vdd 0.4 30 200 * Unit V mA A V V V V A pF A pF V V mA K Vdd ICC I Suspend VIH VIL VIH-s.t VIL-s.t Iin Cin IOZ Cout VOH VOL IOS RPU Low Level Input Voltage (other than XIN, CAPTRN, and RESIN) High Level Input Voltage (XIN, CAPTRN, and RESIN) Low Level Input Voltage (XIN, CAPTRN, and RESIN) Input Current Input Capacitance 3-State Output Leakage Current Output Capacitance High Level Output Voltage (@ Iout = -2mA) Low Level Output Voltage (@ Iout = 2mA) Output Short Circuit Current Pull-Up / Pull-Down Resistance VO = Vdd+0.3 or GND VI = Vdd+0.3 or GND * Vdd+0.3 is for regular inputs. 5-volt Tolerant inputs allow maximum input voltage of 5.25 volt. USB_VP/VM pins ELECTRICAL CHARACTERISTICS (Vdd=3.3V, T A = 0 to 70o C) Characteristic Symbol Min Hi-Z State Data Line Leakage (@ 0 Max +10 2.5 2.0 0.3 3.6 20 20 20 Page 13 of 13 Unit A V V V V V pF nS nS ZORAN Corporation USBvision II Data Decoder Z DRV 28 ZR36505 Data Sheet 43 Driver Output Resistance (@ external serial 24 resistor) VIDEO PARAMETERS SPECIFICATION Parameter Digital Video Input Format (1) Symbol Y/U/V - Value up to 16:1 vertical and horizontal 2-5 taps 2-3 taps 360 /4 any window of length 1 to full image 1-8 48.000 0.5 to 7.5 Mbit/sec o Unit - Down Scaling (V/H independent and arbitrary) Horizontal Anti Aliasing Filter Vertical Anti Aliasing Filter (2) (2) Interpolation Phase Resolution Image Cropping (V/H independent and arbitrary) Video Compression Ratio Video Compressor Clock Frequency Compressed Video Bit Rate Notes: Cr - MHz - 1. Refer to Video Channel chapter for specification of digital video input modes and waveforms. 2. Filter uses interpolation process. USB INTERFACE PARAMETERS SPECIFICATION Parameter USB Maximum Data Rate Compressed Video Maximum Data Rate I/O channel Rate Capacity(1) Notes: Value 12 7.5 0-16 Unit Mbit/sec Mbit/sec Kbit/sec USB Pipe mode Isochronous Control & Bulk 1. I/O channel uses transactions of up to 8-bytes per package. AUDIO PARAMETERS SPECIFICATION Parameter Digital Audio Sampling Rate Audio channel Bit Rate Audio CODEC clock frequency Note: 1. Programmable to either 1.536 or 2.048 MHz. Symbol Fs - Value 8.0/16.0 0.25% 64-512 Kb/sec -Law or A-Law (1) 1.536, 2.048 Unit KHz MHz November-99 Page 14 of 14 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 1. General Architecture The following diagram describes the general architecture of the ZR36504, regarding it as a standard USB device: Host Computer ZR36504 Software Drivers Buffers Message Pipe Message Pipe Bulk Pipe 0-2Mb/s End Point 0 CONTROL type Descriptors & Configurations Stream Pipe 0.5-7.5Mb/s End Point4 BULK DATA IN type Stream Pipe 64-512Kb/s End Point 2 ZR36504 Camera Device End Point3 End Point 1 CONTROL type Register Bank Control & Status Video Data (Compressed or Raw) ISOCHRONOUS DATA IN type ISOCHRONOUS DATA IN type Audio Data November-99 Page 15 of 15 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet The ZR36504 has 5 USB End-Points located on chip: End-Point #0: This is the Descriptors and Configuration End-Point, which is mandatory by the USB standard. This is the ZR36504 Register Bank; the host computer uses these End-Point #1: registers to control the ZR36504 and Camera. End-Point #2: This End-Point produces and sends the digital Video Data to the host computer. It uses 0.5 to 7.5Mb/s of the USB bandwidth, depending on how much bandwidth is available for the camera. End-Point #3: This End-Point sends the input digital Audio Data to the host computer. It uses 64 to 512Kb/s of the USB bandwidth, depending on the audio quantization and sampling rate. End-Point #4: This End-Point sends the external Bulk Data input to the host computer. It uses 0 to 2Mb/s of the USB bandwidth, depending on the external source of data. The ZR36504 has a default set of USB Descriptors on-chip, which are automatically used in absence of an external serial EEPROM (otherwise, all descriptors are read from the EEPROM). The default descriptors allow the host computer to select one of 4 different configurations to operate the camera. Most camera vendors can now use the ZR36504 without an external EEPROM. Also Vendor USB ID and Product ID are now pin programmable, and do not require to add an extra EEPROM. Camera vendors need not use an external EEPROM for a low-cost solution. The ZR36504 and a 4Mb DRAM are sufficient for a fully USB standard compatible camera (this includes the specific given Vendor ID, which identifies the camera with the specific manufacturer). If an external 8-pin serial EEPROM is added, the camera manufacturer can define new configurations (which combine only the available End-Points). Also, String-Descriptors can be added (in multiple languages) to define the camera vendor's name, product name, serialnumber, and others; the USB standard regards these features as optional. The ZR36504 supports USB Power-Management-Protocol. The Camera and external circuits can be power-controlled by their vendor-specific software drivers, via serial Data/Clock, and I/O ports; also, the PWR_DWN output pin can be used to turn off the local power supply to these external circuits (refer to ZR36504 application notes). The ZR36504 uses a single 12MHz crystal to derive all its internal clock sources. Power November-99 Page 16 of 16 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Management also involves switching of internal clock sources which are not in use in certain modes of operation; this further reduces the power consumption of the device. The ZR36504 has two sources of Reset control: The Power-On Reset that comes from a dedicated input pin RESIN, and the USB-Reset command received from the host computer. Both reset sources produce a single reset signal inside the ZR36504, which initializes the ZR36504. It is assumed that a power-on-reset should be applied to the RESIN pin before any USB transaction is sent to the ZR36504 by host; this is required so that the Serial-Interface-Engine inside the ZR36504 will be able to receive any valid host command that will follow (including a USB-Reset command). The total USB bandwidth that is occupied by the ZR36504 is mainly affected by the bandwidth of the Video Data Stream (End -Point #2). In order for a host computer, which initially has a small available bandwidth, not to reject the camera device, the ZR36504 uses the Alternate-Interface mechanism to enable variable bandwidth. This allows the host computer to select the highest bit-rate that it can reserve for the Video Stream, starting from 7.5Mb/s down to 0.5Mb/s in 0.5MHz down steps (the selected bit-rate affects the video quality). November-99 Page 17 of 17 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 2. Registers Bank (Control and Status) The ZR36504 uses the End-Point #1 message pipe for ZR36504 and camera control. As a bi-directional pipe, this channel allows the host computer to write contents to control registers, as well as to read status registers. Also, the control registers can be read by host computer to check their contents. All registers are byte-oriented. The following section defines a USB vendor-specific protocol for Read and Write operations applied to the ZR36504 register bank. This protocol uses a standard USB Request of a vendor-specific type (defined in chapter 9.3 of USB standard rev.1.0) to perform a data transfer of up to 8 bytes long to/from End-Point #1. A single Write operation will write 1-8 concurrent bytes to the register bank, and a single Read operation will read 18 concurrent bytes from the register bank. The USB Request Command always defines the address of the first I/O -register to be read or write; this address is automatically incremented by the ZR36504 for the following data bytes. The first byte of the USB Request Command defines the direction of the data transfer (0x42 for Write, and 0xC2 for Read); the second byte is a ZR36504 specific code - 0x33. The address of the first I/O-register in list is defined in the wIndex parameter of the standard USB Request Command (these are bytes 4 & 5 of the command). All the other bytes in the Request Command are not important to the ZR36504. November-99 Page 18 of 18 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Write transaction protocol: SETUP PID Device Address End-Point #1 Host initiates I/O-Reg operation byte5=0x00 byte0=0x42 byte1=0x33 byte4 = RA I/O-Reg address Host defines Reg-Address ACK PID NT1004 sends handshake to host Device Address End-Point #1 OUT PID Host initiates Write operation DATA-byte #8 (optional) DATA0(1) PID DATA-byte #1 DATA-byte #2 (optional) Reg Data ACK PID NT1004 sends handshake to host ...Empty IN Packet Host terminates Setup Command Host sends handshake to NT1004 IN PID ACK PID The following table specifies the addresses where the ZR36504 stores each of the bytes that appear in the data-section of the USB OUT transaction. These addresses relate to the contents of the wIndex parameter (bytes 4&5 of the SETUP command), which is denoted here by RA. DATA byte # 1 2 3 4 5 6 7 8 Contents Out Data Out Data Out Data Out Data Out Data Out Data Out Data Out Data Description Will be stored in register at address RA. Optional. Will be stored in register at address RA+1. Optional. Will be stored in register at address RA+2. Optional. Will be stored in register at address RA+3. Optional. Will be stored in register at address RA+4. Optional. Will be stored in register at address RA+5. Optional. Will be stored in register at address RA+6. Optional. Will be stored in register at address RA+7. November-99 Page 19 of 19 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Read transaction protocol: SETUP PID Device Address End-Point #1 Host initiates I/O-Reg operation byte5=0x00 byte0=0xC2 byte1=0x33 byte4 = RA I/O-Reg address Host defines Reg-Address ACK PID NT1004 sends handshake to host Device Address End-Point #1 IN PID Host initiates Read operation DATA-byte #8 (optional) DATA0(1) PID DATA-byte #1 DATA-byte #2 (optional) NT1004 sends Data bytes 1-8 ACK PID Host sends handshake to NT1004 ...Empty OUT Packet Host terminates Setup Command NT1004 sends handshake to host OUT PID ACK PID DATA byte # 1 2 3 4 5 6 7 8 Contents Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Description Byte read from register at address RA. Optional. Byte read from register at address RA+1. Optional. Byte read from register at address RA+2. Optional. Byte read from register at address RA+3. Optional. Byte read from register at address RA+4. Optional. Byte read from register at address RA+5. Optional. Byte read from register at address RA+6. Optional. Byte read from register at address RA+7. Note: Reading from an address that does not exist is legal, but will return unpredicted data. November-99 Page 20 of 20 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet The tables in the following pages specify all the Control and Status registers in the ZR36504. A brief description is given for every specific bit in these registers, and the default values (after Reset operation) are defined. For more details about a specific register, consult the appropriate session in this data sheet. General Control Registers (Power, Restart EP, USB, IO-pins, Camera Control): Reg. Reg. Name Function Address 0 PWR_REG d0: WD_EN: '1' Enables USB Watch-Dog timer d1: SSPND_EN: '0' Enables Suspend-Resume logic d2: RES2: '0' Restarts End-Point #2 logic, '1' Releases d3: CLK48_EN: '1' Enables 48MHz at CLK48 output pin. d4: reserved d5: PWR_VID: '1' Video-logic Power-On d6: reserved d7: E2_EN: '1' Enables EEPROM R/W 1 CONFIG_REG d7-d0: Configuration (set via USB). Read-Only reg. 2 ADRS_REG d6-d0: Device Address (set via USB). Read-Only reg. d7: '0'. reserved. 3 ALTER_REG d3-d0: Video Bandwidth (set via USB). Read-Only reg. d7-d4: '0000'. reserved. 4 FORCE_ d3-d0: NEW_ALT Forced Video Bandwidth. R/W reg. ALTER_REG d7: FORCE_ALT ('1'=force, '0'=ignore) d6-d4: '000'. reserved. 5 STATUS_REG d0: VFRM_BLNK Vertic. Blank (if '1'). Read-Only reg. d7-d1: '0000000'. reserved. 6 IOPIN_REG d0: IO_1 Read/Write level of ZR36504 pin IO-1 d1: IO_2 Read/Write level of ZR36504 pin IO-2 d7-d4: TEST[3..0], must be '0000' for proper operation. d3-d2: '00'. reserved 7 SER_MODE d7-d4: MODE (Soft, IICC, Cam1,Cam2,,,) normally (when not in Soft mode): d0: CLK_RATE ('0' = 93.75KHz, '1' =1.5MHz) d1: CLK_POL ('0' = Normal, '1' = Inverted) d2: TEST(auto bulk). Must be '0' for proper operation. d3: VSYNC ('1' = wait to new input video field) Soft mode: d0: CLK_OUT (functional in Soft mode only) d1: DAT_IO (functional in Soft mode only) d2: SENS_OUT (functional in Soft mode only) 8 SER_ADRS d7-d0: Address of serial device/camera-param. 9 SER_CONT d2-d0: SER_LEN Number of bytes to Wr/Rd d3: SER_DIR ('0' = Wr, '1' = Rd) d4: SER_GO/SER_BUSY d5: NACK_RCV (Read-Only. '1' means Not Ack.) d6: CONTINUE (Do not send START signal next time) d7: NO_STOP (Do not send STOP signal this time) st 10 SER_DAT1 d7-d0: 1 serial byte to be sent/received nd 11 SER_DAT2 d7-d0: 2 serial byte to be sent/received rd 12 SER_DAT3 d7-d0: 3 serial byte to be sent/received th 13 SER_DAT4 d7-d0: 4 serial byte to be sent/received November-99 Default Value 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Page 21 of 21 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet EEPROM Read/Write Registers: Reg. Reg. Name Function Address 14 EE_DATA d7-d0: EEPROM byte to be Written/Read 15 EE_LSBAD d7-d0: 8-LSbits of byte address in EEPROM 16 EE_CONT d2-d0: 3-MSbits of byte address in EEPROM d3: EE_DIR ('0' = Write, '1' = Read) d4: EE_GO/EE_BUSY d7-d5: EE_CLK_FORCE (This field is Read-Only) DRAM and Memory Buffers Setup Registers: Reg. Reg. Name Function Address 18 DRM_CONT d0: REF ('0' = 8.2ms, '1' = 128ms refresh rate) d1: DRAM_SIZE. '0' selects 4M, '1' selects 16M d2: RES_UR Restart video out buff. read logic d3: RES_FDL Restart video-frame-delay logic d4: RES_VDW Restart vid.out buff. write logic d5: Bit 9 of UR_1ST_ROW parameter (16M only) also Bit 9 of VDW_1ST_ROW parameter (16M only) d6: Bit 9 of UR_LST_ROW parameter (16M only) also Bit 9 of VDW_LST_ROW parameter (16M only) d7: DRM_COL_SLCT for UR/VDW_LST_ROW 19 DRM_PRM1 d0: Bit 8 of UR_1ST_ROW parameter d1: Bit 8 of UR_LST_ROW parameter d2: Bit 8 of FDL_1ST_ROW parameter d4-d3: Bits 17-16 of FDL_LST_WORD param. d5: Bit 8 of VDW_1ST_ROW parameter d6: Bit 8 of VDW_LST_ROW parameter d7: Bit 18 of FDL_LST_WORD param (16M only). 20 DRM_PRM2 d7-d0: Bits 7-0 of UR_1ST_ROW parameter 21 DRM_PRM3 d7-d0: Bits 7-0 of UR_LST_ROW parameter 22 DRM_PRM4 d7-d0: Bits 7-0 of FDL_1ST_ROW parameter 23 DRM_PRM5 d7-d0: Bits 7-0 of FDL_LST_WORD param. 24 DRM_PRM6 d7-d0: Bits 15-8 of FDL_LST_WORD param. 25 DRM_PRM7 d7-d0: Bits 7-0 of VDW_1ST_ROW parameter 26 DRM_PRM8 d7-d0: Bits 7-0 of VDW_LST_ROW parameter Video Setup and Control Registers: Reg. Reg. Name Function Address 27 VIN_REG1 d2-d0: VIN_MODE Digital video input format d3: VSNC_POL Vertical-Sync. pulse polarity d4: HSNC_POL Horizontal-Sync. pulse polarity d5: FID_POL Field Identity signal polarity d6: HVALID_POL Pixel Envelope polarity d7: VCLK_POL ('1'=data valid on up -going clock) 28 VIN_REG2 d0: AUTO_FID Auto Field Identity generation. When set to '1', the ZR36504 ignores the FID input from camera, and generates an internal toggling signal of its own instead. November-99 Default Value 00H 00H 00H or xxx0000 (when no EPROM) Default Value 00H 00H 00H 00H 00H 00H 00H 00H 00H Default Value 00H 00H Page 22 of 22 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet d1: NONE_INTERLACE Interlace/Non-Interlace mode. If set to '1', all the input fields from camera are processed, otherwise the odd fields are ignored. d2: NO_HVALID If set to '1', HVALID input ignored. d3: UV_ID If set to '1', use V7 pin as UV-id ('1'=U). d4: FIX_2C If set to '1', U7 & V7 are inverted (2's comp ). d5: SEND_FID If set to '1', Frame_Phase[0]=FID. d6: '0' reserved. d7: KEEP_BLANK Set to '1' to drop incoming frames. Video Setup and Control Registers (Continued): Reg. Address 29 30 31 32 33 34 35 36 37 Reg. Name LXSIZE_IN MXSIZE_IN LYSIZE_IN MYSIZE_IN LX_OFFST MX_OFFST LY_OFFST MY_OFFST FRM_RATE Function d7-d0: bits 7-0 of input video line length d1-d0: bits 9-8 of input video line length d7-d2: '000000' reserved. d7-d0: bits 7-0 of input video number of lines d1-d0: bits 9-8 of input video number of lines d7-d2: '000000' reserved. d7-d0: bits 7-0 of input video horizontal offset d1-d0: bits 9-8 of input video horizontal offset d7-d2: '000000' reserved. d7-d0: bits 7-0 of input video vertical offset d1-d0: bits 9-8 of input video vertical offset d7-d2: '000000' reserved. d4-d0: Frame-Rate factor Numerator for video data output d6-d5: Frame-Rate factor Denumerator code: '00': 32, '01': 30, '10': 25 d7: '0' reserved. d7-d0: bits 7-0 of output video line length d1-d0: bits 9-8 of output video line length d7-d2: '000000' reserved. d7-d0: bits 7-0 of output video number of lines d1-d0: bits 9-8 of output video number of lines d7-d2: '000000' reserved. d2-d0: XFILT_CONT Horizontal-Filter select d4-d3: YFILT_CONT Vertical-Filter select d7-d5: '000' reserved. d5-d0 Digital Video-Out format (4:2:2, 4:2:0, compress.) d6: ('1' = Compressed Vid, '0' = Raw) d7: '0' reserved. d7-d0: Intra-Compression cycle (in frame units) d3-d0: ACT_STRIP Actual Strip width (# of vid.lines) d7-d4: VIRT_STRIP Virtual Strip width (# of vid.lines) d0: ('1' = Force next frame Intra) d7-d4: MIN_DENUM[3..0] d3-d1: '000' reserved. d0: ('1' = Force Up -mode Intra segments) d7-d1: STRIP_DAT_LIMIT[6..0]. d7-d0: Threshold for buffer space Frame-Drop decision (given in units of 2KB). d2-d0: Code for YUV re -order processor. d4-d3: BUF_THR[9..8]. Extension for 16Mbit DRAM Default Value 00H 00H 00H 00H 00H 00H 00H 00H 00H 38 39 40 41 42 LXSIZE_O MXSIZE_O LYSIZE_O MYSIZE_O FILT_CONT 00H 00H 00H 00H 00H 43 VO_MODE 00H 44 45 46 INTRA_CYC STRIP_SZ FORCE_INTRA 00H 00H 00H 47 48 49 November-99 FORCE_UP BUF_THR DVI_YUV 00H 00H 00H Page 23 of 23 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet d6: SLOW_CLK12 '1' Select 12MHz for Horiz. blank d7: SLOW_CLK16 '1' Select 16MHz for Horiz. blank d5: '0' reserved. Audio & Bulk-Data Port Read/Write Registers: Reg. Address 50 Reg. Name AUDIO_CONT Function d0: E_A - Enable Audio channel ('1' enables, '0' disables) d1: E_B - Enable Bulk-Data port ('1' enables, '0' disables) d3-d2: BPS - bits/samp: 00: 8b, 01: 12b, 10: 14b, 11: 16b d4: S/M - Select Stereo/Mono. '0': Mono, '1': Stereo. d5: FS - Audio Samp.Rate: '0': 8Ks/sec, '1': 16Ks/sec. d7-d6: BK - Bit-Clk Freq: 1: 64, 2: 1544, 3: 2048 [KHz] d7-d0: Max. number of bytes in Audio packet (0 to 128). d6-d0: Max. number of bytes in Bulk packet (0 to 64). d7: '0' reserved. Default Value 00H 51 52 AUD_PK_LEN BLK_PK_LEN 00H 00H USB Watch-Dog Register: Reg. Address 53 Reg. Name WD_COUNT Function d7-d0: USB_frame Watch-Dog delay parameter. A value 0x00 produces a 686 micro-seconds delay. A value of 0xE9 produces a 996 micro-seconds delay. Any value between these two values affects the delay in steps of 1.33 microseconds. Values bigger than 0xE9 have no effect. Default Value 00H Compression Ratio Management Registers (Continued): Reg. Address 56 57 58 59 60 61 62 Reg. Name PCM_THR1 PCM_THR2 DIST_THR_I DIST_THR_A MAX_DIST_I MAX_DIST_A VID_BUF_ LEFT LFP_LSB LFP_MSB Function d7-d0: PCM Threshold 1 (unsigned 0-255) d7-d0: PCM Threshold 2 (unsigned 0-255) d7-d0: DIST_THR_I (Distortion. Threshold for Inter) d7-d0: DIST_THR_I (Distortion. Threshold for Intra) d7-d0: MAX_DIST (Maximum Distortion for Inter) d7-d0: MAX_DIST (Maximum Distortion for Intra) d7-d0: Space left in ZR36504 DRAM buffer for compressed video data (given in units of 2KB). Read-Only Register. d7-d0: bits 10-3 of LAST_FRM_PNTR (DRAM pointer). Read-Only Register. d6-d0: bits 17-11 of LAST_FRM_PNTR (DRAM pointer) d7: RAM_FULL ('1' if event occurred from last Read). Read-Only Register. d1-d0: VID_BUF_LEFT[9..8]. Ext. for 16Mbit DRAM. d3-d2: LPF[19..18]. Extension for 16Mbit DRAM. d7-d4: '0000' reserved. Read-Only Register. Default Value 00H 00H 00H 00H 00H 00H 00H 63 64 00H 00H 65 VID/LPF 00H November-99 Page 24 of 24 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 3. Power Management In order to meet the USB standard, the ZR36504 should be able to control USB power supply for the whole device. Two pins of the ZR36504 were dedicated to this task: PWR_DWN and SUSPND. Both pins are Open-Drain, and active when Hi-Z. The USB standard requires that soon after a device is hot-connected to the computer, it should consume no more than 100mA from USB port; After configuration, the device may consume up to 500mA from the port. Also it is required that in the Suspend mode the device must not consume more than 0.5mA from the USB port. The ZR36504 uses its power management pins as follows: The PWR_DWN pin was designed to switch the USB 5v source to the video/audio source circuit (CCD, DSP, ADC, -Controller, Video-Decoder, audio CODEC, etc.). The only ICs that continue to get normal power supply in the Power-Down state are the ZR36504, DRAM, and EEPROM (all these are 3.3v operated). The SUSPND pin was designed to enable the designer to shut-down any additional element in the ZR36504 application circuit, which may increase the total current consumption to more than the USB standard allows (> 0.5mA). Refer to the ZR36504 Application Notes for an example of how the PWR_DWN and SUSPND pins should be used, and for the 3.3v supply in application design. The ZR36504 software driver can control part of the power-management process through the following registers of the ZR36504: Parameter SSPND_EN Register address Reg.0/d1 SSPND_EN Reg.0/d5 PWR_VID Reg.0/d2 RES2 Usage Enable Suspend state: 0: Default (after Reset). Responds to USB Suspend condition as required by USB standard. 1: Suspend state is disabled Apply USB 5v to Video/Audio Source 0: Default (after Reset). Video/Audio Source is OFF 1: Video/Audio Source is powered ON Restart End-Point #2 (Vid. pipe) in t he ZR36504: 0: Default (after Reset). Restart ZR36504 video path. 1: Enable ZR36504 Video Processor and Pipe circuit (after video source is powered on). PWR_VID RES2 After USB-Reset, the ZR36504 is in its Power Down state (PWR_DWN pin is Hi-Z). After configuration, software sets PWR_VID bit to '1' to turn on camera circuit November-99 Page 25 of 25 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet (PWR_DWN='0'). Suspend (if SSPND_EN bit not set by S/W), occurs if USB Idle state detected for 3ms, and it also resets PWR_VID bit. November-99 Page 26 of 26 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 4. Video Input Interface The ZR36504 digital video input is YUV format. The ZR36504 interface for this format is flexible and supports 4:4:4 (24-bit) as well as 4:2:2 (8-bit, or 16-bit), and 4:1:1 timings (12bit). Horizontal and Vertical controls can be physical pulses or coded signals; Also, Pixel Clock and pulse polarity of control signals can be programmed to be either positive or negative. All the input buffers in the ZR36504 that are supposed to be connected to the digital video source are 5-volt tolerant. This means that a camera that has 5-volt CMOS outputs will not cause any damage to the ZR36504, even though the ZR36504 operating voltage is 3.3 volts. The ZR36504 digital video input consists of the following signals: Y0-Y7 In the 4:4:4 format (24-bit), 4:2:2 16-bit, and 4:1:1 (12-bit) modes, this is the Luminance input bus. In the 4:2:2 8-bit mode, this bus is used for mux YUV data. This bus is sampled by the VCLK input clock for the unsigned binary value (0-255) of the Y component (or U and V as well in the 8-bit mode). U0-U7 This is the Color (U or U/V) input bus. In the 4:4:4 format (24-bit), This bus is sampled by the VCLK input clock for the unsigned binary value (0-255) of the U component. In the 4:2:2 16-bit and 4:1:1 (12-bit) formats, this bus is sampled by the even cycles of VCLK input clock for the binary value (0-255) of the U component, and by the odd cycles of VCLK input clock for the binary value (0-255) of the V component. V0-V7 This is the Color (V) input bus, which is used in the 4:4:4 format only. This bus is sampled by the VCLK input cl ck for the binary value (0-255) of the V component. In the 4:2:2 o mode (16-bit or 8-bit) and the 4:1:1 mode (12-bit), most of this bus is ignored by the ZR36504 - only V7 is used as an optional U/V identifier. VSNC This is the Vertical Synchronization pulse, which indicates the start of a new video field (in Interlace mode) or the start of a new video frame (in Non-Interlace mode). Normally this pulse is negative. HSNC This is the Horizontal Synchronization pulse, which indicates the start of a new video line. Normally this pulse is negative. November-99 Page 27 of 27 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet FID This signal is used in the Interlace mode, to indicates whether the current field is even or odd. In the Non-Interlace mode this input is ignored by the ZR36504. VCLK This signal is the video pixel clock. It is used by the ZR36504 to sample all the other inputs in the digital video interface. HVALID This input is the pixel valid qualifier. When not active, the ZR36504 refers to the samples that come from the Y, U, and V buses as Blank pixels (which are not considered a part of the digital image). The ZR36504 can be programmed to ignore the HVALID input. The timing of a camera signal that the ZR36504 expects to receive in its digital video interface is normally as specified in the following timing diagram: November-99 Page 28 of 28 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet VSNC HSNC FID First Line Last Line ODD FIELD (if Interlace) EVEN FIELD (if Interlace) not less than 63us HSNC not more than 53us HVALID VCLK Y[0:7] U[0:7] V[0:7] xx y0 y1 y2 y3 xx xx u0 u1 u2 u3 xx xx v0 v1 v2 v3 xx YUV-4:4:4 mode (24-bit) Y[0:7] U[0:7] V7 xx y0 y1 y2 y3 y4 y5 xx xx u0 v0 u2 v2 u4 v4 xx YUV-4:2:2 mode - 16-bit. Note that the order of U/V is set by Reg.49/d0. VCLK Y[0:7] u0 y0 v0 y1 u2 y2 v2 y3 u4 y4 v4 y5 u6 y6 v6 y7 u8 y8 v8 YUV-4:2:2 mode 8-bit. Note that the order of Y/U/V is set by Reg.49/d2-d0 Note: In the YUV 8-bit mode the VCLK frequency is twice the pixel rate. November-99 Page 29 of 29 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet VCLK Y[0:7] U[0:3] xx y0 y1 y2 y3 y4 y5 xx xx VM0 UM0 VL0 UL0 VM1 UM1 xx VM0 = v0[7..4], VL0 = v0[3..0] UM0 = u0[7..4], UL0 = u0[3..0] YUV-4:1:1 mode (12-bit) Video Interface Timing Parameters 90% VCLK_POL = '1' VCLK 10% VCLK_POL = '0' tSU > 15ns tH > 10ns VSNC, HSNC, FID, HVALID, Y[0:7], U[7:0], V[7:0] 90% 90% VALID 10% 10% Input Video Parameters The ZR36504 was designed to interface to m available YUV formats. To make this ost possible, most of video parameters are programmable via specific registers from the ZR36504 Register Bank. The following tables specifies all the parameters that can be set by host computer to fit a specific video source (digital camera, video decoder, etc.): November-99 Page 30 of 30 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Parameter VIN_MODE[2..0] Register address Reg.27/d2-d0 VIN_REG1 Usage Video input mode: 000: 8-bit 4:2:2 mode, using synchronization pulses 001: 8-bit 4:2:2 mode, using CCIR 656 sync. codes 010: 16-bit 4:2:2 mode, using synchronization pulses 011: 16-bit 4:2:2 mode, using CCIR 656 sync. codes 100: 24-bit 4:4:4 mode, using synchronization pulses 110: 12-bit 4:1:1 mode, using synchronization pulses 101, 111: spare. Polarity of VSNC pulse: 0: Synchronize on up-going edge 1: Synchronize on down-going edge Polarity of HSNC pulse: 0: Synchronize on up-going edge 1: Synchronize on down-going edge Polarity of FID (Field Identifier in Interlace mode) : 0: FID='0' during first (odd) field 1: FID='0' during second (even) field Polarity of HVALID signal: 0: input signal HVALID='1' for active pixels 1: input signal HVALID='0' for active pixels Polarity of VCLK (pixel clock): 0: Camera data valid at VCLK falling edge 1: Camera data valid at VCLK rising edge 0: Use external FID signal 1: Generate internal toggling FID. Ignore FID pin. 0: Interlace mode. Only even fields are transferred. 1: Non-interlace mode. All frames are transferred. 0: Normal operation 1: Ignore the HVALID input (assume constant '1') 0: Normal operation 1: Use V7 input as a U/V identifier ('1'=U, '0'=V) Fix 2's Compliment U/V values 0: Normal operation 1: Invert U[7] and V[7] to fix to Unsigned Binary Number of pixels in active line of video source VSNC_POL HSNC_POL FID_POL HVALID_POL VCLK_POL AUTO_FID NON_INTERLACE NO_HVALID UV_ID FIX_2C XSIZE_IN[9..0] Reg.27/d3 VIN_REG1 Reg.27/d4 VIN_REG1 Reg.27/d5 VIN_REG1 Reg.27/d6 VIN_REG1 Reg.27/d7 VIN_REG1 Reg.28/d0 VIN_REG2 Reg.28/d1 VIN_REG2 Reg.28/d2 VIN_REG2 Reg.28/d3 VIN_REG2 Reg.28/d4 VIN_REG2 Regs.29-30 LXSIZE_IN MXSIZE_IN November-99 Page 31 of 31 ZORAN Corporation (continued...) Parameter YSIZE_IN[9..0] USBvision II Data Decoder ZR36505 Data Sheet X_OFFST[9..0] Y_OFFST[9..0] DVI_YUV[2..0] Register address Regs.31-32 LYSIZE_IN MYSIZE_IN Regs.33-34 LX_OFFST MX_OFFST Regs.35-36 LY_OFFST MY_OFFST Reg.49/d2-d0 DVI_YUV Usage Number of active lines in frame (/field) of video source Horizontal offset (number of pixels to be skipped after start of line). Vertical offset (number of lines to be skipped after start of frame). SLOW_CLK12 SLOW_CLK16 Reg.49/d7-d6 DVI_YUV Order of Ya/U/V/Yb components of a pixel-pair in 8-bit modes (d0 affects 16-bit mode also): d0: '0': U comes before V '1': U comes after V d1: '0': Ya comes before U/V '1': Ya comes after U/V d2: '0': Yb comes before U/V '1': Yb comes after U/V Use these control bits for cameras that have slow VCLK or too short Horiz.Blank time interval: d6: '0': Normal operation '1': Select 12MHz clock during Horiz.Blank d7: '0': Normal operation '1': Select 16MHz clock during Horiz.Blank Frame-Rate Control Normally a camera or any other video source provides a fixed number of frames per second - for example, a NTSC based camera will always provide 30 frames/sec. The ZR36504 allows the application software to modify the effective frame rate to fit its needs; in this way some of the frames coming from camera are dropped before processing, which eliminates the effort that could be wasted on those frames that would be dropped by the computer anyway. The parameter that controls the effective frame-rate is called FRM_RATE, and is specified in the following table: Parameter Numerator[4..0] Denum.code[1..0] Register address Reg.37/d4-d0 n Reg.37/d6-d5 code for d Usage Frame Drop factor (n = 0-31). Effective frame rate is: NTSC: 30*(n+1)/ d PAL: 25*(n+1)/d '00': d=32 '01': d=30 '10': d=25 November-99 Page 32 of 32 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet The n parameter ranges from 0 to d-1. The value n=d-1 indicates to the ZR36504 to transfer to host computer full frame-rate that is delivered from the video source. Any value n that is less than d-1 results in a frame-dropping from time to time, so that the effective frame rate is only (n+1)/d of full frame-rate. Video Scaling The ZR36504 has two independent down scalers: one for frame width and one for frame height. It is the responsibility of the software application to select such scale factors that result in a reasonable aspect ratio. In order to set the scaling factor, the host computer should just specify the desired size of the output frame (assuming XSIZE_IN & YSIZE_IN are initially set). Scaling is done automatically by the ZR36504, regarding the output frame size versus the input frame size. The following table specifies the parameters that are used to set the output frame size: Register Usage address Number of pixels in line of scaled output video frame XSIZE_O[9..0] Regs.38-39 LXSIZE_O MXSIZE_O Number of lines in scaled output video frame/field YSIZE_O[9..0] Regs.40-41 LYSIZE_O MYSIZE_O Note that if host computer specifies the same values fo r input frame size and output frame size, then no scaling occurs (scaling factor is 1:1). The ZR36504 performs no Up-Scaling(1). This means that XSIZE_O should never be greater than XSIZE_IN, and YSIZE_O should never be greater than YSIZE_IN. (1) To produce CIF size from 240-line video fields, a special interpolation process is applied by software driver. Parameter Video Filters The ZR36504 uses internal programmable anti aliasing filters for the scaling process. There are two filters that are used: One for the horizontal scaling, and the other for the vertical scaling. The filters are programmed independently of each other, and independently of the scaling factors. Both horizontal and vertical filters use a combination of FIR structure and interpolation to eliminate the pixel jitter in the output frame. The interpolation process effectively improves x4 the resolution of the input frame both horizontally and vertically. November-99 Page 33 of 33 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet The following table specifies the register that is used to set the filter parameters: Register Usage address XFILT_CONT[2..0] Reg.42/d2-d0 Select one of 5 possible Horizontal Filters FILT_CONT YFILT_CONT[1..0] Reg.42/d4-d3 Select one of 3 possible Horizontal Filters FILT_CONT The following table specifies the Horizontal filters: XFILT_CONT[2..0] 000 001 010 011 100 FIR filter applied (Horizontally) FIR = (1.0) FIR = (1.0) FIR = (0.5, 0.5) FIR = (0.25, 0.5, 0.25) FIR = (0.25, 0.25, 0.25, 0.25) Parameter Interpolation (Horizontally) NO YES YES YES YES The following table specifies the Vertical filters: YFILT_CONT[1..0] 00 01 10 FIR filter applied (Vertically) FIR = (1.0) FIR = (1.0) FIR = (0.5, 0.5) Interpolation (Vertically) NO YES YES Video Output Format The ZR36504 supports 3 different formats for the output video data: One is the Compressed data format, and the other two are YUV 4:2:2 and 4:2:0 Raw data formats. The following table specifies the register that is used to set the output video format: Parameter VO_MODE[6..0] Register address Reg.43/d6-d0 VO_MODE Usage Select one of 3 Video Output formats: 0x60 = Compressed data format 0x03 = YUV 4:2:2 Interleaved format 0x14 = YUV 4:2:0 Planar format It is the responsibility of the ZR36504 software driver to make conversions to provide the application software with several OS standard video data formats, but the data that is transferred via USB must be one of these 3 formats. November-99 Page 34 of 34 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet November-99 Page 35 of 35 ZORAN Corporation Compressed Data Format USBvision II Data Decoder ZR36505 Data Sheet The ZR36504 compressor is designed to compress YUV 4:2:0 frames (12 bit/pixel) in a factor between 1:3 to 1:15 (resulting in 4 to 0.8 bit/pixel). The compression algorithm is a proprietary development of Zoran, which meets 3 important requirements that were made to guarantee the high performance of the ZR36504: Fits the selectable bandwidth of the USB (0.5-7.5 Mbit/sec) Variable Compression Rate (in very small steps) Requires minimum CPU time for Decompression (also, fits MMX(R) concept) The ZR36504 compressor compresses specific frames using its Intra mode, and all the others - using its Inter mode. The Intra mode does not require any one of the previous frames, while the Inter mode is always based on the reconstructed previous frame. The Intra frames provide the algorithm some robustness against error propagation between frames, but consume more bits per pixel than the Inter frames. Error propagation within the frame itself (from higher lines to lower lines) is eliminated by dividing the frame into many horizontal strips. The ZR36504 uses 6 parameters to determine how deep a compression to apply. These parameters are expected to b dynamically modified by the software driver in order to e achieve the desired frame rate for a given USB bandwidth. The following table specifies the registers that are used to control the Intra/Inter relationship, and the number of lines in every strip. The table also contains the special threshold parameters that affect the compression rate. Note that these parameters are only relevant when using the Compressed data format: Parameter INTRA_CYC[7..0] Register address Reg.44 INTRA_CYC Usage Automatic Intra cycle length. Specifies the number of Inter frames between every two automatic Intra frames: n = 0: Apply Intra mode on all frames n = 1-254: Allow n Inter frames between every two automatic Intra frames. n = 255: Never apply Intra mode automatically Force Intra mode on all new frames. The software driver is supposed to set this bit temporarily to prevent a channel error from propagating to further frames. 0: Normal operation (do not force Intra) 1: Force Intra mode Force usage of previous video line to compress current line. The software driver may set this bit to 1 if certain cameras are used as the video source. Page 36 of 36 FORCE_INTRA Reg.46 FORCE_INTRA FORCE_UP Reg.47 FORCE_UP November-99 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet ACT_STRIP[3..0] Reg.45/d4-d0 STRIP_SZ Reg.45/d7-d4 STRIP_SZ VIRT_STRIP[3..0] 0: Normal operation (do not force) 1: Force dependency on previous line. Actual Strip width. This parameter specifies to the ZR36504 compressor how many video lines should be packed into a single strip packet. A strip packet contains up to 400 bytes. Virtual Strip width. This parameter specifies to the ZR36504 compressor the maximum number of video lines that are allowed to be dependent. n = 0: Use same value as ACT_STRIP n = 1-14: Use 4xn lines for Virtual strip width n = 15: Use frame full height for Virtual strip width (continued...) Parameter STRIP_DAT_ LIMIT[6..0] Register address Reg.47/d7-d1 FORCE_UP Usage This parameter specifies the maximum number of bytes to be packed in a single Actual Strip. The default value of this parameter is 0, and it sets the max number of bytes to 400. Any other value N between 1-127 will set the max number of bytes to 273+N. Compression Threshold 1. Recommended range: [0,20] (0 for best quality, 20 for minimum bits/pixel). Compression Threshold 2. Recommended range: [0,9] (0 for best quality, 9 for minimum bits/pixel). Compression Average Distortion Threshold for Inter frames. Recommended range: [0,255] (0 for best quality, 255 for minimum bits/pixel). Compression Average Distortion Threshold for Intra frames. Recommended range: [0,200] (0 for best quality, 200 for minimum bits/pixel). Compression Maximum Distortion Threshold for Inter frames. Recommended range: [0,50] (0 for best quality, 50 for minimum bits/pixel). Compression Maximum Distortion Threshold for Intra frames. Recommended range: [0,28] (0 for best quality, 28 for minimum bits/pixel). PCM_THR1[7..0] PCM_THR2[7..0] DIST_THR_I[7..0] DIST_THR_A[7..0] MAX_DIST_I[7..0] MAX_DIST_A[7..0] Reg.56 PCM_THR1 Reg.57 PCM_THR2 Reg.58 DIST_THR_I Reg.59 DIST_THR_A Reg.60 MAX_DIST_I Reg.61 MAX_DIST_A November-99 Page 37 of 37 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet YUV 4:2:2 Interleaved Format In this format the ZR36504 transfers to host computer 2 bytes per every pixel (16-bit/pixel). The Y -component is available for every pixel, but the U and V components are each available for every second pixel (Y0,U0,Y1,V2,Y2,U2,Y3...). YUV 4:2:0 Planar Format In this format the ZR36504 transfers to host computer 3 bytes per every 2 pixels (12bit/pixel). The Y-component is available for every pixel, but the U and V components are only available for every second pixel in even lines. In this mode the host computer gets the frame already formatted in the planar mode; this can save CPU time in the host computer in most Video Conferencing applications. The Y and U/V components are packed by the ZR36504 in 64-bytes packets, and have the following structure: Packet number 1 2 3 Contents Pixels 0-63 of the Y-Image Pixels 64-127 of the Y-Image Pixels 0-63 of the U-Image (o r V-Image) The U-Image and V-Image are half-size of the Y-Image in both horizontal and vertical dimensions. The ZR36504 produces a line of U pixels followed by a line of V pixels, and then U pixels again in a toggling manner. These pixels are always packed in this modulo -3 packet. The host computer - knowing the frame -size - can separate between U and V components. Pixels 128-191 of the Y-Image Pixels 192-255 of the Y-Image Pixels 64-127 of the U-Image (or V-Image) 4 5 6 . . . Video Buffer Control registers The ZR36504 uses a pre-defined DRAM space to store the output video data before being transferred to USB; this buffer is called Video Buffer, and it is used as a Fifo which observes data bursts at the video frame rate (up to 30Hz) and supplies data bursts at the USB frame rate (1000 packets per second). November-99 Page 38 of 38 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet The size of the Video Buffer is set by the host computer via the DRAM registers. Depending on USB bandwidth and output frame size and rate, this buffer may become full in the middle of a video streaming. In this case, additional frames will be dropped out by the ZR36504, until enough free space is available in buffer. When operating in the Compressed mode, the host computer can alter the compression rate by modifying some threshold registers on the fly; in this way it can prevent most of the "buffer-full" events, which results in a stable framerate (that is to say, frames are not dropped). To enable the host computer to monitor the status of the Video Buffer and control frame-dropping, the ZR36504 provides the following registers: Parameter BUF_THR [9..0] Register address Reg.48/d7-d0 Reg.49/d4-d3 Usage Minimum remaining buffer space to begin frame dropping (units are in 2KB). "Buffer-Full" occurs when remaining buffer space is less than the value in this register. The host computer sets this register according to the maximum space that a video frame may occupy. This is a Read-Only register that provides the actual remaining buffer space (units are in 2KB). The host computer can prevent "Buffer-Full" occurrence by monitoring this register and changing compression thresholds. This is a Read-Only register that provides the DRAM address for data write in the Video Buffer at the end of every video-frame (units are in 16-byte). The host computer can keep track of the current compression rate by monitoring this register from time to time. VID_BUF_LEFT [9..0] Reg.62/d7-d0 Reg.65/d1-d0 LFP [19..0] Reg.63/d7-d0 Reg.64/d6-d0 Reg.65/d3-d2 Special Video Control bits The ZR36504 has two special bits in the VIN_REG2 register, which can alter the input video sequence. These bits are normally used during still capture operation, and are specified in the following table: Parameter SEND_FID Register address Reg.28/d5 VIN_REG2 Usage Send FID information in frame header data. The FID information is used for reconstructing a 2 -field frame from an Interlace camera. 0: Default value. 1: FID bit overrides bit 0 of Frame_Phase[4..0]. Force a "blank" position on the input video frame source, and drop new frames. Software driver should take care to switch this bit from '0' to '1' during a true blank position. 0: Default value. Page 39 of 39 KEEP_BLANK Reg.28/d7 VIN_REG2 November-99 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 1: Keep existing blank longer by forcing "blank". November-99 Page 40 of 40 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet USB Pipe Video Data Format Data Packets: The Video data is received by the host computer as a stream of bytes via End -Point 2 Isochroneous pipe. There is an incoming data packet every 1ms (every USB-Frame), and its size is limited by the maximum bandwidth that was initially set for End-Point 2; The maximum byte-count for each packet is one of the following numbers: 959 (for 7.5Mb/sec), 895, 831, 767, 703, 639, 575, 511, 447, 383, 319, 255, 191, 127, or 63 (for 0.5Mb/sec). Regarding the data on the USB - the data of a new Video-Frame always starts in a new data packet, so in most cases the last packet of a video frame is shorter than a normal packet. The ZR36504 sends one ore more empty packets between every two video frames. Video Frame Synchronization: In all modes of operation (Compressed or Raw video) two concurrent Video Frames will be separated by at least one empty Data Packet. This is used by the ZR36504 S/W driver to detect a Start-Of-Video-Frame. Also, the first two bytes of the Video Frame Header contain a Start-Of-Video-Frame-Pattern (=0xAA55), which are used by S/W driver as a qualifier to verify that the data represents an uncorrupted Video-Frame. Video Frame Header: Every Video Frame has a header that comes first. The header data is organized in Little Endian format; That's to say, the LSB of a 2-bytes parameter comes prior to the MSB (LSB occupies the lower address). The same header format is used in all modes of operation. The following table specifies the parameters of this header: Offset 0 2 3 Param. Name Vid_Frm_Patt Header_Length Frame_Numb No. of Bytes 2 1 1 Description & Specification 0xAA55 = Start of Video -Frame Pattern Number of bytes in this header = 12 D4-D0: Unsigned integer. Incremented (mod 32) on every frame that is delivered to host computer. D7: Capture_Pressed (active if '1'). D6: Resumed ('1': first frame after Suspend) D5: spare D4-D0: Unsigned integer. Incremented mod 30 on every frame that is acquired from camera. D7-D5: spare Unsigned integer. Number of milliseconds elapsed from the moment that the camera began delivery of this frame to ZR36504, to the moment that the ZR36504 began delivery of frame-header to USB. D7: '0'=Vendor Specific (like ZR36504) ( '1'=Class Specific ) D6: '0'=Raw Data, '1'=Compressed Data D5-D0: Vid_Format_Code: 0x03 = YUV-4:2:2 0x14 = YUV-4:2:0 Planar 0x06-0x12, 0x15 -0x1F = spare 0x20 = Zoran's Compression D7: Intra_Frame ('1'=Intra, '0'=Inter+Intra). This bit should be ignored in raw data frames. D6: spare 4 Frame_Phase 1 5 Frame_Latency 1 6 Data_Format 1 7 Format_Param 1 November-99 Page 41 of 41 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 8 10 Frame_Width Frame_Height 2 2 D4-D0: Pix_Depth (number of bits per pixel). These bits should be ignored in compressed data frames. Unsigned Word integer - number of pixels per line. Unsigned Word integer - number of lines in frame. 5. DRAM Control and Interface The ZR36504 requires an external 16bit x 256K DRAM to operate (VGA cameras require a 16bit x 1024K DRAM to provide 15f/s). The DRAM operation voltage must be 3.3v, and its access time must be 60nS or less. The ZR36504 uses the Fast-Page-Read and FastPage-Write DRAM access modes only. Refresh cycles are automatically inserted between Read or Write bursts by the ZR36504. The ZR36504 allocates two ranges of memory addresses in the external DRAM, that are regarded as memory buffers: Video Output data buffer. The ZR36504 uses this buffer as a FIFO, to store output data from its compressor (in the Compressed video mode) or from its scaler (in the Raw video mode). Previously written data is read to be sent to host computer via USB transfers (End-Point 2). Video Frame Delay Line buffer. This buffer is used in the Compressed Video mode only. The ZR36504 uses this buffer as a huge FIFO, to store the current reconstructed frame. The compressor always needs to read the previous reconstructed frame as a reference image in the Compression Video mode. Each of these buffers is assigned a Start-Address and an End-Address (which relate to the physical 20-bit address-space 0x00000-0xFFFFF of the DRAM). These addresses are supposed to be defined by the ZR36504 software driver as a part of the video stream initialization. The following registers of the ZR36504 are used to set the addresses of the two buffers: Parameter DRAM_SIZE DRM_COL_SLCT Register address Reg.18/d1 Reg.18/d7 Usage '0': Selects 4Mbit DRAM (16bit x 256K) '1': Selects 16Mbit DRAM (16bit x 1024K) Defines address bit a19 for end of Video Output data buffer if 16Mbit DRAM used. This parameter is used as an extension for UR_LST_ROW and VDW_LST_ROW. Start Address of Video Output data buffer for Read. Only a18..a9 are specified, a8..a0 are always '0' (start of a DRAM row). The bit a19 is also always '0'. End Address of Video Output data buffer for Read. Only a18..a9 are specified, a8..a0 are Page 42 of 42 UR_1ST_ROW [9..0] Reg.18/d5, Reg.19/d0, Reg.20/d7-d0 Reg.18/d6, Reg.19/d1, UR_LST_ROW [9..0] November-99 ZORAN Corporation USBvision II Data Decoder Reg.21/d7-d0 ZR36505 Data Sheet FDL_1ST_ROW [8..0] (continued...) Parameter FDL_LST_WORD [18..0] Reg.19/d2, Reg.22/d7-d0 always '1' (end of a DRAM row). The bit a19 is defined by DRM_COL_SLCT parameter. Start Address of Video Frame Delay Line buffer. Only a17..a9 are specified, the other 11 bits are always '0' (start of a DRAM row). VDW_1ST_ROW [9..0] VDW_LST_ROW [9..0] Register address Reg.19/d7 Reg.19/d4-d3 Reg.23/d7-d0 Reg.24/d7-d0 Reg.18/d5 Reg.19/d5 Reg.25/d7-d0 Reg.18/d6 Reg.19/d6 Reg.26/d7-d0 Usage End Address of Video Frame Delay Line buffer. Start Address of Video Output data buffer Write. Normally should be equal UR_1ST_ROW. End Address of Video Output data buffer Write. Normally should be equal UR_LST_ROW. for to for to Register 18/d0 of the ZR36504 contains 3 bits named RES_UR, RES_FDL, and RES_VDW. These are used to restart the appropriate FIFO pointers that are used for DRAM access. The ZR36504 software driver is supposed to set these bits to '1' and then to '0' if addresses of any of these buffers were modified. The ZR36504 performs a Refresh cycle to DRAM from time to time. A special bit - REF in register 18 specifies the refresh time for the whole address space. This allows the user to use either a 8.2ms refresh chip or a 128ms one (Selecting 8.2ms mode will fit both 4M and 16M DRAM types). DRAM Interface Signals The following signals are used by the ZR36504 for DRAM access: DA[9..0]: DD[15..0]: RASN: CASN: WRN: OEN: November-99 Address-Bus, multiplexed Row address and Column address. If a 4Mbit DRAM is used, DA[9] should be left open. Data-Bus, bi-directional bus with internal pull-down. Raw-Address Select (active Low). Column-Address Select (active Low. Can drive two DRAM pins). Write Enable signal (active Low). Read Enable signal (active Low). Page 43 of 43 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet The timing table and diagrams in the following pages specify the Refresh, Fast-Page-Write, and Fast-Page-Read cycles of the ZR36504: November-99 Page 44 of 44 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Symbol tRC tRAS tRP tCPN tCSR tCHR tRPC tCRP tCSH tRCD tCAS tPC tCP tRSH tASR tRAH tASC tWCS tWCH tCAH tDS tDH tRAD tOCH tCPRH tDSR tDHR Refresh Cycle Time Parameter Min 144 82 60 60 19 40 40 60 81 60 22 40 19 40 5 40 5 19 40 19 5 19 40 60 60 2 0 Max 148 85 64 64 23 44 44 64 85 64 25 44 23 44 23 44 23 23 44 23 22 37 55 64 64 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns RASN low pulse width RASN high pulse width CASN high pulse width CASN setup time before RASN low CASN hold time after RASN low RASN high to CASN low CASN high to RASN low CASNhold time after RASNlow RASNlow to CASNlow CASN low pulse width Fast page mode read/write cycle time CASN high pulse width RASN hold time after CASN low Row address setup time before RASN low Row address hold time after RASN low Column address setup time before CASN low Write setup time before CASN low Write hold time after CASN low Column address hold time after CASN low Write data setup time before CASN low Write data hold time after CASN low Column address delay time from RASN low CASN hold time after OEN low RASN hold time after CASN precharge Read data setup time before CASN high Read data hold time after CASN high November-99 Page 45 of 45 ZORAN Corporation USBvision II Data Decoder Refresh Cycle Timings tRC tRAS tRP ZR36505 Data Sheet RASN CASN tCPN tCSR tCHR tRPC WRN OEN Fast-Page-mode Write Timings tRAS tCSH tRCD tPC tCAS tCP tRSH tRP RASN CASN tCRP tASR tRAH tWCS tCAH tDS tWCH WRN OEN DA[9..0] DD[15..0] ROW ADDRESS DATA VALID-1 tASC COLUMN ADDRESS COLUMN ADDRESS DATA VALID-2 COLUMN ADDRESS DATA VALID-3 tDH COLUMN ADDRESS DATA VALID-4 ROW ADDRESS Fast-Page-mode Read Timings November-99 Page 46 of 46 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet tRAS tCSH tRCD tPC tCAS tCP tRSH tRP RASN CASN tCRP tASR tRAD tRAH tOCH tCAH tCPRH tDSR OEN WRN DA[9..0] DD[15..0] ROW ADDRESS tASC COLUMN ADDRESS COLUMN ADDRESS tDHR COLUMN ADDRESS DATA VALID-1 COLUMN ADDRESS DATA VALID-1 ROW ADDRESS DATA VALID-1 DATA VALID-1 6. Camera Control Serial Port The ZR36504 has a dedicated Programmable Serial Port intended to be used for camera control; this port has several modes of operation, where the ZR36504 is always the busmaster (one of the more useful modes is IICC). The programmable serial port is controlled by the host computer via the following registers of the ZR36504 register bank: SER_MODE, SER_ADRS, SER_CONT, SER_DAT1, SER_DAT2, SER_DAT3, and SER_DAT4. Camera Control uses 3 dedicated pins of the ZR36504 pinout: IICCK is an Open Drain output pin, used to drive the serial port clock signal. It is supposed to be connected to an external 3.3-10K pull-up resistor to 3.3-5v. IICDT is an Open-Drain bi-directional pin, used to send and receive the serial port data. It is supposed to be connected to an external 3.3-10K pull-up resistor to 3.3-5v. SENS is an Open Drain output pin, used as a serial control strobe signal in some modes of operation. It is supposed to be connected to an external 3.3-10K pull-up resistor to 3.35v. There are 6 modes of operation available for the Camera Control Port. These are listed in the following table, and described in more detail in the following paragraphs: Mode Number 0 1 November-99 Mode Name Soft SIO Description Bit-level Software controlled mode Serial clocked I/O Page 47 of 47 ZORAN Corporation 2 3 4 5 IIC LRACK IIC LRNACK CAM1 CAM2 USBvision II Data Decoder ZR36505 Data Sheet IICC with Last Byte Read Acknowledged IICC with Last Byte Read Not Acknowledged Camera 1 - refer to timing diagram Camera 2 - refer to timing diagram Modes number 1 are referred as Automatic modes: In these modes the host computer -5 only needs to write the data bytes (and the device address byte - in some of them) in certain registers (SER_DAT1 to SER_DAT4, and SER_ADRS) and initiate a transfer request; in a similar way the host computer can read received data from same registers. The SER_MODE register has some specific bits that can turn the automatic modes into more flexible serial data formats. These register bits are: CLK_RATE: Writing '0' to this bit will select a 93.75KHz clock at IICCK output. Writing '1' to this bit will select a 1.5MHz clock at IICCK output. CLK_POL: Writing '0' to this bit will select the normal polarity at IICCK output. Writing '1' to this bit will select an inverted polarity at IICCK output. VSYNC: Writing '0' to this bit will select an immediate transfer. Writing '1' to this bit will delay start-of-transfer to camera blank period. Another register that is used by the automatic modes is the SER_CONT register. This register is used by the host computer to control the serial port machine. The SER_CONT register consists of the following control bits: SER_LEN: This field contains a 3-bits binary integer that specify the number of data bytes that the host wishes to transfer in the serial transaction (the address byte is not counted). The range of this parameter is 0 to 4. SER_DIR: Writing '0' to this bit selects a Write operation (host to camera). Writing '1' to this bit selects a Read operation (camera to host). SER_GO/SER_BUSY: This is used as both a command and a status bit. Writing '1' to this bit will initiate a serial transfer request. The serial transfer will either start immediately, or wait until the vertical blank time interval is detected at the camera video signal (depends on VSYNC bit). The SER_GO/SER_BUSY bit will remain '1' till the end of transaction, to indicate to the host computer when a new transaction can be initiated. NACK_RCV: This is a Read-Only bit, and it is used in modes 2 and 3 only (IICC November-99 Page 48 of 48 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet modes). The ZR36504, after completing a serial transfer of this mode, reports to the host computer via this bit whether or not all transmitted bytes were acknowledged by the camera (this includes address byte and all data bytes that were sent from host to camera). A '0' in this bit indicates all ACK, and a '1' indicates a NACK for one or more bytes. NO_STOP: This bit is used in modes 2 and 3 only (IICC modes), and enables multiple transactions inside a single START/STOP frame. When set to '1', it informs the serial machine to omit the STOP pattern at the end of the following transaction. Combined with the CONTINUE bit, this enables the S/W driver to perform long transactions (i.e. for downloading the Gama-Correction table into camera DSP). CONTINUE: This bit is used in modes 2 and 3 only (IICC modes), and enables multiple transactions inside a single START/STOP frame. When set to '1', it informs the serial machine to prepare for multiple transactions mode. It will never affect the following transaction, but the one coming after it, which will not contain a START pattern. The following pages specify all the 6 modes of operation for the camera-control serial port. November-99 Page 49 of 49 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Soft Mode: (MODE=0) This mode is selected when the MODE field (d7-d4) of the SER_MODE register is set to 0. In this mode the host computer can access the serial port pins directly, in order to enable control of cameras that are not supported by the other automatic modes. In the Soft mode, the value of CLK_OUT bit (d0) is reflected in the IICCK output pin. A Write operation to the DAT_IO bit (d1) sets the value of the IICDT pin; A Read operation from the same DAT_IO bit reads the actual voltage level at the IICDT pin. The value of SENS_OUT bit (d2) is reflected in the SENS output pin. SIO Mode: (MODE=1) This is the Serial Clocked I/O automatic mode, and it is selected when the MODE field (d7d4) of the SER_MODE register is set to 1. The following waveform describe the SIO mode: IICCK IICDT SENS NOTE: In both Read and Write sequence, data is sampled in the up-going edge of the clock IICCK. x D7 D6 D5 D4 D3 D2 D1 D0 x IICCK IICDT SENS Byte 1 Byte 2 Byte 4 NOTE: In the SIO mode 1 to 4 bytes are written or read. November-99 Page 50 of 50 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet IIC LRACK Mode: (MODE=2) This is the IIC LRACK (Last Read Acknowledged) automatic mode, and it is selected when the MODE field (d7-d4) of the SER_MODE register is set to 2. In this mode, the IICCK frequency is set to 93.75KHz. IICCK IICDT x D7 D6 D5 D4 D3 D2 D1 D0 Ack NOTE: In both Read and Write sequence, data should be stable during the '1' state of the clock IICCK. D7-D0 are sent by transmitter, Ack is sent by receiver. Start Stop IICCK IICDT Write ADDRESS R/W Byte 1 R/W Byte 4 NOTE: Start is defined when the IICDT turns from '1' to '0' while the IICCK is '1'. Stop is defined when the IICDT turns from '0' to '1' while the IICCK is '1'. The Address byte is written like any other byte. IICCK Stop IICCK Stop Ack End of Write sequence IICDT IICDT Ack End of Read sequence In this mode, The host defines the camera address byte and the data bytes to be written to the camera in the appropriate registers; then the ZR36504 sends these bytes automatically. In a similar way the ZR36504 can read data bytes from the camera. The ZR36504 acknowledges the last byte read like all the other bytes. By using the NO_STOP and CONTINUE bits, one can perform a concatenation of multiple IICC transactions, in order to send or receive more than 4 bytes in a single START/STOP frame. Also, by using these control bits, one can combine Write/Read operations with a single STOP pattern at the end. Note that the SER_LEN parameter can be set to 0 to further support the concatenation mode of operation. IIC LRNACK Mode: (MODE=3) This is the IIC LRNACK (Last Read Not Acknowledged) automatic mode, and it is selected when the MODE field (d7-d4) of the SER_MODE register is set to 3. In this mode, the IICCK frequency is set to 93.75KHz. November-99 Page 51 of 51 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet In this mode, the host defines the camera address byte and the data bytes to be written to the camera in the appropriate registers; then the ZR36504 sends these bytes automatically. In a similar way the ZR36504 can read data bytes from the camera. The ZR36504 does not acknowledge the last byte read from camera; this is done as a signaling to the camera, that no more bytes are needed. The waveforms for this mode of operation are specified in the following page. IICCK IICDT x D7 D6 D5 D4 D3 D2 D1 D0 Ack NOTE: In both Read and Write sequence, data should be stable during the '1' state of the clock IICCK. D7-D0 are sent by transmitter, Ack is sent by receiver. Start Stop IICCK IICDT Write ADDRESS R/W Byte 1 R/W Byte 4 NOTE: Start is defined when the IICDT turns from '1' to '0' while the IICCK is '1'. Stop is defined when the IICDT turns from '0' to '1' while the IICCK is '1'. The Address byte is written like any other byte. IICCK Stop IICCK Stop Ack End of Write sequence IICDT IICDT Nack End of Read sequence In this mode, The host defines the camera address byte and the data bytes to be written to the camera in the appropriate registers; then the ZR36504 sends these bytes automatically. In a similar way the ZR36504 can read data bytes from the camera. The ZR36504 does not acknowledge the last byte read (Nack). By using the NO_STOP and CONTINUE bits, one can perform a concatenation of multiple IICC transactions, in order to send or receive more than 4 bytes in a single START/STOP frame. Also, by using these control bits, one can combine Write/Read operations with a single STOP pattern at the end. Note that the SER_LEN parameter can be set to 0 to further support the concatenation mode of operation. CAM1 Mode: (MODE=4) November-99 Page 52 of 52 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet This mode is selected when the MODE field (d7-d4) of the SER_MODE register is set to 4. In this mode, the IICCK frequency must not exceed 10MHz. In this mode three signals are used: IICCK, IICDT, and SENS. The host defines the desired camera register address byte and a single data byte to be written to that register in the appropriate ZR36504 registers; then the ZR36504 first sends the address and then the data automatically. In a similar way the ZR36504 can read a data byte from any given camera register. The waveforms for the CAM1 mode are specified in the following diagram. Note that every byte transfer has its own start condition, which indicates one of 3 possibilities: Address Write, Data Write, or Data Read. IICCK IICDT SENS 0 0 A7 A6 A5 A4 A3 A2 A1 A0 Start Address Write IICCK IICDT SENS 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Start Data Write IICCK IICDT SENS 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Note: NT1004 relieses data signal (IICDT='1') at this point Start Data Read Register Write operation: Register Read operation: Address Write Data Write Address Write Data Read NOTE: A transaction consists of Address Write, followed by Data Write or Data Read. CAM2 Mode: (MODE=5) November-99 Page 53 of 53 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet This mode is selected when the MODE field (d7-d4) of the SER_MODE register is set to 5. In this mode, the IICCK frequency must not exceed 10MHz. In this mode only two signals are used: IICCK, and IICDT. The host defines the desired camera register address byte and a single data byte to be written to that register in the appropriate ZR36504 registers; then the ZR36504 first sends the address and then the data automatically. Note that in this mode both address and data consist of 7-bit only; In this mode there is no way to read data from camera. The waveforms for the CAM2 mode are specified in the following diagram. Note that every byte transfer has its own Transfer start signaling (which is identical for both address and data), followed by an Address Write condition or a Data Write condition. IICCK 0 IICDT 1 A6 A5 A4 A3 A2 A1 A0 Address Write Transfer start IICCK 0 IICDT 0 D6 D5 D4 D3 D2 D1 D0 Data Write Transfer start Register Write operation: Address Write Data Write NOTE: Data is sampled on the down-going edge of the clock IICCK. A transaction consists of Address Write, followed by Data Write. November-99 Page 54 of 54 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 7. External EEPROM The ZR36504 provides a full USB compliant solution without the need for an external EEPROM (USB Vendor ID is pin programmable). Anyway, when UNICODE names are required, the ZR36504 can use an external 3.3v 2KB Serial EEPROM as an optional source for USB descriptors. There are several vendors that produce these 8-pin EEPROM chips, which are pin-to-pin compatible. Normally the external EEPROM will be only read in a working device (mainly soon after USB insertion). Anyway, the ZR36504 supports On -Board EEPROM programming, which can be used to alter some USB descriptors - especially the product serial number. The ZR36504 register bank includes special registers to perform a byte Read or Write operation to a given address of the EEPROM. EEPROM Data Structure The EEPROM contains the Device-descriptor, up to 4 Configuration-descriptors, and up to 15 String-descriptors in up to 7 different languages. The following diagram specifies the block structure of the EEPROM data: November-99 Page 55 of 55 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet EEPROM ADDRESS (hex) EEPROM CONTENT 000 SUPPORTED UNICODE LANGUAGES TABLE The first byte in this table is the total number of bytes in the table. The second byte is the "STRING" code of the USB standard. This is followed by a list of up to 7 valid codes of Unicode languages . < 010 010 Each pointer consists of 2 bytes: The first one identifies the descriptor, and the second contains the 8 most significant bits of the address where the descriptor starts. The end of this table is identified by the value 0x00 instead of a valid descriptor identifier. Each pointer in this table has its descriptor in the TABLE OF DESCRIPTORS. TABLE OF DESCRIPTOR POINTERS don't care 8*k 0 to 7 bytes skipped, because next table must start in a 8*k address. Each descriptor must start in a 8*k address. DEVICE and STRING descriptors are the same as specified in the USBstandard. In CONFIGURATION descriptors, the first 2 bytes contain a 16bit unsigned value for the number of bytes that the descriptor contains, and all the other bytes of the descriptor are as specified in the USB-standard (this is because this type of descriptors actually consist of a tree of small USB-descriptors, and can result in a more than 255 byte vector). Each descriptor must have an identifier and a pointer in the TABLE OF DESCRIPTOR POINTERS. TABLE OF DESCRIPTORS < 2048 November-99 Page 56 of 56 ZORAN Corporation Supported UNICODE Language Table: USBvision II Data Decoder ZR36505 Data Sheet This table is used as the "string" of index 0, which is defined in the USB -Standard. This "string" is actually a list of all the LANGIDs that are supported by the device. The first two bytes in this table are needed for the standard format of USB String descriptors. EEPROM ADDRESS (hex) 000 001 EEPROM DATA (hex) blength STRING descriptor type (=03) LANGID#1 (LSB) LANGID#1 (MSB) LANGID#2 (LSB) LANGID#2 (MSB) LANGID#3 (LSB) LANGID#3 (MSB) LANGID#4 (LSB) LANGID#4 (MSB) LANGID#5 (LSB) LANGID#5 (MSB) LANGID#6 (LSB) LANGID#6 (MSB) LANGID#7 (LSB) LANGID#7 (MSB) DESCRIPTION Number of bytes in this table (4-16). This is needed for the standard format of USB String descriptors. Code of STRING descriptor type (=03). This is needed for the standard format of USB String descriptors. Bits 7-0 of Language -Identifier of language #1. This language must be supported, and it is also used as the default language if the host specifies a language that is not included in this list. Bits 15-8 of Language -Identifier of language #1. Optional. Bits 7-0 of Language -Identifier of language #2. Must contain FF if not used. Optional.Bits 15-8 of Language -Identifier of language #2. Must contain FF if not used. Optional. Bits 7-0 of Language -Identifier of language #3. Must contain FF if not used. Optional.Bits 15-8 of Language -Identifier of language #3. Must contain FF if not used. Optional. Bits 7-0 of Language -Identifier of language #4. Must contain FF if not used. Optional.Bits 15-8 of Language -Identifier of language #4. Must contain FF if not used. Optional. Bits 7-0 of Language -Identifier of language #5. Must contain FF if not used. Optional.Bits 15-8 of Language -Identifier of language #5. Must contain FF if not used. Optional. Bits 7-0 of Language -Identifier of language #6. Must contain FF if not used. Optional.Bits 15-8 of Language -Identifier of language #6. Must contain FF if not used. Optional. Bits 7-0 of Language -Identifier of language #7. Must contain FF if not used. Optional.Bits 15-8 of Language -Identifier of language #7. Must contain FF if not used. 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F Table Of Descriptor Pointers This table is used by the ZR36504 to locate the start address of a given descriptor. Each item in this table consists of a Descriptor Identifier byte (first byte), and EEPROM address (second byte - contains only 8 most significant bits of address; the other 3 bits always equal '000'). EEPROM ADDRESS (hex) 010 011 012 EEPROM DATA (hex) DDI (=40) DD address CDI#0 (=20) DESCRIPTION Device-Descriptor Identifier code (=40). This descriptor must exist in EEPROM. Device-Descriptor address in this EEPROM (in this table, units are in 8-byte steps for address pointers). Configuration -Descriptor Identifier # 0 code (=20). This descriptor must exist in EEPROM. bits 7-2: '001000' (code of Configuration-Descriptor) November-99 Page 57 of 57 ZORAN Corporation USBvision II Data Decoder bits 1-0: '00' (Configuration Index). Configuration -Descriptor #0 address. Optional. Configuration -Descriptor Identifier # 1 code. Optional. Configuration -Descriptor #1 address. Optional. Configuration -Descriptor Identifier # 2 code. ZR36505 Data Sheet 013 CD#0 address CDI#1 (=21) CD#1 address CDI#2 (=22) (continued...) (continued...) EEPROM ADDRESS (hex) EEPROM DATA (hex) CD#2 address CDI#3 (=23) CD#3 address SDI#1,0 (=90) DESCRIPTION Optional. Configuration -Descriptor #2 address. Optional. Configuration -Descriptor Identifier # 3 code. Optional. Configuration -Descriptor #3 address. String-Descriptor Identifier Lang#1 Indx#0 (=90). This descriptor is actually the first table in EEPROM. bit 7: '1' bits 6-4: '001' (Language number in language-table) bits 3-0: '0000' (String Index). String-Descriptor #1,0 address (=00). SDI#1,0 address (=00) SDI#2,0 (=A0) SDI#2,0 address (=00) SDI#3,0 (=B0) SDI#3,0 address (=00) SDI#4,0 (=C0) SDI#4,0 address (=00) SDI#5,0 (=D0) SDI#5,0 address (=00) SDI#6,0 (=E0) SDI#6,0 address (=00) SDI#7,0 (=F0) SDI#7,0 address (=00) SDI#n1,m1 String-Descriptor Identifier Lang#2 Indx#0 (=A0). This descriptor is actually the first table in EEPROM. String-Descriptor #1,0 address (=00). String-Descriptor Identifier Lang#3 Indx#0 (=B0). This descriptor is actually the first table in EEPROM. String-Descriptor #3,0 address (=00). String-Descriptor Identifier Lang#4 Indx#0 (=C0). This descriptor is actually the first table in EEPROM. String-Descriptor #4,0 address (=00). String-Descriptor Identifier Lang#5 Indx#0 (=D0). This descriptor is actually the first table in EEPROM. String-Descriptor #5,0 address (=00). String-Descriptor Identifier Lang#6 Indx#0 (=E0). This descriptor is actually the first table in EEPROM. String-Descriptor #6,0 address (=00). String-Descriptor Identifier Lang#7 Indx#0 (=F0). This descriptor is actually the first table in EEPROM. String-Descriptor #7,0 address (=00). SDI#n1,m1 address SDI#n2,m2 Optional. String-Descriptor Identifier Lang#n1 Indx#m1. bit 7: '1' bits 6-4: n1 (Language number in language -table) bits 3-0: m1 (String Index). Optional. String-Descriptor #n1,m1 address. Optional. String-Descriptor Identifier Lang#n2 Indx#m2. November-99 Page 58 of 58 ZORAN Corporation SDI#n2,m2 address . . SDI#nk,mk SDI#nk,mk address EOT (=00) USBvision II Data Decoder Optional. String-Descriptor #n1,m1 address. ZR36505 Data Sheet . . Optional. String-Descriptor Identifier Lang#nk Indx#mk. Optional. String-Descriptor #nk,mk address. End-Of-Table code (=00). November-99 Page 59 of 59 ZORAN Corporation Table Of Descriptors USBvision II Data Decoder ZR36505 Data Sheet This table contains the DEVICE descriptor, all CONFIGURA TION descriptors, and all STRING descriptors. DEVICE and STRING descriptors are organized exactly as specified in USB standard. CONFIGURATION descriptors start with a word (= 2 bytes - LSB first, then MSB) that specifies the number of total bytes in the descriptor (not including the first 2 bytes), followed by the descriptor's body which is organized exactly as specified in USB standard. Notes: * * * The Supported UNICODE Languages Table is also used as STRING descriptor #0 for all languages. There is one and only one DEVICE descriptor, which is always 18 bytes long. A descriptor always starts at a 8*k address of the EEPROM (the 3 least significant bits of the address are '000'). This means that there can be up to 7 unused bytes between any two descriptors in the table. EEPROM Access Registers EEPROM access via the ZR36504 registers is enabled when the E2_EN bit in the PWR_REG register is set. The following registers are used for EEPROM access: Parameter E2_EN EE_DATA[7..0] EE_LSBAD[7..0] EE_MSBAD[10..8] EE_DIR EE_GO/EE_BUSY Register address Reg.0/d7 E2_EN Reg.14 EE_DATA Reg.15 EE_LSBAD Reg.16/d2-d0 Reg.16/d3 EE_DIR Reg.16/d4 EE_GO/ EE_BUSY Usage Enable EEPROM access. 0: Default after Reset. EEPROM access disabled. 1: Enable EEPROM Read and Write(1) Data Byte to be written to EEPROM. Also, last Data Byte that was read from EEPROM. 8 Least Significant bits of byte address in EEPROM to be accessed. 3 Most Significant bits of byte address in EEPROM to be accessed. Select EEPROM access direction: 0: Select Write operation to EEPROM. 1: Select Read operation from EEPROM. This is used as both a command and a status bit. Writing '1' to this bit will initiate a byte Read or Write. The SER_GO/SER_BUSY bit will remain '1' till the end of operation, to indicate to the host computer when a (2) EEPROM access can begin. Notes: (1) Write operation to EEPROM requires EEPROM WP pin to be grounded. (2) A Write operation requires additional 10ms in the EEPROM internal circuits. November-99 Page 60 of 60 ZORAN Corporation EEPROM Control Signals USBvision II Data Decoder ZR36505 Data Sheet The SCL/PWR0 and SDA/EEPROM pins of the ZR36504 are the EEPROM control signals. The SCL/PWR0 is used as the clock output, and the SDA/EEPROM signal is used as the data I/O. During Reset operation, the ZR36504 samples its SDA/EEPROM pin to determine if an external EEPROM is connected. If an external EEPROM does not exist (SDA/EEPROM='0'), the ZR36504 automatically uses its internal ROM for USB descriptors; in this case, the ZR36504 relates to hard-coding of the pins SCL/PWR0 and PWR1 to determine the current-consumption parameter for the Configuration-Descriptor. The following table summarizes these two modes of operation: Internal ROM mode SDA/EEPROM pin connected to GND. SCL/PWR0 and PWR1 pins are hard-coded to determine device current consumption for Configuration-Descriptor: PWR1 SCL/PWR0 Current ===== ======== ====== 0 0 200mA 0 1 300mA 1 0 400mA 1 1 500mA External EEPROM mode SDA/EEPROM pin connected to 10K pull-up resistor (3.3v to 5.0v). External Serial 2K*8 EEPROM is connected: SDA/EEPROM connected to Serial-Data (SDA). SCL/PWR0 connected to Serial-Clock (SCL). The following timing diagram and table specify the EEPROM control waveforms that the ZR36504 generates: Start/Stop Timings tSU:STA tHD:STA tSU:STO SCL SDA November-99 Page 61 of 61 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet Data Timings tHIGH tLOW SCL tHD:DI tHD:DO Dn tSU:DI tSU:DO Dn+1 SDA OUT SDA IN Data Valid Data Valid Symbol tSU:STA tHD:STA tSU:STO tHIGH tLOW tSU:DO tHD:DO tSU:DI tHD:DI Parameter START condition setup time START condition hold time STOP condition setup time Clock high time Clock low time Data output setup time Data output hold time Data input setup time Data input hold time Min 5300 5300 5300 5300 5300 2500 2500 20 0 Max 2670 2670 - Unit ns ns ns ns ns ns ns ns ns November-99 Page 62 of 62 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 8. ZR36504 USB and Status Registers The ZR36504 has some registers that allow software driver to directly read and affect some USB device parameters. These are specified in the following table: Parameter Register Usage address Read Only register. Contains the Device Configuration CONFIG_REG Reg.1 number. CONFIG_ REG Read Only register. Contains the Device Address. ADRS_REG Reg.2/d6-d0 ADRS_REG Read Only register. Contains the Alternate setting for ALTER_REG Reg.3/d3-d0 ALTER_REG End-Point 2 (Video bandwidth). Regarding this value as NEW_ALT Reg.4/d3-d0 FORCE_ ALTER_REG Reg.4/d7 FORCE_ ALTER_REG Reg.5/d0 STATUS_ REG Reg.16/d7-d5 EE_CONT FORCE_ALT a binary number in the range [1,15], the number of bytes sent in the Isochronous pipe of EP2 in every millisecond is: N = (16-ALTER_REG)*64 - 1 USB Bandwidth = (16-ALTER_REG)*0.5 Mbit/sec New Alternate setting for End-Point 2, (Video bandwidth), to replace the original setting. This can be used to lower the actual used bandwidth temporarily, without letting know the Operating System. Force New Alternate. 0: Use original setting. 1: Select NEW_ALT value. Read Only register. 0: Valid region of input video frame. 1: Blank or unused region of input video frame. Read Only register. These 3 bits reflect the logical level of the following pins of the ZR36504: EE_CLK_FORCE[0] = SCL/PWR0 pin. EE_CLK_FORCE[1] = PWR1 pin. (1) EE_CLK_FORCE[2] = SDA/EEPROM pin. Some USB host controllers may start an Isochronuos IN transaction too much time after the SOF (Start of USB Frame point). This means that long IN transactions may exceed the 1mS time interval of the USB frame, and cause the USB host controller to disconnect the device. The ZR36504 uses an internal Watch Dog timer to eliminate such problems. The Watch Dog operates if WD_EN control bit is set to '1'. It then starts to count 686uS after the SOF pattern, and automatically terminates any Isochronuos transaction when reaching the value of WD_COUNT register. Every one count is equivalent to 1.33uS. Note that the value of WD_COUNT should be no more than 0xE9 in order to take any effect. Page 63 of 63 VFRM_BLNK EE_CLK_FORCE [2..0] WD_EN & WD_COUNT[7..0] Reg.0/d0 Reg.53/d7-d0 November-99 ZORAN Corporation (1) USBvision II Data Decoder ZR36505 Data Sheet As sampled during Reset operation. '1' indicates existence of external EEPROM. November-99 Page 64 of 64 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 9. Programmable I/O Pins and 48MHz output pin The ZR36504 has two programmable I/O pins for general purpose usage. These are IO-1 and IO-2 pins, which are Open-Drain. Each of these pins - if used - must be connected to an external pull-up resistor to 3.3-5.0v (if not used, it can be tied to GND). The external pull-up resistor should be in the range 110K . To use these pins as inputs, the host computer should write '1' to the appropriate bit in the IOPIN_REG register (in the ZR36504 register bank); these are IO_1 and IO_2 bits respectively. In this condition, the voltage level presented on the IO-1 or IO-2 pin can be read by the host computer via the appropriate bit ('0' represents <0.8v, '1' represents >2.0v). To use these pins as outputs, the host computer should write the output value to the appropriate bit in the IOPIN_REG register; In this condition, and assuming that no external device forces the voltage level presented on the IO-1 or IO-2 pin, the written value will be reflected out ('0' will generate 0v, '1' will generate 3.3-5.0v). Upon a Power On Reset or a USB-Reset operation, the IO-1 and IO-2 pins are cleared to '0'. In the Suspend mode these pins are temporarily set to High-Z. The ZR36504 can provide a 48MHz clock output for general purpose usage. The pin CLK48 is dedicated for this usage, and is enabled when the CLK48_EN bit is set to '1' (Reg.0/d3). When not enabled, the output level in this pin is constant '0'. The 48MHz output is 50% duty cycle with 1nS jitter, and is derived from the external 12MHz crystal (an internal analog PLL is used). November-99 Page 65 of 65 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 10. Audio Channel The audio channel in the ZR36504 is based on a serial 64-512Kb/s data stream from the ZR36504 to the host computer (USB Isochronuos mode is used for this stream). The 64512Kb/s stream comes from a 8,000/16,000 S/sec 16/8-bit audio samples at the external audio CODEC(s). Two external CODECs should be used for Stereo mode recordings. The 8/16KHz sampling clock is derived from the 12MHz external crystal. The ZR36504 pins for the external Codec interface are BCLK, FS_L, FS_R, and DAT_IN. The following table specifies the AUDIO_CONT register (Register address = 50): Bit # 0 1 3-2 Name E_A E_B BPS Description '0': Disables Audio channel. Set FS_L and FS_R outputs to constant '0'. If E_B is also '0', BCLK is set to constant '0'. '1': Enable Audio channel. '0': Disable Bulk Data input. Set BLK_FULL output to constant '0'. If E_A is also '0', BCLK is set to constant '0'. '1': Enable Bulk Data input. '00': 8-bit per sample. '01': 12-bit per sample (Occupies 2 bytes. Bits d3 -d0 of second byte are set to '0000'). '10': 14-bit per sample (Occupies 2 bytes. Bits d1-d0 of second byte are set to '00'). '11': 16-bit per sample. '0': Selects Mono mode. FS_L output is active, FS_R output is constant '0'. '1': Selects Stereo mode. Both FS_L and FS_R outputs are active. '0': Set sampling rate to 8,000 Samp/Sec. '1': Set sampling rate to 16,000 Samp/Sec. '00': BCLK frequency is not defined. '01': Select BCLK frequency = 64KHz. '10': Select BCLK frequency = 1.544MHz. '11': Select BCLK frequency = 2.048MHz. 4 5 7-6 S/M FS BK In addition to the AUDIO_CONT register, there is the AUD_PK_LEN register (Register address = 51), to select the maximum packet size to be sent via the audio Isochronuos pipe. This number is limited by 128, which is the maximum number of bytes that the ZR36504 audio fifo can contain. The S/W driver should set this register to a value that fits the USB descriptor for the E.P#3 maximum packet length (which is 66 if not using an external EEPROM). Codec Interface November-99 Page 66 of 66 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet The Codec Interface is Long Frame Sync Timing based. The BCLK frequency can be selected to be - 2048KHz, 1536KHz, or 64KHz, which enables the designer to use almost any family of low cost Codecs available in market. In the Long Frame Sync Timing modes, the MSb of the "transmitted" data is always expected soon after the rising edge of the FS_L (or FS_R) signal. The ZR36504 produces a positive pulse of 2 BCLK cycles in these output pins every 125us (8KHz) or every 62.5us (16KHz), which indicates the start of sample as specified in the following waveform diagram: Txs BCLK Tsx FS_L FS_R Txd2 DAT_IN XX MSb Txd1 LSb XX The BCLK is derived out of the 12MHz clock from the crystal. This results in a 4.3% jitter at the BCLK signal. The following table specifies the minimum and maximum time intervals for the Codec Interface waveform diagram: Parameter Hold Time from BCLK Low to FS_L / FS_R High Setup Time from FS_L / FS_R High to BCLK Low Delay Time to valid data from FS_L / FS_R Delay Time from BCLK High to DAT_IN valid Jitter at the Bit Clock signal BCLK Symbol Txs Tsx Txd1 Txd2 Cj Min 180 180 - Max 200 200 4.3 Unit ns ns ns ns % November-99 Page 67 of 67 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 11. Bulk Channel The Bulk channel in the ZR36504 is capable of transferring serial data from an external source to the host computer at a bit rate of up to 2Mbit/sec. It uses a bulk end point (E.P#4), with a maximum packet length that can be specified a value between 1-64 bytes (the USB standard does not allow a bulk packet of more than 64 bytes). The Bulk channel takes advantage of the existing interface for the audio codec. In order to work simultaneously with the audio channel, the external data source should be able to stop the data transfer from time to time - as specified in the Bulk waveform diagram. The ZR36504 pins for the Bulk channel interface are BCLK, DAT_IN, BLK_EN, and BLK_FULL. The signals FS_L and FS_R should be monitored by the data source logic, in order to coexist with the audio channel. The following table specifies the control registers that are used for controlling the Bulk channel: Control Name E_B Reg.50/d1 BLK_PK_LEN[6..0] Reg.52/d6-d0 Description '0': Disable Bulk Data input. Set BLK_FULL output to constant '0'. If E_A is also '0', BCLK is set to constant '0'. '1': Enable Bulk Data input. This register specifies the maximum number of bytes to be sent in a single USB Bulk packet. This must be a number between 0-64, and it should fit the content of USB descriptor (64 if no external EEPROM used). This register directly affects the bit rate capability of the Bulk channel. The actual bit rate is also limited by the BCLK frequency, which can be 64KHz, 1544KHz, or 2048KHz. A bit rate of 2Mbit/sec can be reached only in computers that are capable of performing more than one packet in a USB frame (OHCI). The following waveform diagrams specifies the procedure and timings for the ZR36504 Bulk interface. Note that the input data is sampled on the falling edge of the BCLK clock signal. The BLK_EN input is set to '1' by the sending device to indicate the beginning of a byte sequence; it should always turn to '1' before the most significant bit of the first byte, and return to '0' after the least significant bit of the last byte in sequence. When the BLK_FULL output of the ZR36504 turns '1', the sending device should wait (by switching BLK_EN to '0') until the BLK_FULL indication returns to '0'. November-99 Page 68 of 68 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet BCLK BEsu BEh BLK_EN Dh DAT_IN XX B1[7] Dsu B1[6] B1[5] B1[4] Bn[2] Bn[1] Bn[0] XX If the audio channel is enabled, the sending device should wait at least 16 clock cycles after the FS_L (or FS_R) pulse before beginning to send its own data. During this time it should keep its data out signal in the Hi-Z state, in order not to interfere with the audio data. 1 2 3 4 16 BCLK FS_L FS_R BLK_EN Keep device data output pin in Hi-Z DAT_IN XX audio audio audio audio audio B1[7] B1[6] B1[5] BFHsu BFLsu BCLK BLK_FULL BLK_EN DAT_IN Bn[1] Bn[0] Bn+1[7] Bn+1[6] November-99 Page 69 of 69 ZORAN Corporation Parameter USBvision II Data Decoder Symbol BEsu BEh Dsu Dh BFHsu BFLsu Cj Min 100 100 100 100 80 0 - ZR36505 Data Sheet Max 4.3 Unit ns ns ns ns ns ns % Setup Time from BLK_EN High to BCLK Low Hold Time from BCLK Low to BLK_EN Low Setup Time from DAT_IN valid to BCLK Low Hold Time from BCLK Low to DAT_IN valid Setup Time from BLK_FULL High to BCLK High Hold Time from BLK_FULL Low to BCLK High Jitter at the Bit Clock signal BCLK November-99 Page 70 of 70 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 12. Software Package Following is a description of the software components provided with the ZR36504: WDM Video streaming class MiniDriver - MS(R) standard connection and streaming in kernel mode (Capture, Still) - MS(R) standard property sets (TV Tuner, Crossbar) - MS(R) standard way of exposing data formats. - MS(R) standard way of controlling stream flow. all interfaces are exposed through DirectShow architecture. VFW interfaces are also available via WDM to VFW mapper, provided by Microsoft. WDM Audio streaming class MiniDriver - streamss audio data from the ZR36504 chip. TWAIN Compliant Driver - The package includes a TWAIN compliant driver for high resolution still capture. The GUI of the TWAIN driver displays live video for preview. EEPROM Programming Application - An application for programming the ZR36504 EEPROM to contain vendor specific USB Descriptors. It allows to set the Device and Manufacturer names as well as the Serial Number for the device. The drivers are supplied with INF file for easy installation. Customization is done by modifying the name strings in the INF file. November-99 Page 71 of 71 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 13. Mechanical Specification Dimensions in mm (inches). November-99 Page 72 of 72 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet 16.00 0.20(.630 .008)SQ 75 14.00 0.10(.551 .004)SQ 51 Details of "A" part 0.15(.006) 76 50 0.15(.006) 0.15(.006)MAX 0.40(.016)MAX Details of "B" part INDEX 0.10 0.10 .004 .004 100 26 STAND OFF 0~100 LEAD No. 1 25 "A" 0.50(.0197)TYP 0.18+0.08 - 0.03 (.007+.003 ) - .001 0.50 0.20(.020 .008) 0.08(.003)M (Mounting height) "B" 1.50+0.20 - 0.10 (.059+.008 ) - .004 0.10(.004) November-99 +0.05 0.127- 0.02 (.005+.002 ) - .001 12.00(.472)REF 15.00(.591)NOM 100-pin plastic LQFP Page 73 of 73 ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet http://www.zoran.com For more information, contact Zoran's Santa Clara office or the office nearest you: USA Zoran Corporation 3112 Scott Boulevard Santa Clara, CA 95054-3317 Tel: 408-919-4111 Fax: 408-919-4122 Israel Zoran Microelectronics Ltd. Advanced Technology Ctr. P.O. Box 2495 Haifa, 31024 Israel Tel : +972-4-8545-777 Fax: +972-4-8551-551 China Zoran China Office Suite 2507 Electronics Science & Tech Building 2070 Central Shennan Rd. Shenzhen, Guangdong, 518031 P.R. China Tel : +86-755-378-0319 Fax: +86-755-378-0852 Japan Zoran Japan Office 2-2-8 Roppongi, Minato-ku Tokyo 106-0032, Japan Tel : +81-03-5574-7081 Fax: +81-03-5574-7156 Taiwan Zoran Taiwan Office 4F-1, No. 5, Alley 22 Lane 513, Reikuang Rd. Taipei, Taiwan R.O.C. Tel : +886-2-2659-9797 Fax: +886-2-2659-9595 Canada Zoran Toronto Lab 2175 Queen St. East, Suite 302 Toronto, Ontario M4E 1E5 Canada Tel : (416) 690-3356 Fax: (416) 690-336 November-99 Page 74 of 74 |
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