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STV5345 STV5345/H - STV5345/T
TELETEXT DECODER WITH 8 INTEGRATED PAGES
. . . . . . . . . . . .
COMPLETE TELETEXT DECODER INCLUDING ON-CHIP 8 PAGES MEMORY, REDUCING EMC RADIATIONS UPWARD SOFTWARE AND HARDWARE COMPATIBLE WITH PREVIOUS SGS-THOMSON's DECODER SDA5243 DIRECT INTERFACE TO AN EXTERNAL STATIC RAM OF 8kBYTES FOR UP TO 16 PAGES APPLICATION AUTOMATIC SELECTION OF UP TO SIX NATIONAL LANGUAGES FOUR SIMULTANEOUS PAGE REQUESTS DISPLAY OF THE 25TH STATUS ROW MICROPROCESSOR CONTROL VIA AN I2C BUS (SLAVE ADDRESS 0010001 R/W) DATA ACQUISITION AVAILABLE FROM LINES 2 TO 22 OR FROM A COMPLETE FIELD HIGH QUALITY DISPLAY USING A CHARACTER MATRIX OF 12 x 10 DOTS SINGLE + 5V SUPPLY VOLTAGE ON-CHIP MASK PROGRAMMABLE ROM CHARACTER GENERATORS HCMOS PROCESS
DIP40 (Plastic Package) ORDER CODE : STV5345 STV5345/H STV5345/T West European East European Turkish & European
PIN CONNECTIONS
VDD
A11
1
40
A10 A9
2 3 4
5 6
39 38 37
36 35
A12 OE WE
TTD
A8 A7 A6
A5 A4
DESCRIPTION The STV5345 is a HCMOS integrated circuit which performs all the processing of logical data within a 625 lines system teletext decoder. It is designed to operate in conjunction with one-chip : the SAA5231 integrated chip which extracts Teletext information embedded in a composite video signal. Up to 8 pages of display data can be stored in internal memory. Using 8Kbytes of external memory leads to a 16 pages application. A complete system also comprises a microprocessor controlling the STV5345 via a 2-wires serial bus. An on-chip ROM memory contains the character sets. The STV5345 performs automatic selection of one of up to six natural languages. Data bytes may be decoded in either 7-Bit plus parity or in full 8-Bit formats. The chip set also supports facilities for reception and display of higher-level protocol data.
April 1994
TTC
7 8 9
10 11 12
34 33 32
31 30 29
ODD/EVEN F6
VCS SAN D TCS/SCS R
A3 A2 A1
A0 D7 D6
13 14 15
16 17
28 27 26
25 24
G B COR
B LA N Y
D5 D4 D3
D2 D1
18 19 20
23 22 21
SCL SDA
D0
V SS
5345-01.EPS
1/25
STV5345 - STV5345/H - STV5345/T
PIN DESCRIPTION
Pin 1 2,3,40 * 4* 5* Symbol VDD A11, A12, A10 OE WE Function +5V Chapter address Output enable Write enable Description Positive supply voltage Address selection outputs for 1 of 8 external static RAM chapters each of 1 kBytes. Active-low external static RAM output enable control signal. Active-low external static RAM write enable control signal. It supports write-cycles interleaved with read-cycles. An A.C. coupled teletext data input supplied by the SAA5231 chip is latched to VSS between 4 and 8s after each TV line. A 6.9375MHz clock signal, supplied by the SAA5231 chip, is internally A.C. coupled, clamped and buffered. High for even numbered and low for odd-numbered frames. The value is valid 2s before the end of lines 311 and 624. The 6MHz clock signal, supplied by the SAA5231 chip is internally A.C. coupled, clamped and buffered. Active high VCS input. Three level output pulse to the SAA5231 device. Phase lock, blanking signal, and color burst components are contained in this signal. Scan composite input signal (SCS) for the display synchronization or Text composite sync. (TCS) output signal to the SAA5231. Both signals are active low. Character and background colors active-high open-drain outputs. Open-drain active-low output supporting optimal display of characters in "mixed mode" operation. Open-drain active high output for TV-image blanking in normal and mixed-mode operation. Open-drain active-high output with foreground information. Can be used for printer command. Microprocessor clock input via serial bus. Open-drain microprocessor serial data input/output via serial bus. Ground. Eight tri-state input/output for data read/write from/to an external static RAM. Ten addresses output pins for accessing to individual Bytes of a 1 kByte chapter stored in an external Static RAM.
5345-01.TBL
6
TTD
Teletext data input
7
TTC
Teletext clock input
8
ODD/EVEN
Interlaced mode state output
9 10 11
F6 VCS SAND
Character display clock signal Video composite synchronization input signal Sandcastle
12
TCS/SCS
Input / output composite synchronization signal
13,14,15 16 17 18 19 20 21 22-29 * 30-39 *
RGB COR BLAN Y SCL SDA VSS D0-D7 A0-A9
Red, green, blue Contrast reduction Blanking signal output Foreground output Serial clock Serial data input / output 0 Volt Parallel data input / output Address signals
* Pins only activated when 8KBytes of external memory are addressed, otherwise pins OE and WE remain high, and others remain low.
2/25
STV5345 - STV5345/H - STV5345/T
BLOCK DIAGRAM
TCS/ VCS SAND SCS A0 ... A12 D0 ... D7
* *
4
A0 ... A10 / 30 ... 40 A11 - A12 / 2 - 3 D0 ... D7 / 22 ... 29
10
11
12
*
DATA
*
EXTERNAL MEMORY INTERFACE ADDRESS DATA CTRL
OE
F6
9
TIME BASE
CLOC K
5
WE
TTC
7
TTD
6
DATA ACQUISITION & DATA PROCESSING
8 PAGES INTERNAL MEMORY ADDRESS DATA CTRL
SCL 19
I 2 C BUS INTERFACE
SDA 20
DISPLAY & CONTROL INTERFACE
13 RED 14 GREEN 15 BLUE 8
STV5345
V DD
V SS
Y
BLAN
COR ODD/ EVEN
ABSOLUTE MAXIMUM RATINGS
Symbol VDD Power Supply Range Parameter Value -0.3, +6.0 Unit V
INPUT VOLTAGE RANGE : VI VI VCS,SDA,SCL,D0-D7 TTD,F6,TCS/SCS,TT C -0.3, VDD + 0.5 -0.3, +10 V V
OUTPUT VOLTAGE RANGE : VO VO Tstg TA SAND,A0-A12,OE,WE,D0-D7,SDA,ODD/E VEN,R,G,B BLAN,COR, Y, TCS/SCS Storage Temperature Range Operating Ambient Temperature Range -0.3 , VDD -0.3 , VDD -20, +125 -20, +70 V V
o o
5345-02.TBL 5345-03.TBL
C C
ELECTRICAL CHARACTERISTICS VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol VDD IDD Supply Voltage (Pin 1) Supply Current (operating mode) Parameter Min 4.5 Typ 5 15 Max 5.5 40 Unit V mA
3/25
5345-02.EPS
1
21
18
17
16
STV5345 - STV5345/H - STV5345/T
ELECTRICAL CHARACTERISTICS (continued) VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol INPUTS TTD (Pin 6) CEXT VI(p-p) tr , tf tDS tDH II(L) CI VI VI(p-p) VP fTTC fF6 tr , tf II(L) CI VIL VIH tr , tf II(L) CI VIL VIH fSCL tr , tf II(L) CI Ext. Coupling Capacitor Input Voltage p-p Input Rise / Fall Times Input Set-up Time Input Hold Time Input Leakage Current (VI = 0 to VDD) Input capacitance TTC, F6 (Pins 7,9) DC Input Voltage AC Input Voltage F6 AC Input Voltage TTC Input Peak Rel. 50 % Duty TTC Clock Frequency F6 Clock Frequency Clock Rise / Fall Times Input Leakage Current (VI = 0 to 10V) Input Capacitance VCS (Pin 10) Low Level Input Voltage High Level Input Voltage Input Rise / Fall Times Input Leakage Current (VI = 0 to VDD) Input Capacitance SCL (Pin 19) Low Level Input Voltage High Level Input Voltage SCL Clock Frequency Input Rise / Fall Times Input Leakage Current (VI = 0 to VDD) Input Capacitance -10 0 3 1.5 VDD 100 2 +10 7 V V kHz s A pF -10 0 2 0.8 VDD 500 +10 7 V V ns A pF 10 -10 - 0.3 1 1.5 0.2 6.9375 6 80 +10 10 +10 7 7 3.5 V V V V MHz MHz ns A pF 2 10 40 40 -10 +10 7 50 7 80 nF V ns ns ns A pF Parameter Min Typ Max Unit
INPUT/OUTPUTS TCS(output), SCS(input) (Pin12) VIL VIH tr , tf II(L) CI VOL VOH tr , tf CL Low Level Input Voltage High Level Input Voltage Input Rise / Fall Times Input Leakage Current (VI = 0 to VDD and output in high impedance state) Input Capacitance Low Level Output Voltage (IOL = 0.4mA) High Level Output Voltage (-IOH = 0.2mA) Output Rise / Fall Times between 0.6V and 2.2V Load Capacitance 0 2.4 -10 0 3 1.5 8 500 +10 7 0.4 VDD 100 50 V V ns A pF V ns pF
5345-04.TBL
V
4/25
STV5345 - STV5345/H - STV5345/T
ELECTRICAL CHARACTERISTICS (continued) VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol INPUT/OUTPUTS (continued) SDA (Pin 20) VIL VIH tr , tf II(L) CI VOL tf CL VIL VIH II(L) CI VOL VOH tr , tf CL OUTPUTS A0-A12, OE, WE (Pins 30-40,2,3,4,5,) VOL VOH tr , tf CL VOL VOH tr , tf CL VOL VOI VOH tr1 tr2 tf CL Low Level Output Voltage (IOL = 1.6mA) High Level Output Voltage (-I OH = 0.2mA) Output Rise / Fall Times between 0.6V and 2.2V Load Capacitance ODD/EVEN (Pin 8) Low Level Output Voltage (IOL = 0.4mA) High Level Output Voltage (-I OH = 0.2mA) Output Rise / Fall Times between 0.6V and 2.2V Load Capacitance SAND (Pin 11) Low Level Output Voltage (IOL = 0.2mA) Middle Level Output Voltage (IOL = 10 A) High Level Output Voltage (-IOH = 0 to 10A) Output Rise Time : l VOL to VOI from 0.4 to 1.1V l VOI to VOH from 2.9 to 4.0V Output Fall Time V OH to VOl from 4.0 to 0.4V Load Capacitance 0 1.1 4 0.25 2.9 VDD 400 200 50 30 ns pF V V V ns
5345-05.TBL
Parameter
Min
Typ
Max
Unit
Low Level Input Voltage High Level Input Voltage Input Rise / Fall Times Input Leakage Current (VI = 0 to VDD and output in high impedance state) Input Capacitance Low Level Output Voltage (IOL = 3mA) Output Fall Time between 3.0V and 1.0V Load Capacitance D0-D7 (Pins 22-29) Low Level Input Voltage High Level Input Voltage Input Leakage Current (VI = 0 to VDD and output in high impedance state) Input Capacitance Low Level Output Voltage (IOL = 1.6mA) High Level Output Voltage (-I OH = 0.2mA) Output Rise / Fall Times between 0.6V and 2.2V Load Capacitance
0 3 -10 0
1.5 VDD 2 +10 7 0.5 200 400
V V s A pF V ns pF V V A pF V V ns pF
0 2 -10 0 2.4
0.8 VDD +10 7 0.4 VDD 50 120
0 2.4
0.4 VDD 50 120
V V ns pF V V ns pF
0 2.4
0.4 VDD 100 50
5/25
STV5345 - STV5345/H - STV5345/T
ELECTRICAL CHARACTERISTICS (continued) VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol OUTPUTS (continued) R, G, B, COR, BLAN, Y (Pins 13-18) VOL Low Level Output Voltage : l IOL = 2mA l IOL = 5mA Pull-up Voltage (with R = 1k to VDD) Output Fall Time from 4.5 to 1.5V (with R = 1k to VDD) Skew Delay on Falling Edges (at 3V with R = 1k connected to VDD) Load Capacitance Output Leakage Current (V PU = 0 to VDD output off) V 0 0 0.4 1 VDD 20 20 25 20 V ns ns pF A Parameter Min Typ Max Unit
VPU tf tSK CL ILO TIMING
SERIAL BUS (referred to VIH = 3V, VIL = 1.5V) (see Fig. 6) tLOW tHIGH tSU , DAT tHD , DAT tSU , sTO tBUF tHD , STA tSU , STA tCY tOE tADDR tOEW tACC tDH tWE tWEW tDS tDHWE tWR Low Period Clock High Period Clock Data Set-up Time Data Hold Time Stop Set-up Time from Clock High Start Set-up Time Following a Stop Start Hold Time Start Set-up Time Following Clock Low to High Transition MEMORY INTERFACE referred to VIL = 1.5V (see Fig. 7) Cycle Time Adress Change to OE Low Address Active Time OE Pulse Duration Access Time from OE to Data Valid Data Hold Time from OE High or Address Change Address Change to WE Low WE Pulse Duration Data Set-up Time to WE High Data Hold Time from WE High Write Recovery Time 60 450 320 0 40 200 100 20 25 500
-
4 4 250 170 4 4 4 4
-
200 -
s s ns ns s s s s ns ns ns ns ns ns ns ns ns ns ns
5345-06.TBL
500 -
6/25
STV5345 - STV5345/H - STV5345/T
Figure 1 : F6, TTC, TTD Input Internal Connections
F6
9
character display clock input to timing chain
V TTC 7 teletex t clock input to data acquistion circuit
50% duty cycle level VP VP
VI(p-p)
TTD C EXT
6
teletext data input to data acquisition circuit clamping pulses from timing circuit from time 4s to 8s of each television line to maintain correct D.C. level following external A.C. coupling F6, TTC, TTD INPUT CIRCUITRY 0 shaded regions equal in area t
INPUT WAVEFORM PARAMETERS
Figure 2 : Teletext Data Input Timing
t CY 144ns typ. TTC t DS t DH 90% 10% tr 80ns max. Data Stable
5345-04.EPS
90% 10% tf 80ns max.
40ns min. 40ns min. TTD Data Stable
data may change
data may change
data may change
Data Stable : 1 if 2V , 0 if 0.8V
Figure 3 : Synchronization Timing
F1 0 TCS 4.67 SAND 1.5 All timings in s
7/25
continuous internal 1MHz clock 64
Phase lock Phase lock off
5345-05.EPS
8.5
33.5
5345-03.EPS
STV5345 - STV5345/H - STV5345/T
Figure 4 : Composite Sync. Waveforms
LSP 0 EP 0 2.33 BP 0 27.33 32 59.33 64 All timings in s 32 34.33 64 4.66 64
TCS (interlaced) 621 (308) TCS (interlaced) 309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 622 (309) 623 (310) 624 (311) 625 (312) 1 2 3 4 5 6
TCS (non-interlaced) 308 309 310 311 312 1 2 3 4 5 6
The timing reference is specified by the descending edge of the signal LSP, with a tolerance spread of 100ns.
Figure 5 : Display Output Timing
A) LINE RATE LSP (TCS) 0 4.66 40s R.G.B.Y (1) 0 16.67 display period 56.67 All timings in s 64
B) FIELD RATE
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) display period
R.G.B.Y (1) 0 41
(1) Also BLAN in charac ter and box bla nking
Horizontal directio n(line ) - Vertical direc tion (frame)
8/25
5345-07.EPS
291 312 Line numbers
5345-06.EPS
The number positions indicate the end of lines. The Teletext composite synchronization signal (TCS), whether interlacing is present or not, comprise three components. a) the line-synchronization pulses (LSP). b) the equalization pulses (EP) c) the frame-synchronization pulses (BP).
STV5345 - STV5345/H - STV5345/T
Figure 6 : Serial Bus Timing
SDA t BUF t LOW tf
SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT
SDA
5345-08.EPS
t SU,STA
t SU,STO
VIH = 3V , VIL = 1.5V
Figure 7 : Memory Interface Timing
A) READ ADDRESS A0 - A12 valid t ADDR t OE OE t OEW t ACC DATA FROM RAM t DH valid data output t CY
B) WRITE ADDRESS A0 - A12 valid
t CY
t WE WE t WEW t DS DATA TO RAM
t WR
t DHWE
5345-09.EPS
valid data output
9/25
10/25
CVBS
SAA5231
DATA SLICER VIDEOTEXT CONTROLLER
6MHz
F6 9
6
STV5345
27
Figure 8 : Master Synchronization Mode
STV5345 - STV5345/H - STV5345/T
Sync. Separator 17
64
6MHz Oscillator
LINE SYNC
Teletext Data and Clock Separator Phase Detector 22 Video Composite Sync.
VCS
15.625kHz 11 SAND
Signal Quality Detector
25 10 70A
Vertical Sync. Integrator
ENABLE ACQUISITION SYSTEM CLOCK ACQUISITION FIELD SYNC.
28 12 TCS/SCS
Scan Composite Sync. TCS Outputs Buffer TCS
Switch in this position TCS ON Pin 28 Voltage Sensor
Composite Sync. Generator
DISPLAY FIELD SYNC.
ENABLE
I 2 C-Register 1 TCS ON Mode (D2 = 1) (D1/D0)
1
1.2k
VS or
Sync. Output
5345-10.EPS
L C
CVBS
STV5345
20 18
27
VIDEOTEXT CONTROLLER
6MHz Oscillator 17 F6 9
6 64
Figure 9 : Slave Synchronization Mode
Sync. Separator
6MHz
LINE SYNC.
Videotext Data and Clock Separator
Phase Detector 22 15.625kHz 11 SAND
Signal Quality Detector
25 Scan Composite Sync. 12 TCS Outputs Buffer TCS
TCS/SCS
Video Composite Sync. 10 VCS Sync. Integrator
ENABLE ACQUISITION INTERNAL CLOCK FIELD SYNC.
Determines F6 and line sync.
28
Composite Sync. Generator
SCS Field Sync.
DISPLAY FIELD SYNC.
SCS
I 2 C-Register 1 DISABLE TCS OFF EXT-SYNC (D2=0) (D1=D0=1)
DATA SLICER
1
SAA5231
2
Not connected for External synchronization
I C - Register 1, Bit D2=0 to disable TCS output buffer and D1=D0=1 to enable external sync. Acquisition only works when external sync. signal is phase synchronous with CBVS input.
STV5345 - STV5345/H - STV5345/T
11/25
5345-11.EPS
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
OE
D0
D1
D2
D3
D4
D5
D6
21
3
D7
A12
CS
VSS
12/25
10k
+12V 47F
1k
1k
150pF
10
820
22H
6MHz 15pF
4.7F
23nF
15H
27pF
68k
390 8 2 3 1
TEA2014A
7 5
6
SYNC
APPLICATION DIAGRAM
+12V
10pF
7 - 36 13.875MHz
470
10 F 10 F
+12V
VIDEO +12V GND
+5V 2 V0
GND 3
12
23
20
18
11
7
V1 1
10
1
16
SAA5231
27
2.2F
STV5345 - STV5345/H - STV5345/T
L7805
15 28 22 17 14 25
2 21 4 6
24
19 26
13
3 5 8 9
2.7k
1k
BC558B
+12V 10nF
3.7k
47nF 47nF 15pF 1nF 470pF 22nF 270pF100pF 220pF 68nF
BC548B
10k
10k
1N4148
560pF
82
BLK
TS
470
6 12 11 9 7 10
17 13 14 15
8 16 18
BC548B
82
SCL
19
470
SDA
20
+5V
STV5345
R BC548B
82 G
22H
1
0.1F
5
4 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 2
BC548B
82
B
8 4 7 6 5 3 25 24 21 23 2 1
1k 1k 1k
20 27 22 11 12 13 15 16 17 18 19 10 9
F 22
100
6.8k GND
MK48H64 8K x 8 SRAM (for 16 pages applications)
26
28
1.2k
4.7k
14
10F
+5V
5345-12.EPS
STV5345 - STV5345/H - STV5345/T
APPLICATION NOTES ORGANIZATION OF A PAGE-MEMORY The organization of a page-memory is shown in Figure 10. The STV5345 chip provides a display format of 25 rows of 40 characters per row. The organizationis as follows : Row zero contains the page header. The first seven characters (0 - 6) are used for messages regarding the operational status. The eighth character is an alphanumeric control character either "white" or "green" defining the "search" status of the page. When it is "white" the operational state is normal and the header appears PAGE MEMORY ORGANISATION Figure 10
Fixed characters Alphanumerics white for normal, green on searc h
white ; when it is "green" the operational state corresponds to "search mode" and the header appears green. The following twenty-four characters give the header of the requested page when the system is in search mode. The last eight characters display the time of day. Row number twenty-four is used by the microprocessor for the display of information. Row twenty-five comprises ten bytes of control data concerning the received page (see Table 1) and fourteen free bytes which can be used by the microprocessor.
7 Status Characters
24 characters from page header rolling on page search
8 scrolling time characters
ROW
7
1
24
8
0 1 2 3 4 5 6 7 8 9 10 11
MAIN PAGE DISPLAY AREA
12 13 14 15 16 17 18 19 20 21 22 23
this row always free for status 10 14
24 25
5345-13.EPS
10 bytes for received page information
14 bytes free for use by C
13/25
STV5345 - STV5345/H - STV5345/T
GHOST ROW STORAGE ORGANIZATION
Row Address of Stored Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Designation Code 0 00 0 0 00 1 0 01 0 0 01 1 0 10 0 0 10 1 0 11 0 0 11 1 1 00 0 1 00 1 1 01 0 1 01 1 1 10 0 1 10 1 1 11 0 0 01 0 0 00 0 0 00 1 0 01 0 0 01 1 Row (Packet) Number Function
X / 26
Enhanced display facilities Page related data stored in chapter corresponding to level 1 data, i.e. For 0 goes in 4 "1 " "5 "2 " "6 "3 " "7
X / 28 X / 27
Page related character set Linked pages
Table 1 : Row 25 received page control data format
D0 D1 D2 D3 D4 D5 D6 D7 COLUMN
PU0 PU1 PU2 PU3 HAM 0 0 0 0
PT0 PT1 PT2 PT3 HAM 0 0 0 1
MU0 MU1 MU2 MU3 HAM 0 0 0 2
MT0 MT1 MT2 C4 HAM 0 0 0 3
HU0 HU1 HU2 HU3 HAM 0 0 0 4
HT0 HT1 C5 C6 HAM 0 0 0 5
C7 C8 C9 C10 HAM 0 0 0 6
C11 C12 C13 C14 HAM 0 0 0 7
MAG0 MAG1 MAG2 0 FOUND 0 0 0 8
0 0 0 0 0 0 0 9
5345-08.TBL
PBLF
Page number : - MAG = magazine, PU = page units, PT = page tens. Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens. PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.
14/25
5345-07.TBL
0 X
0 X
0 X
0 X
X / 24 X / 25 X / 28 8 / 30
Page extension Page extension Magazine related character set Broadcasting service data packet Not used Not used
Stored in chapter 4 only
STV5345 - STV5345/H - STV5345/T
REGISTER MAP (see Table 2) Registers R0 to R10 and R12 are write only whilst R11A is a read/write and R11B is a read only register respect to the microprocessor. The automatic succession on a byte basis is indicated by the arrows in Table 2. In the normal operating mode TA, TB and TC should be set to logic level 0. After power-up the contents of the registers are as Table 2 : Register specification
D7 * TA D6 * 7 + P/ 8 BIT BANK SELECT A2 * * BKGND IN BKGND IN CURSOR ON * * * D6 (R/W) 0 D5 * ACQ. ON/OFF ACQ. CCT A1 * * COR OUT COR OUT CONCEAL/ REVEAL * * C5 D5 (R/W) 0 D4 * GHOST ROW ENABLE ACQ. CCT A0 PRD4 * COR IN COR IN TOP/ BOTTOM A3 R4 C4 D4 (R/W) 0 D3 * DEW/ FULL FIELD TB D2 EVEN OFF TCS ON START COLUMN SC2 PRD2 A2 TEXT IN TEXT IN BOX ON 24 A2 R2 C2 D2 (R/W) 0 D1 TC T1 D0 SEL11B T0
follows : all bits in registers R0 to R12 are cleared to zero with the exception of bits D0 and D1 in registers R5 and R6 which are set to logical one. After power-up all the memory bytes are preset to hexadecimalvalue 20 H (space) with the exception of the byte corresponding to row 0 of column 7 of chapter 0 which is set to the value corresponding to "alpha white" hexadecimal value 07 H.

R0 R1
Mode 0 Mode 1
BLOCK SELECT A3 * * BKGND OUT BKGND OUT STATUS ROW BTM/TOP * * * D7 (R/W) 60Hz
START START COLUMN COLUMN SC0 SC1 PRD1 A1 PON OUT PON OUT BOX ON 1-23 A1 R1 C1 D1 (R/W) 0 PRD0 A0 PON IN PON IN BOX ON 0 A0 R0 C0 D0 (R/W) VCS signal quality *
R2 R3 R4 R5 R6 R7 R8 R9 R10 R11A R11B R12
Page request adress Page request data Display chapter Display control (normal) Display control (newsflash / subtitle) Display mode Active chapter Active row Active column Active data Status Page request address
5345-09.TBL
PRD3 A3 TEXT OUT TEXT OUT SINGLE/ DOUBLE HEIGHT CLEAR MEM. R3 C3 D3 (R/W) 0
*
*
EROD
A1
A0
*
*
* Reserved register bits : must be set to 0
REFRESH ON DISPLAY FUNCTION This function allows independently to fill the memory using 3 acquisition circuits when the 4th one refreshes the displayed page. When EROD (D5 of Reg. 12) is 0, refresh on display function is not active. Four teletext pages are filled into memory corresponding to addresses of acquisition registers. Two blocks of 8 pages are selected with A3 (D7of Reg. 2) Upper or lower bank of 4 pages is selected with A2 (D6 of Reg. 2). Acquisition circuits are selected with A1/A0 (D5/D4 of Reg. 2). This 2 bits also determine the 1KByte of RAM (the chapter) allocated to each acquisition circuit. When EROD = 1, refresh on display function is active. 3 acquisition circuits store pages as described above. The 4th one stores data into the current displayed chapter. The chapter is selected with addresses A3/A2/A1/A0 (D3/D2/D1/D0 of Reg. 4). Notice that A1/A0 (D1/D0 of Reg. 4) give the circuit number to be used to refresh this displayed chapter. That means A1/A0of refresh ondisplay function (D4/D3 of Reg. 12) have to be written identical to A1/A0 (D1/D0 of Reg. 4), as A2 of acquisition circuit (D6 of Reg. 2) has to be identical to A2 of displayed chapter (D2 of Reg. 4).
15/25
STV5345 - STV5345/H - STV5345/T
REGISTER FUNCTIONS
Register R0 Address 00H Function R11 adressing and pin functions control Bit(s) SEL 11B (D0) TC (D1) EVEN OFF (D2) T1 0 0 1 1 T0 0 1 0 1 Description Selection of register 11B (D0 = 1) or 11A(D0 = 0) Test bit, must be cleared in the normal working mode Control of ODD/EVEN pin : EVEN signal output (D2 = 0) or grounded (D2 = 1) 312/313 line MIX - mode with interlace 312/313 line TEXT - mode without interlace 312/312 line Terminal mode without interlace External synchronization TCS/SCS is an input D2 = 1, TCS output on Pin TCS/SCS D2 = 0, SCS input on Pin TCS/SCS Selection of field flyback mode or full channel mode (D3 = 1) Selection of ghost row mode (D4 = 1) Control of acquisition operation (D5 = 0 enables acquisition)
TCS ON (D2) R1 Address 01H Operating mode controls DEW / FULLFIELD (D3) GHOST ROW ENABLE (D4) ACQUISITION ON / OFF (D5)
7 bits + parity or 8 Selection of received data format either 7 bits with parity bits without parity (D6) (D6 = 0) or 8 bits without parity (D6 = 1). TA (D7) SC0, SC1, SC2 (D0, D1, D2) TB (D3) R2 Address 02H Addressing information for a page request A0, A1 (D4, D5) A2 (D6) A3 (D7) R3 Address 03H R4 Address 04H R5 Address 05H Data relative to the requested page (see Table 3) Selection of one of 16 pages to display PRD0 - PRD4 (D0 - D4) A0, ... A3 (D0, ... D3) PON (D0, D1) Display control for normal operation TEXT (D2, D3) COR (D4, D5) BKGND (D6, D7) IN / OUT R6 Address 06H Display control for news-flash subtitle generation See R5 Test bit, must be cleared in the normal working mode Address the first column of the on chip page request RAM to be written. Test bit, must be cleared in the normal working mode. Address a group of four consecutive pages currently used for data acquisition; Address of one of the two groups of four pages for acquisition in normal mode. Block select: D7 = 0 internal memory, D7 = 1 external memory Written data in the page request RAM, starting with the columns addressed by SC0,SC1,SC2. These 4 bits correspond to the logical states of the 4 address lines (A10, ... A13) during memory read cycles. Picture on (IN: D0, OUT: D1) Text on (IN: D2, OUT: D3) Contrast reduction on (IN: D4, OUT: D5) Background colour on (IN: D6, OUT: D7) Enable inside/outside the box See R5
BOX ON 0, 1-23,24 (D0, D1, D2) R7 Address 07H TOP/BOTTOM Single/Double Height (D4/D3) Conceal/Reveal (D5) Cursor ON/OFF (D6) STATUS ROW BTM / TOP (D7)
The "boxing" function is enabled on row 0,1-23 and 24 by D0, D1 and D2 set to one. X0 = Normal 01 = double height Rows 0 to 11 11 = double height Rows 12 to 23 Conceal Reveal Function The 25th row is displayed before the "Main text Area" (lines 0-23) or after (D7 = 0).
5345-10.TBL
Display mode
Cursor position given by row/column value of R9/R10
16/25
STV5345 - STV5345/H - STV5345/T
REGISTER FUNCTIONS (continued)
Register R8 to R11A Address 08H to 0BH* R11B Address 0BH* R12 Address 0CH Function Bit(s) Description Active chapter address (R8), active row address (R9), active column address (R10). Data contained in R11A read (written) from (to) memory by microprocessor via I2C. VCS Signal Quality (D0) 60Hz (D7) A0, A1 (D3, D4) Page request address EROD (D5) Good VCS quality signal detected (D0 = 1) or disturbed (D0 = 0) VCS received with 60Hz frequency (D7 = 1) or 50Hz (D7 = 0). Only valid when VCS is good (D0 = 1) A0, A1 addresses of displayed page to refresh when using refresh on display function Enable refresh on displayed page function when = 1 normal acquisition storage if EROD = 0
Status
* Reading of R11A or R11B is determined by register 0, bit D0. Nevertheless, write operation is always performed on R11A register.
Table 3 : Register R3
START COLUMN 0 1 2 3 4 5 6 PRD4 Do care magazine Do care page tens Do care page units Do care hours tens Do care hours units Do care minutes tens Do care minutes units PRD3 HOLD PT3 PU3 X HU3 X MU3 PRD2 MAG2 PT2 PU2 X HU2 MT2 MU2 PRD1 MAG1 PT1 PU1 HT1 HU1 MT1 MU1 PRD0 MAG0 PT0 PU0 HT0 MT0 MU0
5345-12.TBL
HU0
The abbreviations have the same significance as in Table 1 with the exception of the "DO CARE" entries. It is only when this bit is "1" that the corresponding digit is taken into consideration on page request. For example, a page defined as "normal" or one defined as "timed" may be selected. If "HOLD" is low the page is held. The addressing of successive bytes via the I2C bus is automatic.
CHARACTER SETS The complete character set with 8-bit decoding is given in Tables 4a, 4b and 4c. Characters in columns 0 and 1 are normally displayed as blanks. Black dots represent the character shape whereas white dots represent the background. Each character can be identified by a pair of corresponding row and column integers : for example the character "3" may be indicated by 3/3. A rectangle may be represented as follows : The characters 8/6, 8/7, 9/5, 9/7 are used as special characters, always in conjunction with 8/5. The 13 national characters are placed in columns with bit 8 = 0.
17/25
5345-11.TBL
* **
18/25
0 0 0 1 1 graphics black graphics red graphics green graphics yellow graphics blue graphics magenta graphics cyan graphics white conceal display continuous graphics separated graphics 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 or 1 0 0 or 1 0
0
b8 b7
0
0
B I T S b4 b 3 b 2 b 1
b6 b5
0
column
r o w
2
0
0
0
0
0
alphanumerics
black
0
0
0
1
1
alphanumerics
red
0
0
1
0
2
alphanumerics
green
STV5345 - STV5345/H - STV5345/T
Case using C12 C13 C14 = 001 (German Set)
** *
ESC black background new background
0
0
1
1
3
alphanumerics
yellow
0
1
0
0
4
alphanumerics
blue
0
1
0
1
5
alphanumerics
magenta
0
1
1
0
6
alphanumerics
Table 4a : Complete character set (with 8 bit codes) - West European Languages (STV5345)
5345-14.EPS
These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins
** ** *
hold graphics
cyan
0
1
1
1
7
alphanumerics
**
white
1
0
0
0
8
flash
**
1
0
0
1
9
steady
**
1
0
1
0
10
end box
1
0
1
1
11
start box
**
1
1
0
0
12
normal height
1
1
0
1
13
double
height
1
1
1
0
14
SO
*
release graphics
**
1
1
1
1
15
SI
Table 4b : Complete character set (with 8 bit codes) - East European Languages (STV5345/H)
* **
0 0 0 1 1 graphics black 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 or 1 0 1 0 or 1 0 1 graphics red graphics green graphics yellow graphics blue graphics magenta graphics cyan graphics white conceal display ** continuous graphics separated graphics * ESC ** black background ** new background * hold graphics ** * release graphics
0
0
B I T S
0
b 4 b3 b2 b 1
b8 b7 b6 b5
0
r o w
column
2
0
0
0
0
0
alphanumerics black
0
0
0
1
1
alphanumerics red
0
0
1
0
2
alphanumerics green
Case using C12 C13 C14 = 111 (Rumanian Set)
0
0
1
1
3
alphanume rics yellow
0
1
0
0
4
alphanumerics blue
0
1
0
1
5
alphanumerics magenta
These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins
0
1
1
0
6
alphanumerics cyan
0
1
1
1
7
** alphanumerics white
1
0
0
0
8
flash
**
1
0
0
1
9
steady
**
1
0
1
0
10
end box
1
0
1
1
11
start box
**
1
1
0
0
12
normal height
1
1
0
1
13
double height
1
1
1
0
14
SO
1
1
1
1
15
SI
STV5345 - STV5345/H - STV5345/T
19/25
5345-15.EPS
* **
20/25
0 0 or 1 0 0 0 1 1 0 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15 0 0 0 0 1 0 0 0 1 1 graphics black graphics red graphics green graphics yellow graphics blue graphics magenta graphics cyan graphics white conceal display continuous graphics separated graphics 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 or 1 0 0 1 1 1 1 1 1
b8
0
0
0
B I T S b4 b3 b 2 b1
b7 b6 b5
0
column
r o w
2
0
0
0
0
0
alphanumerics
black
0
0
0
1
1
alphanumerics
red
0
0
1
0
2
alphanumerics
green
STV5345 - STV5345/H - STV5345/T
Case using C12 C13 C14 = 001 (German Set)
** *
ESC black background new background
0
0
1
1
3
alphanumerics
yellow
0
1
0
0
4
alphanumerics
blue
0
1
0
1
5
alphanumerics
magenta
0
1
1
0
6
alphanumerics
Table 4c : Complete character set (with 8 bit codes) - Turkish European Languages (STV5345/T)
5345-16.EPS
These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins
** ** *
hold graphics
cyan
0
1
1
1
7
alphanumerics
**
white
1
0
0
0
8
flash
**
1
0
0
1
9
steady
**
1
0
1
0
10
end box
1
0
1
1
11
start box
**
1
1
0
0
12
normal height
1
1
0
1
13
double
height
1
1
1
0
14
SO
*
release graphics
**
1
1
1
1
15
SI
STV5345 - STV5345/H - STV5345/T
The basic set of the 96 characters is shown in Table 5.The location of the 13 national characters Table 5 : Basic character set.
2/0 3/0 4/0
National Charact er
are shown in Table 5 whilst full national character sets are depicted in Tables 6, 7 and 8.
5/0
6/0
National Character
7/0
2/1
3/1
4/1
5/1
6/1
7/1
2/2
3/2
4/2
5/2
6/2
7/2
2/3
National Character
3/3
4/3
5/3
6/3
7/3
2/4
National Character
3/4
4/4
5/4
6/4
7/4
2/5
3/5
4/5
5/5
6/5
7/5
2/6
3/6
4/6
5/6
6/6
7/6
2/7
3/7
4/7
5/7
6/7
7/7
2/8
3/8
4/8
5/8
6/8
7/8
2/9
3/9
4/9
5/9
6/9
7/9
2/10
3/10
4/10
5/10
6/10
7/10
2/11
3/11
4/11
5/11
National Character
6/11
7/11
National Character
2/12
3/12
4/12
5/12
National Character
6/12
7/12
National Character
2/13
3/13
4/13
5/13
National Character
6/13
7/13
National Character
2/14
3/14
4/14
5/14
National Character
6/14
7/14
National Character
5345-17.EPS
2/15
3/15
4/15
5/15
National Character
6/15
7/15
21/25
STV5345 - STV5345/H - STV5345/T
Table 6 : Character Set for STV5345 West European Languages Table 7 : Character Set for STV5345/H East European Languages
7/14
7/13
7/12
7/11
6/0
CHARACTER POSITION (COLUMN/ROW)
CHARACTER POSITION (COLUMN/ROW) 0 1 0 1 0 1
5/15
5/14
5/13
5/12
5/11
4/0
2/4
2/3
C14
C14
2/3 0
2/4
4/0
5/11
5/12
5/13
5/14
5/15
6/0
7/11
7/12
7/13
7/14
1
0
1
0
PHCB (1)
PHCB (1)
C13
C13
0
0
1
1
0
0
0
0
1
0
1
C12
C12
0
0
0
0
1
1
0
0
0
1
1
CZECHOSLOVAK
SERBO-CROAT
LANGUAGE
LANGUAGE
5345-18.EPS
POLISH
RUMANIAM
SWEDISH
SWEDISH
SPANISH
GERMAN
GERMAN
ENGLISH
FRENCH
ITALIAN
1
1
1
Note 1 :
Where PHCB are the Page Header Control bits. Other Combinations de fault to English. Only the ab ove cha racters change with the PHCB. All others characters in the basic set are shown in Table 5.
Note 1 :
Where PHCB are the Page Header Control bits. Other Combinations default to German. Only the above cha racters change with the PHCB. All others characters in the basic set are shown in Table 5.
22/25
5345-19.EPS
STV5345 - STV5345/H - STV5345/T
Table 8 : Character Set for STV5345/T Turkish European Languages
7/14 CHARACTER POSITION (COLUMN/ROW) C14 2/3 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13
0
1
0
1
0
PHCB (1)
C13
0
0
1
1
0
C12
0
0
1
0
1
LANGUAGE
ENGLISH
SPANISH
GERMAN
TURKISH
FRENCH
ITALIAN
1
0
1
Note 1 :
Where PHCB are the Page Header Control bits. Other Combinations de fault to Turkish. Only the above characters change with the PHCB. All oth ers characters in the basic set are shown in Table 5.
23/25
5345-20.EPS
STV5345 - STV5345/H - STV5345/T
Figure 11 : Character Format
Alphanumerics and Graphics 'space' characte r 2/0
Alphanumerics character 2/13
Alphanumerics or blast-through alphanumerics character 4/8
Alphanumerics character 7/15
Contiguous graphics character 7/6
Separated graphics character 7/6
Separated graphics character 7/15 Background Color
Contiguous graphics character 7/15 Display Color
5345-21.EPS
=
=
24/25
STV5345 - STV5345/H - STV5345/T
PACKAGE MECHANICAL DATA 40 PINS - PLASTIC DIP
a1 I L
b1 b b2 e3 e E
D
40
21
F
1
20
Dimensions a1 b b1 b2 D E e e3 F i L
Min.
Millimeters Typ. 0.63 0.45 1.27
Max.
Min.
Inches Typ. 0.025 0.018 0.050
Max.
0.23
0.31 52.58 16.68 2.54 48.26 14.1 4.445 3.3
0.009
0.012 2.070 0.657 0.100 1.900 0.555 0.175 0.130
DIP40.TBL
15.2
0.598
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
25/25
PM-DIP40.EPS

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