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GM71C(S)17400C/CL
4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
Description
The GM71C(S)17400C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71C(S)17400C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)17400C/CL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71C(S)17400C/CL to be packaged in a standard 300 mil 24(26) pin SOJ, and a standard 300 mil 24(26) pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply 5.0V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.
Features
* 4,194,304 Words x 4 Bit Organization * Fast Page Mode Capability * Single Power Supply (5.0V+/-10%) * Fast Access Time & Cycle Time (Unit: ns)
tRAC tCAC tRC
GM71C(S)17400C/CL-5 GM71C(S)17400C/CL-6 GM71C(S)17400C/CL-7 50 60 70 13 15 18 90 110 130
tPC
35 40 45
Pin Configuration 24(26) SOJ
VCC I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 26 25 24 23 22 21
* Low Power Active : 660/605/550mW (MAX) Standby : 11mW (CMOS level : MAX) : 0.83mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 2048 Refresh Cycles/32ms * 2048 Refresh Cycles/128ms (L-version) * Battery backup operation (L-version) * Test function : 16bit parallel test mode
24(26) TSOP II
VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 26 25 24 23 22 21
VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS
8 9 10 11 12 13
19 18 17 16 15 14
8 9 10 11 12 13
19 18 17 16 15 14
(Top View)
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
Pin Description
Pin
A0-A10 A0-A10 I/O1-I/O4 RAS CAS
Function
Address Inputs Refresh Address Inputs Data Input/Data Output Row Address Strobe Column Address Strobe
Pin
WE OE VCC VSS NC
Function
Read/Write Enable Output Enable Power (5.0V) Ground No Connection
Ordering Information
Type No.
GM71C(S)17400CJ/CLJ-5 GM71C(S)17400CJ/CLJ-6 GM71C(S)17400CJ/CLJ-7 GM71C(S)17400CT/CLT-5 GM71C(S)17400CT/CLT-6 GM71C(S)17400CT/CLT-7
Access Time
50ns 60ns 70ns 50ns 60ns 70ns
Package
300 Mil 24(26) Pin Plastic SOJ 300 Mil 24(26) Pin Plastic TSOP II
Absolute Maximum Ratings*
Symbol TA TSTG VIN/VOUT VCC IOUT PD Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage on any Pin Relative to VSS Voltage on VCC Relative to VSS Short Circuit Output Current Power Dissipation
Rating
0 ~ 70 -55 ~ 125 -1.0 ~ 7.0 -1.0 ~ 7.0 50 1.0
Unit
C C V V mA W
*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol VCC VIH VIL Parameter
Supply Voltage Input High Voltage Input Low Voltage
Min
4.5 2.4 -1.0
Typ
5.0 -
Max
5.5 6.0 0.8
Unit
V V V
Note: All voltage referred to Vss.
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
DC Electrical Characteristics (VCC = 5.0V+/-10%, Vss = 0V, TA = 0 ~ 70C)
Symbol VOH VOL ICC1 Parameter
Output Level Output "H" Level Voltage (IOUT = -5mA) Output Level Output "L" Level Voltage (IOUT = 4.2mA) Operating Current Average Power Supply Operating Current (RAS, CAS Cycling : tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) Fast Page Mode Current Average Power Supply Current Fast Page Mode (tPC = tPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >= VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) 50ns 60ns 70ns ICC7 Battery Backup Operating Current(Standby with CBR Refresh) (CBR refresh, tRC=62.5us, tRAS<=0.3us, DOUT=High-Z, CMOS interface) Standby Current RAS = VIH CAS = VIL DOUT = Enable Input Leakage Current Any Input (0V<=VIN<= 6V) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 6V) 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns
Min
2.4 0 -
Max
VCC 0.4 100 90 80 2 100 90 80 90 80 70 1 150 100 90 80 350
Unit
V V
Note
mA
1, 2
ICC2
mA
ICC3
mA
2
ICC4
mA
1, 3
ICC5
mA uA 4
ICC6
mA
-
uA
4
ICC8
-
5
mA
1
IL(I) IL(O)
-10 -10
10 10
uA uA
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. L-version.
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
Capacitance (VCC = 5.0V+/-10%, TA = 25C)
Symbol CI1 CI2 CI/O Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out)
Min
-
Max
5 7 7
Unit
pF pF pF
Note
1 1 1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 5.0V+/-10%, Vss=0V, TA = 0 ~ 70C, Notes 1, 2, 18,19)
Test Conditions Input rise and fall times : 5ns Input timing reference levels : 0.8V, 2.4V Output timing reference levels : 0.4V, 2.4V Output load : 2 TTL gate + CL (100pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read or Write Cycle Time RAS Precharge Time CAS Precharge Time RAS Pulse Width CAS Pulse Width Row Address Set up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time RAS to CAS Delay Time RAS to Column Address Delay Time RAS Hold Time CAS Hold Time CAS to RAS Precharge Time OE to DIN Delay Time OE Delay Time from DIN CAS Delay Time from DIN Transition Time (Rise and Fall)
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max
tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tT
90 30 7 50 13 0 7 0 7 17 12 13 50 5 13 0 0 3
10,000 10,000
110 40 10
-
130 50 10
10,000 10,000
60 10,000 70 15 0 10 0 10 20 15 15 60 5 15 0 0 3
10,000
18 0 10 0 15 20 15 18 70 5 18 0 0 3
45 30 50
45 30 50
52 35 50
3 4
5 6 6 7
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
Read Cycle
Symbol Parameter
Access Time from RAS Access Time from CAS Access Time from Address Access Time from OE Read Command Setup Time Read Command Hold Time to CAS Read Command Hold Time to RAS Column Address to RAS Lead Time Column Address to CAS Lead Time CAS to Output in low-Z Output Data Hold Time Output Data Hold Time from OE Output Buffer Turn-off Time to OE Output Buffer Turn-off Time CAS to DIN Delay Time
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
8,9,20
9,11, 17,20 9,10, 17,20
Min Max Min Max Min Max
tRAC tCAC tAA tOAC tRCS tRCH tRRH tRAL tCAL tCLZ tOH tOHO tOEZ tOFF tCDD
0 0 5 25 25 0 3 3 13
50 13 25 13 13 13 -
0 0 5 30 30 0 3 3 15
60 15 30 15 15 15 -
0 0 5 35 35 0 3 3 18
70 18 35 18 15 15 -
9
12 12
13 13 5
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns ns ns
Note
14
Min Max Min Max Min Max
tWCS tWCH
0 7 7 13 13 0 7
-
0 10 10 15 15 0 10
-
0 15 10 18 18 0 15
-
tWP
tRWL tCWL tDS tDH
15 15
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time OE Hold Time from WE
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns
Note
Min Max Min Max Min Max
tRWC tRWD tCWD tAWD tOEH
131 73 36 48 13
-
155 85 40 55 15
-
181 98 46 63 18
-
14 14 14
Refresh Cycle
Symbol Parameter
CAS Setup Time (CAS-before-RAS Refresh Cycle) CAS Hold Time (CAS-before-RAS Refresh Cycle) WE Setup Time (CAS-before-RAS Refresh Cycle) WE Hold Time (CAS-before-RAS Refresh Cycle) RAS Precharge to CAS Hold Time
GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 GM71C(S)17400 C/CL-7
Unit
Note
Min Max Min Max Min Max
tCSR tCHR tWRP tWRH tRPC
5 7 0 10 5
-
5 10 0 10 5
-
5 10 0 10 5
-
ns ns ns ns ns
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode RAS Pulse Width Access Time from CAS Precharge RAS Hold Time from CAS Precharge
GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 GM71C(S)17400 C/CL-7
Unit
ns ns ns ns
Note
Min Max Min Max Min Max
tPC tRASP tACP tRHCP
35 30
100,000
40 35
100,000
45 40
100,000
16
9,17,20
30 -
35 -
40 -
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
Fast Page Mode Read-Modify-Write Cycle
Symbol Parameter
Fast Page Mode Read-Modify-Write Cycle Time WE Delay Time from CAS Precharge
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns
Note
Min Max Min Max Min Max
tPRWC tCPW
76 53
-
85 60
-
96 68
-
14
Test Mode Cycle 19
Symbol Parameter
Test Mode WE Setup Time Test Mode WE Hold Time
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns
Note
Min Max Min Max Min Max
tWTS tWTH
0 10
-
0 10
-
0 10
-
Refresh
Symbol Parameter
Refresh Period Refresh Period (L - version)
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400 C/CL-5 C/CL-6 C/CL-7
Unit
ms ms
Note
2048 cycles 2048 cycles
Min Max Min Max Min Max
tREF tREF
-
32 128
-
32 128
-
32 128
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
Notes: 1. AC Measurements assume tT =5ns. 2. An initial pause of 200us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL(max). 8. Assume that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100pF. (VOH = 2.4V, VOL = 0.8V) 10. Assume that tRCD >=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max). 11. Assume that tRAD >=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS>=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>= tAWD(min) and tCPW>=tCPW(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in Fast page mode cycles. 17. Access time is determined by the longest among tAA or tCAC or tACP.
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance); if tOEH < tCWL, invalid data will be out at each I/O. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-beforeRAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh cycle or RAS-only refresh cycle. 20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
Package Dimension
24(26) SOJ
0.025(0.64) MIN 0.295(7.49) MIN 0.305(7.75) MAX 0.329(8.38) MIN 0.340(8.64) MAX
Unit: Inches (mm)
0.661(16.80) MIN 0.669(17.00) MAX
0.085(2.16) MIN
0.128(3.25) MIN 0.147(3.75) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 0.026(0.66) MIN 0.032(0.81) MAX
24(26) TSOP (TYPE II)
0~5
o
0.016(0.40) MIN 0.024(0.60) MAX
0.296(7.52) MIN 0.303(7.72) MAX
0.670(17.04) MIN 0.678(17.24) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX 0.012(0.30) MIN 0.020(0.50) MAX 0.050(1.27) TYP 0.003(0.08) MIN 0.007(0.18) MAX
0.355(9.02) MIN 0.371(9.42) MAX
0.004(0.12) MIN 0.008(0.21) MAX
Rev 0.1 / Apr'01
0.275(6.99) MAX
0.260(6.60) MIN

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