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| HCF4021B ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER s s s s s s s s MEDIUM SPEED OPERATION : 12 MHz (Typ.) CLOCK RATE AT VDD - VSS = 10V FULLY STATIC OPERATION 8 MASTER-SLAVE FLIP-FLOPS PLUS OUTPUT BUFFERING AND CONTROL GATING QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4021BEY HCF4021BM1 T&R HCF4021M013TR DESCRIPTION The HCF4021B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. This device is an 8-stage parallel or serial input/ serial output register having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop in addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Serial entry is synchronous with the clock but parallel entry is asynchronous. PIN CONNECTION In this device, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of he clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple package is permitted. September 2001 1/11 HCF4021B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 7, 6, 5, 4, 13, 14, 15, 1 11 9 10 2, 3, 12 8 16 SYMBOL PI1 to PI8 SERIAL IN PARALLEL/ SERIAL CONTROL CLOCK Q6, Q7, Q8 VSS VDD NAME AND FUNCTION Parallel Input Serial Input Parallel/Serial Input Control Clock Input Buffered Outputs Negative Supply Voltage Positive Supply Voltage TRUTH TABLE CLOCK X X X X SERIAL INPUT X X X X 0 1 X X : Don't Care PARALLEL/ SERIAL CONTROL 1 1 1 1 0 0 X PI - 1 0 0 1 1 X X X PI - n 0 1 0 1 X X X Q1 (INTERNAL) 0 0 1 1 0 1 Q1 Qn 0 1 0 1 Qn - 1 Qn - 1 Qn LOGIC DIAGRAM 2/11 HCF4021B ABSOLUTE MAXIMUM RATINGS Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C 3/11 HCF4021B DC SPECIFICATIONS Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 0.1 7.5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit IL Quiescent Current A VOH High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current VOL VIH VIL IOH IOL Output Sink Current Input Leakage Current Input Capacitance 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 V V V V mA mA A pF II CI Any Input Any Input The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 4/11 HCF4021B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns) Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 160 80 60 100 50 40 6 12 17 90 40 25 Max. 320 160 120 200 100 80 Unit CLOCKED OPERATION tPLH tPHL Propagation Delay Time ns tTHL tTLH Transition Time ns fCL (1) Maximum Clock Input Frequency Clock Pulse Width tW 3 6 8.5 180 80 50 MHz ns 15 15 15 tr , tf Clock Input Rise or Fall Time Setup Time, serial Input (ref to CL) Setup Time, Parallel Inputs (ref to P/S) Hold Time, serial in, parallel in, parallel /serial control P/S Pulse Widht s tsetup tsetup thold tWH trem P/S Removal Time (ref to CL) 120 80 60 50 30 20 0 0 0 160 80 50 280 140 100 60 40 30 25 15 10 ns ns ns 80 40 25 140 70 50 ns ns (*) Typical temperature coefficient for all VDD value is 0.3 %/C. (1) If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage of the estimated capacitive load. 5/11 HCF4021B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50) WAVEFORM 1 : PROPAGATION DELAY TIMES, CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle) 6/11 HCF4021B WAVEFORM 2 : SETUP AND HOLD TIMES (SI TO CLOCK) (f=1MHz; 50% duty cycle) WAVEFORM 3 : SETUP AND HOLD TIME (PI TO P/S) (f=1MHz; 50% duty cycle) 7/11 HCF4021B WAVEFORM 4 : PULSE WIDTH AND REMOVAL TIME (P/S TO CLOCK) (f=1MHz; 50% duty cycle) 8/11 HCF4021B Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 9/11 HCF4021B SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 10/11 HCF4021B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com 11/11 |
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