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W9961CF H.263/H.261 VIDEO CODEC
W9961CF H.263/H.261 Video Codec
Version 1.0 April, 1999
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W9961CF
Copyright by Winbond Electronics Corp., all rights reserved. The information in this document has been carefully checked and is believed to be correct as of the date of publication. Winbond Electronics Corp. reserves the right to make changes in the product or specification, or both, presented in this publication at any time without notice. Winbond assumes no responsibility or liability arising from the specification listed herein. Winbond makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patents, trademark, copyright, or rights of third parties. No license is granted by implication or other under any patent or patent rights of Winbond Electronics Corp. All other trademarks and registered trademarks are the property of their respective holders.
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W9961CF
TABLE OF CONTENTS
1 2 3 4 GENERAL DESCRIPTION..................................................................................................................... 7 FEATURES............................................................................................................................................... 8 PIN CONFIGURATION ........................................................................................................................ 10 PIN DESCRIPTION ............................................................................................................................... 11
4.1 PIN DEFINITION ........................................................................................................................................ 11 4.2 PIN LIST ................................................................................................................................................... 17 4.3 POWER ON RESET INITIALIZATION............................................................................................................. 22 5 6 7 SYSTEM DIAGRAM ............................................................................................................................. 24 BLOCK DIAGRAM ............................................................................................................................... 26 FUNCTIONAL DESCRIPTION ............................................................................................................ 27
7.1 VPRE PROCESSOR.................................................................................................................................... 27 7.2 VIDEO CODEC........................................................................................................................................... 28 7.2.1 Video Coding .................................................................................................................................... 28
7.2.1.1 I-pictures INTRA Coding .............................................................................................................................28 7.2.1.2 P-pictures INTER Coding ............................................................................................................................29 7.2.1.3 P-pictures INTRA Coding ............................................................................................................................29
7.2.2 Video Decoding ................................................................................................................................ 29 7.3 VPOST PROCESSOR ................................................................................................................................. 30 7.3.1 Video Post-processing....................................................................................................................... 30 7.3.2 Display Control ................................................................................................................................ 31 7.3.3 Video Output Control........................................................................................................................ 31
7.3.3.1 Hue, Saturation, Contrast, and Brightness Adjustments................................................................................31 7.3.3.2 Video Output Interface.................................................................................................................................32
7.4 RISC MICROPROCESSOR ........................................................................................................................... 35 7.4.1 RISC Pipeline Stages ........................................................................................................................ 35 7.4.2 Address Spaces ................................................................................................................................. 36
7.4.2.1 Program Memory Address Space..................................................................................................................36 7.4.2.2 Data Memory Address Space .......................................................................................................................36
7.4.3 RISC Registers.................................................................................................................................. 38
7.4.3.1 General Registers ........................................................................................................................................38 7.4.3.2 Shadow Registers ........................................................................................................................................38
7.4.4 RISC Interrupt Handling................................................................................................................... 39 7.5 INTC (INTERRUPT CONTROLLER).............................................................................................................. 41 7.6 TIMER ...................................................................................................................................................... 43 7.7 FDMA CONTROLLER................................................................................................................................ 44 7.7.1 FDMA Transfer Modes ..................................................................................................................... 45 7.7.2 FDMA Transfer Types....................................................................................................................... 45
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W9961CF
7.7.3 FDMA Programming ........................................................................................................................ 45 7.8 HOST INTERFACE CONTROLLER ................................................................................................................. 48 7.8.1 PCI Address Spaces .......................................................................................................................... 48 7.8.2 PCI Interrupt Control ....................................................................................................................... 48 7.9 DRAM CONTROLLER ............................................................................................................................... 50 7.9.1 Video Memory Arbitration ................................................................................................................ 50 7.9.2 DRAM Interface................................................................................................................................ 51 7.10 ISA-LIKE BUS INTERFACE AND GPIOS ..................................................................................................... 52 7.10.1 ISA-like Bus Interface ..................................................................................................................... 52 7.10.2 GPIO .............................................................................................................................................. 52 7.11 PLL (PHASE LOCKED LOOP).................................................................................................................... 53 8 ELECTRICAL CHARACTERISTICS .................................................................................................. 54
8.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................. 54 8.2 DC CHARACTERISTICS.............................................................................................................................. 54 8.2.1 DAC DC Characteristics................................................................................................................... 54 8.2.2 Digital DC Characteristics ............................................................................................................... 58 8.3 AC CHARACTERISTICS.............................................................................................................................. 59 8.3.1 DAC AC Characteristics ................................................................................................................... 59 8.3.2 PLL AC Characteristics .................................................................................................................... 59 8.3.3 RESET Timing AC Characteristics.................................................................................................... 60 8.3.4 Clock AC Characteristics.................................................................................................................. 60 8.3.5 Input Timing AC Characteristics....................................................................................................... 61 8.3.6 Output Timing AC Characteristics .................................................................................................... 62 9 10 PACKAGE SPEC. .................................................................................................................................. 64 ORDERING INFORMATION............................................................................................................. 65
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W9961CF
LIST OF FIGURES
FIGURE 3.1 W9961CF PIN CONFIGURATION .................................................................................................... 10 FIGURE 5.1 W9961CF-BASED STAND-ALONE VIDEOPHONE SYSTEM DIAGRAM ................................................. 24 FIGURE 6.1 W9961CF BLOCK DIAGRAM ......................................................................................................... 26 FIGURE 7.1 VPRE PROCESSOR BLOCK DIAGRAM ............................................................................................. 27 FIGURE 7.2 VIDEO CODEC BLOCK DIAGRAM .................................................................................................... 28 FIGURE 7.3 VPOST PROCESSOR BLOCK DIAGRAM........................................................................................... 30 FIGURE 7.4 TYPICAL THREE-WINDOW DISPLAY FOR VIDEO CONFERENCING APPLICATIONS................................ 31 FIGURE 7.5 HUE, SATURATION, CONTRAST, AND BRIGHTNESS CONTROLS ........................................................ 32 FIGURE 7.6 RISC MICROPROCESSOR BLOCK DIAGRAM .................................................................................... 35 FIGURE 7.7 PROGRAM MEMORY ADDRESS SPACE............................................................................................. 37 FIGURE 7.8 DATA MEMORY ADDRESS SPACE ................................................................................................... 37 FIGURE 7.9 RISC GENERAL REGISTERS ........................................................................................................... 38 FIGURE 7.10 INTC BLOCK DIAGRAM .............................................................................................................. 41 FIGURE 7.11 TIMER BLOCK DIAGRAM.............................................................................................................. 43 FIGURE 7.12 FDMA CONTROLLER BLOCK DIAGRAM ....................................................................................... 44 FIGURE 7.13 BLOCK TRANSFER MODE WITH BLOCK ADDRESSING..................................................................... 46 FIGURE 7.14 DEMAND TRANSFER MODE WITH LINEAR ADDRESSING................................................................. 47 FIGURE 7.15 HOST INTERFACE CONTROLLER BLOCK DIAGRAM ........................................................................ 48 FIGURE 7.16 DRAM CONTROLLER BLOCK DIAGRAM....................................................................................... 50 FIGURE 7.17 PLL BLOCK DIAGRAM................................................................................................................. 53 FIGURE 8.1 525-LINE (NTSC/PAL-M) Y (LUMINANCE) OUTPUT WAVEFORM................................................... 55 FIGURE 8.2 625-LINE (PAL-B, D, G, H, N) Y (LUMINANCE) OUTPUT WAVEFORM............................................ 55 FIGURE 8.3 525-LINE (NTSC/PAL-M) C (CHROMINANCE) OUTPUT WAVEFORM .............................................. 56 FIGURE 8.4 625-LINE (PAL-B, D, G, H, N) C (CHROMINANCE) OUTPUT WAVEFORM ....................................... 56 FIGURE 8.5 525-LINE (NTSC/PAL-M) COMPOSITE VIDEO OUTPUT WAVEFORM ............................................... 57 FIGURE 8.6 625-LINE (PAL-B, D, G, H, N) COMPOSITE VIDEO OUTPUT WAVEFORM ........................................ 57 FIGURE 8.7 RESET TIMING ............................................................................................................................ 60 FIGURE 8.8 CLOCK WAVEFORM....................................................................................................................... 60 FIGURE 8.9 INPUT TIMING............................................................................................................................... 61 FIGURE 8.10 OUTPUT TIMING.......................................................................................................................... 62 FIGURE 9.1 208L QFP (28X28 MM FOOTPRINT 2.6MM) DIMENSIONS................................................................ 64
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W9961CF
LIST OF TABLES
TABLE 4.1 W9961CF PIN LIST........................................................................................................................ 17 TABLE 4.2 W9961CF POWER ON RESET DEFINITIONS ..................................................................................... 22 TABLE 7.1 W9961CF VIDEO OUTPUT MODES ................................................................................................. 32 TABLE 7.2 W9961CF VIDEO OUTPUT INTERFACE PIN ASSIGNMENT ................................................................. 34 TABLE 7.3 DATA MEMORY ADDRESS MAPPING................................................................................................ 37 TABLE 7.4 RISC INTERRUPT VECTORS ............................................................................................................ 39 TABLE 7.5 INTERRUPT CHANNELS ................................................................................................................... 41 TABLE 7.6 FDMA CHANNELS......................................................................................................................... 44 TABLE 7.7 PCI INTERRUPT CHANNELS ............................................................................................................ 48 TABLE 7.8 SDRAM AND EDO DRAM INTERFACE SIGNALS ............................................................................ 51 TABLE 7.9 ISA-LIKE BUS ACCESS MODES........................................................................................................ 52 TABLE 8.1 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 54 TABLE 8.2 DAC DC CHARACTERISTICS ........................................................................................................... 54 TABLE 8.3 DIGITAL DC CHARACTERISTICS....................................................................................................... 58 TABLE 8.4 DAC AC CHARACTERISTICS ........................................................................................................... 59 TABLE 8.5 TV MODES RESOLUTION AND CLOCK RATE ..................................................................................... 59 TABLE 8.6 PLL AC CHARACTERISTICS ............................................................................................................ 59 TABLE 8.7 RESET TIMING .............................................................................................................................. 60 TABLE 8.8 CLOCK AC CHARACTERISTICS......................................................................................................... 60 TABLE 8.9 PCICLK-REFERENCED INPUT TIMING AC CHARACTERISTICS ........................................................... 61 TABLE 8.10 SMCLK-REFERENCED INPUT TIMING AC CHARACTERISTICS.......................................................... 61 TABLE 8.11 VICLK-REFERENCED INPUT TIMING AC CHARACTERISTICS ........................................................... 62 TABLE 8.12 PCICLK-REFERENCED OUTPUT TIMING AC CHARACTERISTICS...................................................... 62 TABLE 8.13 SMCLK-REFERENCED OUTPUT TIMING AC CHARACTERISTICS ...................................................... 62 TABLE 8.14 PCLK-REFERENCED OUTPUT TIMING AC CHARACTERISTICS.......................................................... 63
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W9961CF
1
GENERAL DESCRIPTION
The W9961CF is a highly integrated single chip video codec provided by Winbond Electronics Corp. The W9961CF performs video compression and decompression fully compliant with ITU-T H.263 and H.261 standards for video conferencing. Working in conjunction with the high performance 32-bit RISC, W90220CF, the W9961CF is aimed to provide a complete video solution that supports both the H.324 international standard for video conferencing over regular telephone lines (Public Switched Telephone Network, or PSTN) as well as the H.320 international standard for ISDN video conferencing. Moreover, the W9961CF integrates a high quality NTSC/PAL TV encoder to directly interface to TV or LCD, eliminating the need for a separate TV encoder for stand-alone or set-top videophone. To achieve high performance video coding and decoding, many hardware engines are integrated in the W9961CF, which perform Motion Estimation and Motion Compensation, Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT), Quatization and Inverse Quantization, Zig-zag Scan, Variable Length Encoding and Variable Length Decoding (VLD), etc. A high performance 16-bit RISC with 5Kx22 bits program memory (PM) and 1Kx16 bits data memory (DM) is also integrated for H.263/H.261 coding/decoding control and intelligent frame rate control. There are three picture formats supported by the W9961 encoder and decoder: sub-QCIF, QCIF, and CIF. The W9961CF, when operated at 70 Mhz clock frequency, is capable to encode/decode subQCIF, QCIF, or CIF at 30 fps. The W9961CF can accept NTSC or PAL video, square, or rectangular pixels, and convert to subQCIF, QCIF, or CIF format. A two-dimensional noise reduction filter is integrated to reduce noise and improve coding efficiency. Built-in cropping window control and arbitrary scaling in both the horizontal and vertical directions can serve as the digital pan and zoom over a user-specified region for camera control. In the video post-processing, the W9961CF supports two movable and arbitrarily scaleable windows with picture-in-picture (PIP) feature for remote and local view video. A built-in post deblocking filter is used to reduce visible artifacts of remote view from video compression. The local view video can be mirrored or unmirrored. A display controller is built-in with 4-/8-/16-bit color modes for background or on-screen-display (OSD). A high quality NTSC/PAL TV encoder is also integrated to directly interface to TV or LCD. An on-chip DRAM controller is used to interface to SDRAM or EDO DRAM through 32-bit data bus. The W9961CF is a 3.3 V device with TTL-compatible 3.3 V or 5.0 V I/O, and is packaged in 208-pin PQFP.
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W9961CF
2
FEATURES
Video Codec
* * * * *
Fully compliant with ITU-T international standards H.263 and H.261 Encodes/decodes in sub-QCIF (128x96), QCIF (176x144), or CIF (352x288) picture format Encodes/decodes sub-QCIF/QCIF/CIF at 30 frames per second (fps) Supports both integer search and half-pixel search motion estimation Supports several H.263 Version 2 preferred modes including Annex D Annex J Annex K Annex L Annex T Unrestricted Motion Vectors (With UUI = 1) Deblocking Filter Slice Structured Mode Supplemental Enhancement Information (Full-Frame Freeze Only) Modified Quantization
Video Pre-processing
* * * * *
Direct connect to digital camera through 8- or 16-bit data bus Glueless interface to NTSC/PAL TV decoder Input video format compliant with YCbCr 4:2:2 CCIR 601 standard Built-in two-dimensional noise reduction filter to reduce noise and improve coding efficiency Built-in cropping and arbitrary scaling for digital pan and zoom camera control Video Post-processing
* * * * * * *
Built-in two moveable and arbitrarily scalable video windows with picture-in-picture (PIP) Built-in post deblocking filter to reduce visible artifacts of remote view from video compression The local view can be mirrored or unmirrored Built-in display controller with 4-/8-/16-bit color modes for background or on-screen-display (OSD) Built-in NTSC/PAL TV encoder with three 9-bit DACs for direct TV output Built-in 3-line 1D/2D flicker-free filter for best text quality Supports three composite video, one S-Video and one composite video, or one RGB output -8-
W9961CF
*
Hue, saturation, contrast, and brightness adjustments ISA-like Interface and GPIOs
* *
Direct connect to DSPG CT802X-series audio processor through 8-bit ISA-like interface Provides several general purpose I/O ports which can be configured as serial ports, keypad control, button control, remote control, etc. Host Interface
* *
Direct connect to Winbond W902X0-series CPU through 32-bit PCI bus PCI 2.1 compliant Memory Interface
* *
Supports SDRAM or 1-cycle EDO DRAM at 70 Mhz maximum clock frequency Supports 32-bit DRAM interface in 1, 2 or 4 Mbytes configuration Built-in Programmable Phase-Locked Loop (PLL) Clock Synthesizer Operating Frequency is 70 Mhz with Video Input Frequency of 13.5 MHz (typical), Video Output Frequency of 27.0 Mhz, and PCI Clock Frequency of 33 MHz 3.3 V Device with TTL-compatible 3.3 V or 5.0 V I/O Fabricated in Advanced 0.35um TLM Technology 208L QFP Package
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W9961CF
3
PIN CONFIGURATION
The W9961CF is packaged in a 208L QFP. The pin configuration is shown in Figure 3.1.
V S Y N C H S Y NPPPP C32 1 0 V I C L HVYY YYYYY Y KSS76 54321 0 GG V PVP SD I D I E S ODO M I 4I3 G P I O 2 G P I O 1 G P I O 0 V D D 5 V
V S S B
V DU UUUUUUU DV VVVVVVV B7 6543210 1 3 5 1 3 0
V S S B
MMMM DDDD 3322 1098
MM DD 22 76
V D D B
MMMM DDDD 2222 5432
M D 2 1
V S S B
MM DD 21 09
P4 P5 P6 P7 PCLK VDDI CP2/C/B CP1/Y/G CP0/R VREF RSET EXTVREF DACAVSS COMP DACAVDD SD0 VDD5V SD1 SD2 SD3 VSSB SD4 SD5 SD6 SD7 VOCLK SA0 SA1 VSSI SA2 SA3 VDDB SA4 SA5 VSSB SA6 SA7 SA8 SA9 SA10 SA11 SA12 EINT# SRD# SWR# PLLAVDD PLLAVSS MCLK VOCLK/2 INTA# RST# PCICLK
1 5 5 160
1 5 0
1 4 5
1 4 0
1 2 5
1 2 0
1 1 5
1 1 0
1 0 5 100
165 95
170 90
175 85
180
W9961CF
(Top View)
80
185
75
190 70
195 65
200 60
205 55 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0
MD18 MD17 MD16 VSSB RAS1#/CS1# VDDB CAS3#/DQM3 CAS2#/DQM2 MD15 MD14 MD13 MD12 MD11 MD10 VSSB MD9 MD8 MD7 MD6 MD5 MD4 MD3 VDDB MD2 MD1 MD0 RAS0#/CS0# VSSB CAS1#/DQM1 CAS0#/DQM0 WE# OE#/CKE SRAS# VDDI SCAS# VSSI SMCLK VSSB BA MA10 MA9 MA8 MA7 VDDB MA6 MA5 VSSB MA4 MA3 MA2 MA1 MA0
1
5
A D 3 1
A D 3 0
V S S B
A D 2 9
A D 2 8
V D D B
A D 2 7
A D 2 6
A D 2 5
A D 2 4
C / B E 3 #
I D S E L
A D 2 3
A D 2 2
A D 2 1
A D 2 0
A D 1 9
A D 1 8
A D 1 7
A D 1 6
V D D I
C / B E 2 #
F R A M E #
V S S I
I R D Y #
T R D Y #
V S S B
D E V S E L #
S T O P #
V D D B
P E R R #
SPCAA EA / DD RRB1 1 E54 R 1 # #
A D 1 3
A D 1 2
A D 1 1
AAAVCAAAAAA AA D D D S / D D D D D D DD 198SB76543210 BE 0 0 #
Figure 3.1 W9961CF Pin Configuration
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W9961CF
4
PIN DESCRIPTION
The following tables provide a brief description of each pin on the W9961CF. The following signal type definitions are used in these descriptions: I IU B O TS STS A P G # Input pin Input pin with internal pull-up resistor Bi-directional input/output pin Output pin Tri-State output pin Sustained Tri-State pin. Must drive it high for at least one PCI clock before letting it float. Analog pin Power supply pin Ground pin Active low
4.1 Pin Definition
PCI Bus Interface (48 pins) Pin Name AD[31:0] Pin Number 1, 2, 4, 5, 710, 13-20, 35-42, 45-52 Type B Description Multiplexed System Address and Data Bus. The address phase is the clock cycle in which FRAME# is asserted. Data is transferred during those clocks where both IRDY# and TRDY# are asserted. Multiplexed Bus Command and Byte Enables. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as Byte Enables. Parity. It is even parity across AD31-AD0 and C/BE[3:0]#. Cycle Frame. Asserted to indicate a bus transaction is beginning. Target Ready. A data phase is completed on any clock both TRDY# and IRDY# are sampled asserted. Initiator Ready. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted.
C/BE[3:0]#
11, 22, 34, 44
I
PAR FRAME#
33 23
TS I
TRDY#
26
STS
IRDY#
25
I
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W9961CF
INTA# STOP#
206 29
TS STS
Interrupt Request. Asserted low, level sensitive. Stop. Asserted to request the master to stop the current transaction. Device Select. Asserted to indicate the W9961CF has decoded its address as the target of the current access. Initialization Device Select. Used as chip select during configuration read and write transactions. Parity Error. It is only for the reporting of data parity errors during the PCI transactions. The W9961CF cannot report a PERR# until it has claimed the access by asserting DEVSEL# and completed a data phase. System Error. It is for reporting address parity errors, or any other system error where the result will be catastrophic. PCI System Clock. Up to 33 Mhz for W9961CF. System Reset.
DEVSEL#
28
STS
IDSEL
12
I
PERR#
31
STS
SERR#
32
TS
PCICLK RST#
208 207
I I
Video Memory Interface (55 pins) Pin Name MD[31:0] Pin Number 120-115,113109, 107, 106, 104-102, 9691, 89-83, 8179 65-62, 60, 59, 57-53 Type B Description Data Bus. Note: MD[15:0] are also used as the system configuration strapping bits, providing system configuration and setup information upon power-on or reset. O Address Bus. Note: for SDRAM, MA[10:0] are sampled during the ACTIVE command (row address MA[10:0]) and READ/WRITE command (column address MA[7:0], with MA10 defining AUTO PRECHARGE) to select one location out of the 512K available in the respective bank. MA10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (MA10 HIGH). RAS[1:0]# CS[1:0]# 100, 78 O EDO DRAM: Row Address Strobes. SDRAM: Chip Select. CS[1:0]# enable the command decoder - 12 -
MA[10:0]
W9961CF
for each external memory bank. CAS[3:0]# DQM[3:0] 98, 97, 76, 75 O EDO DRAM: Column Address Strobes. SDRAM: Input/Output Mask. DQM[3:0] are input mask signals for write accesses and output enable signals for read accesses. DQM0 corresponds to MD[7:0]; DQM1 corresponds to MD[15:8]; DQM2 corresponds to MD[23:16]; DQM3 corresponds to MD[31:24]. 73 O EDO DRAM: Output Enable. SDRAM: Clock Enable. CKE activates the SMCLK signal. The SDRAM enters precharge power-down to deactivate the input and output buffers, excluding CKE, for maximum power saving when CKE is LOW coincident with a NOP. 74 O EDO DRAM: Write Enable. SDRAM: Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. SRAS# 72 O EDO DRAM: Not used. SDRAM: Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. SCAS# 70 O EDO DRAM: Not used. SDRAM: Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. BA 66 O EDO DRAM: Not used. SDRAM: Bank Address Input. BA defines to which internal bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA is also used to program the 12th bit of the Mode Register. SMCLK 68 O EDO DRAM: Not used. SDRAM: Clock.
OE# CKE
WE#
Input Video Interface (19 pins) Pin Name Pin Number Type Description
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W9961CF
Y[7:0]
146-139
I
Digital Y (Luminance) Inputs in 16-bit Mode, or Digital YUV Inputs in 8-bit Mode. Digital UV (Chrominance) Inputs in 16-bit Mode, or Not Used in 8-bit Mode. Horizontal Sync. Input. Programmable polarity. Vertical Sync Input. Programmable polarity. Input Video Clock.
UV[7:0]
137-130
IU
HS VS VICLK
148 147 149
I I I
Output Video Interface (20 pins) Pin Name CP2 C B CP1 Y G CP0 165 O 164 O Pin Number 163 Type O Description Composite Video Mode: Composite Video Output. S-Video + Composite Video Mode: Chrominance Output. RGB Output Mode: Blue Video Output. Composite Video Mode: Composite Video Output. S-Video + Composite Video Mode: Luminance Output. RGB Output Mode: Green Video Output. Composite Video Mode: Composite Video Output. S-Video + Composite Video Mode: Composite Video Output. R P[7:0] 151-154, 157160 B RGB Output Mode: Red Video Output. 8-bit YCbCr Mode: Digital YCbCr Video Output Data. 8-bit RGB Mode: Digital RGB Video Output Data. PCLK 161 TS 8-bit YCbCr Mode: 2x Pixel Clock Output. 8-bit RGB Mode: HSYNC 155 TS Horizontal Sync.
2 x Pixel Clock Output. 3
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W9961CF
VSYNC DEM VREF
156 128 166
TS B A
Vertical Sync. Data Enable control signal for LCD interface. Voltage Reference. A 0.1uF bypass capacitor should always be connected between this pin and TVAVDD, with short leads and in close proximity to the device pins. Reference Resistor. A resistor should be connected from this pin to TVAVSS to control the full-scale current value. External VREF Mode: External Voltage Reference (analog input). An external voltage reference must supply this pin with a 1.235 V (typical) reference. A 0.1uF bypass capacitor should always be connected between this pin and TVAVDD. Internal VREF Mode: A 0.1uF bypass capacitor should always be connected between this pin and TVAVDD.
RSET
167
A
EXTVREF
168
A
COMP
170
A
Compensation Pin. A 0.1uF bypass capacitor should always be connected between this pin and TVAVDD, with short leads and in close proximity to the device pins. Output Video Clock. A stable 27 MHz reference clock input.
VOCLK
182
I
ISA-like Bus Interface and GPIO Ports (29 pins) Pin Name SD[7:0] Pin Number 181-178, 176174, 172 198-192, 190, 189, 187, 186, 184, 183 201 Type B Description Data Bus. ISA-like data bus to interface with the Audio Processor. Address Bus. They are output pins in normal operation (PWON_14-12 = 111), while serve as address inputs when in the Internal RAM/ROM Test mode (PWON_14-12 111). I/O Write. It is output pin in normal operation (PWON_14-12 = 111), while serves as write input when in the Internal RAM/ROM Test mode (PWON_14-12 111). I/O Read. It is output pin in normal operation (PWON_14-12 = 111), while serves as read input when in the Internal RAM/ROM Test mode (PWON_14-12 111). Interrupt Request Input.
SA[12:0]
B
SWR#
B
SRD#
200
B
EINT#
199
IU
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W9961CF
GPIO[4:0]
122-125, 127
B
General Purpose Input/Out Ports. With internal pull-up resistor.
Clock Interface (2 pins) Pin Name VOCLK/2 MCLK Pin Number 205 204 Type TS IU Description VOCLK By 2. A Stable 13.5 MHz clock output. External MCLK Mode: Main Clock Input. Internal MCLK Mode: Not used.
Power and Ground (35 pins) Pin Name VDDB Pin Number 6, 30, 61, 82, 99, 114, 138, 188 105, 173 Type P Description Buffer Power Supply. Provides isolated power to the input and output buffers for improved noise immunity. +3.3 V 0.3 V. 5V Buffer Power Supply. Provides 5V power to the input and output buffers for 5V input tolerance. +5.0 V 0.25 V. Buffer Ground.
VDD5V
P
VSSB
3, 27, 43, 58, 67, 77, 90, 101, 108, 121, 150, 177, 191 21, 71, 126, 162 24, 69, 129, 185 171
G
VDDI
P
Core Power Supply. +3.3 V 0.3 V. Core Ground.
VSSI
G
DACAVDD
P
DAC Analog Power Supply. Provides isolated power to the DAC analog ckts for improved noise immunity. +3.3 V 0.3 V. DAC Analog Ground. PLL Analog Power Supply. Provides isolated power to the PLL analog ckts for improved noise immunity. +3.3 V 0.3 V. PLL Analog Ground.
DACAVSS PLLAVDD
169 202
G P
PLLAVSS
203
G
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W9961CF
4.2 Pin List
Table 4.1 W9961CF Pin List Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Name AD31 AD30 VSSB AD29 AD28 VDDB AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 VDDI C/BE2# FRAME# VSSI IRDY# TRDY# VSSB DEVSEL# STOP# VDDB PEER# SERR# PAR C/BE1# AD15 AD14 AD13 Type B B G B B P B B B B I I B B B B B B B B P I I G I STS G STS STS P STS TS TS I B B B - 17 Pull-up IOH (mA) -3 -3 -3 -3 -3 -3 -3 -3 IOL (mA) 8 8 8 8 8 8 8 8 Load (pf) 50 50 50 50 50 50 50 50
-3 -3 -3 -3 -3 -3 -3 -3
8 8 8 8 8 8 8 8
50 50 50 50 50 50 50 50
-3 -3 -3 -3 -2 -3 -3 -3 -3
8 8 8 8 4 8 8 8 8
50 50 50 50 50 50 50 50 50
W9961CF
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 AD12 AD11 AD10 AD9 AD8 VSSB C/BE0# AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 MA0 MA1 MA2 MA3 MA4 VSSB MA5 MA6 VDDB MA7 MA8 MA9 MA10 BA VSSB SMCLK VSSI SCAS# VDDI SRAS# OE#/CKE WE# CAS0#/DQM0 CAS1#/DQM1 VSSB RAS0#/CS0 MD0 B B B B B G I B B B B B B B B O O O O O G O O P O O O O O G O G O P O O O O O G O B -3 -3 -3 -3 -3 8 8 8 8 8 50 50 50 50 50
-3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -6 -3 -3 -3 -3 -3 -3 -3 -3
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8
50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
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W9961CF
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 MD1 MD2 VDDB MD3 MD4 MD5 MD6 MD7 MD8 MD9 VSSB MD10 MD11 MD12 MD13 MD14 MD15 CAS2#/DQM2 CAS3#/DQM3 VDDB RAS1#/CS1 VSSB MD16 MD17 MD18 VDD5V MD19 MD20 VSSB MD21 MD22 MD23 MD24 MD25 VDDB MD26 MD27 MD28 MD29 MD30 MD31 VSSB B B P B B B B B B B G B B B B B B O O P O G B B B P B B G B B B B B P B B B B B B G -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
- 19 -
W9961CF
122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 GPIO0 GPIO1 GPIO2 GPIO3 VDDI GPIO4 DEM VSSI UV0 UV1 UV2 UV3 UV4 UV5 UV6 UV7 VDDB Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 VS HS VICLK VSSB P0 P1 P2 P3 HSYNC VSYNC P4 P5 P6 P7 PCLK VDDI CP2/C/B CP1/Y/G B B B B P B B G IU IU IU IU IU IU IU IU P I I I I I I I I I I I G B B B B TS TS B B B B TS P O O -2 -2 -2 -2 -2 -3 4 4 4 4 4 8 25 25 25 25 25 50

-3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3
8 8 8 8 8 8 8 8 8 8 8
50 50 50 50 50 50 50 50 50 50 50
- 20 -
W9961CF
165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 CP0/R VREF RSET EXTVREF DACAVSS COMP DACAVDD SD0 VDD5V SD1 SD2 SD3 VSSB SD4 SD5 SD6 SD7 VOCLK SA0 SA1 VSSI SA2 SA3 VDDB SA4 SA5 VSSB SA6 SA7 SA8 SA9 SA10 SA11 SA12 EINT# SRD# SWR# PLLAVDD PLLAVSS MCLK VOCLK/2 INTA# RST# PCICLK O A A A G A P B P B B B G B B B B I B B G B B P B B G B B B B B B B IU B B P G IU TS TS I I
-2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25
-3 -3 8 8 30 30
- 21 -
W9961CF
4.3 Power On Reset Initialization
During system reset and power up, state of the memory data lines MD[15:0] are latched into the W9961CFs internal configuration registers as video subsystem configuration information. Since each MD[15:0] pin is internally pulled up on their I/O buffers, no external pull-up resistor is required. A 4.7K ohm resistor to ground is recommended for pull-down. Table 4.2 shows the system power on reset configuration definitions. 1 is the default value for each bit. Table 4.2 W9961CF Power On Reset Definitions MD Bit(s) MD[0] MD[1] MD[3:2] Definition Video Memory Type DRAM Size Analog Video Output Mode Value 0 1 0 1 0X 10 11 MD[5:4] TV System 00 01 10 11 MD[6] MD[7] MD[8] MD[9] MD[10] MD[11] MD[14:12] CP2/C/B DAC Control CP1/Y/G DAC Control CP0/R DAC Control VREF Control Input Video Mode Internal MCLK Select Test Mode 0 1 0 1 0 1 0 1 0 1 0 1 000 001 010 Function EDO DRAM SDRAM 256Kx16/32 DRAM 1Mx16 DRAM RGB Out, TV encoder is off Composite Video S-Video + Composite Video Reserved PAL-M PAL-B, D, G, H, N NTSC OFF ON OFF ON OFF ON External VREF Internal VREF 8-bit Mode 16-bit Mode From External MCLK Pin From Internal PLL PM Test (5Kx22 bits) DM Test (1Kx16 bits) Reserved - 22 PWON_14-12 PWON_11 PWON_10 PWON_9 PWON_8 PWON_7 PWON_6 PWON_5-4 PWON_3-2 PWON_1 Control Reg. PWON_0
W9961CF
011 100 101 110 111 MD[15] Digital Video Output Mode 0 1
Palette RAM Test (256x18 bits) DTO ROM Test (256x16 bits) DAC Test Reserved Normal Operation 8-bit YCbCr 8-bit RGB PWON_15
Note 1. PM, DM, palette RAM, and DTO ROM are tested through a 13-bit address bus, 22-bit data bus, and read/write signals depicted in the following: Test Mode PM (5Kx22) DM (1Kx16) Palette RAM (256x18) DTO ROM (256x16) Address SA[12:0] SA[9:0] SA[7:0] SA[7:0] Data P[7:0], DEM, GPIO[4:0], SD[7:0] P[1:0], DEM, GPIO[4:0], SD[7:0] P[3:0], DEM, GPIO[4:0], SD[7:0] P[1:0], DEM, GPIO[4:0], SD[7:0] Read SRD# SRD# SRD# SRD# Write SWR# SWR# SWR#
Note 2. For DAC test, the external SA[8:0] pins are copied and sent directly to the inputs of CP2/C/B, CP1/Y/G, and CP0/R DACs to control the DAC output. SA[8:0] VOCLK 9-bit input data for DAC test 2x clock for DAC output
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W9961CF
5
SYSTEM DIAGRAM
Video Memory 1/2/4 MBytes SDRAM or EDO DRAM
Digital Camera
YCbCr 4:2:2
W9961CF
H.263/H.261
LCD (Composite or 8-bit RGB) TV (Composite or/and S-Video) Monitor (RGB)
Keypad, Control Buttons Handset Speaker Microphone
GPIOs/ISA-like Bus
Audio Codec
W90220CF
H.223/H.245 G.723.1
Telephone Line
Modem
V.34/V.80
System Boot ROM
System Memory 4 MBytes EDO DRAM
Figure 5.1 W9961CF-Based Stand-alone Videophone System Diagram
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W9961CF
Figure 5.1 shows an example system diagram for an H.324-compliant stand-alone videophone. For live video input, a digital camera, or an NTSC/PAL camera connected to a TV decoder, is fed into the W9961CF in YCbCr 4:2:2 format through 16- or 8-bit data bus. The input video is cropped and scaled to sub-QCIF, QCIF, or CIF format as the local view video. The W9961CF compresses the local view video according to H.263 for H.324 (or H.261 for H.320) and the resultant compressed video stream is transferred and multiplexed with compressed audio stream by the W90220CF. Then the W90220CF performs multiplex/control according to H.223/H.245 for H.324 (or H.221/H.242/H.230 for H.320) and transmits the bit stream to the PSTN through V.34/V.80 modem for H.324 (or ISDN network for H.320). For the receipt of combined video/audio from the remote end, the H.324-compliant (or H.320compliant) bit stream enters the system through a V.34/V.80 modem for H.324 (or ISDN circuit for H.320), where the W90220CF performs demultiplex/control and separates the stream into two compressed streams. The W9961CF decompresses the video stream according to H.263 for H.324 (or H.261 for H.320) and produces the remote view video. The decompressed remote view video and/or the local view video can be overlaid with graphical background or on-screen-display (OSD) and output to LCD (in NTSC/PAL composite video or RGB format), TV (in NTSC/PAL composite video or S-Video format), or monitor (in RGB format). The W9961CF can also performs post deblocking filtering to reduce artifacts caused by compression/decompression for the remote view video, and the local view video can be mirrored or unmirrored. For audio processing, the near-end audio is compressed and the remote-end audio stream is decompressed by the W90220CF according to G.723.1 for H.324 (or G.711/G.722/G.728 for H.320). The W90220CF also performs Acoustical Echo Cancellation (AEC) between the speaker and microphone to prevent howling. A/D conversion for microphone or handset transmitter input, and D/A conversion to drive the speaker and/or handset receiver are performed by the Audio Codec.
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W9961CF
6
BLOCK DIAGRAM
Video Memory
W9961CF
DRAM Controller/DMA Controller Video In
YCbCr 4:2:2
VPRE Processor ISA-like Interface and GPIOs RISC Microprocessor
VPOST Processor
Audio, Keypad, Buttons
LCD TV Monitor
Video Codec
INTC
Timer
MCLK
PLL
Host Interface Controller
Host CPU
Figure 6.1 W9961CF Block Diagram The block diagram for the W9961CF is shown in Figure 6.1. Please refer to next chapter for detailed functional description.
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W9961CF
7
FUNCTIONAL DESCRIPTION
7.1 VPRE Processor
Video Memory HS, VS Cropping
Y[7:0], UV[7:0] VICLK
FT
Downscaling
Capture FIFO
YCbCr 4:2:2 Local View for Display
VPRE-in FIFO
Upscaling
Pre-filter
VPRE-out FIFO
Local View for Encoding
YCbCr 4:2:0
Figure 7.1 VPRE Processor Block Diagram The VPRE processor generates two video streams from the input video: the local view video for display and the local view video for encoding. The input video is cropped, down-scaled, and stored into the video memory as the local view video for display that is real-time at 30 fps. Built-in cropping window control and arbitrary down-scaling in both the horizontal and vertical directions can serve as the digital pan and zoom over a user-specified region for camera control. The local view video for encoding is generated from the local view video for display through the prefilter and/or up-scaling. Up-scaling is needed to vertically up-scale a 240-line video to a 288-line video when encoding in CIF format by using an NTSC camera. Pre-filter is an adaptive 3x3 low-pass filter which can detect noise induced from the video input device and remove it. Since H.263/H.261 uses motion estimation and DCT for compression, the coding efficiency can be improved significantly by using the pre-filtered video whose most noise is removed.
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W9961CF
7.2 Video Codec
Video Memory
0
DCT ENGINE Video Memory
Local View for Encoding
Mux
1
DCT
Q
ZZ
VLE
Encoding Bitstream Buffer
IQ
0: INTRA 1: INTER
IZZ
VLD
Decoding Bitstream Buffer
IDCT Video Memory
0
0
Mux
1
Current Reconstructed Picture
DBF MC (Motion Compensation)
Previous Reconstructed Picture
ME (Motion Estimation)
Figure 7.2 Video Codec Block Diagram 7.2.1 Video Coding The coding mode in which temporal prediction is applied is called INTER; the coding mode is called INTRA if no temporal prediction is applied. The W9961CF supports both INTRA and INTER coding modes. The INTRA coding mode can be signaled at the picture level (INTRA for I-pictures or INTER for P-pictures) or at the macroblock level in P-pictures.
7.2.1.1 I-pictures INTRA Coding
I-pictures require no motion estimation or compensation. Each macroblock is DCT transformed at first. DCT coefficients are quantized (Q), zig-zag scanned (ZZ), variable-length encoder (VLE) coded, and stored into the video memory. Within each macroblock, processing is performed on 8x8 blocks. - 28 -
W9961CF
The quantized blocks are also inverse quantized (IQ) and transformed into the spatial domain by an inverse DCT (IDCT). This operation yields a copy of the encoded picture as it will be seen by the decoder. That copy is then stored into the video memory and will be used for future predictive coding. Since the VLE operation is lossless, there is no need to include the VLE unit in the feedback path.
7.2.1.2 P-pictures INTER Coding
P-pictures macroblocks may be coded by INTRA or INTER coding mode. For each macroblock in the current P-picture, the motion estimation is performed on the luminance (Y) macroblock. A full search or fast search is made with integer pixel displacement in the Y component at first. The comparisons are made between the incoming macroblock and the displaced macroblock in the previous reconstructed picture. The encoder makes a decision on whether to use INTRA or INTER prediction in the coding after the integer pixel motion estimation. If INTRA mode is chosen, no further operation is necessary for the motion search. We will describe P-picture INTRA coding in the following section 7.2.1.3. If INTER mode is chosen the motion search continues with half-pixel search around the integer pixel motion vector, MV0, position. After the half-pixel search, the best match motion vector is coded using a variable-length encoder (VLE), and stored into the video memory. Motion vector is included for all INTER macroblocks and consists of horizontal and vertical components, both measured in half pixel units. P-pictures INTER coding does not code the picture macroblocks directly. Instead it codes the prediction errors. For each INTER coding macroblock in the current picture, the best match macroblock in the previous reconstructed picture is loaded into the MC and half-pixel motion compensation is performed according to the motion vector. After half-pixel motion compensation, the two macroblocks are subtracted to produce prediction errors (their difference) which will be DCT transformed. DCT coefficients are quantized, zig-zag scanned, coded using a variable-length encoder, and stored into the video memory. The quantized blocks are also inverse quantized and transformed into the spatial domain by an inverse DCT. The IDCT results and the previous reconstructed blocks are added and stored into the video memory as the current reconstructed picture for future predictive coding.
7.2.1.3 P-pictures INTRA Coding
If INTRA mode is chosen for current P-pictures macroblock, no further half-pixel motion search is performed and no motion vector is coded. Each INTRA macroblock is coded as that for I-pictures INTRA coding. 7.2.2 Video Decoding Video decoding operation is very similar to the feedback loop of the video coding. After optional error correction, the compressed bit stream is processed by the variable length decoder (VLD). The decoded data are parsed, inverse zig-zag scanned (IZZ), and then processed by an inverse quantizer and an inverse DCT. Depending on the transmission mode (INTRA or INTER), macroblocks from the previous reconstructed picture may also be added to the current data to form the reconstructed picture. For each INTRA-coded macroblock of I-pictures or P-pictures, no motion compensation is performed. The IDCT results are stored into the video memory as reconstructed picture. - 29 -
W9961CF
For each INTER-coded macroblock of P-pictures, the macroblock pointed to by the motion vector in the previous reconstructed picture is loaded into the MC and half-pixel motion compensation is performed according to the motion vector. The half-pixel motion compensated results and the IDCT results are added and then stored into the video memory as reconstructed picture.
7.3 VPOST Processor
Video Memory DAC VP Overlay Display FIFO GP TV Encoder Adjustment MUX CP0/R
DAC
CP1/Y/G
CSC
YUV to RGB
DAC
CP2/C/B P[7:0]
Postfilter
Display Controller
PCLK DEM HSYNC VSYNC
Figure 7.3 VPOST Processor Block Diagram The VPOST processor performs three main functions: video post-processing, display control, and video output control. 7.3.1 Video Post-processing Video post-processing includes post-filter and video processor (VP). The post-filter is performed on the luminance component and is used to reduce blocking artifacts and mosquito noise, and also for edge enhancement of the decoded remote view video. A 5x3 block classified filer (BCF) is implemented to calculate local mean and local variance of the processed pixel at first. Depending on the local mean and local variance the processed pixel is classified as low-variance, middle-variance, or high-variance pixel. For low-variance pixels, a low-pass filter is applied to remove the blocking artifacts. For middle-variance pixels, the local mean is used in stead to remove the mosquito noise. Edge enhancement is performed for the high-variance pixels. Video processor is used to up-scale or down-scale the video for display. Both local view and remote view video can be arbitrarily up-scaled up to full-screen size, or down-scaled to 1/2 of its original size, horizontally and/or vertically. Either the local view video or remote view video can be up-scaled by using two-dimensional bilinear interpolation for better video quality. 1/2 down-scaling can be used in - 30 -
W9961CF
picture-in-picture display where the local view video may be in CIF format for encoding and in QCIF format for display. 7.3.2 Display Control Display Control includes display controller, graphics processor (GP), and overlay function. The display controller generates horizontal and vertical timings for display. The graphics processor accesses the background data and on-screen-display data from the video memory, and converts it to YCbCr format for overlaying with the video data. The graphics data can be in 16-color, 256-color, or 565 high-color format, where a built-in color look-up-table (LUT) is used to transform the pseudo color data (16- and 256-color modes) to true color data. An advanced twodimensional 3-line flicker-free filter is also incorporated to eliminate the annoying artifacts induced by graphics lines on interlaced TV. The flicker-free filter takes effect on the original RGB data. Background and on-screen-display graphics data, after processed by the graphics processor, are overlaid with the video data by using window key and color key. For example, a typical three-window display is shown in Figure 7.4.
Remote View Video
Defined by window key 1
Background
Defined by window key 2
On-screen Display
Local View Video
Figure 7.4 Typical Three-window Display for Video Conferencing Applications 7.3.3 Video Output Control The VPOST incorporates a TV encoder, color space conversion (CSC), and three 9-bit DACs for direct interface with TV, LCD, and CRT monitor. Before the TV encoder block, an adjustment block is used for adjusting hue, saturation, contrast, and brightness.
7.3.3.1 Hue, Saturation, Contrast, and Brightness Adjustments
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W9961CF
Figure 7.5 illustrates a typical circuit for enabling adjustment of contrast and brightness for Y component, and hue and saturation for CbCr components. The brightness is adjusted after the contrast adjustment to avoid introducing a varying DC offset due to adjusting the contrast. Hue adjustment is implemented by mixing the Cb and Cr data: Cb = Cb cos + Cr sin Cr = Cr cos - Cb sin where is the desired hue angle. An 11-bit hue adjustment value is used to allow adjustments from 0 to 360, in increments of 0.176.
16 Contrast Value Brightness Value 16
+ Y
Y'
Hue Value
128
SIN -
COS
Saturation Value
128
+ Cr
+ Cr' Cb + -
Cb'
Figure 7.5 Hue, Saturation, Contrast, and Brightness Controls
7.3.3.2 Video Output Interface
The built-in TV encoder supports worldwide video standards, including NTSC, PAL-B, D, G, H, N, and PAL-M. The W9961CF supports two digital video output modes (8-bit YCbCr and 8-bit RGB) and three analog video output modes (RGB, Composite, and S-Video + Composite) as shown in Table 7.1. Up to one digital video and one analog video can be output simultaneously. Table 7.2 shows pinout definitions of the video output interface. Table 7.1 W9961CF Video Output Modes PWON_15 0 0 0 PWON_3-2 0X 10 11 Digital Video Output Mode 8-bit YCbCr 8-bit YCbCr 8-bit YCbCr Analog Video Output Mode RGB Composite S-Video + Composite
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W9961CF
1 1 1 0X 10 11 8-bit RGB 8-bit RGB 8-bit RGB RGB Composite S-Video + Composite
- 33 -
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Table 7.2 W9961CF Video Output Interface Pin Assignment PWON_15, 3-2 Pin 171 Pin 170 Pin 168 Pin 167 Pin 157 Pin 154 Pin 153 Pin 152 Pin 151 Pin 156 Pin 155 Pin 128 Pin 160 Pin 159 Pin 158 R G B CP0 CP1 CP2 CP0 Y C 00X PCLK YCbCr7 YCbCr6 YCbCr5 YCbCr4 YCbCr3 YCbCr2 YCbCr1 YCbCr0 VSYNC HSYNC 010 PCLK YCbCr7 YCbCr6 YCbCr5 YCbCr4 YCbCr3 YCbCr2 YCbCr1 YCbCr0 VSYNC HSYNC 011 PCLK YCbCr7 YCbCr6 YCbCr5 YCbCr4 YCbCr3 YCbCr2 YCbCr1 YCbCr0 VSYNC HSYNC 10X PCLK RGB7 RGB6 RGB5 RGB4 RGB3 RGB2 RGB1 RGB0 VSYNC HSYNC DEM R G B 110 PCLK RGB7 RGB6 RGB5 RGB4 RGB3 RGB2 RGB1 RGB0 VSYNC HSYNC DEM CP0 CP1 CP2 111 PCLK RGB7 RGB6 RGB5 RGB4 RGB3 RGB2 RGB1 RGB0 VSYNC HSYNC DEM CP0 Y C
Note 1. Analog video output signals (CP0/R, CP1/Y/G, and CP2/C/B) can be disabled by resetting PWON_8-6 to 000. Note 2. Digital video output signals (PCLK, VSYNC, HSYNC, DEM, and P[7:0]) can be disabled by resetting VPOSTCR_1 to 0 to tri-state these signals. Note 3. P[7:0] and DEM are re-defined for internal memory test and will not be tri-stated by VPOSTCR_1 when the chip is in test mode (PWON_14-12 111). Note 4. PCLK is derived from VOCLK as shown below:
f f
PCLK
= =
f
VOCLK
, if in 8 - bit YCbCr mode (PWON_15 = 0)
PCLK
DISCR _15 - 8 x 256
f
VOCLK / 2
, if in 8 - bit RGB mode (PWON_15 = 1)
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W9961CF
7.4 RISC Microprocessor
INTCTL
PCCTL
ALU
DM
1Kx16
Video Memory Instruction Decoder Execution ARB RISC Interface GR
32x16
PM
5Kx22
Engines Host Interface Controller
WB
Figure 7.6 RISC Microprocessor Block Diagram The RISC microprocessor provides the following: * four-stage instruction pipeline * 16-bit integer arithmetic logic unit (ALU) * 5Kx22 bits program memory (PM) * 1Kx16 bits data memory (DM) * 32x16 bits three-port (2-read/1-write) register file Figure 7.6 is the block diagram of the RISC microprocessor. 7.4.1 RISC Pipeline Stages The RISC has a four-stage instruction pipeline; each stage takes one MCLK cycle. The four pipeline stages are: * IF - Instruction Fetch * DEC - Instruction Decoding * EXE - Instruction Execution * WB - Write Back
- 35 -
W9961CF
Once the pipeline has been filled, four instructions are executed simultaneously. The execution of each instruction takes at least four MCLK cycles. An instruction can take longer, for example, if the required data is not in the DM, register file, or engine registers, the data must be retrieved from the video memory. 7.4.2 Address Spaces The internal RISC provides two address spaces: * Program Memory (PM) Address Space * Data Memory (DM) Address Space
7.4.2.1 Program Memory Address Space
The PM address is 13 bits wide, and data is 22 bits wide. The built-in PM size is 5Kx22 bits. Figure 7.7 shows the PM address space. The RISC always starts from PM address 0000H after it is enabled.
7.4.2.2 Data Memory Address Space
The DM address space is used for RISC access to engine registers, internal DM, and external DRAM. All engine registers and internal DM can be accessed by the RISC by using the DM address space. All DRAM data (maximum 4 Mbytes), except the lower 1.5K words, can be accessed by the RISC. The lower 1.5K words DRAM data can not be accessed by the RISC because that the lower 1.5K DM address space is used for engine registers and internal DM accesses. Figure 7.8 shows the DM address space. The DM address is 21 bits wide, and data is 16 bits wide. Table 7.3 shows the 21-bit DM address, which is composed of a 5-bit segment register (DMSA) and a 16-bit address indicated by the load or store instruction. The 5-bit segment register is a write-only register which can be programmed through the SEGS imm5 instruction.
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W9961CF
0000H 0020H
Booting Main Program
0000H 0001H
Interrupt Vector Address Space
13FFH 22 bits 001FH
Figure 7.7 Program Memory Address Space
000000H 0001FFH 000200H 0005FFH 000600H
Engine Registers
Internal DM
External DRAM
1FFFFFH 16 bits
Figure 7.8 Data Memory Address Space Table 7.3 Data Memory Address Mapping
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W9961CF
20 16 DMSA[4:0] 7.4.3 RISC Registers The internal RISC provides the following registers: * 32 16-bit general purpose registers * 2 registers that hold the results of integer multiply and add (MULA) and divide (DIV) operations * 4 shadow registers that store current status at IF stage (PC0), DEC stage (IR0_L and IR0_H), and EXE stage (MPZ0) during a CALL procedure or an interrupt service. 15 16-bit DM address indicated by the load or store instruction 0
7.4.3.1 General Registers
The 32 general purpose registers provide general resources for all computation. Figure 7.9 shows the 32 general registers (R0 ~ R31). R0 has assigned functions: when R0 is used as a source operand, it provides zero value, when R0 is used as the destination register, the result is discarded.
15 R0 R1 R2 . . . R0 R30 R31 0
Figure 7.9 RISC General Registers
7.4.3.2 Shadow Registers
There are four shadow registers, PC0, IR0_L, IR0_H, and MPZ0, which store current status at pipeline stages to eliminate the state save and restore time in a CALL subroutine or an interrupt service. The behavior of the shadow registers is described below. Before entering CALL subroutine or interrupt service: current status at IF/DEC/EXE pipeline stages are stored into shadow registers in one cycle. When executing RET instruction: contents of shadow registers are restored at IF/DEC/EXE pipeline stages
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W9961CF
Depth of the shadow registers is two, which enables a nested interrupt in a CALL subroutine. 7.4.4 RISC Interrupt Handling There are 31 interrupt vectors stored on top of the PM, each points to the entry of an interrupt service routine. The first 15 interrupt vectors (0001H~00FH) are used for engine interrupts. The last 16 interrupt vectors (0010H~001FH) are used for DMA TC interrupts. These interrupt vectors are shown in Table 7.4. Table 7.4 RISC Interrupt Vectors Vector 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH Description Main program starting address ME ME complete interrupt MC MC complete interrupt DCT/IDCT (D) IDCT complete interrupt DCT/IDCT (E) DCT complete interrupt VPRE Video capture complete interrupt VPRE Pre-filter complete interrupt VLE VLE FIFO full interrupt TIMER TIMER DTR interrupt TIMER TIMER ETR interrupt TIMER TIMER TR interrupt VPOST Post-filter complete interrupt DBF Deblocking filter complete interrupt VLPIO VLD complete interrupt VLPIO BCH frame un-lock, Encode Output FIFO full, Encode Input FIFO empty, or Decode Input FIFO empty interrupt (Note 1) 000FH VLPIO VLD run-level block error interrupt 0010H MC DMA TC interrupt for MC input 0011H ME DMA TC interrupt for Search Window 0012H ME DMA TC interrupt for Current Macro Block 0013H MC DMA TC interrupt for MC output 0014H DCT/IDCT DMA TC interrupt for DCT input 0015H DCT/IDCT DMA TC interrupt for IDCT output of Decoding 0016H DCT/IDCT DMA TC interrupt for IDCT output of Encoding 0017H VLPIO DMA TC interrupt for Encoding bitstream 0018H VLPIO DMA TC interrupt for Decoding bitstream 0019H VLPIO DMA TC interrupt for bitstream from PCI FIFO 001AH DBF DMA TC interrupt for deblocking filter data in/out 001BH ME DMA TC interrupt for Predicted Macro Block 001AH ~ 001FH Reserved Note 1. Controlled by bits 11-8 of the PIO Control register (PIOCR). When an interrupt occurs, program counter jumps to the interrupt service routine pointed by the corresponding interrupt vector. RISC also disables the other interrupt inputs and stores current program counter, instruction, and execution status at IF, DEC, and EXE stages into the shadow registers. Engine
- 39 -
W9961CF
In the interrupt service routine, the Interrupt Vector register (IVEC) or FDMA TC Status register (TCSR) must be read at first to acknowledge the interrupt. At the end of the service routine, an EI instruction must be used to re-enable interrupt, then a RET instruction, which restores RISC pipeline with the shadow registers, is used to return to the main program.
- 40 -
W9961CF
7.5 INTC (Interrupt Controller)
IREQ[15:0] AND IMSK Interrupt Queue
ACK[15:0]
RISCINT INTVEC[3:0]
Mux Trigger
TRIG[15:0] MODE
TRIG_ACK[15:0]
Figure 7.10 INTC Block Diagram The interrupt controller provides 16 interrupt channels that are used for engine interrupts to the RISC. It supports two interrupt modes: interrupt and trigger modes. In interrupt mode, the INTC responds with acknowledgment signal when an interrupt is generated via IREQ[15:0] by the engine, timer, or external interrupt from ISA-like bus. In trigger mode, the RISC first triggers a specific engine to operate via TRIG_ACK[15:0] by programming the Software Trigger register (STG). Once the engine completes operation, it interrupts the RISC via IREQ[15:0]. Each channel can operate with only one specific mode as shown in Table 7.5. The W9961CF can operate correctly only when the Trigger Mode register (TMOD) is programmed with a 181FH or 185FH value. Table 7.5 Interrupt Channels Channel 0 1 2 3 4 5 6 7 8 9 A B C D E Engine ME MC DCT/IDCT DCT/IDCT VPRE VPRE VLETCO TIMER TIMER TIMER VPOST DBF VLPIO VLPIO Mode TRIG TRIG TRIG TRIG INTR TRIG/INTR INTR INTR INTR INTR TRIG TRIG INTR INTR Description Reserved Trigger MB Motion Estimation Trigger current block Motion Compensation Trigger current block IDCT Trigger current block DCT Video capture complete interrupt Trigger pre-filter, or pre-filter complete interrupt (Note 1) VLE FIFO full interrupt TIMER DTR interrupt TIMER ETR interrupt TIMER TR interrupt Trigger post-filter Trigger deblocking filter VLD complete interrupt BCH frame un-lock, Encode Output FIFO full, Encode Input FIFO empty, or Decode Input FIFO empty interrupt (Note 2)
- 41 -
W9961CF
F VLPIO INTR VLD run-level block error interrupt Note 1. Pre-filter can be triggered automatically by the hardware (VCCR_7 = 0, channel 6 must be in INTR mode) or by the software (VCCR_7 = 1, channel 6 must be in TRIG mode). Note 2. Controlled by bits 11-8 of the PIO Control register (PIOCR). All interrupt channels are maskable by the corresponding bits of the Interrupt Mask register (IMSK). A 16-level interrupt queue is used to buffer interrupt from each channel. An interrupt to the RISC will be generated with corresponding interrupt vector when the queue is not empty and the RISC is not executing any interrupt service routine. In the interrupt service routine, the RISC must read the Interrupt Vector register (IVEC) at first to acknowledge the INTC. Once acknowledged, current interrupt status of the INTC will be cleared and next interrupt request queued in the interrupt queue will be processed when the service routine is completed.
- 42 -
W9961CF
7.6 Timer
ETR
8-bit Counter
VOCLK
Pre-scaler
1/2(N+1)
TR Counter
16-bit
ETER Comparator
TP
ETR interrupt DTR
8-bit Counter
Comparator DTER TR interrupt Comparator DTR interrupt
Figure 7.11 Timer Block Diagram The timer provides a 16-bit TR counter for the picture clock frequency (PCF), an 8-bit ETR counter for the encoding temporal reference, and an 8-bit DTR counter for the decoding temporal reference. A stable VOCLK with 27.0 Mhz clock frequency is used as clock input for the timer. The picture clock frequency is generated according to the following equation:
PCF =
(2
( N +1)
* (TP + 1)
)
For example, a picture clock frequency of 30000/1001 (approximately 29.97) pictures per second can be achieved by programming N = 04H and TP = 6DF8H, and a picture clock frequency of 25 pictures per second can be achieved by programming N = 04H and TP = 83D5H.
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W9961CF
7.7 FDMA Controller
DREQ[11:0]
Mask
Queue
S/W DMA
DACK_[11:0] ACK Temp ENG Video Memory
State Machine Write Data Read Data
Figure 7.12 FDMA Controller Block Diagram The FDMA controller supports 12 channels that are used for direct memory access between video memory and hardware engines. The RISC first sets up the FDMA registers, which contain picture start, engine start, picture size, and transfer size. A 16-level request queue is used to buffer request from each FDMA channel. Once the DMA transfer is complete, the controller interrupts the RISC. In addition to accept requests from hardware engines, the FDMA also responds to request that are initiated by software. Software may initiate a DMA service request by programming a channel value into the Software FDMA register. Software FDMA has the highest priority and will be serviced immediately when the FDMA engine is ready. FDMA channels are listed in Table 7.6. Table 7.6 FDMA Channels Channel Engine Addressing Mode R/W 0 MC W 1 ME W 2 ME W 3 MC R 4 DCT/IDCT W 5 DCT/IDCT R 6 DCT/IDCT R 7 PIO Linear Demand W 8 PIO Linear Demand W 9 PIO Linear Demand R/W A DBF R/W B ME R Note 1. R: engines to video memory; W: video memory to engines. Description Block In for MC Block In for Search Window of ME Block In for Current Macro Block Block Out for By-Pass Filter Block In for DCT Block Out for Decoder Re-Construct Block Out for Encoder Re-Construct BCH Encoder Bitstream In Decoder Bitstream In Encoder Bitstream In/Out, BCH Out Deblocking Filter Data In/Out Block Out for Predicted Macro Block
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W9961CF
7.7.1 FDMA Transfer Modes The FDMA supports two transfer modes: Block and Demand. A 16-level request queue is used to buffer request from each FDMA channel. Each channel has associated with it a mask bit which can be set to disable the incoming DREQ. An unrestricted mode is also supported when the picture start is out of picture boundary, where an edge pixel is used instead. In Block Transfer mode the FDMA is activated by DREQ to continue making transfers during the service until a TC is encountered. The FDMA ignores DREQ of that channel during the service. In Demand Transfer mode the FDMA is activated by DREQ to continue making transfers during the service until a TC is encountered, or until DREQ goes inactive. Thus transfers may continue until the hardware engine has exhausted its data capacity. After the hardware engine has had a chance to catch up, the FDMA service is reestablished by means of a DREQ. During the time between services, the intermediate values of address and word count are stored in the temporary registers. 7.7.2 FDMA Transfer Types Two transfer types are supported: Read and Write. Read transfers move data from a hardware engine to video memory. Write transfers move data from video memory to a hardware engine. 7.7.3 FDMA Programming The FDMA supports two addressing modes: Block and Linear. Normally, Block addressing is used by Block Transfer modes, and Linear addressing is by Demand Transfer modes. Block Transfer Mode with Block Addressing Programming Refer to Figure 7.13. Programming sequence is: 1. FDMA Mode register: LIN = 0, DMD = 0, R/W_ = 0 or 1 2. Transfer Size registers: EW = 3, EH = 3, transfer size = (EW+1) x (EH+1) = 16 3. Picture Size registers: PW = 9, PH = 9 4. Frame Memory Start Address: FMSA = 64, physical memory start address (DWORD) = 64x64/4 = 1024 5. Picture Start registers: PSX = 3, PSY = 2 6. Start to calculate finit = PSY x ( PW+1) + PSX + FMSA = 2 x ( 9+1 ) + 3 + 1024 = 1047 7. Engine Start registers: ESX = 1, ESY = 1 8. Enable DMASK Demand Transfer Mode with Linear Addressing Programming Refer to Figure 7.14. Programming sequence is: 1. FDMA Mode register: LIN = 1, DMD = 1, R/W_ = 0 or 1 9 2. Transfer Size registers: EW = 100, EH = 1, transfer size = EH x 2 + (EW+1) = 613 3. Picture Size registers: PW = 9, PH = 9 4. Frame Memory Start Address: FMSA = 64, physical memory start address (DWORD) = 64x64/4 = 1024 5. Picture Start registers: PSX = 15, PSY = 1 6. Start to calculate finit = PSY x ( PW+1) + PSX + FMSA = 1 x ( 9+1 ) + 15 + 1024 = 1049 - 45 -
W9961CF
7. Engine Start registers: ESX = 0, ESY = 0 8. Enable DMASK
Video Memory
0000 (0,0) (3,2) Finit =1047 1050
Picture
PSY
Engine
ESY
(1,1)
PH 1057 1060 1067 1070 PW 1077 1080 DRAM Address 1047 1048 1049 1050 1057 1058 1059 1060 Picture Engine XY XY 2 2 2 2 3 3 3 3 3 4 5 6 3 4 5 6 1 1 1 1 2 2 2 2 1 2 3 4 1 2 3 4 DRAM Address 1067 1068 1069 1070 1077 1078 1079 1080 PW = 9 PH = 9 PSX = 3 PSY =2 (9,9)
EH+1 EW = 3 EH = 3 ESX = 1 ESY = 1
PSX
ESX EW+1
Picture Engine XY XY 4 4 4 4 5 5 5 5 3 4 5 6 3 4 5 6 3 3 3 3 4 4 4 4 1 2 3 4 1 2 3 4
32 bits
Figure 7.13 Block Transfer Mode with Block Addressing
Video Memory
0000
Engine
Finit =1049
0
1661
612
32 bits
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W9961CF
Figure 7.14 Demand Transfer Mode with Linear Addressing
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W9961CF
7.8 Host Interface Controller
AD[31:0]
Address Data Mux/Demux
PCI Address PCI Data
PCI Control
PCI Slave Control Interrupt Control
PCI Configuration
INTA#
Interrupt Requests
Figure 7.15 Host Interface Controller Block Diagram The W9961CF support a glueless interface for a 32-bit PCI bus. The PCI configuration register space occupies 256 bytes. The W9961CF supports or returns 0 for the first 64 bytes region. Refer to section 8.1 for a detailed description of the PCI configuration space supported by the W9961CF. 7.8.1 PCI Address Spaces The W9961CF provides three addressing spaces starting at the base addresses specified in the PCI Base Address 1, 2, and 3 registers. Address space starting at Base Address 1 is used for PCI accesses of W9961CF control registers, RISC data memory, and RISC program memory. Address space starting at Base Address 2 is used for video memory accesses. Address space starting at Base Address 3 is used for ISA-like bus interface accesses. The W9961CF control registers, DM, PM, and video memory can be DWORD-accessed only, while the ISA-like bus interface can be BYTEaccessed only. 7.8.2 PCI Interrupt Control There are 16 interrupt sources which can generate INTA# to PCI bus. Channels 0 ~ 11 are reserved for RISC asserting interrupt to the host. Channel 12 is used for the external ISA-like bus interrupt. Channel 14 is used for the FDMA TC interrupt. Channel 15 is used for the RISC interrupt. All the 16 interrupt sources can be masked by programming a 1 to the corresponding bit of the XMSK register. When INTA# is asserted by the W9961CF, the host has to read the XSTS register to know which interrupt channel is active. Table 7.7 PCI Interrupt Channels Channel 0 ~ 11 12 13 XINT_IN 1 extint Description Reserved for RISC External ISA-like bus interrupt Not used
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W9961CF
14 15 tc_out int FDMA TC output INTC interrupt
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W9961CF
7.9 DRAM Controller
20-bit address from FDMA, RISC, PCI, VPRE, VPOST
MA Mux
BA, MA[11:0]
32-bit data and 4-bit BEs from FDMA, RISC, PCI, VPRE, VPOST MDI[31:0] DRAM request/cycle from/to FDMA, RISC, PCI, VPRE, VPOST
MD/BE Mux
MD[31:0]
Arbitration & State Machine
MSIG
RAS[1:0]#/CS[1:0]#, CAS[3:0]#/DQM[3:0]#, WE#, OE#/CKE, SRAS#, SCAS#, SMCLK
Figure 7.16 DRAM Controller Block Diagram A 32-bit SDRAM or EDO DRAM interface is supported for W9961CF. The DRAM Controller serves as video memory arbiter and interface controller for video memory access. 7.9.1 Video Memory Arbitration The video memory arbiter helps to maximize performance by orchestrating memory access requests from internal engines. Three priority levels are defined for these requests: * First priority: DRAM refresh request, SDRAM mode register write request * Second priority: video capture request, graphics display request, VA1 request, VA2 request * Third priority: FDMA request, RISC request, PCI request, pre-filter request, post-filter request First priority requests are for DRAM refresh and SDRAM mode control. Second priority requests are for video input and video output, which should be real-time processed. A FIFO status is provided by each request such that the DRAM Controller arbitrates according to these FIFO status to prevent any video data loss. Third priority requests are for video coding/decoding and bitstream transfers. Priorities of them can be either RISC, pre-filter, FDMA, post-filter, then PCI access, or PCI, RISC, pre-filter, FDMA, then postfilter access. - 50 -
W9961CF
7.9.2 DRAM Interface The DRAM controller provides many programmable controls for the DRAM operations which include: * DRAM Type: supports SDRAM and EDO DRAM * DRAM Address: programmable 9-bit (256Kx EDO DRAM), 10-bit (1Mx EDO DRAM or 256Kx SDRAM), and 12-bit (1Mx SDRAM) address * DRAM Timing: adjustable Trp, Trcd, Tras, and Tcas timings * DRAM Refresh: 1 ~ 8 refresh cycles per scan line * SDRAM Read Latency: 1 ~ 3 clocks * SDRAM Burst Type: sequential or interleaved * SDRAM Burst Length: 1, 2, 4, 8, or full page Table 7.8 shows the interface signals for SDRAM and EDO DRAM. Table 7.8 SDRAM and EDO DRAM Interface Signals Pin Name MD[31:0] MA[10:0] BA RAS[1:0]#/CS[1:0]# CAS[3:0]#/DQM[3:0] OE#/CKE WE# SRAS# SCAS# SMCLK 256Kx EDO DRAM MD[31:0] MA[8:0] RAS[1:0]# CAS[3:0]# OE# WE# 1Mx EDO DRAM MD[31:0] MA[9:0] RAS[1:0]# CAS[3:0]# OE# WE# 256Kx SDRAM MD[31:0] MA[8:0] BA CS[1:0]# DQM[3:0] CKE WE# SRAS# SCAS# SMCLK 1Mx SDRAM MD[31:0] MA[10:0] BA CS[1:0]# DQM[3:0] CKE WE# SRAS# SCAS# SMCLK
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W9961CF
7.10 ISA-like Bus Interface and GPIOs
7.10.1 ISA-like Bus Interface The ISA-like Bus provides a 13-bit address bus, an 8-bit data bus, one write strobe signal, one read strobe signal, and one interrupt input as interface with an external co-processor. It can be accessed directly by the host through PCI bus, or indirectly by the host or RISC via the ISA-like Bus Control registers as described in Table 7.9. The external interrupt input can be either level-triggered (ISAINT_2 = 1) or falling edge-triggered (ISAINT_2 = 0). Table 7.9 ISA-like Bus Access Modes Mode PCI Direct Access Address Space BA3 000000H ~ 00003FH Description 64-byte address space, byte-access only. ISA-like Bus signals are automatically generated when a PCI I/O read or write command to this address space is issued. 8K-byte address space. ISA-like Bus signals are generated via the ISA-like Bus Control registers. 8K-byte address space. ISA-like Bus signals are generated via the ISA-like Bus Control registers.
PCI Indirect Access
BA1 0040H ~ 004CH
RISC Indirect Access
RISC DM 000010H ~ 000013H
7.10.2 GPIO The W9961CF provides 5 general purpose I/O ports. Each GPIO can be configured as an input or output port, depending on the corresponding bit of the GPIO Output Enable register (GPIOOE).
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W9961CF
7.11 PLL (Phase Locked Loop)
fREF
1 (M+1)
PHASE DETECT
CHARGE PUMP LOOP FILTER
VCO
1 2K
fOUT
1 (N2+1)
1 2N1
Figure 7.17 PLL Block Diagram The built-in PLL frequency synthesizer is used to generate the internal MCLK clock. A stable reference frequency is required by dividing VOCLK by 2 (VOCLK/2 with typical 13.5 Mhz frequency) as the reference clock input for the PLL. The output frequency resulting from a given set of parameters is specified by the following formula:
f OUT =
2 N 1 x ( N 2 + 1) x f REF ( M + 1) x 2 K
where M is a 6-bit value that can be programmed with any integer value from 1 to 63, N1 is a 2-bit value that can be programmed with any integer value from 0 to 3, N2 is a 6-bit value that can be programmed with any integer value from 1 to 127, and K is a 2-bit value that can be programmed with any integer value from 0 to 3.
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W9961CF
8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Table 8.1 Absolute Maximum Ratings Ambient temperature Storage temperature DC supply voltage I/O pin voltage with respect to VSS 0 C to 70 C -40 C to 125 C -0.5V to 7V -0.5V to VDD + 0.5V
8.2 DC Characteristics
8.2.1 DAC DC Characteristics Table 8.2 DAC DC Characteristics Parameter Power Supply AVDD, TVAVDD DAC Coding TVDAC Resolution Integral Linearity Error Differential Linearity Error Gray Scale Error LSB Size DAC-to-DAC Matching Output Compliance Gray Scale Current Range Output Impedance Output Capacitance (f = 1 MHz; IOUT = 0 mA) Monotonicity Internal VREF Power Supply Reject Ratio (f = 1 KHz) Note 1. Measured with VREF = 1.06 V, RSET = 100 . 1.06 0.5 10K 30 -1.0 69.1 2 5 1.5 35 9 9 9 1 1 5 Min. 3.0 Typ. 3.3 Max. 3.6 Unit V Binary Bits LSB LSB %Gray A % V mA pF Guaranteed V %%AVDD
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W9961CF
Level White Yellow Cyan Green Magenta Red Blue Black Blank
mA 26.68
V 1.000
IRE 100.0000 89.4550 72.3425 61.7972 45.7025 35.1575 18.0450
DAC Data 400 370 321 291 245 215 166 136 114 Black Level Blank Level White Level
9.07 7.60
0.340 0.285
7.5000 0.0000
Sync
0.00
0.000
-40.0000
0
Sync Level
Note: Nominal RSET, 75 doubly-terminated load, with setup on. SMPTE 170M levels are assumed. 100% saturation color bars (100/7.5/100/7.5).
Figure 8.1 525-line (NTSC/PAL-M) Y (Luminance) Output Waveform
Level White Yellow Cyan Green Magenta Red Blue Black Blank
mA 26.68
V 1.000
IRE 100.0000
DAC Data 400 368 316 284 236 204 152 White Level
8.00 8.00
0.300 0.300
0.0000 0.0000
120 120
Black Level Blank Level
Sync
0.00
0.000
-43.0000
0
Sync Level
Note: Nominal RSET, 75 doubly-terminated load, with setup off. CCIR 624 levels are assumed. 100% saturation color bars (100/0/100/0).
Figure 8.2 625-line (PAL-B, D, G, H, N) Y (Luminance) Output Waveform
- 55 -
W9961CF
Magenta
Yellow
Green
White
Color
mA
V 1.058
IRE 58.5000 54.6000 41.4000
DAC Data 423
Cyan/Red 28.21 Green/Magenta Yellow/Blue Burst High Blank Burst Low Yellow/Blue Green/Magenta Cyan/Red 5.93 20.88 17.07 13.27
0.783 0.640 0.498
20.0000 0.0000 -20.0000 -41.4000 -54.6000
313 256 199 Color Burst (9 Cycles) 89 Blank Level
0.222
-58.5000
Note: Nominal RSET, 75 doubly-terminated load, with setup on. SMPTE 170M levels are assumed. 100% saturation color bars (100/7.5/100/7.5).
Figure 8.3 525-line (NTSC/PAL-M) C (Chrominance) Output Waveform
Magenta
Yellow
Green
White
Color
mA
V 1.083
IRE 63.2500 59.0500 44.7500 21.5000 0.0000 -21.5000 -44.7500 -59.0500 -63.2500
DAC Data 433
Cyan/Red 28.88 Green/Magenta Yellow/Blue Burst High Blank Burst Low Yellow/Blue Green/Magenta Cyan/Red 5.27 21.08 17.07 13.07
0.791 0.640 0.490
316 256 196 Color Burst (10 Cycles) 79
0.198
Note: Nominal RSET, 75 doubly-terminated load, with setup off. CCIR 624 levels are assumed. 100% saturation color bars (100/0/100/0).
Figure 8.4 625-line (PAL-B, D, G, H, N) C (Chrominance) Output Waveform
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Black Blank Level
Cyan
Blue
Red
Black
Cyan
Blue
Red
W9961CF
Magenta Red
Yellow
Cyan Green
White
Level
mA
V 1.221 1.000
IRE 130.8333 100.0000
DAC Data 488 400
Peak Chroma 32.55 (High) White 26.68
Black White Level Black Level Blank Level Sync Level Black White Level Black Level Blank Level Sync Level
Burst High Black Blank Burst Low Peak Chroma (Low) Sync
11.41 9.07 7.60 3.80 3.20 0.00
0.423 0.340 0.285 0.143 0.120 0.000
20.0000 7.5000 0.0000 -20.0000 -23.3333 -40.0000
171 136 114 57 48 0 Color Burst (9 Cycles)
Note: Nominal RSET, 75 doubly-terminated load, with setup on. SMPTE 170M levels are assumed. 100% saturation color bars (100/7.5/100/7.5).
Figure 8.5 525-line (NTSC/PAL-M) Composite Video Output Waveform
Magenta Red Yellow Cyan Green
White
Level
mA
V 1.233 1.000
IRE 133.3333 100.0000
DAC Data 493 400
Peak Chroma 32.88 (High) White 26.68
Burst High Black Blank Burst Low Peak Chroma (Low) Sync
12.01 8.00 8.00 4.00 1.80 0.00
0.450 0.300 0.300 0.150 0.068 0.000
21.5000 0.0000 0.0000 -21.5000 -33.3333 -43.0000
180 120 120 60 27 0 Color Burst (10 Cycles)
Note: Nominal RSET, 75 doubly-terminated load, with setup off. CCIR 624 levels are assumed. 100% saturation color bars (100/0/100/0).
Figure 8.6 625-line (PAL-B, D, G, H, N) Composite Video Output Waveform
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Blue
Blue
W9961CF
8.2.2 Digital DC Characteristics Table 8.3 Digital DC Characteristics Symbol Parameter VDD5V VDD VIL VIH VOL VOH IIL IIH IUP CIO IDD 5V Power Supply 3V Power Supply Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Pull-up Current Pin Capacitance Active Current FMCLK = 70 MHz VIN = 0.4V VIN = 2.4V VIN = 0V -133.2 2.4 +70 -70 -400.6 10 500 Conditions Min. 5.25 3.0 -0.5 2.0 VSS+0.4 Max. 5.75 3.6 0.8 Unit V V V V V V A A A pF mA
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W9961CF
8.3 AC Characteristics
8.3.1 DAC AC Characteristics Table 8.4 DAC AC Characteristics Parameter Luminance Bandwidth Chrominance Bandwidth Hue Accuracy Color Saturation Accuracy DAC Output Delay DAC Output Rise/Fall Time DAC Output Settling Time Input Clock Frequency (Fin) Table 8.5 TV Modes Resolution and Clock Rate Mode NTSC PAL-M PAL-B, D, G, H, N Active Pixels 720x485 720x484 720x576 Total Pixels 858x525 858x525 864x625 TV Clock 13.5000 MHz 13.5000 MHz 13.5000 MHz 12.27 3 8 13.5 14.75 Min. Typ. Fin/2 1.3 1.5 1.5 3 3 30 Max. Unit MHz MHz % ns ns ns MHz
8.3.2 PLL AC Characteristics Table 8.6 PLL AC Characteristics Parameter Input Clock Frequency Input Clock Duty Cycle MCLK Clock Frequency MCLK Clock Frequency Error MCLK Clock Duty Cycle 40 50 40 Min. Typ. 13.5 50 70 0.5 60 60 Max. Unit MHz % MHz % %
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W9961CF
8.3.3 RESET Timing AC Characteristics
RST#
TRST TSU TH
MD[15:0]
Figure 8.7 RESET Timing Table 8.7 RESET Timing Symbol Parameter TRST TSU TH Reset Pulse Width MD[15:0] Setup Time MD[15:0] Hold Time Conditions Min. 100 20 10 Max. Unit ns ns ns
8.3.4 Clock AC Characteristics
TCYC THIGH TLOW
2.0 V 1.5 V 0.8 V
Figure 8.8 Clock Waveform Table 8.8 Clock AC Characteristics Symbol Parameter 1/TCYC PCICLK Frequency VICLK Frequency VOCLK Frequency VOCLK/2 Frequency Conditions Min. 30 5 26.999 13.499 60 Max. 40 30 27.001 15.001 80 Unit MHz MHz MHz MHz MHz
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W9961CF
SMCLK Frequency THIGH PCICLK High Time VICLK High Time VOCLK High Time VOCLK/2 High Time SMCLK High Time TLOW PCICLK Low Time VICLK Low Time VOCLK Low Time VOCLK/2 Low Time SMCLK Low Time 8.3.5 Input Timing AC Characteristics PCICLK = 33 Mhz VICLK = 13.5 Mhz VOCLK = 27 Mhz VOCLK/2 = 13.5 Mhz SMCLK = 70 MHz 12 29.6 14.8 29.6 5.7 18 44.5 22.3 44.5 8.6 ns ns ns ns ns PCICLK = 33 Mhz VICLK = 13.5 Mhz VOCLK = 27 Mhz VOCLK/2 = 13.5 Mhz SMCLK = 70 MHz 12 29.6 14.8 29.6 5.7 18 44.5 22.3 44.5 8.6 ns ns ns ns ns
CLK TSU INPUT
1.5 V
1.5 V
TH
1.5 V
input valid
Figure 8.9 Input Timing Table 8.9 PCICLK-Referenced Input Timing AC Characteristics Symbol Parameter TSU TH AD[31:0], C/BE[3:0]#, FRAME#, IRDY#, IDSEL AD[31:0], C/BE[3:0]#, FRAME#, IRDY#, IDSEL Conditions Min. 7 7 Max. Unit ns ns
Table 8.10 SMCLK-Referenced Input Timing AC Characteristics Symbol Parameter TSU TH MD[15:0] , SD[7:0] Setup Time MD[15:0] , SD[7:0] Hold Time Conditions Min. 0 7 Max. Unit ns ns
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W9961CF
Table 8.11 VICLK-Referenced Input Timing AC Characteristics Symbol Parameter TSU TH Y[7:0], UV[7:0], HS, VS Y[7:0], UV[7:0], HS, VS Conditions Min. 5 5 Max. Unit ns ns
8.3.6 Output Timing AC Characteristics
CLK
1.5 V
TVAL OUTPUT DELAY
1.5 V
TOFF TON Tri-State OUTPUT
Figure 8.10 Output Timing Table 8.12 PCICLK-Referenced Output Timing AC Characteristics Symbol Parameter TVAL Ton AD[31:0], TRDY# AD[31:0] DEVSEL#, TRDY#, INTA#, PAR, PERR#, SERR# Toff AD[31:0] DEVSEL#, TRDY#, INTA#, PAR, PERR#, SERR# Table 8.13 SMCLK-Referenced Output Timing AC Characteristics Symbol Parameter TVAL MD[15:0], MA[10:0], BA, RAS[1:0]#/CS[1:0]#, CAS[1:0]#/DQM[1:0], OE#/CKE, WE#, SRAS#, SCAS# SA[12:0], SD[7:0], SRD#, SWR# TON MD[15:0] Conditions Min. 2 Max. 7 Unit ns Conditions Min. 2 2 2 Max. 11 11 11 28 28 Unit ns ns ns ns ns
2 2
11 7
ns ns
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W9961CF
TOFF MD[15:0] 2 7 ns
Table 8.14 PCLK-Referenced Output Timing AC Characteristics Symbol Parameter TVAL HSYNC, VSYNC, P[7:0] Conditions Min. Max. 10 Unit ns
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W9961CF
9
PACKAGE SPEC.
The W9961CF is packaged in a 208L QFP (28x28 mm footprint 2.6mm) as shown in Figure 9.1.
H D
208 157 D
1
156
E
E
H
52
105
53
e
b
104
c A
2
A See Detail F Seating Plane
1
L L
1
y
A
Detail F
control dimensions are in mm
Symbol
Dimension in inch
Dimension in mm
Min
0.004 0.122 0.006 0.004 1.097 1.097 0.016 1.193 1.193 0.012 0.043
Nom
Max
0.145
Min
0.10
Nom
Max
3.68
A A1 A2 b c D E e HD HE L L1 y
0.127 0.008 0.006 1.102 1.102 0.020 1.205 1.205 0.020 0.051
0.132 0.010 0.010 1.107 1.107 0.024 1.217 1.217 0.028 0.059 0.004
3.10 0.15 0.10 27.87 27.87 0.40 30.30 30.30 0.30 1.10
3.23 0.20 0.15 28.00 28.00 0.50 30.60 30.60 0.50 1.30
3.35 0.25 0.25 28.13 28.13 0.60 30.90 30.90 0.70 1.50 0.10
0
10
0
10
Figure 9.1 208L QFP (28X28 mm footprint 2.6mm) Dimensions
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W9961CF
10
ORDERING INFORMATION
Package 208L QFP
Part Number W9961CF
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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