View MC33410FTA_226826.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Order this document by MC33410/D
MC33410
Product Preview
Dual CVSD/PLL Cordless Phone System
The MC33410 Dual CVSD/Cordless Phone system is designed to fit the requirements of a 900 MHz digital cordless telephone system. The device c o n t a i n s a C V S D ( C o n t i n u o u s l y Va r i a b l e S l o p e D e l t a Modulator/Demodulator) Encoder to digitize the speech for the RF transmission, and a CVSD Decoder to reconstruct the received digital speech from the RF receiver. Provisions are made to transmit and receive data as well. Included are three PLLs (Phase-Locked Loops). Two are intended for use with external VCOs and 64/65 or 128/129 dual modulus prescalers, and can control the transmit and receive (LO1) frequencies for the 900 MHz communication. The third PLL is configured as the 2nd local oscillator (LO2), and is functional to 80 MHz. Also included are muting, audio gain adjust (internal and external), low battery/carrier detect, and a wide range for the PLL reference frequency. The power supply range is 2.7 to 5.5 V. A data only (non-voice) mode is also included.
DUAL CVSD/PLL CORDLESS PHONE SYSTEM
SEMICONDUCTOR TECHNICAL DATA
* * * * * * * * * * * * * * * * *
Two Complete CVSD Sections for Full Duplex Operation Two PLLs and an LO Suitable for a 900 MHz System Adjustable Detection for Low Battery or Carrier Signal (RSSI) Minimal External Components Encode Path Includes Adjustable Gain Amplifiers, Filters, Mute, CVSD Encoder, Data Insert, and Scrambler Decoder Path Contains Data Slicer, Clock Recovery, Descrambler, Data Detect, CVSD Decoder, Filters, Mute and Power Amplifier Data can be Transmitted During Voice Conversation with Minimal or No Noticeable Audio Disruption Idle Channel Noise Control Independent Power Amplifier with Differential Outputs, Mute Selectable Frequency for Switched Capacitor Filters, CVSD Function, PLLs, and the LO Reference Frequency Source can be a Crystal or System Clock Serial P Port to Control Gain, Mute, Frequency Selection, Phase Detector Gain, Power Down Modes, Idle Channel Control, Scrambler Operation, Low Battery Detect, and Others Mode Available for Data Only Transmission (non-voice) Ambient Temperature Range: -40 to 85_C Power Supply Range: 2.7 to 5.5 V Power Down Modes for Power Conservation 48 Pin LQFP with 0.5 mm Lead Pitch
FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP-48)
ORDERING INFORMATION
Device XC33410FTA Operating Temperature -40 to +85C Package LQFP-48
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 1998
Rev 0
MOTOROLA RF/IF DEVICE DATA
1
MC33410
Simplified Block Diagram
Analog Speech Gain Adj. Ref LP Filter CVSD Decoder Anti-Alias LPF Gain Adj. Analog Speech Mute Mute LP Filter Programmable Counters MPU Interface Low Batt /CD Dec. Clock SC Encode Clock Data Det. Register Idle Channel SC
Mute
CVSD Encoder
Data Register
Scrambler Idle Channel
Digital Speech/ Data Out Data Out
Descrambler
Clock Recovery Data Slicer
Digital Speech/ Data In Dec. Clock Status Low Battery/ CD
SC
-1 Power Amp
Ref
LO PLL #1 PLL #2 2nd LO
Ref. Freq.
VCO+ 64/65 PreScaler
VCO+ 64/65 PreScaler
LPF
Tank
MPU
PRELIMINARY SPECIFICATIONS (Subject to change)
Parameter Supply Voltage Supply Current (All sections active) Remote Gain Adjust Range Receive Path Gain Control Range Output Current Capability (PAO+, PAO-) Max. 2nd LO frequency Phase Detector Charge Pump Output Current High Low Digital Input Signal Amplitude to Data Slicer Operating Ambient Temperature
NOTE: 1. Above specs represent design objectives, and are subject to change.
Symbol
Min - - - - - - - - - -
Typ 2.7 to 5.5 13 16 28.5 5.0 80 400 100 >200 -40 to +85
Max - - - - - - - - - -
Units V mA dB dB mA MHz A
mVpp C
2
MOTOROLA RF/IF DEVICE DATA
MC33410
Figure 1. Typical Applications Circuit
Battery
MP1 Dec. Out 36 Battery VCC Rx Dig. Input MP2 39 Gnd 37 CD 35
Rx Audio In 34
VB 33
Rx Audio Out 32 Mute
0.1 PAI 31 Gnd 30 PAO- 29 PAO+ 28 VCC 27 Dec. Cap 26 Vag 25 To CVSD Encoder VB VB 23 Rem. Gain Adjust SMTH LPF Mute Ref 20 Tx Audio Out Enc. In Battery 18 SPI Tx 1010 Generator Enc Clk 16x Clk / 16 /2 12b Ref. Ctr. 6b Enc. Ctr. SPI 6b SCF Ctr. Ref. Clk 7b A SPI MPU Serial Interface 15 Fref Out VCC MCI Enc. Cap Audio Input
AALPF LPF
VB Gain Adjust
R Mute R
24
38 Data Slicer Data Clock Recovery Rx 1010 Generator Status SCF Clk. CVSD Decoder VB
SCF Clk. LPF Idle Channel Detect
22
MCO
VCC
40
21
Gnd
LO2 Out Battery LO2 VCC LO2+
41
16x Clk Clk
Data Detect Descrambler Rx Data Register SPI
42
43 VCC CD 44
BG Ref.
Low Battery Carr. Det.
Idle Chan Control
CVSD Encoder
19
LO2 Ctl
LO2-
45
2nd LO VCO
Idle Chan Ctrl 4b Idle Chan Ctr.
Scrambler Tx Data Register
17
Enc. Out
VCC
/ 32 SCF Clk
16
Low Battery/CD
LO2 Gnd
46 LO2 Phase Detector 47 7b A'
14b Ctr. PLL Ref. Freq. 13b N'
LPF
LO2PD
13b N
14
Fref In
LO2 Gnd 48 Mod Ctl 1 2 FRx MC FRx 3
Rx Phase Detector
Tx Phase Detector
Mod Ctl
13
Status
4 PLL VCC Rx PD
5 PLL Gnd
6 Tx PD
7 PLL VCC
8 FTx
9 FTx MC
10 EN
11 CLK
12 Data
Battery 64/65 PS VCO LPF LPF
Battery VCO 64/65 PS
To Microprocessor
NOTE:
Pin numbers are not firm and are not to be used for design-in purposes.
MOTOROLA RF/IF DEVICE DATA
3
MC33410
RECOMMENDED OPERATING CONDITIONS (Subject to change)
Parameter Supply Voltage CVSD Clock Rate Encoder in Signal Level (max) Peak Output Current at PAO+, PAO- Reference Frequency Amplitude (Fref In) Rx Digital Input Signal Amplitude Min Max Crystal or Reference Frequency at Pin 14 Max. Input Frequency at FRx, FTx LO2 VCO Control Voltage (Pin 44) Max. 2nd LO Frequency 12 Bit Reference Counter Range (Note 1) 13 Bit N Counter Range (Note 1) 7 Bit A Counter Range (Note 1) with a 64/65 Modulus Prescaler with a 128/129 Modulus Prescaler 14 Bit LO2 Counter Range (Note 1) 6 Bit Counters (for SCF and Encode Clock) (Note 1) Receive Path Gain Control Code Range (Note 1) Operating Ambient Temperature
NOTES: 1. Values specified are pure numbers to the base 10. 2. Above specs represent design objectives, and are subject to change.
Symbol
Min - - - - - - - - - - - - - - - - - - -
Typ 2.7 to 5.5 32, 50, or 64 3.0 5.0 >200 0.20 0 to VCC 4.0 to 18.25 TBD TBD 80 3 to 4095 3 to 8191 0 to 63 0 to 127 12 to 16383 3 to 63 6 to 25 -40 to 85
Max - - - - - - - - - - - - - - - - - - -
Units V kHz Vpp mA mVpp Vpp
MHz MHz V MHz - - -
- - - C
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Name Description FRx MC FRx Modulus Control Output to the Rx 64/65 or 128/129 dual modulus prescaler. Input to the Rx PLL. PLL VCC Rx PD PLL Gnd Tx PD PLL VCC FTx FTx MC EN CLK Data Status Supply pin for the Rx PLL section. Allowable range is 2.7 to 5.5 V. Phase detector charge pump output of the Rx PLL. Ground pin for the PLL sections. Phase detector charge pump output of the Tx PLL. Supply pin for the Tx PLL section and the MPU Serial Interface section. Allowable range is 2.7 to 5.5 V. Input to the Tx PLL. Modulus Control Output to the Tx 64/65 or 128/129 dual modulus prescaler. Enable input for the P port. This signal latches in the register address and data. Clock input for the P port. Maximum frequency is 2.0 MHz. Bi-directional data line for the P port. In Data Modem mode, this pin provides the recovered clock. Logic output which indicates that a predetermined 16 or 24-bit code word has been detected in the Data Detect register, and the following data word has been loaded into register 10. In Data Modem mode, this pin provides the Transmit Data clock. A crystal, in the range of 4.0 to 18.25 MHz can be connected to these pins to provide the reference frequency. If an external reference source is used, it is to be capacitively coupled to Fref In. 14, 15
NOTE:
Fref In, Fref Out
1. All VCC pins must be within 0.5 V of each other.
4
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION (continued)
Description Pin 16 17 18 19 20 21 22 23 24 25 26 27 28, 29 30 31 32 33 34 35 36 Name Low Battery/CD Enc Out VCC Enc In Tx Audio Out Ground MCO MCI Enc Cap VAG Dec Cap VCC PAO+, PAO- Gnd PAI Rx Audio Output VB Rx Audio In Dec Out MP1 An open collector output. When low, indicates either the supply voltage (VCC) is low, or the carrier level is above the threshold. This output is off when disabled. The digital output of the scrambler, which passes data from the CVSD encoder, or the Tx Data register, or the Tx 1010 Generator. Source selection is done through the mP port. Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V. Internally connected to Pins 27 and 37. The analog input to the CVSD encoder. Max. input level is 3.0 Vpp. Output of the transmit speech processing section. Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 30 and 40. Output of the microphone amplifier, and input to the filters. This output has rail-to-rail capability. Inverting input of the microphone amplifier. Gain and frequency response is set with external resistors and capacitors. This capacitor sets the time constant for the CVSD encoder. This pin is sensitive to leakage. Analog ground for the audio section and the CVSD encoder and decoder. The capacitor sets the time constant for the CVSD decoder. This pin is sensitive to leakage. Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V. Internally connected to Pins 18 and 37. Differential outputs of the power amplifier stage for driving an earpiece or hybrid network. The gain and frequency response are set with external resistors and capacitors. Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 21 and 40. Input to the power amplifier stage. This pin is a summing node. Output of the receive speech processing section. The capacitor filters the internal 1.5 V reference voltage. If VB is adjusted, it may be monitored at this pin. Max. load current is 10 mA. Input to the receive speech processing section. The analog output of the CVSD decoder. As an output, provides the recovered Rx data, or the Data Detect output, or the data slicer output. Or it can be set to a high impedance input (600 kW) for the carrier detect input signal. Selection is done through the mP port. See Table 6. Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V. Internally connected to Pins 18 and 27. The digital stream from the RF receiver is applied to the data slicer at this pin. Minimum amplitude is 200 mVpp. Hysteresis 50 mV. As an output, this pin provides the recovered clock from the Clock Recovery block. As an input, the CVSD decoder clock can be applied to this pin. Or this pin may be set to a disabled state. Selection is done through the mP port. See Table 7. In Data Modem mode, the data to be transmitted is input to this pin. Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 21 and 30. Buffered output of the 2nd LO frequency. A pullup resistor is required. Supply pin for the 2nd LO. Allowable range is 2.7 to 5.5 V. A tank circuit is connected to these pins for the 2nd LO. The varactor control pin for the 2nd LO. Ground for the 2nd LO section. Phase detector charge pump output of the 2nd LO PLL. Ground for the 2nd LO section. 37 38 39 VCC Rx Digital Input MP2 40 41 42 43, 45 44 46 47 48
NOTE:
MC33410
Gnd LO2 Out LO2 VCC LO2+, LO2- LO2 Ctl LO2 Gnd LO2 PD LO2 Gnd
1. All VCC pins must be within 0.5 V of each other.
MOTOROLA RF/IF DEVICE DATA
5
MC33410
Note: In the following descriptions, control bits in the MPU Serial Interface for the various functions will be identified by register number and bit number. For example, bit 3/19 indicates bit 19 of register 3. Bits 5/14-11 indicates register 5, bits 14 through 11. Please refer to Figure 1. Transmit Speech Processing Section This section is made up of the externally adjustable microphone amplifier (Pins 22 to 23), internally adjustable gain stage, two low pass filters, and a mute switch. The gain of the microphone amplifier is set with external resistors to receive the audio from the microphone (in the handset), or from the hybrid (in the base unit), or from any other audio source. The MCO output has rail-to-rail capability, and the dc bias level is at VB (1.5 V). The adjustable gain stage, referred to as the Remote Gain Adjust, provides 5 levels of gain in 4.0 dB increments. It is controlled with bits 6/15-11 as shown in Table 1.
Table 1. Remote Gain Adjust
Register 6
Bits 15-11 00001 00010 00100 01000 10000
Gain
-8.0 dB -4.0 dB 0 dB
+4.0 dB +8.0 dB
CVSD Encoder/Idle Channel/Tx Data Register The analog signals to be digitized are input at Pin 19 to the CVSD Encoder. The output of the encoder will be the digital equivalent of the audio, at the selected clock rate. Based on the reference frequency, bits 4/23-18 are used to set the 6 Bit Encoder Counter, in conjunction with the subsequent /16 divider, to set the CVSD Encoder frequency to 32, 50, or 64 kHz. Bits 3/16-15 will set the CVSD for proper operation at the selected frequency, according to Table 2.
Table 2. CVSD Clock/Data Rates
Register 3
Bit 16 0 1 1
Bit 15 1 0 1
Clock/Data Rate 32 kHz 50 kHz 64 kHz
The Encoder's minimum step size can be selected using bits 2/22-21, according to Table 3.
6
AAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAA
Other combinations for the 5 bits are invalid. The Low Pass Filter after the gain stage is a switched capacitor filter with a corner frequency at 5.0 kHz. The subsequent smoothing low pass filter has a corner frequency at 30 kHz, and is designed to filter out high frequency clock noise from the previously mentioned switched capacitor filter. The mute switch at Pin 20 will mute a minimum of 60 dB. Bit 6/2 controls the mute.
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
Table 3. Minimum Step Size
Decoder Register 1 Bits 22, 21 00 01 10 11 Encoder Register 2 Bits 22, 21 00 01 10 11 Step Size No minimum 1.4 mV 5.6 mV 22.4 mV
FUNCTIONAL DESCRIPTION
The Tx 1010 Generator, when selected, provides an alternating "1-0" pattern (a square wave at half the CVSD clock rate) to the scrambler. This represents the lowest amplitude analog signal, and can be used when it is desired to send a quiet signal. Selection of this block can occur either automatically, or intentionally, as follows: a. The automatic selection occurs when the Idle Channel Detector senses the average audio signal at Pin 19 is below a threshold which is set with bits 5/17-15 (See Table 4). Bits 5/14-11 select a time delay for the automatic threshold detection to occur. The minimum delay is zero, with these bits set to 0000. Changing the bits provides delay in increments of 32 clock cycles (of the CVSD Encoder clock). The maximum delay is 480 clock cycles, (7.5 mS at 64 kHz). When the average audio signal at Pin 19 increases above the threshold, the Tx 1010 Generator will be deselected with no delay. This automatic switchover feature can be disabled with bit 7/2. Bit 5/21 indicates when an idle channel condition has been detected. This output bit will be functional even when the idle channel detector is disabled with bit 7/2. Bit 5/18 will power down the Idle Channel Detect Circuit as a power saving measure. b. Bit 6/4 can be used to intentionally select the Tx 1010 Generator at any time. Table 4. Idle Channel Detection Threshold
Register 5
AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAA
Register 5
Bits 17-15 000 001 010 011
Threshold -50 dBV -52.5 -55 -57.5
Bits 17-15 100 101 110 111
Threshold -60 dBV -62.5 -65 -67.5
The Tx Data Register is used for the transmission of data between the handset and base units. The procedure is as follows: a. At the receiving unit: The code word (16 or 24 bits, set with bit 7/11) identifying that a data transmission is occurring must be loaded into the Tx Data Register (by loading register 8). This is used to detect when a code word is sent from the transmitting unit. b. At the transmitting unit: The same code word as above is loaded into register 8. It is automatically loaded into the Tx Data Register. c. The data word (16 or 24 bits, set with bit 7/12) is then loaded into register 9.
MOTOROLA RF/IF DEVICE DATA
MC33410
d. Upon loading register 9, the MC33410 automatically sends out (at Pin 17) the code word, followed by the data word, at the CVSD clock rate. When the data word is completely sent out, the MC33410 will then return Pin 17 to its previous source of digital information (CVSD Encoder or Tx 1010 Generator). Scrambler/Digital Output The scrambler receives digital data from the CVSD Encoder, or the Tx 1010 Generator, or the Tx Data Register, to be output at Pin 17. The output level is 0 to VCC. The scrambler can be bypassed with Bit 7/1. The scrambler, better known as a randomizer, provides not only a level of communication security, but also helps ensure the digital output will not contain an abnormally long string of 1s or 0s which can adversely affect the CVSD Decoder operation, as well as the RF section. The scrambler is a maximal-length shift register sequence generator. The length of the shift register is selectable to one of eight values with bits 7/10-8 (the descrambler in the receiving unit must be set the same). Table 5 lists the polynomial associated with each tap selection.
AAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAA
Data Slicer/Clock Recovery The data slicer will receive the low level digital signal from the RF receiver section at Pin 38. The input signal to the data slicer must be >200 mVpp. Hysteresis of 50 mV is internally provided. The output of the data slicer will be same waveform, but with an amplitude of 0 to VCC, and can be observed at Pin 36 (MP1) if bits 7/5-4 are set to 10. The output can be inverted by setting bit 5/19 = 1. The clock recovery block will generate a phase locked clock, equal to the CVSD data rate, from the incoming data, as long as the Encoder Counter (bits 4/23-18) is set for that data rate. The recovered clock can be observed at Pin 39 (MP2) if bits 7/7-6 are set to 00. The data from the clock recovery block can be observed at Pin 36 if bits 7/5-4 are set to 00. The clock recovery block may be bypassed by setting bit 7/0 to 1. With this setting the data slicer output will go directly to the descrambler, and the encoder clock will replace the Clock Recovery Clock. Tables 6 and 7 summarize the options available at MP1 and MP2 (Pins 36 and 39). Table 6. MP1 Options (Pin 36)
Register 7
Bit 5 0 0 1 1
Bit 4 0 1 0 1
Function
Data from clock recovery block Data Detect Output Data Slicer Output Hi-Z/ CD Input
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 5. Scrambler/Descrambler Tap Selection
Bit 8 0 1 0 1 0 1 0 1 Tap No. 0 1 2 3 4 5 6 7 Register 7 Bit 9 0 0 1 1 0 0 1 1 Bit 10 0 0 0 0 1 1 1 1 Shift Register Length Shif R i L h 2 3 4 5 6 7 9 10 Polynomial Pl il 1 + z-1 + z-2 1 + z-2 + z-3 1 + z-3 + z-4 1 + z-3 + z-5 1 + z-5 + z-6 1 + z-6 + z-7 1 + z-5 + z-9 1 + z-7 + z-10
Table 7. MP2 Options (Pin 39)
Register 7
Bit 7 0 0 1
Bit 6 0 1
Function
Output recovered clock
Input CVSD Decoder clock Disabled (Hi-Z)
X
When MP1 is set to a Hi-Z condition, the pin is an input for the CD (Carrier Detect) function, with an input impedance of 600 K. See the section entitled Low Battery/Carrier Detect for an explanation of this function. Descrambler The descrambler receives the scrambled data from the clock recovery block (or the data slicer if bit 7/0 = 1), and descrambles it to the original data as long as the selected taps are the same as those in the transmitting scrambler (see Table 5). The descrambler block is the same configuration as the scrambler, and is self-synchronizing. The descrambler can be bypassed with bit 7/1. Data Detect Register/Status Output/Rx Data Register The Data Detect register will continuously compare the descrambled data it receives with the 16 or 24-bit code word stored in the Tx Data Register (loaded through register 8). Upon detecting a match, and after the code word passes through the shift register, the following (16 or 24-bit) data word will be stored into the Rx Data Register, and then loaded into register 10 of the MPU Interface. At this time the Status
7
output at Pin 13, and bit 5/22, will go high. The external microprocessor can then retrieve the data word by reading register 10, at which time the Status pin and bit will go low. Upon detection of a code word as described above, the CVSD Decoder will be provided with 32, 40, or 48-bits of a 1010 pattern (idle channel) to minimize disturbances to the audio. After the data word is loaded into register 10, the CVSD Decoder resumes receiving data from the descrambler. The audio is therefore interrupted with a low level signal for a maximum of 48 clock cycles (0.75 mSec at 64 kHz). The Data Detect register can be bypassed by setting bit 7/3 = 1. CVSD Decoder/Decoder Clock/Idle Channel The CVSD Decoder will provide the analog equivalent, at Pin 35, of the digital data it receives from the descrambler, or from the 1010 generator (idle channel generator). There is a single pole filter at the Decoder output to reduce the clock noise normally present on a CVSD analog output. The CVSD Decoder is self synchronizing as long as the decoder clock matches the data rate, and the Decoder has been set with bits 3/16-15 according to Table 2. The Decoder clock is provided from the Clock Recovery block by setting bits 7/7-6 to 00 or 1X. The clock is internally provided to the Decoder, and is available at Pin 39. Alternately, a Decoder clock can be provided from an external source to Pin 39 by setting bit 7/7-6 to 01 (see Table 7). The Rx 1010 Generator provides an alternating 1-0 pattern (a square wave at half the CVSD clock rate) to the CVSD Decoder, resulting in the lowest amplitude analog signal at Pin 35. The 1010 Generator is automatically selected whenever data is detected and received by the Data Detection Circuit, as described above. Additionally, the 1010 Generator can be selected with bit 6/3 at any time. The Decoder's minimum step size can be selected using bits 1/22-21, according to Table 3. Receive Audio Path The Receive Audio Path (Pins 34 to 32) consists of an anti-aliasing filter, a low pass filter, a gain adjust stage, and a mute switch. Since the analog output of the CVSD Decoder (typically input at Pin 34) will contain noise at the CVSD clock rate, the anti-aliasing filter, with a corner frequency at 30 kHz, is provided to prevent aliasing of that clock noise with the subsequent switched capacitor filter. The switched capacitor low pass filter is a 3 pole filter, with a corner frequency at 5.0 kHz. This is designed to remove the clock noise from the CVSD Decoder output signal, as well as provide bandwidth limiting in the audio range. The gain stage provides 28.5 dB of gain adjustment in 19 steps (1.5 dB each), measured from Pin 34 to 32. Bits 6/10-6 are used to set the gain according to Table 8. The mute switch at Pin 32, controlled by bit 6/1, will mute a minimum of 60 dB.
8
AAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAA
Table 8. Receive Gain Adjustment
Register 6 Bits 10...6 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 Register 6 Bits 10...6 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Gain Gain -13.5 dB -12.0 dB -10.5 dB -9.0 dB -7.5 dB -6.0 dB -4.5 dB -3.0 dB -1.5 dB 0.0 dB +1.5 dB +3.0 dB +4.5 dB +6.0 dB +7.5 dB +9.0 dB +10.5 dB +12.0 dB +13.5 dB +15.0 dB
MC33410
Power Amplifiers The power amplifiers (Pins 28, 29, 31) are designed to drive the earpiece in a handset, or the telephone line via a hybrid circuit in the base unit. Each output (PAO+ and PAO-) can source and sink 5 mA, and can swing 2.0 Vpp each. The gain of the amplifiers is set with a feedback resistor from Pin 29 to 31, and an input resistor at Pin 31. The differential gain is 2x the resistor ratio. Capacitors can be used for frequency shaping. The pins' dc level is VB (1.5 V). The Mute switch, controlled with bit 6/0, will provide 90 dB of muting with a 50 k feedback resistor. The amount of muting will depend on the value of the feedback resistor. Reference Clock The reference clock provides the frequency basis for the three PLLs, the switched capacitor filters, and the CVSD Encoder section. The source for the reference clock can be a crystal in the range of 4.0 to 18.25 MHz connected to Pins 14 & 15, or it can be an external source connected to Fref In (Pin 14). The reference frequency is directed to: a. A programmable 12-bit counter to provide the reference frequency for the three PLLs. The 12-bit counter is to be set such that, in conjunction with the programmable counters within each PLL, the proper frequencies can be produced by each VCO. b. A programmable 6-bit counter, followed by a /2 stage, to set the frequency for the switched capacitor filters to 256 kHz, or as close to that as possible. c. A programmable 6-bit counter which provides the 16x clock for the Clock Recovery block. This is followed by a /16 stage which provides the CVSD Encoder clock. This is followed by a /32 stage, and a programmable 4-bit counter which sets the delay for the Idle Channel Detect circuit. Transmit and Receive (LO1) PLL Sections The transmit and receive PLLs (Pins 6 to 9 and 1 to 4, respectively) are designed to be part of a 900 MHz system. In
MOTOROLA RF/IF DEVICE DATA
MC33410
a typical application the Transmit PLL section will be set up to generate the transmit frequency, and the Receive PLL section will be set up to generate the LO1 frequency. The two sections are identical, and function independently. External requirements for each include a low pass filter, a 900 MHz VCO, and a 64/65 or 128/129 dual modulus prescaler. The frequency output of the VCO is to be reduced by the dual modulus prescaler, and then input to the MC33410 (at Pin 2 or 8). That frequency is then further reduced by the programmable 13-bit counter (bits 1/19-7 or 2/19-7), and provided to one side of the Phase Detector, where it is compared with the PLL reference frequency. The output of the phase detector (at Pin 4 or 6) is a bi-directional charge pump which drives the VCO through the low pass filter. Bits 1/20 and 2/20 set the gain of each of the two charge pumps to either 100/2 A/Radian or 400/2 A/Radian. The polarity of the two phase detector outputs is set with bits 7/22 and 7/23. If the bit=0, the appropriate PLL is configured to operate with a non-inverting low pass filter/VCO combination. If the low pass filter/VCO combination is inverting, the polarity bit should be set to 1. The 7-bit A and A' counters (bits 1/6-0 and 2/6-0) are to be set to drive the Modulus Control input of the 64/65 or 128/129 dual modulus prescalers. The Modulus Control outputs (Pins 1 and 9) can be set to either a voltage mode or a current mode with bit 7/13. To calculate the settings of the N and A registers, the following procedure is used: f VCO Equation 1 Nt (Nt must be an integer) f PLL Bits 7/20-18 are used to select an internal capacitor, with a value in the range of 0 to 7.6 pF, to parallel the varactor diodes and the tank's external capacitor. This permits a certain amount of fine tuning of the oscillator's performance. See Table 9. A buffered output is provided to drive, e.g., a mixer. The frequency is set with the programmable 14-bit counter (bits 3/13-0) in conjunction with the PLL reference frequency. For example, if the reference frequency is 50 kHz, and the 2nd LO frequency is to be 63.3 MHz, the 14-bit counter needs to be set to 1266d (00 0100 1111 0010). The output level is dependent on the value of the impedance at Pin 41, partly determined by the external pullup resistor. The output of the phase detector is a bi-directional charge pump which drives the varactor diodes through an external low pass filter. Bit 3/14 sets the gain of the charge pump to either 100/2 A/Radian or 400/2 A/Radian. Bit 7/21 sets its polarity - if 0, the PLL is configured to operate with a non-inverting low pass filter/VCO combination. If the low pass filter/VCO combination is inverting, the polarity bit should be set to 1. Table 9. LO2 Capacitor Selection
Capacitor Value 0 pF Register 7
+
Nt P
+N
Equation 2
A = Remainder of Equation 2 Equation 3 (decimal part of N x P) where: fVCO = the VCO frequency fPLL = the PLL Reference Frequency set within the MC33410 P = the smaller divisor of the dual modulus prescaler (64 for a 64/65 prescaler) N = the whole number portion is the setting for the N (or N') counter within the MC33410 A = the setting for the A (or A') counter within the MC33410 For example, if the VCO is to provide 910 MHz, and the internal PLL reference frequency is 50 kHz, then the equations yield: 910 x 10 6 Nt 18, 200 50 x 10 3
+
+
N
200 + 18,64 + 284.375
A 0.375 x 64 24 The N register setting is 284d (0 0001 0001 1100), and the A register setting is 24d (001 1000). 2nd LO (LO2) This PLL is designed to be the 2nd Local Oscillator in a typical 900 MHz system, and is designed for frequencies up to 80 MHz. The VCO and varactor diodes are included, and are to be used with an external tank circuit (Pins 43 to 45).
+
+
MOTOROLA RF/IF DEVICE DATA
AAAAA AAAAA AAAAAAAAAAAAAAAA AAAAA AA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAAAAA AA AAAAAAAAAAAAAAAA
Register 7 Bits 20-18 000 001 010 011 Bits 20-18 100 101 110 111 Capacitor Value 4.3 pF 5.4 pF 6.5 pF 7.6 pF 1.1 pF 2.2 pF 3.3 pF
VB Reference Voltage The VB voltage (1.5 V) is available at Pin 33. It will have a production tolerance of 6%, and can be adjusted over a 9% range using bits 3/20-17. The adjustment steps will be 1.2% each. VB can be used to bias external circuitry, as long as the load current on this pin does not exceed 10 A. Low Battery/Carrier Detect This circuit will provide an indication of either Low Battery voltage, or a low carrier signal applied to Pin 36 (MP1) from an RSSI circuit. The desired mode is selected with bit 6/5. A) Low Battery Mode (Bit 6/5 = 0) The supply voltage at Pin 18 is applied to the comparator through an internal resistor divider, and is compared to the internal reference VB (1.5 V). The comparator has 15 mV of hysteresis, measured at VCC. The resistor divider is adjustable using bits 3/23-21. The Low Battery threshold voltage will then be equal to the VB voltage multiplied by the factor listed in Table 10. For example, if VB = 1.5 V, and bits 3/23-21 = 011, the threshold will be 3.21 V. B) Carrier Detect Mode (Bit 6/5 = 1) Pin 36 (MP1) must be set to the Hi-Z/CD Input mode by setting bits 7/5-4 to 11. MP1 will then be an input with an input impedance of 600 k, referenced to VB. An analog signal applied to MP1 will be applied to the comparator through an internal adjustable gain stage (adjustable using bits 3/23-21), and is compared to the internal reference VB. The comparator has 18.0 mV of hysteresis, measured at Pin 36. The threshold voltage will then be equal to the VB voltage multiplied by the factor listed in Table 10. For
9
MC33410
example, if VB = 1.5 V, and bits 3/23-21 = 011, the threshold will be 0.576 V. Internally there are 10 data registers, 24 bits each, addressed with four bits ranging from $1 to $A. Register 10, and bits 23-21 of register 5 contain data to be read out by the microprocessor, while all other register bits are to be written to by the microprocessor. The contents of the 10 registers can be read out at any time. All bits are written in, or read out, on the clock's positive transition. The write and read operations are as follows: a) Write Operation: To write data to the MC33410, the following sequence is required (see Figure 2): 1. The Enable line is taken high. 2. Five bits are entered: - The first bit must be a 0 to indicate a Write operation. - The next four bits identify the register address (0001-1010). The MSB is entered first. 3. After the 5th clock pulse is low, the Enable line is taken low. At this transition, the address is latched in and decoded. 4. The Enable line is maintained low while the data bits are clocked in. The MSB is entered first, and the LSB last. If 24 bits are written to a register which has less than 24 active bits (e.g., register 6), the unassigned bits are to be 0. 5. After the last bit is entered, the Enable line is to be taken high and then low. The falling edge of this pulse latches in the just entered data. The clock line can be at a logic high or low, but must not transition in either direction during this Enable pulse. 6. The Enable line must then be kept low until the next communication. Note: If less than 24 bits are to be written to a data register, it is not necessary to enter the full 24 bits, as long as they are all lower order bits. For example, if bits 0-6 of a register are to be updated, they can be entered as 7 bits with 7 clock cycles in step 4 above. However, if this procedure is used, a minimum of 4 bits, with 4 clock pulses, must be entered.
AAAAAAAAAAA A A AAAAAA A A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAA
Table 10. LB/CD Threshold Adjustment Factor
Low B L Battery M d Mode 1.96 2.02 2.08 2.14 2.19 2.25 2.30 2.37 Register 3 Bits 23-21 000 001 010 011 100 101 110 111 Carrier Detect Mode 0.574 0.524 0.453 0.384 0.314 0.247 0.177 0.110
The comparator output is at bit 5/23, and at Pin 16 (open collector output). The outputs are high if the monitored VCC voltage is above the threshold, or if the Carrier signal is below the threshold. Pin 16 requires an external pullup resistor. When this circuit is disabled (bit 5/10 = 1), bit 5/23 and Pin 16 will be high. MPU Serial Interface The MPU Serial Interface is a 3-wire interface, consisting of a Clock line, an Enable line, and a bi-directional Data line. The interface is always active, i.e. it cannot be powered down as all other sections of the MC33410 are disabled and enabled through this interface. The clock must be supplied to the MC33410 at Pin 11 to write or read data, and can be any frequency up to 2.0 MHz. The clock need not be present when data is not being transferred. The Enable line must be low when data is not being transferred.
Figure 2. Writing Data to the MC33410
1 2 3 24
Clock Data
4-Bit Address
MSB 24-Bit Data from MPU Latch Address
LSB
Latch Data
Enable
Figure 3. Reading Data from the MC33410
Sets Data Pin to Output 1 2 3 24
Clock Data
4-Bit Address
MSB 24-Bit Data from MC33410 Latch Address and Load Data into Shift Register
LSB Sets Data Pin to Input
Enable
10
MOTOROLA RF/IF DEVICE DATA
MC33410
b) Read Operation: To read the output bits (bits 5/23-21, or all of register 10), or the contents of any register, the following sequence is required (see Figure 3): 1. The Enable line is taken high. 2. Five bits are entered: - The first bit must be a 1 to indicate a Read operation. - The next four bits identify the register address (0001-1010). The MSB is entered first. 3. After the 5th clock is taken low, the Enable line is taken low. At this transition, the address is latched in and decoded, and the contents of the selected register is loaded into the 24-bit output shift register. At this point, the Data line (Pin 12) is still an input. 4. While maintaining the Enable line low, the data is read out. The first clock rising edge will change the Data line to an output, and the MSB will be present on this line. 5. The full contents of the register are then read out (MSB first, LSB last) with a total of 24 clock rising edges, including the one in step 4 above. It is recommended that the MPU read the bits at the clock's falling edge. If only bit 23, 22, or 21 of register 5 are to be read, this can be done with one, two, or three clock rising edges, respectively. 6. After the last clock pulse, the Enable line is to be taken high and then low. The falling edge of this pulse returns the Data pin to be an input. The clock line can be at a logic high or low, but must not transition in either direction during this Enable pulse. 7. The Enable line must then be kept low until the next communication. Data Modem Mode For applications where the MC33410 is to be used in a 900 MHz wireless system for transmitting data only (non-voice), a mode can be set which bypasses the speech digitizing sections. The resulting configuration makes use of those sections associated with data only, i.e., the scrambler, descrambler, and clock recovery section. Also functional are the three PLLs, the audio receive path (Pins 34 to 28), the transmit audio path (Pins 23 to 20), and the Low Battery circuit (but not the Carrier Detect mode). In this mode, the MC33410 will provide the transmit data clock from the crystal, in conjunction with the internal 6-bit counter (bits 4/23-18) and the /16 block associated with that counter. The transmit data clock is available at Pin 13, and can be used to synchronize the external data source. The Tx data is input at Pin 39, passes through the scrambler, and outputs at Pin 17. The demodulated data from the RF receiver is input at Pin 38, and is applied to the data slicer, and the clock recovery block. The recovered clock is output at Pin 12. The data passes through the descrambler, and is output at Pin 36. Figure 4 is a diagram of the data paths through the MC33410. The procedure for entering the Data Modem mode is in Table 11:
Figure 4. Data Modem Mode Configuration
Tx Data Input
39
Scrambler
14 Crystal 15 Data Slicer Rx Data Input 38 Clock Recovery
Prog. 6-bit Counter
MC33410
Descrambler
MOTOROLA RF/IF DEVICE DATA
AAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAAA
Table 11. Entering Data Modem Mode
Function Bits Bit Value As Desired As Desired 1 01 110 1 N/A Set Tx Clock to desired frequency Tx Clk = Fcrystal/(16 x Counter). Set Scrambler & Descrambler tap setting (Bit 7/1 = 0). Bypass Data Detect. Set MP1 to Data Detect Output. Set Test Mode bits to connect Encode Clock to Status (Pin 13). Set Data Modem Mode (MP2 to scrambler Input). Write to Register 11 as shown in Figure 5 to configure Pin 12. 4/23 - 18 7/10 - 8 7/3 7/5 - 4 7/17 - 15 5/20 N/A
The above sequence is not critical, except that the last two steps must be the setting of bit 5/20, and writing to register 11. Writing to register 11 is shown in Figure 5.
17
Tx Data Out Tx Clock Out Rx Data Out Recovered Rx Clock
/16
13
36
12
11
MC33410
Figure 5. Entering/Exiting Data Modem Mode
Clock Data
Address 1011 Sets Data Pin to Output Recovered Clock Output @ Pin 12 Sets Data Pin to Input
Enable
After address 11 is clocked in, the Enable falling edge will cause Pin 12 (Data) to switch to an output, providing the recovered clock. The microprocessor's data pin must be changed to an input prior to this falling edge. This sequence is effective only if bit 5/20 is set to a 1. During the time that recovered clock is available at Pin 12, the microprocessor port is unavailable for any control functions. To exit the Data Modem mode, the Enable line is to be taken high and low (the clock is to be stable during this active high pulse). The falling edge will set Pin 12 to be an input, allowing normal use of the microprocessor port. The next step is to set bit 5/20 to a 0. Other register bits can then be set as needed. To prevent inadvertent incorrect operation of the microprocessor port, bit 5/20 must always be set to 0 when the Data Modem mode is not in use. Power Supply/Power Saving Modes The power supply voltage, applied to all VCC pins, can range from 2.7 to 5.5 V. All VCC pins must be within 0.5 V of each other, and each must be bypassed. It is recommended a ground plane be used, and all leads to the MC33410 be as short and direct as possible. The supply and ground pins are distributed as follows: 1. Pins 18, 27 and 37 are internally connected together, and provide power to the audio amplifiers, filters, CVSD encoder and decoder, and the low frequency (CVSD rate) logic circuits. Pins 21, 30 and 40 are the ground pins for these sections. 2. Pin 3 provides power to the Rx PLL section. Pin 5 is the ground pin. 3. Pin 7 provides power to the Tx PLL section, and the MPU interface. Pin 5 is the ground pin. 4. Pin 42 provides power to the 2nd LO section. Pins 46 and 48 are the ground pins. To conserve power, various sections can be individually disabled, using bits 5/10-0 (setting a bit to 1 disables the section).
1. Reference Oscillator Disable (bit 5/0) - The reference oscillator at Pins 14 and 15 is disabled, thereby denying a clock to the three PLLs, the CVSD Encoder, and the switched capacitor filters. 2. Tx PLL Disable (bit 5/1) - The 13-bit and 7-bit counters, input buffer, phase detector, and modulus control blocks are disabled. The charge pump output at Pin 6 will be in a Hi-Z state. 3. Rx PLL Disable (bit 5/2) - The 13-bit and 7-bit counters, input buffer, phase detector, and modulus control blocks are disabled. The charge pump output at Pin 4 will be in a Hi-Z state. 4. LO2 PLL Disable (bit 5/3) - The VCO, 14-bit counter, output buffer, and phase detector are disabled. The charge pump output at Pin 47 will be in a Hi-Z state. 5. Rx Data Path Disable (bit 5/4) - The data slicer, clock recovery block, descrambler, data detect register, and the status output circuit are disabled. The state of the status line (Pin 13 and bit 5/22) will not change upon disabling this section. 6. CVSD Decoder Disable (bit 5/5) - The CVSD Decoder and the Rx 1010 Generator are disabled. 7. Rx Audio Path Disable (bit 5/6) - The anti-aliasing filter, low pass filter, and variable gain stage are disabled. 8. Power Amplifier Disable (bit 5/7) - The two power amplifiers are disabled. Their outputs will go to a Hi-Z state. 9. Tx Audio Path Disable (bit 5/8) - Disables the microphone amplifier, low pass filter, and smoothing filter. 10. CVSD Encoder Disable (bit 5/9) - The CVSD Encoder, Idle Channel detect circuit, the Tx 1010 Generator, the Tx Data register, and the scrambler are disabled. 11. Low Battery/Carrier Detect Disable (bit 5/10) - The LB/CD circuit is disabled. The output, at bit 5/23 and Pin 16 will be at a logic high. 12. Idle Channel Detect Disable (bit 5/18) - Powers down the Idle Channel Detect circuit. Note: The 12-bit reference counter is disabled if the three PLLs are disabled (bits 5/1-3 = 1).
12
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAA A A A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 12. Control Bit Listing (By Register Number)
Register Bit No. 6-0 Power Up Default 1000000 10....0 0 Function (when bit = 1 if appropriate) 1 (23 bits total) Sets the 7-bit Tx A counter for the Tx PLL. 19 - 7 20 Sets the 13-bit Tx N counter for the Tx PLL. Sets the Tx phase detector charge pump output current. 0 = 100 A, and 1 = 400 A. Sets CVSD Decoder minimum step size per Table 3. Sets the 7-bit Rx A' counter for the Rx PLL. Sets the 13-bit Rx N' counter for the Rx PLL. Sets the Rx phase detector charge pump output current. 0 = 100 A, and 1 = 400 A. Sets CVSD Encoder minimum step size per Table 3. Sets the 14-bit counter for the 2nd LO. Sets the LO2 phase detector charge pump output current. 0 = 100 A, and 1 = 400 A. Set the CVSD encoder/decoder for the selected clock rate. (Table 2) Adjusts the VB reference voltage (1.5 V) to improve low battery detection accuracy. Total adjustment range is 9%. Selects the threshold for Low Battery Detection or Carrier Signal Detection. See Table 10. Sets the 12-bit counter for the PLL Reference Clock. Sets the 6-bit counter for the Switched Capacitor Filter clock. Sets the 6-bit counter to set the CVSD Encoder clock rate. Power down the Reference Oscillator Power down the Tx PLL. Power down the Rx PLL. Power down the LO2 PLL. Power down the Rx Data Path. Includes Data Slicer, Clock Recovery, Descrambler, Data Detect, and Status circuits. Power down the CVSD Decoder. Power down the Rx Audio path (Pin 32 to 30). Includes AALPF, LPF, and Gain Adjust circuits. Power down the Power Amplifiers (Pins 27, 28) Power down the Tx Audio Path (Pin 25 to 22). Includes micro-phone amplifier, LPF, and Smoothing LPF circuits. Power down the CVSD Encoder, Idle Channel Detector, 1010 Generator, Tx Data Register, and Scrambler circuits. Power down the Low Battery/Carrier Detect Circuit. Sets the 4-bit counter to set the response delay for the idle channel detect circuit. Sets the idle channel detect threshold level. See Table 4. Power down the Idle Channel Detect Circuit. Inverts the Data Slicer output. Sets the Data Modem mode of operation. Indicates an idle channel condition has been detected (Output). This output is unaffected by bit 7/2. The Status Output (same as Pin 13) is read out from this bit. The output of the Low Battery/Carrier Detect Circuit is read from this bit. 22, 21 2 (23 bits total) 6-0 19 - 7 20 22, 21 3 (24 bits total) 13 - 0 14 16 - 15 20 - 17 23 - 21 4 (24 bits total) 11 - 0 17 - 12 23 - 18 5 (24 bits total) 0 1 2 3 4 5 6 7 8 9 10 14 - 11 17 - 15 18 19 20 21 22 23 00 1000000 10....0 0 00 10....0 0 11 0111 011 $800 100000 100000 0 0 0 0 0 0 0 0 0 0 0 0111 100 0 0 0 N/A N/A N/A
MC33410
MOTOROLA RF/IF DEVICE DATA
13
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 12. Control Bit Listing (By Register Number) (continued)
Power Up Default 0 0 0 0 0 0 01111 00100 0 0 0 0 00 00 010 1 1 0 0 000 000 0 0 0 $000000 $000000 $000000 Register Bit No. 0 1 2 3 4 5 10 - 6 15 - 11 7 (24 bits total) 0 1 2 3 5-4 7-6 10 - 8 11 12 13 14 17 - 15 20 - 18 21 22 23 8 9 10 23 - 0 23 - 0 23 - 0 Function (when bit = 1 if appropriate) 6 (16 bits total) Mutes the power amplifiers (Pins 27 to 29). Mutes the receive speech processing path (Pin 30). Mutes the transmit speech processing path (Pin 22). Selects the Rx 1010 Generator to the CVSD decoder. Selects the Tx 1010 Generator to the scrambler. Sets Carrier Detect Mode vs. Low Battery mode. Provides 19 steps, 1.5 dB each (28.5 dB range), of gain adjust in the receive speech audio path (Pins 32 to 30). See Table 8. Provides 4 steps of 4.0 dB each, for the remote gain adjust in the transmit speech audio path (Pins 23 to 20). Bypass the Clock Recovery Block (Data slicer output goes directly to the descrambler). Bypass the scrambler and descrambler. Disables the automatic idle channel detect at the CVSD encoder. Bit 5/21 is still active. Bypass the Data Detect block (Descrambler output goes directly to the CVSD Decoder). Determines the function for Pin 36 (MP1). See Table 6. Determines the function for Pin 39 (MP2). See Table 7. Selects one of 8 programmable taps in the scrambler and descrambler. See Table 5. Sets the code word size to be sent out via the Tx Data Register to 24 bits. If this bit is 0, the code word size is 16 bits. Sets the data word size to be sent out via the Tx Data Register to 24 bits. If this bit is 0, the data word size is 16 bits. Sets the FTx MC and FRx MC output level to be from ground to VCC. If this bit is 0, the output level is 100 A. Disables the CVSD charge compensation circuit. Test modes for production testing only. Selects the value of the internal capacitor between Pins 43 to 45, to fine tune the LO2 tank circuit. See Table 9. Sets the polarity of the 2nd LO phase detector charge pump output for an inverting low pass filter/VCO combination. Sets the polarity of the Rx phase detector charge pump output for an inverting low pass filter/VCO combination. Sets the polarity of the Tx phase detector charge pump output for an inverting low pass filter/VCO combination. Code word for the Tx Data Register is entered into this register. Data word for the Tx Data Register is entered into this register. The data word received into the Rx Data Register is read out via the P port from this register.
MC33410
14
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 13. Control Bit Listing (By Function) PLL Controls
Register 1 1 2 2 3 4 7 Bit No. 6-0 Power Up Default 1000000 10....0 Function (when bit = 1 if appropriate) Sets the 7-bit Tx A counter for the Tx PLL. 19 - 7 6-0 Sets the 13-bit Tx N counter for the Tx PLL. Sets the 7-bit Rx A' counter for the Rx PLL. 1000000 10....0 10....0 $800 0 19 - 7 13 - 0 11 - 0 13 Sets the 13-bit Rx N' counter for the Rx PLL. Sets the 14-bit counter for the 2nd LO. Sets the 12-bit counter for the PLL Reference Clock. Sets the FTx MC and FRx MC output level to be from ground to VCC. If this bit is 0, the output level is 100 A.
MC33410
AAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PLL Phase Detectors
Register 1 2 3 7 7 7 7 Bit No. 20 20 14 20 - 18 21 22 23 Power Up Default 0 0 0 000 0 0 0 Function (when bit = 1 if appropriate) Sets the Tx phase detector charge pump output current. 0 = 100 A, and 1 = 400 A. Sets the Rx phase detector charge pump output current. 0 = 100 A, and 1 = 400 A. Sets the LO2 phase detector charge pump output current. 0 = 100 A, and 1 = 400 A. Selects the value of the internal capacitor between Pins 43 to 45, to fine tune the LO2 tank circuit. See Table 9. Sets the polarity of the 2nd LO phase detector charge pump output for an inverting low pass filter/VCO combination. Sets the polarity of the Rx phase detector charge pump output for an inverting low pass filter/VCO combination. Sets the polarity of the Tx phase detector charge pump output for an inverting low pass filter/VCO combination.
AAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
CVSD Controls
Register 1 2 3 4 6 6 7 Bit No. 22, 21 22, 21 Power Up Default 00 00 11 Function (when bit = 1 if appropriate) Sets CVSD Decoder minimum step size per Table 3. Sets CVSD Encoder minimum step size per Table 3. 16 - 15 23 - 18 3 4 14 Set the CVSD encoder/decoder for the selected clock rate. (Table 2) Sets the 6-bit counter to set the CVSD Encoder clock rate. Selects the Rx 1010 Generator to the CVSD decoder. Selects the Tx 1010 Generator to the scrambler. Disables the CVSD charge compensation circuit, which affects idle channel performance. 100000 0 0 0
AAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Idle Channel Detector
Register 5 5 5 7 Bit No. Power Up Default 0111 100 Function (when bit = 1 if appropriate) 14 - 11 Sets the 4-bit idle channel counter to set the response delay for the idle channel detect circuit. Sets the idle channel detect threshold level. See Table 4. 17 - 15 21 2 N/A 0 Indicates an idle channel condition has been detected (Output). This output is unaffected by bit 7/2. Disables the automatic idle channel detect at the CVSD encoder. Bit 5/21 is still active.
MOTOROLA RF/IF DEVICE DATA
15
AAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 13. Control Bit Listing (By Function) (continued) Data Transmission/Reception
Register 5 5 5 7 7 7 7 8 9 10 Bit No. 19 20 22 0 3 11 12 23 - 0 23 - 0 23 - 0 Power Up Default 0 0 Function (when bit = 1 if appropriate) Inverts Data Slicer output. Sets Data Modem mode. N/A 0 0 1 1 $000000 $000000 $000000 The Status Output (same as Pin 13) is read out from this bit. A logic 1 indicates the Data Detect register has detected a code word. Bypass the Clock Recovery Block (Data slicer output goes directly to the descrambler). Bypass the Data Detect block (Descrambler output goes directly to the CVSD Decoder). Sets the code word size to be sent out via the Tx Data Register to 24 bits. If this bit is 0, the code word size is 16 bits. Sets the data word size to be sent out via the Tx Data Register to 24 bits. If this bit is 0, the data word size is 16 bits. Code word for the Tx Data Register is entered into this register. Data word for the Tx Data Register is entered into this register. The data word received into the Rx Data Register is read out via the P port from this register.
MC33410
AAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAA AAAA AAA AAAAA AAAAAAAAAAAAAAAAAAAAA A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Scrambler/Descrambler
Register 7 7 Bit No. 1 Power Up Default 0 Function (when bit = 1 if appropriate) Bypass the scrambler and descrambler. 10 - 8 010 Selects one of 8 programmable taps in the scrambler and descrambler. See Table 5.
Multi Purpose Pin Control
Register 7 7 Bit No. 5-4 7-6
Power Up Default 00 00
Function (when bit = 1 if appropriate)
Determines the function for Pin 36 (MP1). See Table 6. Determines the function for Pin 39 (MP2). See Table 7.
Audio Paths
Register 4 6 6 6 6 6
Bit No.
Power Up Default 100000 0 0 0 01111 00100
Function (when bit = 1 if appropriate)
17 - 12 0 1 2 10 - 6 15 - 11
Sets the 6-bit counter for the Switched Capacitor Filter clock. Mutes the power amplifiers (Pins 27 to 29).
Mutes the receive speech processing path (Pin 30).
Mutes the transmit speech processing path (Pin 22). Provides 19 steps, 1.5 dB each (28.5 dB range), of gain adjust in the receive speech audio path (Pins 32 to 30). See Table 8. Provides 4 steps of 4.0 dB each, of gain adjust in the transmit speech audio path (Pins 23 to 20).
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Low Battery/Carrier Detection
Register 3 3 5 6 Bit No. Power Up Default 0111 011 Function (when bit = 1 if appropriate) 20 - 17 23 - 21 23 5 Adjusts the VB reference voltage (1.5 V) to improve low battery detection accuracy. Total adjustment range is 9%. Selects the threshold for Low Battery Detection or Carrier Signal Detection. See Table 10. The output of the Low Battery/Carrier Detect Circuit is read from this bit. Sets Carrier Detect Mode vs. Low Battery Mode N/A 0
16
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 13. Control Bit Listing (By Function) (continued) Power Down Control
Register 5 5 5 5 5 5 5 5 5 5 5 5 Bit No. 0 1 2 3 4 5 6 7 8 9 10 18 Power Up Default 0 0 0 0 0 0 0 0 0 0 0 0 Function (when bit = 1 if appropriate) Power down the Reference Oscillator Power down the Tx PLL. Power down the Rx PLL. Power down the LO2 PLL. Power down the Rx Data Path. Includes Data Slicer, Clock Recovery, Descrambler, Data Detect, and Status circuits. Power down the CVSD Decoder. Power down the Rx Audio path (Pin 32 to 30). Includes AALPF, LPF, and Gain Adjust circuits. Power down the Power Amplifiers (Pins 27, 28) Power down the Tx Audio Path (Pin 25 to 22). Includes micro-phone amplifier, LPF, and Smoothing LPF circuits. Power down the CVSD Encoder, Idle Channel Detector, 1010 Generator, Tx Data Register, and Scrambler circuits. Power down the Low Battery/Carrier Detect Circuit. Power down the Idle Channel Detection Circuit.
MC33410
MOTOROLA RF/IF DEVICE DATA
17
Table 14. Register Map
18
MSB 23 22 20 18 16 13 Bit Tx N Counter Divide Value (Bits 19 - 7) 13 Bit Rx N' Counter Divide Value (Bits 19 - 7) Adjust VB Reference Voltage Set CVSD for the selected Clock Rate LO2 PhD Curr. Sel. 14 bit LO2 Counter Divide Value (Bits 13 - 0) 15 14 13 17 Tx PhDet. Curr. Sel. Rx PhDet. Curr. Sel. 19 CVSD Decoder Minimum Step Size CVSD Encoder Minimum Step Size Sets Low Battery/Carrier Detect Threshold 6 Bit Encode Clock Counter Divide Value LB/CD Det. Out Sets Idle Channel Threshold Level Status Output Idle Chan. Output Data Modem Mode Invert Data Slicer Idle Channel Disable 21 12 6 Bit Switched Capacitor Filter Counter Divide Value 4 Bit Idle Channel Counter Delay Value (Bits 14 - 11) Remote Gain Adjust (Bits 15 - 11) Tx Phase Detector Polarity LO2 Ph. Detector Polarity LO2 Capacitor Select 16 or 24 Bit Code Word for the Tx Data Register (Bits 23 - 0) 16 or 24 Bit Data Word for the Tx Data Register (Bits 23 - 0) 16 or 24 Bit Data Word Output from the Rx Data Register (Bits 23 - 0) Rx Phase Detector Polarity Production Test Modes & Data Modem Mode Idle Charge Disable FTxMC/ FRxMC Level Data Word Size (16/24 bit) 11 13 Bit Tx N Counter Divide Value (Bits 19 - 7) 13 Bit Rx N' Counter Divide Value (Bits 19 - 7) 14 bit LO2 Counter Divide Value (Bits 13 - 0) 12 Bit Reference Counter Divide Value 4 Bit Idle Channel Ctr. Value LB/CD Detect Disable CVSD Encoder Disable Tx Audio Path Disable Remote Gain Adj. Code Word Size (16/24 bit) Scrambler/Descrambler Tap Selection Power Amplifier Disable Rx Audio Path Disable CVSD Decoder Disable Set CD Mode MP2 Mode (See Table 7) Rx Data Path Disable Tx 1010 Generator MP1 Mode (See Table 6) 16 or 24 Bit Code Word for the Tx Data Register (Bits 23 - 0) 16 or 24 Bit Data Word for the Tx Data Register (Bits 23 - 0) 16 or 24 Bit Data Word Output from the Rx Data Register (Bits 23 - 0) LO2 PLL Disable Rx 1010 Generator Bypass Data Detect Rx PLL Disable Mute Tx Audio Disable Idle Chnl. Detection Tx PLL Disable Mute Rx Audio Bypass Scrambler/ Descrambler Ref. Osc. Disable Mute Pwr. Amps Bypass Clock Recovery 10 9 8 7 6 5 4 3 7 Bit Tx A Counter Divide Value 7 Bit Rx A' Counter Divide Value 2 1 LSB 0 Rx Audio Path Gain Adjust (28.5 dB range)
Register Address
Register Number
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
MC33410
1010
10
Register Address
Register Number
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
10
MOTOROLA RF/IF DEVICE DATA
Note: Shaded areas represent output bits to be read out.
MC33410
OUTLINE DIMENSIONS
FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP-48) ISSUE D 0.200 (0.008) AB T-U Z 9 A1
48 37 NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BASIC 0.050 0.150 0.090 0.200 0.500 0.700 12 _REF 0.090 0.160 0.250 BASIC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 BASIC 0.002 0.006 0.004 0.008 0.020 0.028 12 _REF 0.004 0.006 0.010 BASIC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
4X
A
DETAIL Y
P
1
36
-T- B B1
12 25
-U- V AE V1 AE
13
24
-Z- S1 -T-, -U-, -Z- S
4X
DETAIL Y 0.200 (0.008) AC T-U Z
G -AB- -AC- AD
BASE METAL
0.080 (0.003) AC
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
M_
TOP & BOTTOM
R
GAUGE PLANE
0.080 (0.003)
SECTION AE-AE
MOTOROLA RF/IF DEVICE DATA
CCCC EEE CCCC EEE CCCC EEE
F D
M
N
J C E
0.250 (0.010)
AC T-U
S
Z
S
H DETAIL AD
W K X
Q_
19
MC33410
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
20
MC33410/D MOTOROLA RF/IF DEVICE DATA

▲Up To Search▲

Price & Availability of MC33410FTA

	To Download MC33410FTA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .