View MPC974_231967.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3.3V PLL Clock Driver
The MPC974 is a fully integrated PLL based clock generator and clock distribution chip which operates from a 3.3V supply. The MPC974 is ideally suited for high speed, timing critical designs which need a high level of clock fanout. The device features 15 high drive LVCMOS outputs, each output has the capability of driving a 50 parallel terminated transmission line or two 50 series terminated transmission lines on the incident edge.
MPC974
* * * * * * * *
Fully Integrated PLL Two Reference Clock Inputs for Redundant Clock Applications High Impedance Output Control Logic Enable on the Outputs 3.3V VCC Supply Output Frequency Configurable TQFP Packaging 100ps Typical Cycle-to-Cycle Jitter
LOW VOLTAGE PLL CLOCK DRIVER
The MPC974 features 3 independent frequency programmable banks of outputs. The frequency programmability offers the capability of establishing output frequency relationships of 1:1, 2:1, 3:1, 3:2 and 3:2:1. In addition, the device features a separate feedback output which allows for a wide variety of input/output frequency multiplication alternatives. FA SUFFIX The VCO_Sel pin provides an extended VCO lock range for added 52-LEAD TQFP PACKAGE flexibility and general purpose usage. CASE 848D-03 The TCLK0 and TCLK1 inputs provide a method for dynamically switching the PLL between two different clock sources. The PLL has been optimized to provide small deviations in output pulse width and well controlled, slow transition back to lock when the inputs are switched between two references that are equal in frequency but out of phase with each other. This feature makes the MPC974 an ideal solution for fault tolerant applications which require redundant clock sources. All of the control pins are LVTTL/LVCMOS level inputs. The Fsel pins control the VCO divide ratios that are applied to the various output banks and the feedback output. The MR input will reset the internal flip flops and place the outputs in high impedance when driven LOW. The OE pin will force all of the outputs except the feedback output LOW to allow for acquiring phase lock prior to providing clocks to the rest of the system. Note that the OE pin is not synchronized to the internal clock. As a result, the initial pulse after de-assertion of the OE pin may be distorted. The PLL_En pin allows the PLL to be bypassed for board level functional test. When bypassed the signal on the selected TCLK will be routed around the PLL and will drive the internal dividers directly. The MPC974 is packaged in the 52-lead TQFP package to provide optimum electrical performance as well as minimize board space requirements. The device is specified for 3.3V VCC.
1/97
(c) Motorola, Inc. 1997
1
REV 2
MPC974
GNDFB VCCFB 28 Ext_FB GNDb GNDb VCCb VCCb
QFB
Qb1
Qb2
Qb3
Qb4
39 Qb0 VCCb NC GNDc Qc3 VCCc Qc2 GNDc Qc1 VCCc Qc0 GNDc VCO_Sel 40 41 42 43 44 45 46 47 48 49 50 51 52 1
38
37
36
35
34
33
32
31
30
29
NC 27 26 25 24 23 22 21 VCCa Qa0 GNDa Qa1 VCCa Qa2 fselFB1 GNDa Qa3 VCCa Qa4 GNDa fselFB0 20 19 18 17 16 15 14 13 VCCA
MPC974
2
3
4
5
6
7
8
9
10
11
12
PLL_EN
GNDI
TClk_Sel
TClk0
Figure 1. 52-Lead Pinout (Top View)
FUNCTION TABLE 1
fsela 0 1 Qa /2 /4 fselb 0 1 Qb /2 /4 fselc 0 1 Qc /4 /6
FUNCTION TABLE 2
fselFB0 0 0 1 1 fselFB1 0 1 0 1 QFB /4 /6 /8 /12
FUNCTION TABLE 4
Control Pin MR PLL_EN TClk_Sel OE Logic `0' Master Reset/Output High Z Bypass PLL TCLK0 Qa, Qb, Qc Logic LOW Logic `1' - Enable PLL TCLK1 All Outputs Enabled
FUNCTION TABLE 3
VCO_Sel 0 1 fVCO VCO/2 VCO/4
MOTOROLA
2
TClk1
VCCI
MR
fselb
fsela
OE
fselc
NC
TIMING SOLUTIONS BR1333 -- Rev 6
MPC974
fsela TCLK_Sel TCLK0 TCLK1 FB_In PLL_EN VCO_Sel
(Int. Pulldown) (Int. Pulldown) (Int. Pulldown) (Int. Pullup)
0 1 PLL
0 1
/2 /4
0 1 0 1 /2 /4 /6 R 0 1 D Q R 0 1 D Q R 5
(Int. Pullup)
Qa0:4
(Int. Pullup) (Int. Pulldown)
5
fselb
(Int. Pulldown)
Qb0:4
D Q R
4
fselc
(Int. Pulldown)
Qc0:3
MR
(Int. Pullup)
0 1 fselFB1 fselFB0 OE
(Int. Pulldown) (Int. Pulldown)
/2
0 1
D Q R QFB
(Int. Pullup)
Figure 2. Logic Diagram
ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 5.6 VDD + 0.3 8 125 Unit V V mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
DC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol VIH VIL VOH VOL IIN ICC CIN Cpd Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Maximum Quiescent Supply Current Input Capacitance Power Dissipation Capacitance 25 2.4 0.5 100 120 8 Min 2.0 Typ Max VCC 0.8 Unit V V V V A mA pF pF Per Output IOH = -20mA (Note 1.) IOL = 20mA (Note 1.) Note 2. Condition
1. The MPC974 outputs can drive series or parallel terminated 50 (or 50 to VCC/2) transmission lines on the incident edge (see Applications Info section). 2. Inputs have either pull-up or pull-down resistors which affect input current.
TIMING SOLUTIONS BR1333 -- Rev 6
3
MOTOROLA
MPC974
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70C)
Symbol tr, tf fref frefDC Characteristic TCLK Input Rise/Falls Reference Input Frequency Reference Input Duty Cycle Note 3. 25 Min Max 3.0 Note 3. 75 Unit ns MHz % Condition
3. Input reference frequency is limited by the divider selection and the VCO lock range.
AC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol tr, tf tpw fVCO tpd tos fmax Characteristic Output Rise/Fall Time (Note 4.) Output Duty Cycle (Note 4.) PLL VCO Lock Range fseln, fselFBn = /4 to /12 SYNC to Feedback Propagation Delay Output-to-Output Skew Maximum Output Frequency Q (/2) Q (/4) Q (/6) 2 2 100 10 Min 0.15 tCYCLE/2 -800 200 -250 tCYCLE/2 500 Typ Max 1.5 tCYCLE/2 +800 500 100 350 125 63 42 10 10 ps ps MHz Notes 4., 6. Note 4. VCO_Sel = 0 Unit ns ps MHz Note 5. Condition 0.8 to 2.0V
tPZL tPLZ, tPHZ tjitter tlock
Output Enable Time Output Disable Time Cycle-to-Cycle Jitter (Peak-to-Peak) Maximum PLL Lock Time
ns ns ps ms
4. 50 transmission lines terminated to VCC/2. 5. The PLL will be unstable if the total divide between the VCO and the feedback pin is less < 8. VCO_SEL = `0', fsela or fselb = `0' cannot be used for the PLL feedback signal. 6. tpd is specified for 50MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. The tpd does not include jitter.
APPLICATIONS INFORMATION
Programming the MPC974 The MPC974 clock driver outputs can be configured into several frequency relationships, in addition the external feedback option allows for a great deal of flexibility in establishing unique input-to-output frequency relationships. The output dividers for the four output groups allows the user to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1 frequency ratios. The use of even dividers ensures that the output duty cycle is always 50%. Function Table 1 illustrates the various output configurations, the table describes the outputs using the VCO frequency as a reference. As an example for a 3:2:1 relationship the Qa outputs would be set at VCO/2, the Qb's and Qc's at VCO/4 and the Qd's at VCO/6. These settings will provide output frequencies with a 3:2:1 relationship. The division settings establish the output relationship, but one must still ensure that the VCO will be stable given the frequency of the outputs desired. The VCO lock range can be found in the specification tables. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL is such that for output frequencies between 10 and 125MHz the MPC974 can generally be configured into a stable region. The relationship between the input reference and the output frequency is also very flexible. The separate PLL feedback output allows for a wide range of output vs input frequency relationships. Function Table 1 can be used to identify the potential relationships available. Figure 3 illustrates several programming possibilities, although not exhaustive it is representative of the potential applications. Using the MPC974 as a Zero Delay Buffer The external feedback option of the MPC974 clock driver allows for its use as a zero delay buffer. By using one of the outputs as a feedback to the PLL the propagation delay through the device is near zero. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The static phase offset is a function of the input reference frequency of the MPC974. The Tpd of the device is specified in the specification tables.
MOTOROLA
4
TIMING SOLUTIONS BR1333 -- Rev 6
MPC974
5 5 4 5 5 4
33MHz
TCLK FB_In
Qa Qb Qc
66MHz 66MHz 33MHz
33MHz
TCLK FB_In
Qa Qb Qc
100MHz 50MHz 33MHz
QFB 33MHz fsela 0 fselb 0 fselc 0 fselFB 00 VCO_Sel 0 fsela 0 33MHz fselb 1
QFB
fselc 1
fselFB 10
VCO_Sel 0
25MHz
TCLK FB_In
Qa Qb Qc
5 5 4
100MHz 50MHz 33MHz
50MHz
TCLK FB_In
Qa Qb Qc
5 5 4
50MHz 50MHz 50MHz
QFB 25MHz fsela 0 fselb 1 fselc 1 fselFB 01 VCO_Sel 0 fsela 1 50MHz fselb 1
QFB
fselc 0
fselFB 00
VCO_Sel 0
Figure 3. MPC974 Programming Schemes To minimize part-to-part skew the external feedback option again should be used. The PLL in the MPC974 decouples the delay of the device from the propagation delay variations of the internal gates. From the specification table one sees a Tpd variation of only 150ps, thus for multiple devices under identical configurations the part-to-part skew will be around 850ps (300ps for Tpd variation plus 350ps output-to-output skew plus 200ps for jitter). To minimize this value, the highest possible reference frequencies should be used. Higher reference frequencies will minimize both the tpd parameter as well as the input to output jitter. Power Supply Filtering The MPC974 is a mixed analog/digital product and exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC974 provides separate power supplies for the output buffers (VCCO) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC974. Figure 4. Power Supply Filter Figure 4 illustrates a typical power supply filter scheme. The MPC974 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC974. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 4 must have a resistance of 10-15 to meet
3.3V
RS=5-15 VCCA 22F MPC974 VCC 0.01F 0.01F
TIMING SOLUTIONS BR1333 -- Rev 6
5
MOTOROLA
MPC974
the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC974 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC974 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D).
3.0 OutA tD = 3.8956 OutB tD = 3.9386
When taken to its extreme the fanout of the MPC974 clock driver is effectively doubled due to its capability to drive multiple lines. The waveform plots of Figure 6 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC974 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC974. The output waveform in Figure 6 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal:
2.5
VOLTAGE (V)
2.0 In 1.5
1.0 MPC974 OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutA 0 2 MPC974 OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutB1 4 6 8 TIME (nS) 10 12 14
0.5
Figure 6. Single versus Dual Waveforms
RS = 43 ZO = 50 OutB0
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 7 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use.
Figure 5. Single versus Dual Transmission Lines In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC974 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 5 illustrates an output driving a single series terminated line vs two series terminated lines in parallel.
MOTOROLA
6
TIMING SOLUTIONS BR1333 -- Rev 6
MPC974
MPC974 OUTPUT BUFFER 7
RS = 36
ZO = 50
RS = 36
ZO = 50
7 + 36 k 36 = 50 k 50 25 = 25
Figure 7. Optimized Dual Line Termination
TIMING SOLUTIONS BR1333 -- Rev 6
7
MOTOROLA
MPC974
OUTLINE DIMENSIONS
FA SUFFIX TQFP PACKAGE CASE 848D-03 ISSUE C
C L
4X 4X TIPS
-X- X=L, M, N
AB AB
G
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N
52 1
40 39
VIEW Y F
BASE METAL
3X VIEW
Y -M- B V
PLATING
-L-
J
B1
13 14 26 27
V1
0.13 (0.005)
SECTION AB-AB
ROTATED 90_ CLOCKWISE
A1 S1 A S
-N-
C -H- -T-
SEATING PLANE
4X
2 0.10 (0.004) T
4X
3 VIEW AA
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _
0.05 (0.002)
S
W 1 C2
2XR
R1
0.25 (0.010)
GAGE PLANE
K C1 E Z VIEW AA
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
MOTOROLA
8
CCCC EEEE CCCC EEEE
M
U
D T L-M
S
N
S
TIMING SOLUTIONS BR1333 -- Rev 6
MPC974
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
TIMING SOLUTIONS BR1333 -- Rev 6
9
MPC974/D MOTOROLA

▲Up To Search▲

Price & Availability of MPC974

	To Download MPC974 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .