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LIN-Transceiver LDO
Target Data Sheet
1 1.1 * * * * * * * * * * * * * * * * * Overview Features
TLE 6285
Single-wire transceiver, suitable for LIN protocol Transmission rate up to 20 kBaud Compatible to LIN specification Compatible to ISO 9141 functions Very low current consumption in sleep mode Control output for voltage regulator Short circuit proof to ground and battery Overtemperature protection Output voltage 5V, tolerance 2 % 150 mA output current capability Low-drop voltage Overtemperature protection Reverse polarity protection Short-circuit proof Adjustable reset threshold Wide temperature range Suitable for use in automotive electronics
P-DSO-16-4
Type TLE 6285 G
Ordering Code on request
Package P-DSO-16-4
1.2
Description
The TLE 6285 is a single-wire transceiver with a LDO. It is chip by chip integrated circuit in a P-DSO-16-4 package. It works as an interface between the protocol controller and the physical bus. The TLE 6285 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. In order to reduce the current consumption the TLE 6285 offers a sleep operation mode. In this mode a voltage regulator can be controlled in order to minimize the current consumption of the whole application (VR in sleep mode <1A!). The on-chip voltage regulator (VR) is designed for this application but it is also possible to use an external
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Target Data TLE 6285
voltage regulator. A wake-up caused by a message on the bus enables the voltage regulator and sets the RxD output low until the device is switched to normal operation mode. To achieve proper operation of the C, the device supplies a reset signal. The reset delay time is selected application specific by an external capacitor. The reset threshold is adjustable. The IC is based on the Smart Power Technology SPT(R) which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuit. The TLE 6285 is designed to withstand the severe conditions of automotive applications.
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1.3
Pin Configuration (top view)
GND
1
16
GND
INHI
2
15
RD
RO
3
14
RTh
VCCO
4
13
VBAT
INHO
5
12
BUS
RxD
6
11
TxD
ENLIN
7
10
VCCI
GND
8
9
GND
P-DSO-16-4
GND INHI RO VCCO INHO RxD ENLIN GND
1
Leadframe
16
GND RD RTh VBAT BUS TxD VCCI GND
2
15
3
Chip: Voltage Regulator
14
4
13
5
12
6
Chip: Transceiver
11
7
10
8
9
P-DSO-16-4
Figure 1
Pinout
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1.4 Pin No. 1,8,9,16 2 3 4 5 6 7 10 11 12 13
Pin Definitions and Functions: Symbol GND INHI RO VCCO INHO RxD ENLIN VCCI TxD BUS VBAT Function Ground; place to cooling tabs to improve thermal behavior Inhibit Voltage Regulator Input; TTL compatible, HIGH active (HIGH switches the VR on); connect to VBAT if not needed Reset Output; open collector output connected to the output via a resistor of 20kW 5V Output; connected to GND with 22F capacitor, ESC<3W Inhibit LIN Output; to control a voltage regulator Receive Data Output; internal 30kW pull up to Vs, LOW in dominat state Enable LIN Input; integrated 30kW pull down, transceiver in normal operation mode when HIGH 5V Supply Input; VCC input to supply the LIN transceiver Transmit Data Input; internal 30kW pull up to Vs, LOW in dominant state LIN BUS Output/Input; internal 30kW pull up to Vs, LOW in dominant state Battery Supply Input; a reverse current protection diode is required, block GND with 100nF ceramic capacitor and 22F capacitor Reset Threshold; internal defined typical 4.6V, adjustable down to 3.5V according to the voltage level on this pin; connect to GND if not needed Reset delay; connected to ground via external delay capacitor
14
RTh
15
RD
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1.5
Functional Block Diagram
VBAT
13
5
INHO VCCI ENLIN
10
30 k9 Bus
12
Output Stage
Driver Temp.Protection
Mode Control 30 k9
7
11
TxD
Receiver
6
RxD
TLE 6259 G
5
GND
TLE 4299
13 VBat I
BandGapReference Current and Saturation Control
4Q VCCO
RSO
INHI 2 INH
Inhibit Control
RRO
SO
SI Reference Reset Control
3RO RO
RTh 14 RADJ
1,8,9,16 15
D GND
RD
GND
AEB03104
Figure 2
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Block Diagram
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Target Data TLE 6285
2
Circuit Description
The TLE 6285 is a single-wire transceiver combined with a LDO. It is a chip by chip integrated circuit in a P-DSO-16-4 package. It works as an interface between the protocol controller and the physical bus. The TLE 6285 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. The on-chip voltage regulator with watchdog is designed for sleep mode applications but it is also possible to use an external voltage regulator.
Start Up Power Up
Normal Mode ENLIN INHO VCC ON high high
ENLIN high
ENLIN
low
Stand-By
ENLIN INHO RxD VCC low high low1) ON high3)
ENLIN (VCC
high ON)
Sleep Mode ENLIN INHO VCC low floating OFF2)
1) 2) 3)
Wake Up t > tWAKE
after wake-up via bus ON when INHO not connected to INHI after start up
Figure 3 2.1
Operation Mode State Diagram
Operation Modes
In order to reduce the current consumption the TLE 6285 offers a sleep operation mode. This mode is selected by switching the enable input EN low (see figure 3, state diagram). In the sleep mode a voltage regulator can be controlled via the INHO output in order to minimize the current consumption of the whole application. A wake-up caused by a message on the communication bus automatically enables the voltage regulator by switching the INHO output high. In parallel the wake-up is indicated by setting the RxD output low. When entering the normal mode this wake-up flag is reset and the RxD output is released to transmit the bus data.
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In case the voltage regulator control input is not connected to INH output or the microcontroller is active respectively, the TLE6285 can be set in normal operation mode without a wake-up via the communication bus. 2.2 LIN Transceiver
The LIN Transceiver has already a pull up resistor of 30kW as termination implemented. There is also a diode in this path, to protect the circuit from feedback of voltages from the bus line to the power supply. To configure the TLE 6285 as a master node, an additional external termination resistor of 1kW is required. To avoid reverse currents from the bus line into the battery supply line in case of an unpowered node, it is also recommended to place a diode in series to the external pull up. For small systems (low bus capacitance) the EMC performance of the system is supported by an additional capacitor of at least 1nF in the master node (see figure 6, application circuit). An capacitor of 10F at the supply voltage input VS buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. 2.3 Input Capacitor
The input capacitor CI is necessary for compensation of line influences. Using a resistor of approx. 1 W in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values 22 mF and an ESR of 5 W within the operating temperature range. For small tolerances of the reset delay the spread of the capacitance of the delay capacitor and its temperature coefficient should be noted. 2.4 Voltage regulator
The 6285 incorporates a PNP based very low drop linear voltage regular. It regulates the output voltage to VCC = 5 V for an input voltage range of 5.5 V VI 45 V. The control circuit protects the device against potential caused by damages overcurrent and overtemperature. The internal control circuit achieves a 5 V output voltage with a tolerance of 2% in the temperature range of Tj = - 40 to 150 C. The device includes a power on reset and an under voltage reset function with adjustable reset delay time and adjustable reset switching threshold as well as a sense control/early warning function. The device includes an inhibit function to disable it when the ECU is not used for example while the motor is off. The reset logic compares the output voltage VCC to an internal threshold. If the output voltage drops below this level, the external reset delay capacitor CD is discharged. When VD is lower than VLD, the reset output RO is switched Low. If the output voltage drop is
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very short, the VLD level is not reached and no reset-signal is asserted. This feature avoids resets at short negative spikes at the output voltage e.g. caused by load changes. As soon as the output voltage is more positive than the reset threshold, the delay capacitor is charged with constant current. When the voltage reaches VUD the reset output RO is set High again. The reset threshold is either the internal defined VRT voltage (typical 4.6 V) or can be lowered by a voltage level at the RTh input down to 3.5 V. The reset delay time and the reset reaction time are defined by the external capacitor CD. The reset function is active down to VI = 1 V. The device is capable to supply 150 mA. For protection at high input voltage above 25 V, the output current is reduced (SOA protection). 2.5 Reset
The power on reset feature is necessary for a defined start of the microprocessor when switching on the application. For the reset delay time after the output voltage of the regulator is above the reset threshold, the reset signal is set High again. The reset delay time is defined by the reset delay capacitor CD at pin RD (refer to figure 4 and 5). The under-voltage reset circuitry supervises the output voltage. In case VQ decreases below the reset threshold the reset output is set LOW after the reset reaction time. The reset LOW signal is generated down to an output voltage VCC to 1 V. Both the reset reaction time and the reset delay time is defined by the capacitor value. The power on reset delay time is defined by the charging time of an external delay capacitor CD.
CD = (td ID) / DV
With
[1]
CD td
DV DV
ID
reset delay capacitor reset delay time = VUD, typical 1.8 V for power up reset = VUD - VLD typical 1.35 V for undervoltage reset charge current typical 6.5 mA
For a delay capacitor CD =100 nF the typical power on reset delay time is 28 ms. The reset reaction time tRR is the time it takes the voltage regulator to set reset output LOW after the output voltage has dropped below the reset threshold. It is typically 1 ms for delay capacitor of 100 nF. For other values for CD the reaction time can be estimated using the following equation:
tRR = 10 ns / nF CD
[2]
The reset output is an open collector output with a pull-up resistor of typical 20 kW to Q. An external pull-up can be added with a resistor value of at least 5.6 kW.
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In addition the reset switching threshold can be adjusted by an external voltage divider. The feature is useful for microprocessors which guarantee safe operation down to voltages below the internally set reset threshold of 4.65 V typical. If the internal used reset threshold of typical 4.65 V is used, the pin RADJ has to be connected to GND. If a lower reset threshold is required by the system, a voltage divider defines the reset threshold VRth between 3.5 V and 4.60 V:
VRth = VRADJ TH (R1 + R2) / R2 VRADJ TH is typical 1.36 V.
[3]
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3 3.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. Unit Remarks
Parameter
Voltages Supply voltage Battery supply voltage Bus input voltage Bus input voltage Logic voltages at EN, TxD, RxD Input voltages at INH Output current at INH Reset output voltage Reset delay voltage Output voltage Vcc INHIBIT voltage Reset Threshold voltage Reset Threshold current Electrostatic discharge voltage at Vs, Bus Electrostatic discharge voltage Temperatures Junction temperature
VCC VS Vbus Vbus VI VINH IINH VR VD VQ VINH VTh ITh VESD VESD
-0.3 -0.3 -20 -20 -0.3 -0.3
6 40 32 40
V V V V V V mA V V V V V mA kV kV human body model (100 pF via 1.5 kW) human body model (100 pF via 1.5 kW) t<1s 0 V < VCC < 5.5 V
VCC
+ 0.3
VS
+ 0.3 1
- 0.3 - 0.3 - 0.3 - 40 - 0.3 - 10 -4 -2
7 7 7 45 7 10 4 2
Tj
-40
150
C
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
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3.2
Operating Range Symbol Limit Values min. max. 5.5 20 150 V V C
-
Parameter Supply voltage Battery Supply Voltage Junction temperature
Unit
Remarks
VCC VS Tj
4.5 6 - 40
Thermal Shutdown (junction temperature) Thermal shutdown temp. Thermal shutdown hyst. Thermal Resistances Junction ambient LIN Junction ambient Vreg
TjSD
DT
150 -
170 10
190 -
C K
Rthj-a Rthj-a
- -
185 70
K/W K/W
- -
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3.3
Electrical Characteristics
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Current Consumption LIN Current consumption Current consumption Current consumption Current consumption Current consumption Current consumption Current Consumption Vreg Current consumption; Iq = II - IQ Current consumption; Iq = II - IQ Current consumption; Iq = II - IQ Current consumption; Iq = II - IQ Current consumption; Iq = II - IQ Receiver Output RD HIGH level output current LOW level output current
ICC IS ICC IS IS IS
0.5 0.5 0.7 0.7 20 20
1.5 1.0 2.0 1.5 30 40
mA mA mA mA A A
recessive state; VTxD = VCC recessive state; VTxD = VCC dominant state; VTxD = 0 V dominant state; VTxD = 0 V sleep mode; Tj = 25 C sleep mode
Iq Iq Iq Iq Iq
- - - - -
65 65 170 0.7 -
105 100 500 2 1
mA mA mA mA mA
Inhibit ON; IQ 1 mA, Tj < 85 C Inhibit ON; IQ 1 mA, Tj = 25 C Inhibit ON; IQ = 10 mA Inhibit ON; IQ = 50 mA VINHI = 0 V; Tj = 25 C
IRD,H IRD,L
-0.7 0.4 0.7
-0.4
mA mA
VRD = 0.8 x VCC, VRD = 0.2 x VCC,
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3.3
Electrical Characteristics (cont'd)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Bus receiver Receiver threshold voltage, recessive to dominant edge Receiver threshold voltage, dominant to recessive edge Receiver hysteresis wake-up threshold voltage
Vbus,rd Vbus,dr
0.44 x VS
0.48 x VS 0.52 x VS 0.04 x VS 0.55 x VS 0.56 x VS 0.06 x VS 0.70 x VS
V V mV V
-8 V < Vbus < Vbus,dom Vbus,rec < Vbus < 20 V Vbus,hys = Vbus,rec - Vbus,dom
Vbus,hys 0.02 x VS Vwake 0.40 x VS
Transmission Input TD HIGH level input voltage threshold TxD input hysteresis LOW level input voltage threshold TxD pull up current Bus transmitter Bus recessive output voltage Vbus,rec 0.9 x
VTD,H VTD,hys VTD,L
300
2.9 600
0.7 x
V mV V
recessive state
VCC
0.3 x 2.1
dominant state
VCC
ITD
-150
-110
-80
A
VTxD < 0.3 Vcc
VS
1.5 85 -100 5 20 47 125
V V mA mA mA kW
VTxD = VCC VTxD = 0 V; Vbus,short = 13.5 V VCC = 0 V, VS = 0 V, Vbus = -8 V, Tj < 85 C VCC = 0 V, VS = 0 V, Vbus = 20 V, Tj < 85 C
VS
Bus dominant output voltage Vbus,dom 0 Bus short circuit current Ibus,sc 40 Leakage current
Ibus,lk
-350
Bus pull up resistance
Rbus
20
30
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3.3
Electrical Characteristics (cont'd)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Enable input (pin ENLIN) HIGH level input voltage threshold LOW level input voltage threshold EN input hysteresis EN pull down resistance Inhibit output (pin INHO) HIGH level drop voltage DVINH = VS - VINH Leakage current
VEN,on VEN,off VEN,hys REN
2.8 0.3 x 2.2
0.7 x
V V mV
normal mode
VCC
low power mode
VCC
300 15 600 30 60 kW
DVINH
IINH,lk
- 5.0
0.5
1.0 5.0
V A
IINHO = - 0.15 mA sleep mode; VINHO = 0 V
Vcc Output (pin Vcco) Output voltage Output voltage Current limit Drop voltage Load regulation Line regulation Power Supply Ripple rejection Output voltage Output voltage
VQ VQ IQ Vdr
DVQ DVQ PSRR
4.90 4.85 250 - - - - 4.90 4.90
5.00 5.00 400 0.22 5 10 66 5.00 5.00
5.10 5.15 500 0.5 30 25 - 5.10 5.10
V V mA V mV mV dB V V
1 mA IQ 100 mA; 6 V VI 16 V IQ 150 mA; 6 V VI 16 V - IQ = 100 mA1) IQ = 1 mA to 100 mA VI = 6 V to 28 V; IQ = 1 mA fr = 100 Hz; Vr = 1 VSS; IQ = 100 mA 5 mA IQ 150 mA; 6 V VI 28 V 6 V VI 32 V; IQ = 100 mA; Tj = 100 C
VQ VQ
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3.3
Electrical Characteristics (cont'd)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Reset Generator (pins RO,RD)
Switching threshold Reset pull up Reset low voltage External reset pull up Delay switching threshold Switching threshold Reset delay low voltage Charge current Reset delay time Reset reaction time Reset adjust switching threshold Inhibit Input (pin INHI) Inhibit OFF voltage range Inhibit ON voltage range High input current Low input current
Note: The reset output is low within the range VQ = 1 V to VQ,rt 1) Drop voltage = Vi - VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 6 V input)
Vrt RRO VR VR ext VDT VST VD Ich td trr VRADJ TH
4.50 10 - 5.6 1.5 0.40 - 4.0 17 0.5 1.26
4.60 20 0.17 - 1.85 0.50 - 8.0 28 1.2 1.36
4.80 40 0.40 - 2.2 0.60 0.1 12.0 35 3.0 1.44
V kW V kW V V V mA ms ms V
- - VQ < 4.5 V; internal RRO; IR = 1 mA Pull up resistor to Q - - VQ < VRT VD = 1 V CD = 100 nF CD = 100 nF VQ > 3.5 V
VINH
OFF
-
- - 3 0.5
0.8 - 5 2
V V mA mA
VQ off VQ on VINHI = 5 V VINHI = 0 V
VINH ON 3.5 IINH ON - IINH OFF -
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3.3
Electrical Characteristics (cont'd)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Dynamic Transceiver Characteristics falling edge slew rate
Sbus(L)
-3
-2.0
-1
V/s
80% > Vbus > 20% Cbus= 3.3 nF; Tambient < 85 C; VCC = 5 V; VS = 13.5 V 20% < Vbus < 80% Cbus= 3.3 nF; VCC = 5 V; VS = 13.5 V Cbus = 3.3nF; VCC = 5 V; VS = 13.5 V CRxD = 20 pF Cbus = 3.3 nF; VCC = 5 V; VS = 13.5 V CRxD = 20 nF VCC = 5 V VCC = 5 V VCC = 5V; CRxD = 20pF VCC = 5 V; CRxD = 20 pF tsym,R = td(L),R - td(H),R tsym,T = td(L),T - td(H),T
rising edge slew rate
Sbus(H)
1 2
1.5 5
3 10
V/s s
Propagation delay td(L),TR TxD-to-RxD LOW (recessive to dominant) Propagation delay td(H),TR TxD-to-RxD HIGH (dominant to recessive) Propagation delay TxD LOW to bus Propagation delay TxD HIGH to bus Propagation delay bus dominant to RxD LOW Propagation delay bus recessive to RxD HIGH Receiver delay symmetry Transmitter delay symmetry Wake-up delay time
2
5
10
s
td(L),T td(H),T td(L),R td(H),R tsym,R tsym,T twake
-2 -2 30
1 1 1 1
4 4 4 4 2 2
s s s s s s s
100
200
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4
Diagrams
VI
< trr
VQ VQ, rt VD VDU VDRL
dV ID, ch = dt CD
t
t
trd
VRO
trr
t
t
Power-ON Reset Overtemperature Voltage Drop at Input Undervoltage Secondary Load Bounce Spike
AET03066
Figure 4
Time Response, Watchdog with High-Frequency Clock
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Typical Performance Characteristics Output Voltage VQ versus Temperature Tj
5.2 VQ V 5.1 V = 13.5 V 5.0
8
AED01671
Output Voltage VQ versus Input Voltage VI
12 VQ V 10
AED01808
4.9
6
RL = 50
4.8
4
4.7
2
4.6 -40
0
40
80
120 C 160 Tj
0
0
2
4
6
8 V
V 10
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Charge Current Ich versus Temperature Tj
12
AED03108
Drop Voltage Vdr versus Output Current IQ
400 mV 125 C 300
AED02929
ID A
10
VDR
8
VI = 13.5 V VD = 1 V
250 200 150 100
25 C
6
4
2
50
0 -40
0
40
80
120 C 160
0
0
50
100
150 mA 200
Tj
IQ
Switching Voltage Vdt and Vst versus Temperature Tj
3.2 VD V 2.8 V = 13.5 V 2.4 2.0 1.6 1.2 0.8 VLD 0.4 0 -40 VUD
AED01804
Reset Adjust Switching Threshold VRADJTH versus Temperature Tj
1.5 V
AED03109
VRADJTH
1.4
1.3
1.2
1.1
1.0
0
40
80
120 C 160 Tj
0.9 -40
0
40
80
120 C 160
Tj
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Sense Threshold Vsi versus Temperature Tj
1.6
AED02933
Output Current Limit IQ versus Input Voltage VI
350
AED03110
VSi
V 1.5 Sense Output High
Q mA
300 250
1.4 Sense Output Low
200 Tj = 25 C
1.3
150 Tj = 125 C
1.2
100
1.1
50 0
1.0 -40
0
40
80
120 C 160
0
10
20
30
40 V 50 V
Tj
Current Consumption Iq versus Output Current IQ
1.0 mA 0.8
AED02931
Current Consumption Iq versus Output Current IQ
5 mA 4
AED02932
Iq
Iq
0.6
3
0.4
2
0.2
1
0
0
10
20
30
40
mA 60
0
0
50
100
150 mA 200
IQ
IQ
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5
Application
Vbat LIN bus
master node
13
VBAT
RO ENLIN
3 7 6
22 F 100 nF 1 k
12 5
RxD Bus INHO
P
TxD 11 VCCI 10
100 nF
GND
100 nF
TLE 6285 G
2
INHI
VCCO
4
5V
R1
15
RD
GND
RTh
14
22 F
R2
CD 100 nF
1,8,9,16
ECU 1
slave node
13
VBAT
RO ENLIN
3 7 6
22 F 100 nF
12 5
RxD Bus INHO
P
TxD 11 VCCI 10
100 nF
GND
100 nF
TLE 6285 G
2
INHI
VCCO
4
5V
R1
15
RD
GND
RTh
14
22 F
R2
CD
1,8,9,16
100 nF
ECU X
Figure 5
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Application Circuit
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Target Data TLE 6285
6
Package Outlines P-DSO-16-4 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Dimensions in mm
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Edition 1999-10-12 Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541 Munchen
(c) Infineon Technologies AG1999 All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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