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DM93L14 Quad Latch
June 1989 Revised November 1999
DM93L14 Quad Latch
General Description
The DM93L14 is a multifunctional 4-bit latch designed for general purpose storage applications in high speed digital systems. All outputs have active pull-up circuitry to provide high capacitance drive and to provide low impedance in both logic states for good noise immunity.
Features
s Can be used as single input D latches or set/reset latches s Active low enable gate input s Overriding master reset
Ordering Code:
Order Number DM93L14N Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
VCC = Pin 16 GND = Pin 8
Pin Descriptions
Pin Names E D0 - D3 S0 - S3 MR Q0 - Q3 Description Enable Input (Active LOW) Data Inputs Set Inputs (Active LOW) Master Reset Input (Active LOW) Latch Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS009612
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DM93L14
Functional Description
The DM93L14 consists of four latches with a common active LOW Enable input and active LOW Master Reset input. When the Enable goes HIGH, data present in the latches is stored and the state of the latch is no longer affected by the Sn and Dn inputs. the Master Reset when activated overrides all other input conditions forcing all latch outputs LOW. Each of the four latches can be operated in one of two modes: D-TYPE LATCH--For D-type operation the S input of a latch is held LOW. While the common Enable is active the latch output follows the D input. Information present at the latch output is stored in the latch when the Enable goes HIGH. SET/RESET LATCH--During set/reset operation when the common Enable is LOW a latch is reset by a LOW on the D input, and can be set by a LOW on the S input if the D input is HIGH. If both S and D inputs are LOW, the D input will dominate and the latch will be reset. When the Enable goes HIGH, the latch remains in the last state prior to disablement. The two modes of latch operation are shown in the Truth Table.
Truth Table
MR H H H H H H H H L E L L H L L L L H X D L H X L H L H X X S L L X L L H H X X Qn L L Qn-1 L H L Qn-1 Qn-1 L RESET R/S Mode Operation D Mode
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Qn-1 = Previous Output State Qn = Present Output State
Logic Diagram
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DM93L14
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA tS (H) tS (L) tH (H) tH (L) tS (H) tH (L) tW (L) tW (L) tREC Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW Dn to E Hold Time HIGH or LOW Dn to E Setup time HIGH, Dn to Sn Hold time LOW, Dn to Sn Parameter Min 4.5 2 0.7 Nom 5 Max 5.5 Units V V V
-400
4.8
A
mA
-55
10 20 0 10 15 5 30 25 5
125
C
ns ns ns ns ns ns ns
E Pulse Width LOW MR Pulse Width LOW
Recovery time, MR to E
3
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DM93L14
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current
Note 2: All typicals are at VCC = 5V, TA = 25C Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs open and all inputs grounded.
Conditions VCC = Min, II = -10 mA VCC = Min, IOH = Max, VIL = Max, VIH = Min VCC = Min, IOL = Max, VIH = Min, VIL = Max VCC = Max, VI = 5.5V VCC = Max, VI = 2.4V VCC = Max, VI = 0.3V VCC = Max (Note 3) VCC = Max (Note 4) Inputs Dn Inputs Dn
Min
Typ (Note 2)
Max -1.5
Units V V
2.4 0.3 1 20 30 -400 -600 -2.5 -25 16.5
V mA A A mA mA
Switching Characteristics
VCC = +5.0V, TA = +25C (See Waveforms and Load Configurations) Symbol tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay E to Qn Propagation Delay Dn to Qn Propagation Delay, MR to Qn Propagation Delay, Sn to Qn Parameter Min Max 45 36 30 30 30 33 Units ns ns ns ns
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DM93L14 Quad Latch
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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