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| www.maxim-ic.com DS1846 NV Tri-Potentiometer, Memory, and MicroMonitor PIN CONFIGURATION SDA SCL A0 WP NMI L0 W1 L1 L2 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 FEATURES Three linear taper potentiometers - Two 10kW, 100-position - One 100kW, 256-position 248 bytes of user EEPROM memory Monitors microprocessor power supply, voltage sense, and external override Access to data and potentiometer control through a 2-wire interface External write-protect (WP) pin to protect data and potentiometer settings Operates from a 5V supply Nonvolatile (NV) wiper storage Packaging: 20-pin TSSOP Programming temperature: 0C to +70C Industrial operating temperature: -40C to +85C VCC IN PBRST RST RST H0 W0 H1 W2 H2 20-Pin TSSOP PIN DESCRIPTION - Power-Supply Input - Ground - 2-Wire Serial Data Input/Output SCL - 2-Wire Serial Clock Input WP - Write-Protect Input A0 - Address Input H0, H1, H2 - High End of Potentiometer L0, L1, L2 - Low End of Potentiometer W0, W1, W2 - Wiper Terminal of Potentiometer PBRST - Pushbutton Reset Input NMI - Nonmaskable Interrupt Output IN - NMI Voltage Input RST ORDERING INFORMATION DS1846E-010 DS1846E-010/T&R (Tape-and-Reel Version) VCC GND SDA RST - Active-Low Reset Output - Active-High Reset Output OVERVIEW The DS1846 NV tri-potentiometer, memory, and MicroMonitorTM consists of two 10kW, 100-position linear taper potentiometers, one 100kW, 256-position linear taper potentiometer; 256 bytes of EEPROM memory; and a MicroMonitor. The device provides an ideal method for setting bias voltages and currents in control applications using a minimum of circuitry. MicroMonitor is a trademark of Dallas Semiconductor. 1 of 18 042902 DS1846 The EEPROM memory allows a user to store configuration or calibration data for a specific system or device and provides control of the potentiometer wiper settings. Any type of user information can reside in the first 248 bytes (00h to F7h) of this memory. The next three bytes of memory (F8h to FAh) are for potentiometer settings and the last five addresses of EEPROM memory (FBh to FFh) are reserved. These reserved and potentiometer registers should not be used for data storage. Access to this EEPROM is through an industry-standard 2-wire bus. The interface I/O pins consist of SDA and SCL. The wiper positions of the DS1846, as well as EEPROM data, can be hardware write-protected using the WP input pin. The MicroMonitor is a precision temperature-compensated reference and comparator that monitors certain vital status conditions for a microprocessor. When a sense input detects an out-of-tolerance (VCC) condition, a nonmaskable interrupt is generated. As the voltage at the device degrades, an internal powerfail signal is generated that can be used to reset the processor. When VCC returns to an in-tolerance level, the reset signal is kept in the active state for a minimum time of tRST to allow for the stabilization of the power supply and the microprocessor. The MicroMonitor also functions as a pushbutton reset control. The pushbutton input is debounced internally and generates an active pulse width of tRST minimum. DS1846 BLOCK DIAGRAM Figure 1 DS1846 SCL SDA WP A0 EEPROM 2-Wire Interface Data 5 Reserved Bytes FBh-FFh Potentiometer 2 FAh Potentiometer 0 F9h Potentiometer 1 F8h User EPROM 248 Bytes 00h-F7h MicroMonitor Potentiometer 2 10kW Addr FAh 100-Positions Potentiometer 0 10kW Addr F9h 100-Positions Potentiometer 1 100kW Addr F8h 256-Positions H2 W2 L2 H0 W0 L0 H1 W1 L1 Nonvolatile Digital Potentiometer RPBR PBRST VCC VCCTP VCC RST Timer Delay VCC RST IN VTP Timer Delay 2.4kW typical NMI 2 of 18 DS1846 PIN DESCRIPTIONS VCC--Power-Supply Terminal. The DS1846 will support supply voltages ranging from +4.5V to +5.5V. GND--Ground Terminal SDA--2-Wire Serial Data Interface. The serial data pin is for serial data transfer to and from the DS1846. The pin is open drain and can be wire-ORed with other open-drain or open-collector interfaces. SCL--2-Wire Serial Clock Interface. The serial clock input is used to clock data into the DS1846 on rising edges and clock data out on falling edges. WP--Write Protect. WP must be connected to GND before either the data in memory or potentiometer wiper settings may be changed. WP is pulled high internally and must be either left open or connected to VCC if write protection is desired. A0--Address Input. This input pin specifies the address of the device when used in a multidropped configuration. As many as two DS1846s may be addressed on a single 2-wire bus. H0, H1, H2--High-End Terminals of the Potentiometers. For the three potentiometers, it is not required that these terminals be connected to a potential greater than the low-end terminal of the potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power-supply voltage, VCC, or go below ground. L0, L1, L2--Low-End Terminals of the Potentiometers. It is not required that these terminals be connected to a potential less than the high-end terminals of the pot. Voltage applied to the low end of the potentiometers cannot exceed the power-supply voltage, VCC, or go below ground. W0, W1, W2--Wipers of the Potentiometers. These pins are the wiper terminals of the potentiometers. Three bytes in EEPROM memory locations F8h, F9h, and FAh determine each wiper's setting. Voltage applied to either wiper terminal cannot exceed the power-supply voltage, VCC, or go below ground. PBRST --Pushbutton Reset. This input pin is active low. It acts as the pushbutton reset pin for the MicroMonitor. Pushbutton reset is pulled high internally. NMI --Nonmaskable Interrupt. Active-low signal that is generated to provide for an early power-fail warning. IN--NMI Voltage Input. An input voltage below VTP on this input forces the NMI output low. This can be used with a voltage-divider to set a secondary voltage monitoring level. (See Figure 4.) RST --Active-Low Reset Output. This signal provides an output that can be used to reset a microprocessor. RST--Active-High Reset Output. This signal provides an output that can be used to reset a microprocessor. 3 of 18 DS1846 MEMORY ORGANIZATION The EEPROM of the DS1846 contains 256 bytes. Bytes 00h to F7h are general-purpose user memory. The next three bytes, F8h, F9h, and FAh, contain the wiper settings for each of the potentiometers (see Table 1). The last five bytes, FBh to FFh, are reserved and should not be used. The memory, internal to the device, is organized as 32 pages of eight bytes each. Once an address byte is clocked into the device through the 2-wire interface, the five MSBs decode which page is to be accessed, and the three LSBs decode a particular byte on that page. The selected page is shadowed in SRAM as a staging area while data is clocked in or out through the 2-wire interface. When reading any number of bytes, all eight bytes of the current page are shadowed in SRAM where the requested byte(s) eventually get clocked out. When reading, the page is incremented automatically, and hence transparent to the user. When performing a write, the page of the starting address is shadowed in SRAM. The new data is then written to the SRAM. When the end of the page is reached, the address returns to the beginning of the same page. When the 2-wire master issues a stop, the entire page (even if only a single byte changed) is copied from the SRAM into EEPROM. All reads and writes to the EEPROM are actually executed as page operations even though they are invisible to the user when performing single byte reads and writes. Understanding the internal memory organization is important when performing sequential address writes due to page boundaries. See the Write Operations in the 2-WIRE OPERATION section for more information. MEMORY LOCATIONS Table 1 MEMORY NAME OF MEMORY LOCATION LOCATION 00h to F7h User Memory F8h F9h FAh FBh to FFh Potentiometer 1 Setting Potentiometer 0 Setting Potentiometer 2 Setting Reserved FUNCTION OF MEMORY LOCATION General-purpose user memory. Writing to this byte controls the setting of potentiometer 1, a 256-position pot. Valid settings are 00h to FFh. Writing to this byte controls the setting of potentiometer 0, a 100-position pot. Valid settings are 00h to 63h. MSB is ignored. Writing to this byte controls the setting of potentiometer 0, a 100-position pot. Valid settings are 00h to 63h. MSB is ignored. Reserved 4 of 18 DS1846 2-WIRE OPERATION Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high periods indicates a start or stop condition depending on the conditions discussed below. See the timing diagrams for further details (Figures 2 and 3). Start Condition: A high-to-low transition of SDA with SCL high is a start condition, which must precede any other command. See the timing diagrams for further details (Figures 2 and 3). Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command places the DS1846 into a low-power mode. See the timing diagrams for further details (Figures 2 and 3). Acknowledge: All address and data bytes are transmitted through a serial protocol. The DS1846 pulls the SDA line low during the ninth clock pulse to acknowledge that it has received each word. Standby Mode: The DS1846 features a low-power mode that is automatically enabled after power-on, after a stop command, and after the completion of all internal operations. Memory Reset: After any interruption in protocol, power loss, or system reset, the following steps reset the DS1846: 1) Clock up to nine cycles. 2) Look for SDA high in each cycle while SCL is high. 3) Create a start condition while SDA is high. Device Addressing: The DS1846 must receive an 8-bit device address word following a start condition to enable a specific device for a read or write operation. The address word is clocked into the DS1846 MSB to LSB. The address word consists of 101000 binary followed by A0 then the R/W bit. If the R/W bit is high, a read operation is initiated. If the R/W bit is low, a write operation is initiated. For a device to become active, the value of A0 must be the same as the hard-wired address pins on the DS1846. Upon a match of written and hard-wired addresses, the DS1846 outputs a zero for one clock cycle as an acknowledge. If the address does not match the DS1846 returns to a low-power mode. Write Operations: After receiving a matching device address byte with the R/W bit set low, the device goes into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the device to define the address where the data is to be written. After the byte has been received, the DS1846 transmits a zero for one clock cycle to acknowledge the memory address has been received. The master must then transmit an 8-bit data word to be written into this memory address. The DS1846 again transmits a zero for one clock cycle to acknowledge the receipt of the data byte. At this point, the master must terminate the write operation with a stop condition. The DS1846 then enters an internally timed write process tw to the EEPROM memory. All inputs other than those controlling the MicroMonitor are disabled during this write cycle. The DS1846 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but the master does not send a stop condition after the first data byte. Instead, after the slave acknowledges the data byte has been received, the master can send up to seven more data bytes using the same nineclock sequence. After a write to the last byte in the page, the address returns to the beginning of the same page. The master must then terminate the write cycle with a stop condition or the data clocked into the 5 of 18 DS1846 DS1846 is not latched into EEPROM. Note that in order for eight bytes to be stored sequentially (and to prevent looping around), the address byte must be set to the beginning of the desired page (three LSBs of the address are 0). For detailed information concerning page operations, see the MEMORY ORGANIZATION section. The DS1846 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but the master does not send a stop condition after the first data byte. Instead, after the slave acknowledges receipt of the data byte, the master can send up to seven more data bytes using the same nine-clock sequence. After a write to the last byte in the page, the address returns to the beginning of the page. The master must terminate the write cycle with a stop condition or the data clocked into the DS1846 is not latched into permanent memory. Acknowledge Polling: Once the internally timed write has started and the DS1846 inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a start condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence is only allowed to proceed if the internal write cycle has completed and the DS1846 responds with a zero. Read Operations: After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of operation. There are three read operations: current address read, random read, and sequential address read. CURRENT ADDRESS READ The DS1846 has an internal address register that maintains the address used during the last read or write operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address was the last byte in memory, then the register resets to the first address. This address stays valid between operations as long as power is available. Once the device address is clocked in and acknowledged by the DS1846 with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a stop condition afterwards. RANDOM READ A random read requires a dummy byte write sequence to load in the data word address. Once the device address and data bytes are clocked in by the master, and acknowledged by the DS1846, the master must generate another start condition. The master now initiates a current address read by sending the device address with the R/W bit set high. The DS1846 acknowledges the device address and serially clocks out the data byte. SEQUENTIAL ADDRESS READ Sequential reads are initiated by either a current address read or a random address read. After the master receives the first data byte, the master responds with an acknowledge. As long as the DS1846 receives this acknowledge after a byte is read, the master may clock out additional data words from the DS1846. After reaching address FFh, it resets to address 00h. The sequential read operation is terminated when the master initiates a stop condition. The master does not respond with a zero. For a more detailed description of 2-wire theory of operation, see the following section. 6 of 18 DS1846 2-WIRE SERIAL PORT OPERATION The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a "master." The devices that are controlled by the master are "slaves." The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions. The DS1846 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. Timing diagrams for the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is provided in the AC ELECTRICAL CHARACTERISTICS table for 2-wire serial communications. The following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain high. Start Data Transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data Valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1846 works in both modes. 7 of 18 DS1846 Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a `not acknowledge' can be returned. The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. The DS1846 can operate in the following two modes: 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit has been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1846 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. 3) Slave Address: Command/control byte is the first byte received following the start condition from the master device. The command/control byte consists of a 6-bit control code. For the DS1846, this is set as 101000 binary for read/write operations. The next bit of the command/control byte is the device select bit or slave address (A0). It is used by the master device to select which of two devices is to be accessed. When reading or writing the DS1846, the device-select bits must match the device-select pin (A0). The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a `1', a read operation is selected, and when set to a `0', a write operation is selected. Following the start condition, the DS1846 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 101000 control code, the appropriate device address bit, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line. 8 of 18 DS1846 WRITE PROTECT The WP pin protects EEPROM data and potentiometer position from alteration in an application. This pin must be open or connected high to protect data from alteration. WP has an internal pullup (RWP). READING AND WRITING THE POTENTIOMETER VALUES Reading from and writing to the potentiometers consists of a standard read or write to EEPROM memory at the addresses F8h, F9h, and FAh. The 8-bit value at address F8h controls the wiper setting for potentiometer 1, which has 256 positions. The 8-bit value at addresses F9h and FAh control the wiper setting of potentiometer 0 and 2, respectively; each has 100 positions. Potentiometer 1 may be set to any value between 00h and FFh. A value of 00h sets the wiper of potentiometer 1 to its lowest value and FFh sets the wiper to its highest. Potentiometer 0 or 2 may be set to any value between 00h and 63h. A value of 00h sets the wiper of potentiometer 0 or 2 to its lowest position and 63h sets the wiper to its highest position. Any hexadecimal value is a valid address. Writing a value greater than 63h will set the potentiometer according to the seven LSBs and the MSB is ignored. 2- WIRE DATA TRANSFER PROTOCOL Figure 2 2-WIRE AC CHARACTERISTICS Figure 3 9 of 18 DS1846 DEVICE OPERATION Power Monitor The DS1846 detects out-of-tolerance power-supply conditions and warns a processor-based system of an impending power failure. When VCC falls below the minimum VCC tolerance, a comparator asserts the RST and RST signals. On power-up, RST and RST are kept active for a minimum of tRST to allow the power supply and processor to stabilize. Pushbutton Reset The DS1846 provides an input pin for direct connection to a pushbutton reset (see Figure 4). The pushbutton reset input requires an active-low signal. Internally, this input is debounced and timed such that RST and RST signals of at least tRST minimum are generated. The tRST delay commences as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting the NMI output to the PBRST input as shown in Figure 4. Nonmaskable Interrupt The DS1846 generates a nonmaskable interrupt ( NMI ) for early warning of a power failure. A precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated by an internal bandgap. The IN pin is a high-impedance input allowing for a user-defined sense point. An external resistor voltage-divider network (Figure 4) is used to set a trip point. This sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main system power input. With the IN trip point, VTP, the proper values for R1 and R2 can be determined by the equation as shown in Figure 4. Proper operation of the DS1846 requires that the voltage at the IN pin be limited to VCC. Therefore, the maximum allowable voltage at the supply being monitored (VMAX) can also be derived as shown in Figure 4. A simple approach to solving the equation is to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power-supply system, maximizing the amount of time for system shut-down between NMI and RST/ RST . When the supply being monitored decays to the voltage sense point, the DS1846 pulses the NMI output to the active state for a minimum tNMI. During a power-up, any detected IN pin levels below VTP by the comparator are disabled from generating an interrupt until VCC rises to VCCTP. As a result, any potential NMI pulse is not initiated until VCC reaches VCCTP. Connecting NMI to PBRST allows the nonmaskable interrupt to generate an automatic reset when an outof-tolerance condition occurred in a monitored supply. An example is shown in Figure 4. 10 of 18 DS1846 TYPICAL APPLICATION Figure 4 VCC Optional, see note. VVcc CC To 2-Wire Master Vsense SDA SCL A0 WP Vcc IN /PBRST /RST RST W0 H1 W2 H2 Potentiometer Terminals Reset Outputs To Microprocessor Interrupt /NMI W1 L1 L2 GND L0 DS1846 H0 Potentiometer Terminals Note: NMI can be used to produce a reset, which is shown by the dotted line in Figure 4. The following equations are used to calculate the resistor values when using VSENSE. VSENSE = R1+ R2 X VTPmin R2 VMAX = VSENSE X VCC VTP 11 of 18 DS1846 TIMING DIAGRAM: PUSHBUTTON RESET Figure 5 TIMING DIAGRAM: NONMASKABLE INTERRUPT Figure 6 tNMI 12 of 18 DS1846 TIMING DIAGRAM: POWER-DOWN Figure 7 tVF TIMING DIAGRAM: POWER-UP Figure 8 tVR 13 of 18 DS1846 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Programming Temperature Range Storage Temperature Range Soldering Temperature -0.5V to +6.0V -40C to +85C; Industrial 0C to +70C -55C to +125C See IPC/JEDEC J-STD-020A specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Supply Voltage Input Range PBRST PBRST (-40C to +85C) MAX 5.5 VCC + 0.3 VCC + 0.3 +0.5 VCC + 0.3 0.3VCC 1 VCC + 0.3 UNITS V V V V V V mA V NOTES 1 Input High Level SYMBOL VCC VIR VIH VIL VIH VIL IW L, H,W MIN 4.5 GND - 0.3 2.0 -0.3 0.7VCC GND - 0.3 GND - 0.3 TYP Input Low Level Input Logic 1 Input Logic 0 Wiper Current Resistor Inputs 2 2 18 14 of 18 DS1846 DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current Standby Current Low-Level Output Voltage (SDA) I/O Capacitance Output at 2.4V NMI (-40C to +85C; VCC = 4.5V to 5.5V) MIN -200 100 TYP MAX +200 200 0.4 0.6 10 -1.0 -0.5 4 100 60 4.40 1.25 UNITS nA mA V pF mA mA mA kW kW V V 14 3 NOTES SYMBOL IIL ISTBY VOL1 VOL2 CI/O IOH IOH IOL RWP RPBR VCCTP VTP CONDITION 3mA sink current 6mA sink current 0 0 14 Output at 2.4V Output at 0.4V WP Internal Pullup Resistance /PBRST Internal Pullup Resistance VCC Trip Point IN Input Trip Point 40 25 4.15 1.15 65 40 4.3 1.2 15 of 18 DS1846 AC ELECTRICAL CHARACTERISTICS PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Condition Hold Time (Repeated) Start Condition Low Period of SCL Clock High Period of SCL Clock Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for Stop Condition Pulse Width of Spikes (which must be suppressed by input filter) (-40C to +85C; VCC = 4.5V to 5.5V) MIN 0 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0 0 100 250 20 + 0.1CB 20 + 0.1CB 0.6 4.0 0 TYP MAX 400 100 UNITS kHz ms ms ms ms 0.9 ms ns 300 1000 300 300 50 400 3 150 200 320 5 550 8 10 ns ns ms ns pF ms ns ms ms ms ms ns ns ms ms 16 8 9 NOTES 4 4 4, 5 4 4 4, 6, 7 4 8 8 SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tR tF tSU:STO tSP CB tW tPB tRST tRPD tVF tRPU tVR tPDLY tIPD tNMI CONDITION Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Capacitive Load for each Bus Line EEPROM Write Time = VIL Reset Active Time VCC Detect to RST and RST (Power-Down) VCC Slew Rate VCC Detect to RST and RST (Power-Up) VCC Slew Rate PBRST Stable Low to RST and RST IN Detect (Falling) to PBRST NMI 16 20 200 0 320 550 15 250 5 200 700 8 IN Detect (Rising) to NMI 16 of 18 DS1846 ANALOG RESISTOR CHARACTERISTICS (-40C to +85C; VCC = 4.5V to 5.5V) PARAMETER Wiper Resistance End-to-End Resistance Absolute Linearity Relative Linearity -3dB Cutoff Frequency Temperature Coefficient SYMBOL RW CONDITION 10kW pot 100kW pot 10kW pot 100kW pot fcutoff 10kW pot 100kW pot MIN 7 70 -1 -3 -0.25 TYP 300 9 90 MAX 600 11 110 +1 +3 +0.25 UNITS W kW LSB LSB kHz ppm/C NOTES 15 11 12 350 34 750 13 17 of 18 DS1846 NOTES: 1) All voltages are referenced to ground. 2) I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off. 3) ISTBY specified with VCC = 5.0V and control port logic pins are driven to the appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for the corresponding inactive state. All inputs should be connected high. 4) A fast-mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. 5) After this period, the first clock pulse is generated. 6) The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal. 7) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. MIN 8) CB--total capacitance of one bus line in picofarads, timing referenced to (0.9 x VCC) and (0.1 x VCC). 9) EEPROM write begins after a stop condition occurs. 10) Resistor inputs can not go beneath GND by more than 0.5V or above VCC by more than 0.5V. 11) Absolute linearity is used to measure expected wiper voltage as determined by wiper position. 12) Relative linearity is used to determine the change of wiper voltage between two adjacent wiper positions. 13) When used as a rheostat or variable resistor the temperature coefficient applies: 750ppm/C. When used as a voltage-divider or potentiometer, the effective temperature coefficient approaches 30ppm/C. 14) Valid for VCC = 5V only. 15) Valid at +25C only. 16) Noise immunity pulses < 2ms at VCCTP minimum do not cause a reset. 18 of 18 |
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