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HA16163T
Synchronous Phase Shift Full-Bridge Control IC
REJ03F0001-0500Z Rev.5.0 Mar.15.2004
Features
* * * * * High frequency operation; oscillator frequency = 2 MHz max. Full-bridge phase-shift switching circuit with adjustable delay times Integrated secondary synchronous rectification control with adjustable delay times Three-level over current protection; pulse by pulse, timer Latch, one shot OCP Package: TSSOP-20
Application
* 48 V input isolated DC/DC converter * Primary; Full-bridge circuit topology * Secondary; current doubler or center-tapped rectification
Illustrative Circuit
+48V +
-
FET Driver
Vbias FET Driver FET Driver FET Driver FET Driver FET Driver
VCC
OUT -A
OUT -B
CS
RAMP
OUT -C
OUT -D
OUT -E
OUT -F Optical feedback circuitry COMP
VREF
FB DELAY DELAY DELAY -1 -2 -3
GND
RT
SYNC
SS
REMOTE
Rev.5.0, Mar.15.2004, page 1 of 29
HA16163T
Pin Arrangement
SYNC RAMP CS COMP REMOTE FB SS DELAY-1 DELAY-2 DELAY-3 1 2 3 4 5 6 7 8 9 10 (Top view) 20 19 18 17 16 15 14 13 12 11 RT GND OUT-A OUT-B OUT-C OUT-D OUT-E OUT-F VCC VREF
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name SYNC RAMP CS COMP REMOTE FB SS DELAY-1 DELAY-2 DELAY-3 VREF VCC OUT-F OUT-E OUT-D OUT-C OUT-B OUT-A GND RT Pin Function Synchronization I/O for the oscillator Current sense signal input for the full-bridge control loop Current sense signal input for OCP Error amplifier output Remote on/off control Voltage feedback input Timing capacitor for both soft start and timer latch Delay time adjustor for the full-bridge control signal (OUT-A and B) Delay time adjustor for the full-bridge control signal (OUT-C and D) Delay time adjustor for the secondary control signal (OUT-E and F) 5 V/20 mA Output IC power supply input Secondary control signal Secondary control signal Full-bridge control signal Full-bridge control signal Full-bridge control signal Full-bridge control signal Ground level for the IC Timing resistor for the oscillator
Rev.5.0, Mar.15.2004, page 2 of 29
HA16163T
Block Diagram
VCC
H UVLO L
+ - VREF
UVL
5V Generator
VREF
H VREF GOOD L
REMOTE
ON: 1.417V OFF: 1.333V
RT
Current Ref. Generator
Start-up counter 32 clock
VREFGOOD
Circuit Bias VREF
DELAY
OUT-A DELAY-1
VREF
Oscillator
RES SYNC. I/O Error Amp VREF Q
SYNC
DELAY VREF R Q S DELAY
OUT-B
FB
1.25V
- +
500
OUT-C DELAY-2
VREF
20k
COMP
10k
Comparator - + 0.4V
-+
1.55V 1.46V
DELAY
OUT-D
RAMP
Clamp Circuit VREF R Q S VREFGOOD 4V 10 RES SS IN LOCKOUT SEQ. ONE PULSE DISCHARGE + - + - PULSE BY PULSE DELAY VREF Zero Delay
SS
R Q S 87A
OUT-E DELAY-3
VREF
0.4V
FAULT LOGIC
LIMIT IN
Zero delay DELAY
CS
0.6V
ONE SHOT
OUT-F
GND Note that all switches in the block diagram are turned on when control signal is high.
Rev.5.0, Mar.15.2004, page 3 of 29
HA16163T
Absolute Maximum Ratings
(Ta = 25C) Item Power supply voltage Peak output current DC output current VREF output current COMP sink current DELAY set current RT set current VREF terminal voltage Terminal group 1 voltage Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. 5. Symbol Vcc Ipk-out Idc-out Iref-out Isink-comp Iset-delay Iset-rt Vter-ref Vter-1 Tj-opr Tstg Rating 20 50 5 -20 2 0.3 0.3 -0.3 to 6 -0.3 to (Vref +0.3) -40 to +125 -55 to +150 Unit V mA mA mA mA mA mA V V C C Note 1 2, 3 3 3 3 3 3 1, 4 1, 5 6
Rated voltages are with reference to the GND pin. Shows the transient current when driving a capacitive load. For rated currents, inflow to the IC is indicated by (+), and outflow by (-). VREF pin voltage must not exceed VCC pin voltage. Terminal group 1 is defined the pins; REMOTE, CS, RAMP, COMP, FB, SS, RT, SYNC, DELAY-1 to 3, OUT-A to F 6. ja 228C/W Board condition; Glass epoxy 55 mm x 45 mm x 1.6 mm, 10% wiring density.
Rev.5.0, Mar.15.2004, page 4 of 29
HA16163T
Electrical Characteristics
(Ta = 25C, Vcc = 12 V, RT = 33 k, Rdelay = 51 k, unless otherwise specified.)
Item Supply Start threshold Shutdown threshold UVLO hysteresis Start-up current Operating current VREF Output voltage Line regulation Load regulation Temperature stability Oscillator Oscillator frequency Switching frequency Line stability Temperature stability RT voltage SYNC Input threshold Output high Output low Minimum input pulse Output pulse width Remote On threshold voltage Off threshold voltage Input bias current Error amplifier FB input voltage FB input current Open-loop DC gain Unity gain bandwidth
Output source current
Symbol VH VL dVUVL Is Icc Vref Vref-line Vref-load dVref/dTa fosc fsw fsw-line dfsw/dTa VRT VTH-SYNC VOH-SYNC VOL-SYNC TI-MIN TO-SYNC VON VOFF IREMOTE VFB IFB Av BW ISOURCE ISINK VOH-EO VOL-EO VCLAMP-EO
Min 9.0 7.3 1.7 -- -- 4.9 -- -- -- -- 412 -1.5 -- 2.5 2.5 3.5 -- 50 -- 1.374 1.293 0 1.225 -1.0 -- -- -610 2.0 3.7 -- -0.16
Typ 9.8 7.9 1.9 90 7 5.0 0 6 80 *1 960 *1 480 0 0.1 *1 2.7 2.85 4.0 0.05 -- 500 1.417 1.333 0.4 1.250 0 80 * 2 *1 -430 6.5 3.9 0.1 -0.07
1
Max 10.6 8.5 2.1 150 10 5.1 10 20 -- -- 547 1.5 -- 2.9 3.2 -- 0.15 -- -- 1.460 1.373 2 1.275 1.0 -- -- -350 -- -- 0.4 0.0
Unit V V V A mA V mV mV ppm/C kHz kHz % %/C V V V V ns ns V V A V A dB MHz A mA V V V
Test Conditions
Vcc = 8.5V No load on VREF pin Vcc = 10V to 16V Iref = -1mA to -20mA Ta = -40 to 105C Measured on OUT-A, -B Vcc = 10V to 16V Ta = -40 to 105C
RSYNC = 33k to GND RSYNC = 33k to VREF
REMOTE = 2V
FB and COMP are shorted
FB = 1.25V
FB = 0.75V, COMP = 2V FB = 1.75V, COMP = 2V FB = 0.75V, COMP; open FB = 1.75V, COMP; open FB = 0.75V, COMP; open SS = 1V
Output sink current Output high voltage Output low voltage Output clamp voltage *2
Notes: 1. Reference values for design. Not 100% tested in production. 2. VCLAMP-EO = VCOMP - SS voltage (1V)
Rev.5.0, Mar.15.2004, page 5 of 29
HA16163T
Electrical Characteristics (cont.)
(Ta = 25C, Vcc = 12 V, RT = 33 k, Rdelay = 51 k, unless otherwise specified.)
Item Phase modulator RAMP offset voltage RAMP bias current RAMP sink current Minimum phase shift Maximum phase shift Delay to OUT-C, -D *2 Delay Soft start DELAY-1, -2, -3 *3 Terminal voltage Source current Discharge current Soft-start reset voltage SS high voltage Symbol VRAMP IRAMP ISINK-RAMP Dmin Dmax Tpd TD1, 2, 3 VD1, 2, 3 ISS IRES-SS VRES-SS VOH-SS Min -- -5 8 -- -- -- 22 1.9 -14 5 0.25 3.9 Typ 0.4 *1 -0.8 26 0 *1 *4 97.0 *1 *4 30 33.5 2.0 -10 10 0.40 4.0 Max -- 5 -- -- -- 60 45 2.1 -6 -- 0.55 4.1 Unit V A mA % % ns ns V A mA V V RAMP = 0.3V RAMP = 1V, COMP = 0V RAMP = 1V, COMP = 0V RAMP = 0V, COMP = 2.1V COMP = 2.1V Delay set R = 51k Delay set R = 51k SS = 1V SS = 1V, REMOTE = 0V Measured on SS Test Conditions
Notes: 1. Reference values for design. Not 100% tested in production. 2. Tpd is defined as; RAMP OUT-C/D
1V 0V 5V 0V Tpd 50%
50%
3. TD1, 2, 3 are defined as;
TD1 OUT-A TD1
OUT-B
50%
For primary control
OUT-C TD2 OUT-D TD2
OUT-E
For secondary control
OUT-F
TD3 TD3
4. Maximum/Minimum phase shift is defined as;
D= T2 x 2 x 100 (%) T1 OUT-A
T2
OUT-D
T1
OUT-B
T2
OUT-C
T1
Rev.5.0, Mar.15.2004, page 6 of 29
HA16163T
Electrical Characteristics (cont.)
(Ta = 25C, Vcc = 12 V, RT = 33 k, Rdelay = 51 k, unless otherwise specified.)
Item Over current protection Pulse-by-pulse current limit threshold One-shot OCP threshold Delay to OUT pins *1 Timer latch integration time Output High voltage Low voltage Rise time Fall time Timing offset *2 Symbol VCS-PP VCS-SD Tpd-cs TTL VOH-OUT VOL-OUT tr tf TD4 Min 0.36 0.54 -- 44 4.3 -- -- -- -- Typ 0.40 0.60 40 63 4.8 0.1 5 5 3 *3 Max 0.44 0.66 80 82 -- 0.4 15 15 -- Unit V V ns s V V ns ns ns CS = 0V to 0.47V CS = 0.47V step function, SS = 0.022F IOUT = -5mA IOUT = 5mA COUT = 33pF COUT = 33pF Test Conditions
Notes: 1. Tpd-cs is defined as;
CS
0.47V 0 50%
OUT-C/D
Tpd-cs
50%
2. TD4 is defined as;
OUT-D OUT-E
TD4 50%
OUT-C
50%
50%
OUT-F
TD4
50%
3. Reference values for design. Not 100% tested in production.
Rev.5.0, Mar.15.2004, page 7 of 29
HA16163T
Timing Diagram
Note: All voltage, current, time shown in the diagram is typical value. Full Bridge and Secondary Control
COMP
COMP/3(internal signal) RAMP+0.4V (internal signal)
RAMP
TD1
0.4V
TD1
OUT-A OUT-B OUT-C
TD2 TD2
OUT-D
TD3
OUT-E
TD3
OUT-F
VIN OUT-A DRIVE MA MC DRIVE OUT-C
OUT-B
DRIVE RAMP
MB
MD
DRIVE
OUT-D
DRIVE
ME
MF
DRIVE
OUT-E
OUT-F
External Power Stage
Rev.5.0, Mar.15.2004, page 8 of 29
HA16163T Start-up and Shutdown
9.8V
7.9V
VCC
ON
ON OFF
REMOTE
5V
VREF
0V
RES
(Internal signal) 32 counts 32 counts High Low 4.0V
VREFGOOD
(Internal signal)
SS
0V
DISCHARGE
(Internal signal)
High Low
From Error Amp
COMP
20k 10k
Comparator - + 0.4V
For Phase Modulation
Current information
RAMP
Clamp VREF
4.0V
SS
Css
Iss 10A SS IN Discharge
Soft-start Block
Rev.5.0, Mar.15.2004, page 9 of 29
HA16163T Timer Latch and One Shot OCP
CS
0.4V 0.6V 0.4V
4V
3.78V
3.9V
3.9V
SS
0.4V
OUT ENABLE
LOCKOUT SEQ.
(Internal signal) OUT DISABLE
(Internal signal)
FAULT LOGIC
FOR PHASE MODULATION 3.9V 4V 10A RES SS IN R Q S 87A 0.4V SHORT DET. DISCHARGE + - + - PULSE BY PULSE R ONE SHOT LIMIT IN VREFGOOD Q S LOCKOUT SEQ. - + S Q R 3.78V - + - + S Q R
SS
0.4V
CS
0.6V
All Flip-flop are initialized by VREFGOOD in turn on period.
OCP Block
SS IN : Voltage detector input of SS pin. SEQ. : Timer Latch function is not activated when SEQ. signal is Low. SHORT DET. : Once ONE SHOT comparator detect short current in the power supply, SHORT DET. is High until SS voltage reaches down to 0.4V. DISCHARGE : Gate control for SS capasitor reset. LIMIT IN : One shot OCP input. LOCKOUT : Lock-out signal for OUT-A to F. VREFGOOD : System reset signal. VREFGOOD is High when either VREF<4.6V or Remote off mode.
Rev.5.0, Mar.15.2004, page 10 of 29
HA16163T
Functional Description
Note: All voltage, current, time shown in the diagram is typical value unless otherwise noted. UVLO UVLO (Under Voltage Lockout Operation) is a function that halts operation of the IC in the event of a low IC power supply voltage. When IC operation is halted, the 5 V internal voltage generation circuit (VREF) halts, and therefore operation of circuitry using VREF as the operating power supply halts. Circuit blocks other than UVLO use VREF as their operating power supply. Therefore, the power supply current of the IC becomes equal to the current dissipated by the UVLO circuit. The following graphs show the relationship between the VCC input current and VCC input voltage, and between VREF and the VCC input voltage.
ICC
ICC
Is 0 7.9V 8.5V 9.8V 12V 20V
VCC
VREF
5V
0
7.9V
9.8V
20V
VCC
Figure 1 REMOTE IC outputs (OUT-A through OUT-F) can be halted by means of the REMOTE pin. In this case, the IC output logic level is low. In the remote off state, VREF output is not halted, and therefore the current dissipation of the IC does not decrease to the start-up level. Also, control by means of the REMOTE pin is not possible when the IC has been halted by UVLO. The soft start capacitance is discharged in the remote off state. Therefore, operation begins from soft start mode when the next remote on operation is performed. The relationship between the REMOTE pin and the operating mode of the IC is shown in the following figure.
IC operating ON mode
OFF 0V
1.333V 1.417V
5V
REMOTE
Figure 2
Rev.5.0, Mar.15.2004, page 11 of 29
HA16163T The remote on and off threshold voltages are provided with hysteresis of 84 mV (typ). Remote control can be performed by means of analog input as shown in the diagram below as well as by means of logic control. The following diagram shows an example in which the power supply set input voltage is sensed by means of the REMOTE pin, and the power supply set start-up voltage is set to 34 V, and the shutdown voltage to 32 V.
VIN
5V(VREF) VIN(on) = VON(remote) x (R1+R2)/R2 = 1.417V x 24 = 34.008V VIN(off) = VOFF(remote) x (R1+R2)/R2 = 1.333V x 24 = 31.992V 220k
HA16163
R1
10k REMOTE Full-bridge control
R2
10k
100p
GND
Remote control circuit VIN sense circuit (logic input) (analog input)
Power Stage
Figure 3 Start-up Counter When the VREFGOOD signal (internal signal) goes to the logic low level, the HA16163 starts operating as a controller. The VREFGOOD signal is created from the REMOTE comparator and VREFGOOD circuit output via a 32-clock startup counter.
VCC
H UVLO L
UVL
5V Generator
VREF
H VREF GOOD L
REMOTE
ON: 1.417V OFF: 1.333V
+ - From Oscillator Start-up counter 32 clock
VREFGOOD
Circuit Bias
Figure 4 Therefore, the start of IC operation is a 32-count later than UVLO release or the remote on trigger. When the oscillator frequency is set to 1 MHz, this represents a delay of 32 s. This delay enables operation to be halted until VREF (5 V) stabilizes when UVLO is released. Note that the start-up counter operates when VREF rises or when a remote on operation is performed, but does not operate when VREF falls or when a remote off operation is performed (there is no logic delay due to the start-up counter).
9.8V
7.9V
VCC
4.6V
4.4V 32 counts
VREF RES
(Internal signal)
VREFGOOD
(Internal signal) Start of Operation operation halted
Figure 5
Rev.5.0, Mar.15.2004, page 12 of 29
HA16163T Oscillator The oscillation frequency of the oscillator is set by means of a resistance connected between the RT pin and GND. The following graph shows the relationship between the external resistance and the oscillation frequency. The typical value of the oscillation frequency is given by the following equation.
fosc = 1 30p[F] x RT[] + 50[ns] [Hz]
10000
fosc vs. RT
SYNC pin: open
HA16163
SYNC
fosc (kHz)
1000
CSYNC = 5pF
(2.7V)
RT
100
RT
GND
10 10
100 RT (k)
1000
Figure 6 Place the resistor for connection to the RT pin as close to the pin as is possible. Please design the pattern so that the level of cross-talk from other signals is minimized. Synchronized Operation Parallel synchronized operation is possible by connecting the SYNC pins of HA16163s. In this case, up to four slave ICs can be connected to one master IC. A value of at least twice the master RT value should be set for the slave IC RT values.
HA16163 MASTER
(2.7V)
HA16163 SLAVE
SYNC RT GND
(2.7V)
RT SYNC GND
RT
2*RT
HA16163 SLAVE
SYNC RT GND
(2.7V)
2*RT
Max. 4 slaves
Figure 7 Parallel Synchronized Operation
Rev.5.0, Mar.15.2004, page 13 of 29
HA16163T External synchronized operation is possible by supplying a synchronization signal to the SYNC pins of HA16163s. In this case, a frequency not exceeding 1/2 that of the master clock should be set for the HA16163s. A maximum master clock frequency of 4 MHz should be used. See the figure below for the input waveform conditions.
TTL or CMOS MASTER
MASTER CLOCK
HA16163 SLAVE
SYNC RT GND
(2.7V)
RT
HA16163 SLAVE
SYNC RT GND
(2.7V)
RT
Figure 8 External Synchronized Operation
TCYCLE TI-MIN TIH-SYNC Item TCYCLE TI-MIN TIL-MIN VIH-SYNC VIL-SYNC TIL-MIN Input Range 250ns min. 50ns min. 100ns min. 3.2V to Vref 0V to 2.5V
TIL-SYNC
Figure 9 SYNC Pin Input Conditions
Rev.5.0, Mar.15.2004, page 14 of 29
HA16163T Synchronous Phase Shift Full-Bridge Control The HA16163 is provided with full-bridge control outputs OUT-A through OUT-D, and secondary-side synchronous rectification control outputs OUT-E and OUT-F. ZVS (Zero Voltage Switching) can be performed by adjusting timing delays TD1 and TD2 between the OUT-A through OUT-D outputs by means of an external resistance. OUT-E and OUTF have an output timing suitable for secondary-side full-wave rectification, and so can be used in either current doubler or center tap applications. The following figure shows full-bridge ZVS + current doubler operation using an ideal model.
RES pulse
(Internal signal)
SA
TD1
SB Full-bridge control switch (on when high) SC
TD2
SD Synchronous SE rectification control switch (on when high) SF Transformer primary both-side voltage
VIN 0 -VIN
TD3
Transformer VIN/N secondary 0 both-side -VIN/N voltage
Subinterval: Time: t0 1 t1 2 t2 3 t3 4 t4 5 t5
Figure 10 * Subinterval:1 In interval 1, SA and SD are turned on, and VIN is generated on the transformer primary side. On the transformer secondary side, a value proportional to the winding ratio is generated, and the primary-side power is transmitted to the load side. At this time, secondary-side switch SE is off and SF is on.
VIN L1
SA V11 Lr Cr1 SB
SC V12 SD Cr2
SE VOUT SF
L2
Subinterval: 1
Rev.5.0, Mar.15.2004, page 15 of 29
HA16163T * Subinterval:2 As SD is turned off at point t1, the primary-side current flows into resonant capacitance Cr2. At this time Cr2 is charged, and therefore the potential of V12 rises. Considering that the exciting current and the L1 and L2 ripple currents are considerable smaller than Io, the following is an approximate equation for the slope of V12.
dV12 1 0.5 Io = dt Cr2 N [V/s] (1)
Here, N is the ratio of the primary coil to the secondary coil (N = N1/N2), and Io is the output current. As SE and SF are on, the transformer secondary side is in the shorted state, and the value of the current flowing up to that time is retained.
VIN L1
SA V11 Lr Cr1 SB
SC V12 SD Cr2
SE VOUT SF
L2
Subinterval: 2 * Subinterval:3 SC is turned on at point t2. ZVS operation can be attained by setting the SD off (t2) SC on (t3) delay to the optimal value. This delay time can be expressed by equation (2).
TD2 = N Cr2 VIN 0.5 Io [s] (2)
After SC is turned on, the transformer primary side is in the shorted state, and therefore the current value immediately after SC was turned on is retained.
VIN L1
SA V11 Lr Cr1 SB
SC V12 SD Cr2
SE VOUT SF
L2
Subinterval: 3
Rev.5.0, Mar.15.2004, page 16 of 29
HA16163T * Subinterval:4 As SA is turned off at point t3, the primary-side current discharges resonant capacitance Cr1, and the potential of V11 falls. A negative potential is applied to resonant inductor Lr, and a flux reset starts. At this time, since the series resonance circuit is composed of Cr1 and Lr, the V11 waveform changes to a sine wave. The resonance frequency is given by equation (3).
fr = 1 2 (Cr1 Lr) [Hz] (3)
VIN
L1
SA V11 Lr Cr1 SB
SC V12 SD Cr2
SE VOUT SF
L2
Subinterval: 4 * Subinterval:5 When synchronous switch SF is turned off at point t4, the current flowing in SF up to that time continues to flow through the SF body diode. SF turn-off must be performed before completion of the resonant inductor Lr flux reset. If SF is not off on completion of the Lr flux reset, power transmission will be performed with the transformer secondary-side shorted, and therefore an excessive current will flow in the transformer primary and secondary sides, and parts may be damaged. Also, if the SF body diode is on for a long period, loss will be high. Therefore, optimal timing should be set by means of the HA16163's delay adjustment pin, DELAY-3. Lr reset time tr is given by equation (4) when the resonance voltage peak value is within the input voltage.
treset(Lr)|vppVIN = 11 4 fr [s] (4)
= 0.5 (Cr1 Lr)
Io 1 (Lr/Cr1) 2N
Here, vpp is the resonance voltage peak value.
vpp = [V] (5)
L1
VIN
SA V11 Lr Cr1 SB
SC V12 SD Cr2 SF
SE VOUT
L2
Subinterval: 5
Rev.5.0, Mar.15.2004, page 17 of 29
HA16163T * Time:t5 SB is turned on at point t5. The SB switching loss can be minimized by turning on SB when the SB both-side voltages are at a minimum (when the resonance voltage is at a peak). The SB turn-on timing can be set with TD1 of the HA16163. The time when the resonance voltage is at a peak is given by equation (4). From t5 onward, operation is on the same principle as in Subinterval 1 through Subinterval 5.
VIN L1
SA V11 Lr Cr1 SB
SC V12 SD Cr2 SF
SE VOUT
L2
Time:t5
Rev.5.0, Mar.15.2004, page 18 of 29
HA16163T Delay Setting Inter-output delays (TD1, TD2, TD3) are set by means of a resistance connected between the DELAY-1 (-2, -3) pin and GND. The following graph shows the relationship between the external resistance and delay. The typical value of the delay set time is given by the following equation.
TD = 0.5p[F] x RD[] + 8n[s] [s]
When the RD value is small, the set time will be larger than the above calculated value due to the effect of internal delay, etc., and therefore a constant setting should be made with reference to the following graph.
1.00E+03 TD vs. RD HA16163
TD (ns)
1.00E+02
(2.0V)
1.00E+01 RD
DELAY-1 (DELAY-2) (DELAY-3) GND
1.00E+00
1
10
100 RD (k)
1000
Figure 11 Place the resistor for connection to the DELAY-1,2,3 pin as close to the pin as is possible. Please design the pattern so that the level of cross-talk from other signals is minimized. DELAY-3 (TD3) There is a condition that secondary-side control output OUT-E and OUT-F delay TD3 is 0 s (typical) in order to prevent shorting of the transformer secondary side. The relationship between TD3 and the IC operating state is shown in the following table.
Mode Light load Pulse by pulse OCL One shot OCL Definition COMP < 1.65V CS 0.4V CS 0.6V Operation of OUT-E, OUT-F TD3 = 0 TD3 = 0 Fixed low (operation halted) Note 1 2
Notes: 1. Light-load detection is performed by means of the error amplifier output voltage. Light-load detection characteristics are as shown in the following diagram.
VREF
FB
Error Amp. - + 1.25V
500
Light Load Detector - +
TD3 TD3 set value
20k
COMP
10k
Comparator 0.4V
- +
0
1.46V 1.55V COMP voltage
Light Load Detector Characteristics
RAMP
2. TD3 of the next OUT-E or OUT-F after the pulse-by-pulse current limiter (PBP OCL) operates is 0 s (typical). When OUT-C and OUT-D are subsequently inverted by the Phase Shift Comparator, not the PBP OCL, TD3 is restored to the value set by means of the DELAY-3 pin.
Rev.5.0, Mar.15.2004, page 19 of 29
HA16163T
Application
Note: All voltage, current, time shown in the diagram are typical value. Sample application circuits are given here. Confirmatory experiments should be carried out when applying these examples to products. Slope Compensation In order to improve the unstable operation characteristic of current mode, voltage slopes in a current sense signal can be superimposed. The following is a possible slope compensation method.
5V(VREF)
HA16163 OUT-B OUT-C
Compensated signal Comparator - + 0.4V S Q R RES
OUT-A OUT-D
Current sense signal
RAMP
Figure 12 Driving a Pulse Transformer OUT-A through OUT-F of this IC are CMOS outputs that use Vref as their power supply. When directly driving a pulse transformer, the Vref voltage fluctuates according to the exciting current. As Vref fluctuation may make internal circuit operation unstable, direct drive of a pulse transformer should be avoided. * Case 1 (NG) The figure below shows a case where a pulse transformer is driven directly. Vref voltage fluctuation occurs due to the exciting current.
HA16163
Vref value fluctuates due to this exiting current
Vref Cref Internal Circuitry OUT-E
Case 1 (NG)
Rev.5.0, Mar.15.2004, page 20 of 29
HA16163T * Case 2 The figure below shows an example in which a current amplifier is added by means of transistors. A reverse current due to the exciting current is prevented by a blocking diode, and therefore capacitance CB is charged. In this way, fluctuation of the Cref potential is suppressed and stable operation can be achieved. As well as a buffer implemented by means of a transistor, standard logic IC or buffer IC connection is also possible. The buffer circuit power supply method should be implemented in the same way.
Blocking diode
HA16163
CB
Vref Cref Internal Circuitry OUT-E
Case 2 * Case 3 The figure below shows an example of a drive power supply method using emitter following. For the same reason as described above, fluctuation of the Cref potential is suppressed and stable operation can be achieved.
VCC
HA16163
CB
Vref Cref Internal Circuitry OUT-E
Case 3 Supplying Power from an External Power Supply It is also possible to use an external source as the power supply for the HA16163T as shown in figure 13. The VREFGOOD circuit controls whether the IC is operating or stopped. The threshold voltage of the VREFGOOD circuit is 4.6 V (typ.) on the rising edge and 4.4 V on the falling edge. Since the IC's characteristics vary with the value of the external voltage, this voltage must be provided by a high-precision 5-V source.
Vcc Vext 5V 2% VREF HA16163T
Figure 13
Rev.5.0, Mar.15.2004, page 21 of 29
HA16163T
Characteristic Curves
UVL Voltage vs. Ambient Temperature Characteristics 11.0 10.5 10.0 9.5
VH
VH (V)
9.0 8.5 8.0 VL 7.5 7.0 -40
-25
0
25
50 Ta (C)
75
100
125
Standby Current vs. Ambient Temperature Characteristics 160 Vcc = 8.5V 140 120 100
Is (A)
80 60 40 20 0 -40
-25
0
25
50 Ta (C)
75
100
125
Rev.5.0, Mar.15.2004, page 22 of 29
HA16163T
Operating Current vs. Ambient Temperature Characteristics 12
No load on VREF pin
10
8
Icc (mA)
6
4
2
0 -40
-25
0
25
50 Ta (C)
75
100
125
VREF Output Voltage vs. Ambient Temperature Characteristics 5.20 5.15 5.10 5.05
Vref (V)
5.00 4.95 4.90 4.85 4.80 -40
-25
0
25
50 Ta (C)
75
100
125
Rev.5.0, Mar.15.2004, page 23 of 29
HA16163T
Remote-on Voltage vs. Ambient Temperature Characteristics 1.48
1.46
1.44
VON (V)
1.42
1.40
1.38
1.36
1.34 -40
-25
0
25
50 Ta (C)
75
100
125
Remote-off Voltage vs. Ambient Temperature Characteristics 1.40
1.38
1.36
VOFF (V)
1.34
1.32
1.30
1.28
1.26 -40
-25
0
25
50 Ta (C)
75
100
125
Rev.5.0, Mar.15.2004, page 24 of 29
HA16163T
Error Amplifier Feedback Voltage vs. Ambient Temperature Characteristics 1.30 FB and COMP are shorted
1.28
1.26
VFB (V)
1.24 1.22 1.20 -40
-25
0
25
50 Ta (C)
75
100
125
Error Amplifier Source Current vs. Ambient Temperature Characteristics 0 FB = 0.75V, COMP = 2V -100
-200
ISOURCE (A)
-300
-400
-500
-600 -40
-25
0
25
50 Ta (C)
75
100
125
Rev.5.0, Mar.15.2004, page 25 of 29
HA16163T
Error Amplifier Sink Current vs. Ambient Temperature Characteristics 20 FB = 1.75V, COMP = 2V 18 16 14
ISINK (mA)
12 10 8 6 4 2 0 -40 -25 0 25 50 Ta (C) 75 100 125
Soft-start Pin Current vs. Ambient Temperature Characteristics -5 SS = 1V -6 -7 -8 -9
Iss (A)
-10 -11 -12 -13 -14 -15 -40 -25 0 25 50 Ta (C) 75 100 125
Rev.5.0, Mar.15.2004, page 26 of 29
HA16163T
Switching Frequency vs. Ambient Temperature Characteristics 580 560 540 520
fsw (kHz)
500 480 460 440 420 400 380 -40 -25 0 25 50 Ta (C) 75 100 125
TD1 Delay vs. Ambient Temperature Characteristics 50
45
40
TD1 (ns)
35
30
25
20
15 -40
-25
0
25
50 Ta (C)
75
100
125
Rev.5.0, Mar.15.2004, page 27 of 29
HA16163T
Current Sense Delay Time vs. Ambient Temperature Characteristics 70
60
50
Tpd (ns)
40
30
20
10
0 -40
-25
0
25
50 Ta (C)
75
100
125
Overcurrent Protection Delay Time vs. Ambient Temperature Characteristics 100
80
Tpd-cs (ns)
60
40
20
0 -40
-25
0
25
50 Ta (C)
75
100
125
Rev.5.0, Mar.15.2004, page 28 of 29
HA16163T
Package Dimensions
As of January, 2003
Unit: mm
6.50 6.80 Max 20 11
1
10 0.65 1.0 6.40 0.20 0.65 Max
*0.20 0.05
0.13 M
4.40
*0.15 0.05
1.10 Max
0.10
0.07 +0.03 -0.04
0 - 8
0.50 0.10
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-20DAV -- -- 0.07 g
Rev.5.0, Mar.15.2004, page 29 of 29

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