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ILX521A
256-pixel CCD Linear Image Sensor (B/W)
Description The ILX521A is a rectangular reduction type CCD linear image sensor designed for image scanner sensor. A built-in timing generator and clock driver ensure single 5V power supply for easy use. Features * Number of effective pixels: 256 pixels * Pixel size: 14m x 14m (14m pitch) * Built-in timing generator and clock driver * Built-in S/H circuit * Maximum data rate: 2MHz * Single 5V power supply * Clear mold package (12-pin SDIP) Absolute Maximum Ratings * Supply voltage VDD * Operating temperature * Storage temperature 12 pin SDIP (MOLD)
Block Diagram
ROG pulse generator
Mode selector
Pin Configuration (Top View)
VOUT 2 TEST 3 CLK 4 S/H SW 5 ROG 6
11 NC 10 NC 9 NC 8 VDD
256 7 NC
* Output amplifier * S/H circuit
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E99154-PS
TEST
3
VOUT
2
,
Clock driver GND 1 VDD 8 CLK 4
D7 D8
1
D12 S1 S2
12 NC
Clock pulse generator
GND 1
CCD analog shift register
Readout gate
S/H SW
5
S255 S256 D13
D17
6 -10 to +60 -30 to +80
V C C
ROG
6
ILX521A
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol GND VOUT TEST CLK S/H SW ROG NC VDD NC NC NC NC GND Signal output Test (open) Clock pulse input Switching of with S/H or without S/H Readout gate pulse input NC 5V power supply NC NC NC NC Description
Recommended Voltage Item VDD Min. 4.75 Typ. 5.0 Max. 5.25 Unit V
Mode Description Used mode with S/H without S/H Pin 5 S/H SW GND VDD
Input Clock Voltage Condition1 Item High level Low level VIH VIL Symbol Min. 4.5 0 Typ. VDD -- Max. VDD + 0.5 0.5 Unit V V
1 This is applied to the all external pulses. (CLK, ROG)
Input Pin Capacity Item Input capacity of CLK pin Input capacity of ROG pin Symbol CCLK CROG Min. -- -- Typ. 10 10 Max. -- -- Unit pF pF
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ILX521A
Electrooptical Characteristics (Ta = 25C, VDD = 5V, Data rate = 1MHz, Without S/H mode, Light source = 3200K, IR cut filter CM-500S (t = 1mm)) Item Sensitivity Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure Current consumption Total transfer efficiency Output impedance Offset level Symbol R PRNU VSAT VDRK DSNU IL DR SE IVDD TTE ZO VOS Min. 13.3 -- 0.6 -- -- -- -- -- -- 92.0 -- -- Typ. 19.0 5.0 0.8 0.3 0.5 0.02 2666 0.042 5.0 98.0 350 3.8 Max. 24.7 12.0 -- 2.0 3.0 -- -- -- 10.0 -- -- -- lx * s mA % V Unit V/(lx * s) % V mV mV % Remarks Note 1 Note 2 -- Note 3 Note 3 Note 4 Note 5 Note 6 -- -- -- Note 7
Note) 1. For the sensitivity test light is applied with a uniform intensity of illumination. 2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = (VMAX - VMIN)/2 x 100 [%] VAVE
D8 Vout
GND
,
D9 D10 D11 D12 S1 VOS
The maximum output of the 256 pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. 3. Integration time is 10ms. 4. VOUT = 500mV. 5. DR = VSAT/VDRK When optical integration time is shorter, the dynamic range sets wider because dark output voltage is in proportion to optical integration time. 6. SE = VSAT/R1 7. Vos is defined as indicated below.
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Clock Timing Diagram (without internal S/H mode)
5V
ROG
0V 269 271 273 268 270 272 1
5V
1
2
3
6
7
8
9 10 11 12 13 14
CLK
0V
D1
D2
D3
D6
D7
D8
D9
D10 D11 S1
D12 S2
S256 D13 D14
D15
D16
VOUT
Optical black (4 pixels)
Effective pixel signal (256 pixels)
Dummy signal (5 pixels)
Dummy signal (12 pixels) 1-line output period (273 pixels)
ILX521A
Note) 280 or more clock pulses are required.
D17
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Clock Timing Diagram (with internal S/H mode)
5V
ROG
0V
5V
0 6 7 8 9 10 11 12 13 14 1
1
2
3
269 271 273 268 270 272
CLK
0V
D0
D1
D2
D6
D7
D8
D9
D10 D11 S1
D12
S256 D13
D14
D15
D16
VOUT
Optical black (4 pixels)
Effective pixel signal (256 pixels)
Dummy signal (5 pixels)
Dummy signal (13 pixels) 1-line output period (274 pixels)
ILX521A
Note) 280 or more clock pulses are required.
D17
-5-
ILX521A
CLK Timing (For all modes)
t1 90% CLK 50% 10% t3 t4 t2
Item CLK pulse rise/fall time CLK pulse Duty1 1 100 x t4/(t3 + t4)
Symbol t1, t2 --
Min. 0 40
Typ. 10 50
Max. 100 60
Unit ns %
ROG, CLK Timing
t6 90% ROG 10% t7 90% CLK t5 t9 t8
Item ROG, CLK pulse timing 1 ROG, CLK pulse timing 2 ROG pulse rise/fall time ROG pulse period
Symbol t5 t9 t6, t8 t7
Min. 500 500 0 500
Typ. 1000 1000 10 1000
Max. -- -- -- --
Unit ns ns ns ns
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ILX521A
CLK Output Signal Timing (Note 1)
(Note 3)
CLK
t10 VOUT
t11
VOUT (Note 2)
t12
Item CLK - VOUT output delay time 1 CLK - VOUT output delay time 2 CLK - VOUT (with S/H) output delay time
Symbol t10 t11 t12
Min. -- -- --
Typ. 150 220 110
Max. -- -- --
Unit ns ns ns
Note 1) fck = 1MHz, CLK pulse Duty = 50%, CLK pulse rise/fall time = 10ns Note 2) Output waveform when internal S/H circuit is used. Note 3) * is data period.
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ILX521A
Application Circuit (without internal S/H mode)
5V
12 NC
11 NC
10 NC
9 NC
8 VDD S/H SW 5
7 NC ROG 6
TEST 3
1
2
3k Signal output CLK 2SA1175 ROG 0.01 22/10V
Note) This circuit diagram is the case when internal S/H mode is not used. Connect Pin 5 to GND when internal S/H mode is used.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CLK 4
VOUT
GND
ILX521A
Example of Representative Characteristics
Spectral sensitivity characteristics (Standard characteristics)
1 0.9 0.8 Relative sensitivity 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wavelength [nm] 800 900 1000
Output voltage vs. Temperature characteristics (Standard characteristics)
100 50
10 Output voltage rate 5
1 0.5
0.1 0.05
0.01 -10
0
10
20
30
40
50
60
Ta - Ambient temperature [C]
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ILX521A
Offset level vs. Temperature characteristics (Standard characteristics)
7 7
Offset level vs. VDD characteristics (Standard characteristics)
Ta = 25C
6 Vos ~ - -2mV/C Ta 5 Vos - Offset level [V] Vos - Offset level [V]
6 5
Vos ~ - 0.8 VDD
4
4 3
3
2
2
1
1
0 -10
0
10
20
30
40
50
60
0 4.75
5 VDD [V]
5.25
Ta - Ambient temperature [C]
Supply current vs. VDD characteristics (Standard characteristics)
10 9 8 IVDD - Supply current [mA] 7 6 5 4 3 2 1 0 4.75 5 VDD [V] 5.25 1 Output voltage rate 5 10
Output voltage vs. Integration time (Standard characteristics)
1
5 - Integration time [ms]
10
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ILX521A
Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering tool, ground the controller. For the temperature control system, use a zero-cross type. 3) Dust and dirt protection a) Operate in clean environments. b) Do not either touch mirror surfaces by hand or have any object come in contact with mirror surfaces. Should dirt stick to a mirror surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the mirror surfaces are grease stained. Be careful not to scratch the mirror surfaces. d) Keep in a case to protect from dust and dirt. To prevent dew condensation on the mirror surfaces, preheat or precool when moving to a room with great temperature differences. 4) Do not expose to intense light for long periods. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on.
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Package Outline
Unit: mm
12pin DIP (300mil)
0 to 15
A O3.0 depth 0.05 7
4.06 0.4
12
6.4 0.3 7.62
3.41 0.4
H 6
O1.0 depth 0.05 1st.pin Index.
1
6.2
1.27
2.26 0.1
11.43 0.3
0.05
0.15
V
No.1 Pixcel
3.0
0.8
0.3
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
Plastic
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42ALLOY
PACKAGE MASS
0.28g
ILX521A
DRAWING NUMBER
LS-F5(E)
3.5 0.3
- 12 -
0.5 DETAIL A 0.9
1. The height from the sensor surface is 1.41 0.3mm. 2. The refractive index of the resin is 1.57.
1.778

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