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IN82C55AN CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
The Integral IN82C55AN is a high-performance, CHMOS version of the industry standard IN82C55AN general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration. FEATURES
* * * * * * * * * * Compatible with all Intel and Most Other Microprocessors High Speed, Zero Wait State Operation with 8MHz 8086/88 and 80186/188 24 Programmable I/O Pins Low Power CHMOS Completely TTL Compatible Control Word Read-Back Capability Direct Bit Set/Reset Capability 2.5mA DC Drive Capability on all I/O Port Outputs Available in 40-Pin DIP Available in EXPRESS Standard Temperature Range Extended Temperature Range
GROUP A CONTROL
GROUP A PORT A (8)
PA7-PA0
D7-D0
DATA BUS BUFFER 8 BIT INTERNAL DATA BUS
GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4)
PC7-PC4
PC3-PC0
RD WR A1 A0 Reset
READ/ WRITE CONTROL LOGIC
GROUP B CONTROL
GROUP B PORT B (8)
PB7-PB0
CS
PA3 PA2 PA1 PA0 RD CS VSS A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2
1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
PA4 PA5 PA6 PA7 WR Reset D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3
Figure 1
Figure 2
1
IN82C55AN
Symbol PA3-0
RD
Pin number 1-4 5 6 7 8-9
Type I/O I I
Name and Function PORT A, PINS 0-3: Lower nibble of an 8-bit data output latch buffer and an 8-bit data input latch. READ CONTROL: This input is low during CPU read operations. CHIP SELECT: A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise. System Ground. ADDRESS: These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers. Input Operation (Read) A1 A0 CS WR RD Port A - Data Bus 0 0 0 1 0 Port B - Data Bus 0 1 0 1 0 Port C - Data Bus 1 0 0 1 0 Control Word - Data Bus 1 1 0 1 0
Output Operation (Write)
CS
GND A1-0
I
0 0 1 1
0 1 0 1
1 1 1 1
0 0 0 0
0 0 0 0
Data Bus - Port A Data Bus - Port B Data Bus - Port C Data Bus - Control Disable Function
PC7-4
10-13
I/O
PC0-3 PB0-7 VCC D7-0 RESET
WR
14-17 18-25 26 27-34 35 36 37-40
I/O I/O I/O I I I/O
PA7-4
Data Bus-3-State x x x x 1 Data Bus-3-State x x 1 1 0 PORT C, PINS 4-7: Upper nibble of an 8-bit data output latch/buffer and an 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. PORT C, PINS 0-3: Lower nibble of Port C. PORT B, PINS 0-7: An 8-bit data output latch/buffer and an 8bit data input buffer SYSTEM POWER: +5V Power Supply DATA BUS: Bi-directional, tri-state data bus lines, connected to system data bus RESET: A high on this input clears the control register and all ports are set to the input mode WRITE CONTROL: This input is low during CPU write operations PORT A PINS 4-7: Upper nibble of an 8-bit data output latch/buffer and an 8-bit data input latch
2
IN82C55AN
IN82C55AN FUNCTIONAL DESCRIPTION General The IN82C55AN is a programmable peripheral interface device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configuration of the IN82C55AN is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures. Data Bus Buffer This 3-state bidirectional 8-bit buffer is used to interface the IN82C55AN to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the IN82C55AN. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control Logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0) The control word register can be both written and read as shown in the address decode table in the pin descriptions. Figure 6 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic "1", as this implies control word mode information. Ports A, B, and C The IN82C55AN contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the IN82C55AN. Port A. One 8-bit data output latch/buffer and one 8-bit input latch/buffer. Both "pull-up" and "pull-down" bus hold devices are present on Port A. Port B. One 8-bit data input/output latch/buffer. Only "pull-up" bus hold devices are present on Port B. Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. Only "pull-up" bus hold devices are present on Port C. See Figure 4 for the bus-hold circuit configuration for Port A, B, and C.
3
IN82C55AN
GROUP A CONTROL GROUP A PORT A (8) PA7-PA0
D7-D0
DATA BUS BUFFER 8 BIT INTERNAL DATA BUS
GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4)
PC7-PC4
PC3-PC0
RD WR A1 A0 Reset
READ/ WRITE CONTROL LOGIC
GROUP B CONTROL
GROUP B PORT B (8)
PB7-PB0
CS
Figure 3. IN82C55AN Block Diagram Showing Data Bus Buffer and Read Write Control Logic Functions
RESET *
INTERNAL DATA IN
EXTERNAL INTERNAL PORT A DATA OUT PIN
INTERNAL DATA OUT
WR RESET P*
VCC
EXTERNAL PORT B,C PIN
INTERNAL DATA OUT
WR *NOTE: Port pins loaded with more than 20pF capacitance may not have their logic level guaranteed following a hardware reset.
Figure 4. Port A, B, C, Bus-hold Configuration
4
IN82C55AN
IN82C55AN OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software: Mode 0 - Basic input/output Mode 1 - Strobed Input/output Mode 2 - Bi-directional Bus When the reset input goes "high" all ports will be set to the input mode with all 24 port lines held at a logic "one" level by the internal bus hold devices (see Figure 4 Note). After the reset is removed the IN82C55AN can remain in the input mode with no additional initialization required. This eliminates the need for pullup or pulldown devices in "all CMOS" designs. During the execution of the system program, any of the other modes may be selected by using a single output instruction. This allows a single IN82C55AN to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be "tailored" to almost any I/O structure. For instance; Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis.
ADRESS BUS CONTROL BUS DATA BUS 8 RD, WR MODE 0 B D7-D0 C A0, A1 A
8 PB7-PB0
4 PC3-PC0 C
4 PC7-PC4
8 PA7-PA0
MODE 1
B
A
8 PB7-PB0
CONTROL OR I/O CONTROL OR I/O
8 PA7-PA0
MODE 2
B
C
A
8 PB7-PB0
I/O CONTROL
8 PA7-PA0
Figure 5. Basic Mode Definitions and Bus Interface
5
IN82C55AN
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 0 = MODE 0 1 = MODE 1 GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2 MODE SET FLAG 1 = ACTIVE
Figure 6. Mode Definition Format The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. Single Bit Set/Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. This feature reduces software requirements in Control-based applications. When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports.
D7 D6 D5 D4 D3 D2 D1 D0
BIT SET/RESET 1 = SET 0 =RESET
DON'T CARE
BIT SELECT 01234567 0 1 0 1 0 1 0 1 B0 0 0 1 1 0 0 1 1 B1 0 0 0 0 1 1 1 1 B2
BIT SET/RESET FLAG 0 = ACTIVE
Figure 7. Bit Set/Reset Format
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IN82C55AN
Interrupt Control Functions When the IN82C55AN is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. This function allows the Programmer to disallow or allow a specific I/O device to interrupt the CPU without affecting any other device in the interrupt structure. INTE flip-flop definition: (BIT-SET) - INTE is SET - Interrupt enable (BIT-RESET) - INTE is RESET - Interrupt disable Note: All Mask flip-flops are automatically reset during mode selection and device Reset. Operating Modes Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No "handshaking" is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions: * * * * * Two 8-bit ports and two 4-bit ports. Any port can be input or output. Outputs are latched. Inputs are not latched. 16 different Input/Output configurations are possible in this Mode.
MODE 0 (BASIC INPUT)
tRR RD tIR INPUT tAR CS, A 1 , A 0 tRA tHR
D 7 -D 0 tRD tDF
7
IN82C55AN
MODE 0 (BASIC OUTPUT)
WR tWW
tDW D7-D0 tAW CS ,A1,A0
tWD
tWA
OUTPUT tWB
MODE 0 Port Definition
A
D4 D3 D1
B
D0
GROUP A
PORT A PORT C (UPPER) #
GROUP B
PORT B PORT C (LOWER )
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
OUTPU T OUTPU T OUTPU T OUTPU T INPUT INPUT INPUT INPUT OUTPU T OUTPU T OUTPU T OUTPU T INPUT INPUT INPUT INPUT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OUTPU T OUTPU T INPUT INPUT OUTPU T OUTPU T INPUT INPUT OUTPU T OUTPU T INPUT INPUT OUTPU T OUTPU T INPUT INPUT
OUTPU T INPUT OUTPU T INPUT OUTPU T INPUT OUTPU T INPUT OUTPU T INPUT OUTPU T INPUT OUTPU T INPUT OUTPU T INPUT
8
IN82C55AN
MODE 0 Configurations
CONTROL WORD #0 D7 D6 D5 D4 1 0 0 0 D3 0 A D2 0 8 PA7-PA0 4 PC7-PC4 D7-D0 C... 4 PC3-PC0 8 B CONTROL WORD #2 D7 D6 D5 D4 1 0 0 0 PB7-PB0 B CONTROL WORD #3 D7 D6 D5 D4 1 0 0 0 8 PB7-PB0 D7-D0 C... 4 PC3-PC0 A D1 0 D0 0 CONTROL WORD #1 D7 D6 D5 D4 1 0 0 0 D3 0 D2 0 8 PA7-PA0 4 PC7-PC4 D1 0 D0 1
D3 0 A
D2 0 8
D1 1
D0 0
D3 0 A
D2 0 8
D1 1
D0 1
PA7-PA0 4 PC7-PC4
PA7-PA0 4 PC7-PC4
D7-D0
C...
4 PC3-PC0 8
D7-D0
C...
4 PC3-PC0 8
B CONTROL WORD #4 D7 D6 D5 D4 1 0 0 0
PB7-PB0
B CONTROL WORD #5 D7 D6 D5 D4 1 0 0 0
PB7-PB0
D3 1 A
D2 0 8
D1 0
D0 0
D3 1 A
D2 0 8
D1 0
D0 1
PA7-PA0 4 PC7-PC4
PA7-PA0 4 PC7-PC4
D7-D0
C...
4 PC3-PC0 8
D7-D0
C...
4 PC3-PC0 8
B CONTROL WORD #6 D7 D6 D5 D4 1 0 0 0
PB7-PB0
B CONTROL WORD #7 D7 D6 D5 D4 1 0 0 0
PB7-PB0
D3 1 A
D2 0 8
D1 1
D0 0
D3 1 A
D2 0 8
D1 1
D0 1
PA7-PA0 4 PC7-PC4
PA7-PA0 4 PC7-PC4
D7-D0
C...
4 PC3-PC0 8
D7-D0
C...
4 PC3-PC0 8
B
PB7-PB0
B
PB7-PB0
9
IN82C55AN
CONTROL WORD #8 D7 D6 D5 D4 1 0 0 1 D3 0 A D2 0 8 PA7-PA0 4 PC7-PC4 D7-D0 C... 4 PC3-PC0 8 B CONTROL WORD #10 D7 D6 D5 D4 1 0 0 1 PB7-PB0 B CONTROL WORD #11 D7 D6 D5 D4 1 0 0 1 8 PB7-PB0 D7-D0 C... 4 PC3-PC0 A D1 0 D0 0 CONTROL WORD #9 D7 D6 D5 D4 1 0 0 1 D3 0 D2 0 8 PA7-PA0 4 PC7-PC4 D1 0 D0 1
D3 0 A
D2 0 8
D1 1
D0 0
D3 0 A
D2 0 8
D1 1
D0 1
PA7-PA0 4 PC7-PC4
PA7-PA0 4 PC7-PC4
D7-D0
C...
4 PC3-PC0 8
D7-D0
C...
4 PC3-PC0 8
B CONTROL WORD #12 D7 D6 D5 D4 1 0 0 1
PB7-PB0
B CONTROL WORD #13 D7 D6 D5 D4 1 0 0 1
PB7-PB0
D3 1 A
D2 0 8
D1 0
D0 0
D3 1 A
D2 0 8
D1 0
D0 1
PA7-PA0 4 PC7-PC4
PA7-PA0 4 PC7-PC4
D7-D0
C...
4 PC3-PC0 8
D7-D0
C...
4 PC3-PC0 8
B
PB7-PB0
B
PB7-PB0
CONTROL WORD #14 D7 D6 D5 D4 1 0 0 1
D3 1 A
D2 0 8
D1 1
D0 0
CONTROL WORD #15 D7 D6 D5 D4 1 0 0 1
D3 1 A
D2 0 8
D1 1
D0 1
PA7-PA0 4 PC7-PC4
PA7-PA0 4 PC7-PC4
D7-D0
C...
4 PC3-PC0 8
D7-D0
C...
4 PC3-PC0 8
B
PB7-PB0
B
PB7-PB0
10
IN82C55AN
Operating Modes MODE 1 (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or "handshaking" signals. In mode 1, Port A and Port B use the lines on Port C to generate or accept these "handshaking" signals. Mode 1 Basic functional Definitions: * Two Groups (Group A and Group B). * Each group contains one 8-bit data port and one 4-bit control/data port. * The 8-bit data port can be either input or output * Both inputs and outputs are latched. * The 4-bit port is used for control and status of the * 8-bit data port. Input Control Signal Definition
STB (Strobe Input). A "low" on this input loads data into the input latch.
IBF (Input Buffer Full F/F) A "high" on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgement. IBF is set by STB input being low and is reset by the rising edge of the RD input. INTR (Interrupt Request) A "high" on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the STB is a "one", IBF is a "one" and INTE is a "one". It is reset by the falling edge of RD . This procedure allows an input device to request service from the CPU by simply strobing its data into the port. INTE A Controlled by bit set/reset of PC4. INTE B Controlled by bit set/reset of PC2
MODE 1 (PORT A) CONTROL WORD D6 D5 D4 D7 1 0 1 1
INTE A
PA7-PA0 PC4 PC5
8
D3 1/0
D2 X
D1 X
D0 X
STBA IBFA
PC6,7 1 = INPUT 0 = OUTPUT PC3 RD 2 PC6,7 INTRA
MODE 1 (PORT B) CONTROL WORD D6 D5 D4 D7 1 X X X
INTE B
PB7-PB0 PC2 PC1
8
D3 X
D2 1
D1 1
D0 X
STBB IBFB
RD
PC0
INTRB
Figure 8. MODE 1 Input
11
IN82C55AN
tST STB tSIB IBF tSIT
tRIB tRIT
INTR
RD tPH INPUT FROM PERIPHERAL tPS
Figure 9. MODE 1 (Strobed Input) Output Control Signal Definition
OBF (Output Buffer Full F/F). The OBF output will go "low" to indicate that the CPU has written data out to the specified port. The OBF F/F will be set by the rising edge of the WR input and reset by ACK Input being low.
ACK (Acknowledge Input). A "low" on this input informs the IN82C55AN that the data from Port A or Port B has been accepted. In essence, a response from the peripheral device indicating that it has received the data output by the CPU.
INTR (Interrupt Request). A "high" on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set when ACK is a "one", OBF is a "one" and INTE is a "one". It is reset by the falling edge of WR . INTE A Controlled by bit set/reset of PC6. INTE B Controlled by bit set/reset of PC2.
MODE 1 (PORT A) CONTROL WORD D7 D6 D5 D4 1 0 1 0
INTE A
PA7-PA0 PC6 PC7
8
D3 1/0
D2 X
D1 X
D0 X
ACKA OBFA
PC6,7 1 = INPUT 0 = OUTPUT PC3 WR 2 PC4,5 INTRA
MODE 1 (PORT B) CONTROL WORD D7 D6 D5 D4 1 X X X
INTE B
PB7-PB0 PC2 PC1
8
D3 X
D2 1
D1 0
D0 X
ACKB OBFB
WR
PC0
INTRB
Figure 10. MODE 1 Output
12
IN82C55AN
WR tAOB OBF tWOB INTR tWIT
ACK tAK OUTPUT tWB tAIT
Figure 11. MODE 1 (Strobed Output) Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
PA7-PA0 CONTROL WORD D7 D6 D5 D4 1 0 1 1 D3 1/0 D2 1 D1 0 D0 X PC4 PC5 PC6,7 1 = INPUT 0 = OUTPUT PC3 PC6,7 PB7-PB0 PC1 PC2 PC0 2
8
PA7-PA0 STBA IBFA INTRA CONTROL WORD D7 D6 D5 D4 1 0 1 0 D3 1/0 D2 1 D1 1 D0 X PC7 PC6 PC4,5 1 = INPUT 0 = OUTPUT PC3 PC4,5 PB7-PB0 PC2 PC1 PC0
8
OBFA ACKA 2 INTRA
8
WR
8
OBFB ACKB INTRB PORT A - STROBED OUTPUT PORT B - STROBED INPUT
WR
STBB IBFB INTRB
PORT A - STROBED INPUT PORT B - STROBED OUTPUT
RD
RD
Figure 12. Combinations of MODE 1 Operating Modes MODE 2 (Strobed Bidirectional Bus I/O).This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). "Handshaking" signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions: * * * * Used in Group A only. One 8-bit, bi-directional bus port (Port A) and a 5- bit control port (Port C). Both inputs and outputs are latched. The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A).
Bidirectional Bus I/O Control Signal Definition INTR (Interrupt Request). A high on this output can be used to interrupt the CPU for input or output operations. Output Operations
OBF (Output Buffer Full). The OBF output will go "low" to indicate that the CPU has written data out to port
A.
13
IN82C55AN
ACK (Acknowledge). A "low" on this input enables the tri-state output buffer of Port A to send out the data. Otherwise, the output buffer will be in the high impedance state.
INTE 1 (The INTE Flip-Flop Associated with OBF ). Controlled by bit set/reset of PC6. Input Operations STB (Strobe Input). A "low" on this input loads data into the input latch. IBF (Input Buffer Full F/F). A "high" on this output indicates that data has been loaded into the input latch. INTE 2 (The INTE Flip-Flop Associated with IBF). Controlled by bit set/reset of PC4.
CONTROL WORD D6 D5 D4 D7 1 1 X X
D3 X
D2 1/0
D1 1/0
D0 1/0 PC2-0 1 - INPUT 0 - OUTPUT PORT B 1 - INPUT 0 - OUTPUT GROUP B 1 - INPUT 0 - OUTPUT
WR
INTE 2 INTE 1
PC3
INTRA
PA7-PA0
PC7 PC6
OBFA ACKA
PC4 PC5 3 PC2-0
STBA IBFA
RD
Figure 13. MODE Control Word
Figure 14. MODE 2
14
IN82C55AN
DATA FROM CPU TO IN82C55AN WR
tAOB OBF tWOB INTR
tAK ACK tST STB tSIB IBF tAD tPS PERIPHERAL BUS tKD
tPH RD
tRIB
DATA FROM PERIPHERAL TO IN82C55AN
DATA FROM IN82C55AN TO PERIPHERAL
DATA FROM IN82C55AN TO 8080
Figure 15. MODE 2 (Bidirectional) NOTE: Any sequence where WR occurs before ACK , and STB ( INTR = IBF MASK STB RD + OBF MASK ACK WR ) occurs before
RD
is permissible.
15
IN82C55AN
PC3 CONTROL WORD D7 D6 D5 D4 1 1 X X D3 X D2 0 D1 1 D0 1/0 PA7-PA0 PC7 PC6 PC2-0 1 = INPUT 0 = OUTPUT WR RD PB7-PB0
8 8
INTRA CONTROL WORD D7 D6 D5 D4 1 1 X X D3 X D2 0 D1 0 D0 1/0
PC3 PA7-PA0 PC7 PC6 PC2-0 1 = INPUT 0 = OUTPUT WR RD PB7-PB0
8 8
INTRA
OBFA ACKA STBA IBFA 3
OBFA ACKA STBA IBFA 3
PC4 PC5 PC2-0
PC4 PC5 PC2-0
MODE 2 AND MODE 0 (INPUT)
MODE 2 AND MODE 0 (OUTPUT)
PC3 CONTROL WORD D7 D6 D5 D4 1 1 X X D3 X D2 1 D1 0 D0 X PA7-PA0 PC7 PC6 PC4 PC5 MODE 2 AND MODE 1 (OUTPUT) WR RD PB7-PB0 PC1 PC2 PC0
8 8
INTRA CONTROL WORD D7 D6 D5 D4 1 1 X X D3 X D2 1 D1 1 D0 X
PC3 PA7-PA0 PC7 PC6 PC4 PC5 MODE 2 AND MODE 1 (INPUT) WR RD PB7-PB0 PC1 PC2 PC0
8 8
INTRA
OBFA ACKA STBA IBFA
OBFA ACKA STBA IBFA
OBFB ACKB INTRB
STBB IBFB INTRB
Figure 16. MODE 1/4 Combinations Mode Definition Summary IN PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN MODE0 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN MODE1 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT INTRB
OBF B ACK B
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN INTRB IBFB STB B INTRA STB A IBFA I/O I/O
INTRA I/O I/O
ACK A OBF A
MODE2 GROUP A ONLY I/0 I/O I/O INTRA STB A IBFA
ACK A OBF A
MODE 0 OR MODE1 ONLY
16
IN82C55AN
Special Mode Combination Considerations There are several combinations of modes possible. For any combination, some or all of the Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a "Set Mode" command. During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 18. Through a "Write Port C" command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a "Write Port C" command, nor can the interrupt enable flags be accessed. To write to any Port C output programmed as an output in a Mode 1 group or to change an interrupt enable flag, the "Set/Reset Port C Bit" command must be used. With a "Set/Reset Port C Bit" command, any Port C line programmed as an output (including INTR, IBF and OBF ) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C are not affected by a "Set/Reset Port C Bit" command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the "Set/Reset Port C Bit" command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 18. Current Drive Capability Any output on Port A, B or C can sink or source 2.5mA. This feature allows the IN82C55AN to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. Reading Port C Status In Mode 0, Port C transfers data to or from the peripheral device. When the IN82C55AN is programmed to function in Modes 1 or 2, Port C generates or accepts "hand-shaking" signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the "status" of each peripheral device and change the program flow accordingly. There is no special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function.
D7 I/O D6 I/O INPUT CONFIGURATION D5 D4 D3 D2 D1 D0 IBFA INTEA INTRA INTEB IBFB INTRB GROUP A GROUP B
D7 OBFA
OUTPUT CONFIGURATION D6 D5 D4 D3 D2 D1 D0 INTEA I/O I/O INTRA INTEB OBFB INTRB GROUP A GROUP B
Figure 17a. MODE 1 Status Word Format
D5 D4 D3 IBFA INTE2 INTRA GROUP A (Defined by mode 0 or mode 1 selektion) D7 OBFA D6 INTE1 D2 D1 GROUP B D0
Figure 17b. MODE 2 Status Word Format
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IN82C55AN
Interrupt Enable Flag INTEB INTEA2 INTEA1 Position PC2 PC4 PC6 Alternate ACKB (Output Mode 1) or STBB (Input Mode 1) STBA (Input Mode 1 or Mode 2) ACKA (Output Mode 1 or Mode 2)
Figure 18. Interrupt Enable Flags in Modes 1 and 2
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias Storage Temperature Supply Voltage Operating Voltage Voltage on any Input Voltage on any Output Power Dissipation 0OC to + 70OC - 65OC to + 150OC - 0.5 to + 8.0V + 4V to + 7V GND-2V to + 6.5V GND-0.5V to VCC + 0.5V 1Watt
NOTICE: This is a production data sheet. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
D.C. CHARACTERISTICS
Symbol VIL VIH VOL VOH IIL IOFL IDAR IPHL IPHH IPHLO IPHHO ICC ICCSB
TA = 0OCto70OC, VCC =+5V 10%, GND = 0V (TA =-40OC to +85OC for Extended Temperature)
Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current Output Float Leakage Current Darlington Drive Current Port Hold Low Leakage Current Port Hold High Leakage Current Port Hold Low Overdrive Current Port Hold High Overdrive Current VCC Supply Current VCC Supply CurrentStandby Min -0.5 2.0 3.0 VCC - 0.4 1 10 2.5 +50 -50 -350 +350 10 10 (Note 4) +300 -300 Max 0.8 VCC 0.4 Units V V V V V A A mA A A A A mA A Test Conditions
IOL = 2.5mA IOH =-2.5mA IOH =-100A VIN = VCC to 0V (Note 1) IN = VCC to 0V (Note 2) Ports A,B,C Rext = 500 Vext = 1.7V VOUT = 1.0V Port A only VOUT = 3.0V Ports A,B,C VOUT = 0.8V VOUT = 3.0V (Note 3) VCC = 5.5V VIN = VCC or GND Port Conditions If I/P = Open/High O/P = Open Only With Data Bus = High/Low CS = High Reset = Low Pure Inputs = Low/High
NOTES:
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IN82C55AN
1. 2. 3. 4. Pins A1, A0, CS, WR, RD, Reset Data Bus; Ports B, C Outputs open. Limit output current to 4.0mA.
CAPACITANCE
TA = 25OC, VCC = GND = 0V Symbol Parameter CIN Input Capacitance CI/O I/O Capacitance NOTE: 5. Sampled not 100% tested. Min Max 10 20 Units pF pF TestConditions Unmeasured pins returned to GND fC = 1MHz(5)
A.C. CHARACTERISTICS
TA = 0O to 70OC, VCC = +5V 10%, GND = 0V TA = -40OC to +85OC for Extended Temperature
BUS PARAMETERS READ CYCLE
Symbol Parameter Min Max Units Test Conditions
tAR tRA tRR tRD tDF tRV
Address Stable Before RD _ Address Hold Time After RD _ RD Pulse Width Data Delay from RD _ RD _ to Data Floating Recovery Time between RD / WR Parameter
0 0 150 10 200
Min
120 75
ns ns ns ns ns ns
Units Test Conditions
WRITE CYCLE
Symbol Max
tAW tWA tWW tDW tWD
Address Stable Before WR _ Address Hold Time After WR _
WR Pulse Width Data Setup Time Before WR _ Data Hold Time After WR _
0 20 20 100 100 30 30
ns ns ns ns ns ns ns
PortsAB PortC
PortsAB PortC
19
IN82C55AN
OTHER TIMINGS
Symbol tWB tlR tHR tAK tST tPS tPH tAD tKD tWOB tAOB tSIB tRIB tRIT tSIT tAIT tWIT tRES Parameter
WR = 1 to Output Peripheral Data Before RD Peripheral Data After RD ACK Pulse Width STB Pulse Width Per. Data Before STB High Per. Data After STB High ACK = 0 to Output ACK = 1 to Output Float WR = 1 to OBF = 0 ACK = 0 to OBF = 1 STB = 0 to IBF = 1 RD = 1 to IBF = 0 RD = 0 to INTR = 0 STB = 1 to INTR = 1 ACK = 1 to INTR = 1
Min 0 0 200 100 20 50 20
Max 350
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Test
Conditions
WR = 0 to INTR = 0
Reset Pulse Width 500
175 250 150 150 150 150 200 150 150 200
see note1 see note2
NOTE 1. INTR_ may occur as early as WR _. 2. Pulse width of initial Reset pulse after power on must be at least 50Sec. Subsequent Reset pulses may be 500ns minimum. The output Ports A B or C may glitch low during the reset pulse but all port pins will be held at a logic "one" level after the reset pulse. WRITE TIMING
A0-1,CS tAW DATA BUS tDW WR tWW tWD tWA
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IN82C55AN
READ TIMING
A0-1,CS tAR DATA BUS
HIGH IMPEDANCE VALID
tRA
HIGH IMPEDANCE
tRD RD tRR
tDR
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
2.4 2.0 TEST POINTS 0.45 0.8 0.8 2.0 CL=150pF
A.C. Testing Inputs Are Driven At 2.4V For A Logic 1 And 0.45V For A Logic 0 Timing Measurements Are Made At 2.0V For A Logic 1 And 0.8 For A Logic 0.
A.C. TESTING LOAD CIRCUIT
DEVICE UNDER TEST CL=150pF
VEXT*
*VEXT Is Set At Various Voltages During Testing To Guarantee The Specification. C L Includes Jig Capacitance.
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