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19-3585; Rev 0; 2/05
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface
General Description
The MAX5109 dual 8-bit digital-to-analog converters (DACs) feature nonvolatile registers. These nonvolatile registers store the DAC operating modes and output states, allowing the DACs to initialize to specified configurations at power-up. Precision on-chip output buffers swing rail-to-rail, and provide 8s settling time. The I2C*-compatible, 2-wire serial interface allows for a maximum clock frequency of 400kHz. The MAX5109 has independent high and low reference inputs allowing maximum output voltage range flexibility. The reference rails accept voltage inputs that range from ground to the positive supply rail. This device operates from a single +2.7V to +5.25V supply and consumes 200A per DAC. A software-controlled power-down mode decreases supply current to less than 25A. A software-controlled mute mode sets each DAC, or both DACs simultaneously, to their respective REFL_ voltages. The MAX5109 also includes an asynchronous MUTE input, that drives both DAC outputs simultaneously to their respective REFL_ voltages. The MAX5109 is available in a 16-pin QSOP and is specified for operation over the extended (-40C to +85C) temperature range.
Features
o Nonvolatile Registers Initialize DACs to Stored States o +2.7V to +5.25V Single-Supply Operation o Dual 8-Bit DACs with Independent High and Low Reference Inputs o Rail-to-Rail Output Buffers o Low 200A per DAC Supply Current o Power-Down Mode Reduces Supply Current to 25A (max) o 400kHz, I2C-Compatible, 2-Wire Serial Interface o Asynchronous MUTE Input o Small 16-Pin QSOP Package
MAX5109
Ordering Information
PART MAX5109EEE TEMP RANGE -40C to +85C PIN-PACKAGE 16 QSOP
Applications
Digital Gain and Offset Adjustments Programmable Attenuators Portable Instruments Power-Amp Bias Control ATE Calibration Laser Biasing
MUTE SCL SDA A3 A2 A1 A0 2-WIRE SERIAL INTERFACE/ CONTROL MAX5109
Simplified Diagram
VDD REFH0 REFL0 DAC0 NONVOLATILE/ VOLATILE REGISTERS
DAC0 OUT0
REFH1 REFL1 DAC1 NONVOLATILE/ VOLATILE REGISTERS
Pin Configuration and Typical Operating Circuit appear at end of data sheet.
DAC1 OUT1
GND
*Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associate Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification defined by Philips. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.) VDD, A0, A1, A2, A3, SCL, SDA, MUTE.................-0.3V to +6.0V OUT0, OUT1, REFH0, REFH1 REFL0, REFL1 .......................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................50mA Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3mW/C above +70C)...........667mW Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V, GND = 0, REFH_ = VDD, REFL_ = GND, RLOAD = 5k, CL = 100pF, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1)
PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity (Note 2) Offset Error Offset Temperature Coefficient Gain Error Gain-Error Temperature Coefficient Power-Supply Rejection Ratio PSRR INL DNL ZCE Code range 0A hex to F0 hex Full code range Code range 0A hex to F0 hex Full code range Code = 0A hex Code = 0A hex Code = F0 hex (Note 3) Code = F0 hex Code = FF hex or 0A hex, VREFH_ = 2.5V, VREFL_ = 0, f = DC 0.002 1 20 1 1 20 2 0.5 8 1 Bits LSB LSB mV V/C LSB LSB/C LSB/V SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE INPUT (REFH_, REFL_) Input Voltage Range Input Resistance Input-Resistance Temperature Coefficient Input Capacitance DAC OUTPUTS (OUT_) Load Regulation Output Leakage Amplifier Output Resistance DIGITAL INPUTS (A_, MUTE) Input High Voltage (Note 4) VIH 2.7V VDD < 3.6V 3.6V VDD 5.25V 0.7 x VDD 2.52 V Code = F0 hex, RLOAD 5k DAC powered down, not muted 0.5V VOUT_ (VDD - 0.5V) 0.5 0.5 1 10 LSB A VREFH_, VREFL_ VREFH_ VREFL_ 0 320 460 35 10 VDD 600 V k ppm/C pF
2
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, GND = 0, REFH_ = VDD, REFL_ = GND, RLOAD = 5k, CL = 100pF, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1)
PARAMETER Input Low Voltage (Note 4) SYMBOL VIL CONDITIONS 2.7V VDD < 3.6V 3.6V VDD 5.25V Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (SDA) Output Low Voltage Tri-State Leakage Tri-State Output Capacitance DYNAMIC PERFORMANCE SCL to OUT_ Settling Crosstalk Multiplying Signal-to-Noise Plus Distortion Multiplying Bandwidth Reference Feedthrough Clock Feedthrough Output Noise Power-Up Time Power-Down Time INTERFACE PORTS (SCL, SDA) VIL Input Voltage VIH Input Hysteresis Input Current Input Capacitance POWER SUPPLIES Power-Supply Voltage Supply Current Power-Down Current VDD IDD ILOAD = 0, digital inputs at GND or VDD Normal operation During nonvolatile write 2.70 0.4 5.25 0.7 2 25 mA A V VHYS IIN CIN 5 0.7 x VDD 0.05 x VDD 1 V A pF 0.3 x VDD eN tSDR tSDN From power-down state SINAD tCOS (Note 5) VREFH_ = 2.5VP-P at 10kHz (Note 6) VREFH_ = 2.5VP-P at 1kHz VREFH_ = 2.5VP-P at 10kHz VREFH_ = 0.5VP-P, 3dB bandwidth VREFH_ = 2.5VP-P at f = 10kHz (Note 7) 8 55 65 52 325 88 2.5 800 4 1.5 s dB dB kHz dB nVs nV/Hz s s VOL IL COUT 15 ISINK = 3mA ISINK = 6mA 0.4 0.6 1 V A pF VHYS IIN CIN VIN = 0 or VDD 10 0.05 x VDD 1 MIN TYP MAX 0.3 x VDD 1.1 V A pF UNITS V
MAX5109
V
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, GND = 0, REFH_ = VDD, REFL_ = GND, RLOAD = 5k, CL = 100pF, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1)
PARAMETER DIGITAL TIMING (Figure 3, Note 8) SCL Clock Frequency Setup Time for START Condition Hold Time for START Condition SCL High Time SCL Low Time Data Setup Time Data Hold Time SDA, SCL Rise Time SDA, SCL Fall Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of Spike Suppressed Maximum Capacitive Load for Each Bus Line Write NV Register Busy Time NONVOLATILE MEMORY RELIABILITY Data Retention Endurance TA= +85C TA= +25C TA= +85C 50 200,000 50,000 Years Stores fSCL tSU:STA tHD:STA tHIGH tLOW tSU:DAT tHD:DAT tR tF tSU:STO tBUF tSP CB (Note 9) (Note 10) 400 15 0.6 1.3 50 0.6 0.6 0.6 1.3 100 0 0.9 300 300 400 kHz s s s s ns s ns ns s s ns pF ms SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: All devices are 100% production tested at TA = +25C. All temperature limits are guaranteed by design. Note 2: Guaranteed monotonic. Note 3: Gain error is defined as:
256 x (VF0,Meas - ZCE - VF0,Ideal ) VREFH _
where VF0,Meas is the DAC voltage with input code F0 hex and VF0,Ideal is the ideal DAC voltage with input code F0 hex or (VREFH - VREFL) x (240 / 256) + VREFL. Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND + 0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 5: Output settling time is measured from the 50% point of the rising edge of the last SCL of the data byte to 0.5 LSB of OUT_'s final value for a code transition from 10 hex to F0 hex. Note 6: Crosstalk is defined as the coupling from a DAC switching from code 00 hex to code FF hex to any other DAC that is in a steady state at code 00 hex. Note 7: Reference feedthrough is defined as the coupling from one driven reference with input code = FF hex to any other DAC output with the reference of the DAC at a constant value and input code = 00 hex. Note 8: SCL clock period includes rise and fall times tR and tF. All digital input signals are specified with tR = tF = 2ns and timed from a voltage level of (VIL + VIH) / 2. Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf. Note 10:The busy time begins from the initiation of the stop pulse.
4
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
Typical Operating Characteristics
(VDD = +3V, VREFH_ = +3V, VREFL_ = GND, RL = 5k, CL = 100pF, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. INPUT CODE
MAX5109 toc01
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5109 toc02
INTEGRAL NONLINEARITY vs. TEMPERATURE
1.75 INTEGRAL NONLINEARITY (LSB) 1.50 1.25 1.00 0.75 0.50 0.25 0
MAX5109 toc03
2.0 INTEGRAL NONLINEARITY (LSB) 1.5 1.0 0.5 0 -0.5 -1.0 0 64 128 INPUT CODE 192
2.00 1.75 INTEGRAL NONLINEARITY (LSB) 1.50 1.25 1.00 0.75 0.50 0.25 0
2.00
256
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
MAX5109 toc04
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5109 toc05
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
MAX5109 toc06
1.00 DIFFERENTIAL NONLINEARITY (LSB) 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 64 128 INPUT CODE 192
0 DIFFERENTIAL NONLINEARITY (LSB) -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 2.5 3.0 3.5 4.0 4.5 5.0
-0.8 DIFFERENTIAL NONLINEARITY (LSB)
-0.9
-1.0
-1.1
-1.2 5.5 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C)
256
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX5109 toc07
OFFSET ERROR vs. TEMPERATURE
MAX5109 toc08
GAIN ERROR vs. SUPPLY VOLTAGE
MAX5109 toc09
0.5
0.40
-0.06 -0.08 GAIN ERROR (LSB) -0.10 -0.12 -0.14 -0.16 -0.18
OFFSET ERROR (LSB)
0.3
OFFSET ERROR (LSB)
0.4
0.35
0.30
0.2
0.25
0.1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
0.20 -40 -15 10 35 60 85 TEMPERATURE (C)
-0.20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
Typical Operating Characteristics (continued)
(VDD = +3V, VREFH_ = +3V, VREFL_ = GND, RL = 5k, CL = 100pF, TA = +25C, unless otherwise noted.)
OFFSET OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
MAX5109 toc10 MAX5109 toc11
GAIN ERROR vs. TEMPERATURE
-0.08 -0.10 GAIN ERROR (LSB) -0.12 -0.14 -0.16 -0.18 -0.20 -40 -15 10 35 60 85 TEMPERATURE (C) 0.40
FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX5109 toc12
5.0 FULL-SCALE OUTPUT VOLTAGE (V) 4.5 4.0 3.5 3.0 2.5 2.0 VDD = VREFH_ = 3V
VREFL_ = 0.2V OFFSET OUTPUT VOLTAGE (V) 0.35
VDD = VREFH_ = 5V
0.30 VDD = VREFH_ = 5V 0.25
0.20 VDD = VREFH_ = 3V 0.15 0 2 4 6 8 10 OUTPUT SINK CURRENT (mA)
0
3
6
9
12
15
OUTPUT SOURCE CURRENT (mA)
SUPPLY CURRENT vs. INPUT CODE
MAX5109 toc13
SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE
NO LOAD VDD = VREFH_ = +5V
MAX5109 toc14
SUPPLY CURRENT vs. TEMPERATURE
A 340 SUPPLY CURRENT (A) 320 300 280 260 240 NO LOAD C D B
MAX5109 toc15
450 NO LOAD 425 SUPPLY CURRENT (A) 400 375 350 325 300 275 250 0 64 128 INPUT CODE 192
1000
360
SUPPLY CURRENT (A)
256
100 0 1 2 3 4 5 DIGITAL INPUT VOLTAGE (V)
220 -40 -15 10 35 60 85 TEMPERATURE (C) A: VDD = 5V, VREFH_ = 4.096V, CODE = FFh B: VDD = 5V, VREFH_ = 4.096V, CODE = 00h C: VDD = 3V, VREFH_ = 2.5V, CODE = FFh D: VDD = 3V, VREFH_ = 2.5V, CODE = 00h
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
Typical Operating Characteristics (continued)
(VDD = +3V, VREFH_ = +3V, VREFL_ = GND, RL = 5k, CL = 100pF, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5109 toc16
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX5109 toc17
REFERENCE FEEDTHROUGH vs. FREQUENCY
MEASURED AT OUT1, VREFL1 = VREFL0 = GND, VREFH1 = VDD, VREFH0 = 2.5VP-P, SIGNAL CENTERED AT VDD/2, OUT0 = FFh, OUT1 = 00h, NO LOAD V = 5V
DD
MAX5109 toc18
360 340 SUPPLY CURRENT (A) 320 300 280 260 240 220 2.5 3.0 3.5 4.0 4.5 5.0 TA = -40C TA = +85C TA = +25C NO LOAD CODE 00h
400 NO LOAD 375 SUPPLY CURRENT (A) 350 325 300 275 250 225 200 VDD = 3V CODE = 00h 0 1 2 3 4 5 REFERENCE VOLTAGE (V) VDD = 3V CODE = FFh VDD = 5V CODE = 00h VDD = 5V CODE = FFh
-40 REFERENCE FEEDTHROUGH (dB) -50 -60 -70 -80 -90 -100
VDD = 3V
5.5
0.01
0.1
1
10
100
1000 10,000 100,000
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
STARTUP GLITCH
MAX5109 toc19
POWER-DOWN TRANSITION
MAX5109 toc20
POWER-UP TRANSITION
MAX5109 toc21
SCL 2V/div VDD 2V/div GND 26 GND 25 26 27
SCL 2V/div GND
OUT_ 1V/div GND NV REGISTER PREVIOUSLY SET TO CODE FFh 100s/div 400ns/div
OUT_ 500mV/div GND
OUT_ 500mV/div GND 1s/div
POSITIVE CARRY TRANSITION
MAX5109 toc22
NEGATIVE CARRY TRANSITION
MAX5109 toc23
POSITIVE SETTLING TIME
MAX5109 toc24
SCL 2V/div OUT_ 50mV/div AC-COUPLED OUT_ 50mV/div AC-COUPLED 25 26 27 GND
OUT_ 1V/div GND 4s/div 2s/div 2s/div
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
Typical Operating Characteristics (continued)
(VDD = +3V, VREFH_ = +3V, VREFL_ = GND, RL = 5k, CL = 100pF, TA = +25C, unless otherwise noted.)
NEGATIVE SETTLING TIME
MAX5109 toc25
CLOCK FEEDTHROUGH
MAX5109 toc26
OUTPUT CROSSTALK
MAX5109 toc27
SCL 2V/div 25 GND 26 27
SCL 2V/div GND
SCL 2V/div GND OUT0 2V/div GND
OUT_ 1V/div GND 2s/div OUT_ SET TO 7Fh 1s/div
OUT_ 10mV/div AC-COUPLED OUT1_ SET TO 7Fh 2s/div
OUT1 10mV/div AC-COUPLED
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME A3 A2 A1 A0 REFH1 REFL1 OUT1 GND MUTE N.C. OUT0 REFL0 REFH0 SCL VDD SDA FUNCTION Address Select 3. Connect to VDD or GND to set the device address. Address Select 2. Connect to VDD or GND to set the device address. Address Select 1. Connect to VDD or GND to set the device address. Address Select 0. Connect to VDD or GND to set the device address. DAC1 High Reference Input. REFH1 must be equal to or greater than REFL1. DAC1 Low Reference Input. REFL1 must be equal to or less than REFH1. DAC1 Output. OUT1 is buffered with a unity-gain amplifier. Ground Active-Low Mute Input. Connect MUTE low to drive all DAC outputs to their respective reference low voltages. Connect MUTE to VDD for normal operation. No Connection. Not internally connected. DAC0 Output. OUT0 is buffered with a unity-gain amplifier. DAC0 Low Reference Input. REFL0 must be equal to or less than REFH0. DAC0 High Reference Input. REFH0 must be equal to or greater than REFL0. Serial Clock Input. Connect SCL to VDD through a 2.4k pullup resistor. Positive Power Input. Connect VDD to a +2.7 to +5.25V power supply. Bypass VDD to GND with a 0.1F capacitor as close to the device as possible. Serial Data Input/Output. Connect SDA to VDD through a 2.4k pullup resistor.
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
VDD 15 MAX5109 MUTE 9 SCL 14 SDA 16 A3 1 A2 2 A1 3 A0 4 POR 8 GND DAC1 NONVOLATILE REGISTER DAC1 VOLATILE REGISTER DAC1 7 OUT1 2-WIRE SERIAL INTERFACE/ CONTROL DAC0 NONVOLATILE REGISTER DAC0 VOLATILE REGISTER DAC0 11 OUT0 13 REFH0 12 REFL0
5 REFH1 6 REFL1
Figure 1. MAX5109 Functional Diagram
Detailed Description
The MAX5109 8-bit DACs feature internal, nonvolatile registers that store the DAC states for initialization during power-up. This device consists of resistor-string DACs, rail-to-rail output buffers, a shift register, poweron reset (POR) circuitry, and volatile and nonvolatile memory registers (Figure 1). The shift register decodes the control and address bits, routing the data to the proper registers. Writing data to a selected volatile register immediately updates the DAC outputs. The volatile registers retain data as long as the device is powered. Removing power clears the volatile registers. The nonvolatile registers retain data even after power is removed. On startup, when power is first applied, data from the nonvolatile registers is transferred to the volatile registers to automatically initialize the device. Read data from the nonvolatile or volatile registers using the 2-wire serial interface.
REFH_ R0 R1 R15
D7 D6 D5 D4 MSB DECODER R16
R255 REFL_
LSB DECODER D3 D2 D1 D0
DAC
DAC Operation
The MAX5109 uses a DAC matrix decoding architecture that saves power. A resistor string divides the difference between the external reference voltages, VREFH_ and VREFL_. Row and column decoders select the appropriate tap from the resistor string, providing the equivalent analog voltage. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. Figure 2 shows a simplified diagram of one DAC.
Figure 2. DAC Simplified Circuit Diagram
Output Buffer Amplifiers
The MAX5109 analog outputs are internally buffered by precision unity-gain amplifiers. The outputs swing from GND to VDD with a VREFL_-to-VREFH_ output transition. The amplifier outputs typically settle to 0.5 LSB in 8s when loaded with 5k in parallel with 100pF.
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9
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
tR SDA tSU:DAT tLOW tHD:DAT tSU:STA tHD:STA tSU:STO tBUF tF
SCL tHD:STA S PARAMETERS ARE MEASURED FROM 30% TO 70%. tHIGH tR tF Sr ACK P S
Figure 3. 2-Wire Serial-Interface Timing Diagram
DAC Registers
The MAX5109 features two registers per DAC, a volatile and a nonvolatile register, that store the DAC data. The volatile DAC register holds the current value of each DAC. Write data to the volatile registers directly from the 2-wire serial interface or by loading the previously stored data from the respective nonvolatile register. Clear the volatile registers by removing power to the device. The volatile registers are read/write. The nonvolatile register retains the DAC values even after power is removed. Read stored data using the 2wire serial interface. On power-up, the device is automatically initialized with data stored in the nonvolatile registers. The nonvolatile registers are read/write and programmed to all zeros at the factory.
S SDA Sr P
SCL
Figure 4. START and STOP Conditions
ported. The device's address is compatible with 7-bit I2C addressing protocol only. No 10-bit address formats are supported.
Serial Interface
The MAX5109 features an I2C-compatible, 2-wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX5109 and the master at rates up to 400kHz (Figure 3). The master (typically a microcontroller) initiates data transfer on the bus and generates SCL. SDA and SCL require pullup resistors (2.4k or greater; see the Typical Operating Circuit). Optional resistors (24) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit transfers during each SCL rising edge. Nine clock cycles are required to transfer the data into or out of the MAX5109. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are read as control signals (see the START and STOP Conditions section). Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high. The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of a transmission to the MAX5109. The master terminates transmission by issuing a STOP condition. The STOP condition frees the bus. If a REPEATED START condition (Sr) is generated instead of a STOP condition, the bus remains active.
I2C Compatibility
The MAX5109 is compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open-drain output. The Typical Operating Circuit shows an I2C application. The communication protocol supports standard I2C 8-bit communications. The general call address is ignored, and CBUS formats are not sup10
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
Early STOP Conditions
The MAX5109 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 5). This condition is not a legal I2C format.
Acknowledge Bit (ACK) and NotAcknowledge Bit (NACK)
Successful data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX5109 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 6). To generate a not acknowledge, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time.
REPEATED START Conditions
A REPEATED START (Sr) condition is used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5109 serial interface supports continuous write operations with an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow.
SCL SDA STOP START
Slave Address
A master initiates communication with a slave device by issuing a START condition followed by a slave address (Figure 7). The slave address consists of 7 address bits and a read/write bit (R/W). When idle, the device continuously waits for a START condition followed by its slave address. When the device recognizes its slave address, it acquires the data byte and executes the command. The first 3 bits (MSBs) of the slave address have been factory programmed and are always 010. Connect A3-A0 to VDD or GND to program
LEGAL STOP CONDITION
SCL SDA
ILLEGAL STOP ILLEGAL EARLY STOP CONDITION
START
Figure 5. Early STOP Conditions
S SDA ACKNOWLEDGE SCL 1 8 9
NOT ACKNOWLEDGE
Figure 6. Acknowledge and Not-Acknowledge Bits
S SDA 0 1 0 A3 A2 A1 A0 R/W ACKNOWLEDGE SCL 1 2 3 4 5 6 7 8 9 ACK
Figure 7. Slave Address Byte ______________________________________________________________________________________ 11
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
MSB S 0 1 0 A3 A2 A1 A0 LSB R/W =0 ACK MSB C7 1 LSB C0 R0 ACK
C6 0
C5 NV
C4 V
C3 R3
C2 R2
C1 R1
ADDRESS AND COMMAND BYTES GENERATED BY MASTER DEVICE MSB Sr 0 1 0 A3 A2 A1 A0 LSB R/W =1 ACK MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 NACK P
DATA BYTE GENERATED BY MAX5109
NACK GENERATED BY MASTER DEVICE
Figure 8. Example Read Word Data Sequence
the remaining 4 bits of the slave address. The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX5109. (R/W = 0 selects a write condition. R/W = 1 selects a read condition.) After receiving the address, the MAX5109 (slave) issues an acknowledge by pulling SDA low for one clock cycle.
write cycle does not update the DAC. See Table 4 for a summary of the write commands.
Read Cycle
A read command requires 36 clock cycles. In read mode, the MAX5109 sends the contents of the volatile and nonvolatile registers to the bus. Reading a register requires a REPEATED START (Sr) condition. To read a register first, write a read command (R/W = 0, Figure 8). Set the most significant 2 bits of the command byte to 10 (C7 = 1 and C6 = 0). Set bits C5 and C4 to read from either the volatile or nonvolatile register (Table 5). Set bits C3-C0 to select the desired DAC register (Table 6). After the command byte, send a Sr condition followed by the address of the device (R/W = 1). The MAX5109 then acknowledges and sends the data to the bus.
Write Cycle
The write command requires 27 clock cycles. In write mode (R/W = 0), the command byte that follows the address byte controls the MAX5109 (Table 1). For a write function, set bits C7 and C6 to zero. Set bits C5 and C4 to select the volatile or nonvolatile register (Table 2). Set bits C3-C0 to select the respective DAC register (Table 3). The registers update on the rising edge of the 26th SCL pulse. Prematurely aborting the
Table 1. Write Operation
START ADDRESS BYTE R/W 010 A 3 A 2 A 1 A 0 0 A C K C 7 C 7 C 6 C 6 COMMAND BYTE C 5 N V C 4 V CCC 321 RRR 321 C 0 R 0 A C K D 7 D 6 DATA BYTE STOP D 5 D 4 D 3 D 2 D 1 D 0 P A C K
Master S SDA Slave SDA
D7-D0
12
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
Table 2. Volatile and Nonvolatile Write Selection
NONVOLATILE VOLATILE (NV) (V) 0 0 1 1 0 1 0 1 FUNCTION Transfer data from NVREG_ to VREG_ Write to VREG_ Write to NVREG_ Write to NVREG and VREG_
Table 3. DAC Write Selection
R3 0 0 1 R2 0 0 1 R1 0 0 1 R0 0 1 1 FUNCTION DAC0 DAC1 All DACs*
*This option is only valid for a write to all volatile registers.
Table 4. Write-Command Summary
S T A R T S ADDRESS BYTE DATA BYTE A C K C 7 0 C 6 0 COMMAND BYTE A C K C 0 R 0 1 MSB D 7 D 6 D 5 D 4 D 3 D 2 D 1 LSB D 0 P A C K STOP
COMMAND
R/W 0
C 5 0
C 4 1
C 3 R 3 1
C 2 R 2 1
C 1 R 1 1
Write VREG_ Write All VREG_*
D7-D0
S
0
0
0
0
1
D7-D0
P
Write NVREG_
S
0
0
0
1
0
R 3
R 2
R 1
R 0
D7-D0
P
Write VREG_ and NVREG_ Transfer NVREG_ to VREG_
S
0
0
0
1
1
R 3 R 3
R 2 R 2
R 1 R 1
R 0 R 0
D7-D0
P
S
0
0
0
0
0
--
P
*This option is only valid for a write to all volatile registers.
Mute/Power-Down Mode
The MAX5109 features software-controlled mute and power-down modes for each DAC. The power-down mode places the DAC output in a high-impedance state and reduces quiescent-current consumption (25A (max) with all DACs powered-down). Mute drives the selected DAC output to the corresponding REFL_ voltage. The volatile DAC registers retain data and the output returns to its previous state when mute is
disabled. The MAX5109 also features an asynchronous MUTE input that mutes all DACs simultaneously. The volatile and nonvolatile registers remain active while the MAX5109 is in mute and/or power-down modes. Writing to or reading from the volatile or nonvolatile registers does not remove the MAX5109 from mute or power-down mode. Writing or transferring data to the volatile registers while the device is muted or powered down updates the DAC outputs to the new state upon exiting mute or power-down mode.
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13
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
Table 5. Volatile and Nonvolatile Read Selection
NONVOLATILE (NV) 0 1 VOLATILE (V) 1 0 FUNCTION Read from VREG_ Read from NVREG_
Table 6. DAC Read Selection
R3 0 0 R2 0 0 R1 0 0 R0 0 1 FUNCTION DAC0 DAC1
Table 7. Mute/Power-Down Operation
S T A R T S S ADDRESS BYTE R/ W 0 0 DATA BYTE A C K A A LSB C C MSB K K CCCCCCCC DDDDDDDD 76543210 76543210 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 Control register* Control register* COMMAND BYTE STOP
COMMAND
Write VCTL Write NVCTL
P P
Write VCTL and NVCTL Transfer NVCTL to VCTL
S
0
0
0
1
1
0
1
0
0
Control register*
P
S
0
0
0
0
0
0
1
0
0
Control register*
P
*See Mute/Power-Down Control Register (Table 8).
Table 8. Mute/Power-Down Control Register
BIT IN REGISTER D7 (MSB) CONTROLLING FUNCTION X D6 X D5 Mute DAC1 D4 Mute DAC0 D3 X D2 X D1 D0 (LSB)
Power-down Power-down DAC1 DAC0
X = Don't care.
Mute/Power-Down Register and Operation
Separate nonvolatile and volatile control registers store and update the state of the mute/power-down mode for each DAC. Tables 7 and 8 show how to access and control each register. Register access is gained by setting control bits C3-C0 to 0100. Bits C5 and C4 indicate whether the nonvolatile or volatile control register is accessed. The volatile register maintains data while the device remains powered. The nonvolatile register maintains data even after power is removed. The MAX5109 starts up (power first applied) by transferring the mute/power-down modes from the nonvolatile con14
trol register to the volatile control register. The nonvolatile control register is set to 00 hex at the factory.
Power-On Reset
Power-on reset (POR) circuitry controls the initialization of the MAX5109. A POR loads the volatile registers with the data stored in the nonvolatile registers. This initialization period takes 500s (typ). During this time, the DAC outputs are held in mute mode. At the completion of the initialization period, the DAC outputs update in accordance with the data stored in the nonvolatile registers.
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface
DAC Data
The 8-bit DAC data is decoded as offset binary, MSB first, with 1 LSB = (VREFH_- VREFL_) / 256, and converted into the corresponding analog voltage as shown in Table 9.
MAX5109
Table 9. Unipolar Code Output Voltage
DAC CODE 1111 1111 OUTPUT VOLTAGE (V)
Applications Information
DAC Linearity and Offset Voltage
The output buffer can have a negative input offset voltage that would normally drive the output negative, but with no negative supply, the output remains at GND (Figure 9). Determine linearity using the end-point method, measuring between code 10 (0A hex) and code 240 (F0 hex) after calibrating the offset and gain error (Figure 9).
255 x (VREFH _ - VREFL _ ) + VREFL _ 256 128 x (VREFH _ - VREFL _ 256 + VREFL _
1000 0000
0000 0001 0000 0000
(VREFH _ - VREFL _ ) + VREFL _ 256
VREFL_
External Voltage Reference
The MAX5109 features two reference inputs for each DAC (REFH_ and REFL_). REFH_ sets the full-scale voltage, while REFL_ sets the zero code output. A 460k typical input impedance is independent of the code.
Power Sequencing
The voltage applied to REFH_ and REFL_ should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REFH_, REFL_, and VDD to ensure compliance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered.
OUTPUT VOLTAGE
Power-Supply Bypassing and Ground Management
Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD, REFH_, and REFL_ to GND with a 0.1F capacitor, located as close to the device as possible. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs.
O NEGATIVE OFFSET
DAC CODE
Figure 9. Effect of Negative Offset (Single Supply)
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface MAX5109
Typical Operating Circuit
VDD C SDA VDD A3 1 SCL RP RP A2 2 A1 3 A0 4 R S* SCL R S* SDA REFH0 REFH1 REFL0 REFL1 MAX5109 OUT0 OUT1 A3 A2 A1 A0 MUTE ADDRESS 0101 110 R S* SCL R S* SDA REFH0 REFH1 REFL0 REFL1 MAX5109 OUT0 OUT1 A3 A2 A1 A0 MUTE ADDRESS 0101 111 VDD VDD REFH1 5 REFL1 6 OUT1 7 GND 8 16 SDA 15 VDD 14 SCL
Pin Configuration
TOP VIEW
MAX5109
13 REFH0 12 REFL0 11 OUT0 10 N.C. 9 MUTE
QSOP
Chip Information
TRANSISTOR COUNT: 40,209 PROCESS: BiCMOS
REFH REFL *OPTIONAL
16
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Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
MAX5109 MAX5109
21-0055
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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