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| FEDD514800DSL-01 This version : Dec. 2000 1 Semiconductor MSM514800D/DSL 524,288-Word x 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514800D/DSL is a 524,288-word x 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514800D/DSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM514800D/DSL is available in a 28-pin plastic SOJ. The MSM514800DSL (the self-refresh and lower-power version) is specially designed for lower-power applications. FEATURES * * * * * * * * * 524,288-word x 8-bit configuration Single 5V power supply, 10% tolerance Input Output Refresh : TTL compatible, low input capacitance : TTL compatible, 3-state : 1,024 cycles/16 ms, 1,024 cycles/128 ms (SL Version) Fast page mode, read modify write capability CAS before RAS refresh, hidden refresh, RAS-only refresh capability CAS before RAS self-refresh capability (SL version) Package options: 28-pin 400mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM514800D/DSL-xxJS) xx : indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC 60ns 70ns tAA 30ns 35ns tCAC 20ns 20ns tOEA 20ns 20ns Cycle Time (Min.) 110ns 130ns Power Dissipation Operating (Max.) 660mW 605mW Standby (Max.) 5.5mW/ 1.1mW (SL Version) MSM514800D/DSL 1/14 FEDD514800DSL-01 1Semiconductor This Version: Dec.2000 MSM514800D/DSL PIN CONFIGRATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 NC 6 WE 7 RAS 8 A9R 9 A0 10 A1 11 A2 12 A3 13 VCC 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ8 DQ7 DQ6 DQ5 CAS OE NC A8 A7 A6 A5 A4 VSS 28-Pin Plastic SOJ Pin Name A0 - A8, A9R RAS CAS DQ1 - DQ8 OE WE VCC VSS NC Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5V) Ground (0V) No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/14 FEDD514800DSL-01 1Semiconductor BLOCK DIAGRAM RAS CAS Timing Generator This Version: Dec.2000 MSM514800D/DSL Timing Generator Write Clock Generator 8 Refresh Control Clock Sense Amplifiers 8 I/O Selector 8 8 Input Buffers 8 WE OE Output Buffers 8 8 9 Column Address Buffers Internal Address Counter 9 Column Decoders A0 - A8 DQ1 - DQ8 9 A9R 1 Row Address Buffers 10 Row Decoders Word Drivers Memory Cells VCC On Chip VBB Generator VSS 3/14 FEDD514800DSL-01 1Semiconductor This Version: Dec.2000 MSM514800D/DSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg *: Ta = 25C Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C Recommended Operating Conditions (Ta = 0C to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. 4.5 0 2.4 -1.0 *2 Typ. 5.0 0 Max. 5.5 0 6.5 *1 0.8 Unit V V V V VCC VSS VIH VIL Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VSS is applied). Capacitance (VCC = 5V 10%, Ta = 25C, f=1MHz) Parameter Input Capacitance (A0 - A8, A9R) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ8) Symbol Typ. Max. 7 7 8 Unit pF pF pF CIN1 CIN2 CI/O 4/14 FEDD514800DSL-01 1Semiconductor DC Characteristics This Version: Dec.2000 MSM514800D/DSL (VCC = 5V 10%, Ta = 0C to 70C) MSM514800 D/DSL-60 Min. Output High Voltage Output Low Voltage Input Leakage Current VOH VOL ILI IOH = -5.0mA IOL = 4.2mA 0V VI 6.5V ; All other pins not under test = 0V DQ disable 0V VO 5.5V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS VCC - 0.2V RAS cycling, CAS = VIH, tRC = Min. RAS = VIH, CAS = VIL, DQ = enable RAS = cycling, CAS before RAS RAS = VIL, CAS cycling, tPC = Min. 2.4 0 -10 Max. VCC 0.4 10 MSM514800 D/DSL-70 Min. 2.4 0 -10 Max. VCC 0.4 10 V V A Parameter Symbol Condition Unit Note Output Leakage Current Average Power Supply Current (Operating) ILO -10 10 -10 10 A ICC1 120 2 1 200 110 2 mA 1,2 mA 1 200 A mA 1 1,5 Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) ICC3 120 110 1,2 ICC5 5 5 mA 1 ICC6 120 110 mA 1,2 ICC7 110 100 mA 1,3 Average Power Supply Current (Battery Backup) Average Power Supply Current (CAS before RAS Self-Refresh) tRC = 125s, ICC10 CAS before RAS, tRAS 1s ICCS RAS 0.2V, CAS 0.2V 300 300 A 1,4,5 300 300 A 1,5 Notes: 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC - 0.2V VIH 6.5V, - 1.0V VIL 0.2V. SL version. 5/14 FEDD514800DSL-01 1Semiconductor AC Characteristic (1/2) This Version: Dec.2000 MSM514800D/DSL (VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3 MSM514800 D/DSL-60 Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH 110 155 40 85 0 0 0 3 40 60 60 15 15 10 20 60 10 35 20 15 0 10 Max. 60 20 30 35 20 15 15 50 16 128 10,000 100,000 10,000 40 30 MSM514800 D/DSL-70 Min. 130 185 45 100 0 0 0 3 50 70 70 20 20 10 20 70 10 40 20 15 0 10 Max. 70 20 35 40 20 20 20 50 16 128 10,000 100,000 10,000 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 11 4,5,6 4,5 4,6 4 4 4 7 7 3 Parameter Symbol Unit Note 6/14 FEDD514800DSL-01 1Semiconductor AC Characteristic (2/2) This Version: Dec.2000 MSM514800D/DSL (VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3 MSM514800 D/DSL-60 Min. Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) tASC tCAH tAR tRAL tRCS tRCH tRRH tWCS tWCH tWCR tWP tOEH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tRASS tRPS tCHS 0 10 50 30 0 0 0 0 15 50 15 15 15 15 0 15 50 15 40 60 90 65 10 10 15 100 110 Max. MSM514800 D/DSL-70 Min. 0 15 55 35 0 0 0 0 15 55 15 20 20 20 0 15 55 20 50 65 100 70 10 10 15 100 130 Max. ns ns ns ns ns ns ns ns s ns ns 11 11 11 9 9 9 9 ns ns ns ns ns ns 10 10 ns ns ns ns ns ns ns ns ns 8 8 9 Parameter Symbol Unit Note -40 -50 7/14 FEDD514800DSL-01 1Semiconductor Notes: 1. This Version: Dec.2000 MSM514800D/DSL A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. The AC characteristics assume tT = 5ns. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. tRCH or tRRH must be satisfied for a read cycle. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 2. 3. 4. 5. 6. 7. 8. 9. 10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. SL version only. 8/14 FEDD514800DSL-01 1Semiconductor Timing Chart * Read Cycle MSM514800D/DSL tRC tRAS tRP tCRP tCSH tRCD tRAD tRAL tASR tRAH tASC Column RAS VIH VIL CAS VIH VIL tRSH tCAS tCRP tCAH Address VIH VIL VIH VIL VIH VIL Row tRCS tAA tROH tOEA tCAC tRAC tRRH tRCH WE OE tOEZ tCLZ Valid Data-out tOFF DQ VOH VOL Open "H" or "L" * Write Cycle (Early Write) RAS VIH VIL tCRP tRCD tRAD tRC tRAS tRP tCSH tRSH tCAS tRAL tCRP CAS VIH VIL tASR tRAH tASC tCAH Column Address VIH VIL Row tCWL tWCS tWP tWCH WE VIH VIL VIH VIL VIH VIL tRWL OE tDS Valid Data-in tDH Open DQ "H" or "L" 9/14 FEDD514800DSL-01 1Semiconductor * Read Modify Write Cycle MSM514800D/DSL tRWC RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAH tASC Column tRAS tRP tCSH tRCD tRSH tCAS tCWL tRWL tCRP tCAH Row tRCS tRWD tCWD tWP WE VIH VIL VIH VIL tRAC tCLZ tCAC tOEZ Valid Data-out tAWD tAA tOEA tOED tDS Valid Data-in tOEH OE tD DQ VI/OH VI/OL "H" or "L" 10/14 FEDD514800DSL-01 1Semiconductor * Fast Page Mode Read Cycle MSM514800D/DSL tRASP RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC tCAC DQ VOH VOL tCLZ tCPA tOFF tOEZ Valid Data-out tRP tPC tRHCP tCP tCAS tRSH tCAS tRAL tASC Column tRCD tCAS tRAD tCSH tRAH tASC tCP tCRP tCAH tASC tCAH tCAH Row Column Column tRCS WE tAA tRCH tAA tOEA tRCS tRCH tAA tRCS tRCH tOEA tCPA tOFF tOEZ Valid Data-out tOEA tRRH OE tCAC tCLZ tCAC tCLZ tOEZ Valid Data-out tOFF "H" or "L" * Fast Page Mode Write Cycle (Early Write) tRASP RAS VIH VIL VIH VIL tASR Address VIH VIL Row tRP tPC tRHPC tCP tCAS tRSH tCAS tRAL tCAH Column tCRP tRCD tCAS tRAD tRAH tASC tCSH tCAH tCP tCRP CAS tASC tCAH tASC Column Column tWCS WE VIH VIL tDS DQ VIH VIL tWCH tWP tCWL tWCS tCWL tWCH tWP tD Valid Data-in tRWL tCWL tWCS tWP tWCH tD Valid Data-in tDS tDS Valid Data-in tD Note: OE = "H" or "L" "H" or "L" 11/14 FEDD514800DSL-01 1Semiconductor * Fast Page Mode Read Modify Write Cycle MSM514800D/DSL tRASP RAS VIH VIL VIH VIL tRAH tASR Address VIH VIL Row tCSH tRCD tRAD tASC Column tPRWC tCAS tCP tCAS tCAH tCAH tCWL tASC tCWL Column Column tRSH tCP tCAS tCAH tASC tCRP tRP CAS tRAL tRCS WE VIH VIL tRAC tAA tPWD tCWD tAWD tWP tDH tDS tOEA tRCS tCPWD tCWD tAWD tCPA tAA tOEA tOED tOEZ Out tCLZ In tCLZ tWP tDS tD tAA tRCS tCPWD tCWD tAWD tROH tCPA tOEA tOED tOEZ Out In tCWL tRWL tWP tD tDS OE VIH VIL tCAC VI/OH VI/OL tCLZ tOED tOEZ Out In tCAC tCAC DQ Note: Out = Valid Data-out, In = Valid Data-in "H" or "L" * RAS-only Refresh Cycle tRC RAS VIH VIL tCRP CAS VIH VIL VIH VIL VOH VOL tASR tRAH tRPC tRAS tRP Address Row tOFF Open Note: WE, OE = "H" or "L" DQ "H" or "L" 12/14 FEDD514800DSL-01 1Semiconductor * CAS before RAS Refresh Cycle MSM514800D/DSL tRP RAS VIH VIL tRPC tCP tCSR tCHR tOFF DQ VOH VOL tRAS tRC tRP tRPC CAS VIH VIL Open Note: WE, OE, Address = "H" or "L" "H" or "L" * Hidden Refresh Read Cycle tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAL tAA tROH OE VIH VIL VOH VOL Open tRAS tCRP tRCD tRAD tRAH Row tRC tRAS tRSH tRP tCHR tRP CAS tASC Column tCAH tRCS WE tCAC tRRH tOFF tOEA tRAC tCLZ Valid Data-out "H" or "L" tOEZ DQ 13/14 FEDD514800DSL-01 1Semiconductor Hidden Refresh Write Cycle MSM514800D/DSL tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL VIH VIL VIH VIL tDS tD tWP tRAD tRAH Row tRC tRAS tRSH tRP tCHR tRAL tRP tRAS tCRP tRCD CAS tASC Column tCAH tWCS WE tWCH OE DQ Valid Data-in "H" or "L" CAS before RAS Self-Refresh Cycle tRP RAS VIH VIL VIH VIL tOFF DQ VOH VOL tRPC tCP CAS tCSR tRASS tRPS tRPC tCHS Open Note: WE, OE, Address = "H" or "L" O S "H" or "L" 14/14 |
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