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PGA202/203
Digitally Controlled Programmable-Gain INSTRUMENTATION AMPLIFIER
FEATURES
q DIGITALLY PROGRAMMABLE GAINS: DECADE MODEL--PGA202 GAINS OF 1, 10, 100, 1000 BINARY MODEL--PGA203 GAINS OF 1, 2, 4, 8 q LOW BIAS CURRENT: 50pA max q FAST SETTLING: 2s to 0.01% q LOW NON-LINEARITY: 0.012% max q HIGH CMRR: 80dB min q NEW TRANSCONDUCTANCE CIRCUITRY q LOW COST
APPLICATIONS
q DATA ACQUISITION SYSTEMS q q q q AUTO-RANGING CIRCUITS DYNAMIC RANGE EXPANSION REMOTE INSTRUMENTATION TEST EQUIPMENT
DESCRIPTION
The PGA202 is a monolithic instrumentation amplifier with digitally controlled gains of 1, 10, 100, and 1000. The PGA203 provides gains of 1, 2, 4, and 8. Both have TTL or CMOS-compatible inputs for easy microprocessor interface. Both have FET inputs and a new transconductance circuitry that keeps the bandwidth nearly constant with gain. Gain and offsets are laser trimmed to allow use without any external components. Both amplifiers are available in ceramic or plastic packages. The ceramic package is specified over the full industrial temperature range while the plastic package covers the commercial range.
VOS Adjust 6 9 10 Filter B 5.3pF* 30k * Front End and Logic Circuits I
1
+VIN 8
11 Sense 12 VOUT 4 VREF
- +
+VIN 7
I
2
30k * 5.3pF* *20%
5 Filter A
1
2 14
A0 A1 Digital Common
Covered by U.S. PATENT #4,883,422 International Airport Industrial Park * Mailing Address: PO Box 11400 Tel: (520) 746-1111 * Twx: 910-952-1111 * Cable: BBRCORP * * Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
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(c)1989 Burr-Brown Corporation
PDS-1006C 1
PGA202/203
Printed in U.S.A. August, 1993
SPECIFICATIONS
ELECTRICAL
At +25C, VCC = 15V unless otherwise noted. PGA202/203AG (1) PARAMETER GAIN Error (2) Nonlinearity Gain vs Temperature CONDITION G < 1000 G = 1000 G < 1000 G = 1000 G < 100 G = 100 G = 1000 |IOUT | 5mA See Typical Perf. Curve |VOUT | 10V 10 5 MIN TYP 0.05 0.1 0.002 0.02 3 40 100 12 9 10 0.5 13 10 || 3 10 || 1 (0.5 + 5/G) (3 + 50/G) 50 10 + 250/G 10 640 5 320 G=1 G = 10 G = 100 G = 1000 INPUT NOISE Noise Voltage 0.1 to 10Hz Noise Density at 10kHz (5) OUTPUT NOISE Noise Voltage 0.1 to 10Hz Density at 1kHz (5) DYNAMIC RESPONSE Frequency Response Full Power Bandwidth Slew Rate Settling Time (0.01%) (7) Overload Recovery Time (7) DIGITAL INPUTS Digital Common Range Input Low Threshold (6) Input Low Current Input High Voltage Input High Current POWER SUPPLY Rated Voltage Voltage Range Quiescent Current TEMPERATURE RANGE Specification Operating Storage JA * Same as the PGA202/203AG NOTES: (1) All specifications apply to both the PGA202 and the PGA203. Values given for a gain of 10 are the same for a gain of 8 and other values may be interpolated. (2) Measured with a 10k load. (3) The analog inputs are internally diode clamped. (4) Adjustable to zero. (5) VNOISE (RTI) = (VN INPUT)2 + (VN OUTPUT/Gain)2. (6) Threshold voltages are referenced to Digital Common. (7) From input change or gain change. G G G G G G G G < = < = < = < = 1000 1000 1000 1000 10 1000 1000 1000 1000 -VCC 2.4 10 15 6.5 -25 -55 -65 100 85 125 150 * * * * * * * * * * 0 -25 -40 * * * * 70 85 100 80 86 92 94 100 110 120 120 1.7 12 32 400 1000 250 400 100 20 2 10 5 10 VCC - 8 0.8 10 (2 + 24/G) (24 + 240/G) 100 + 900/G 50 3200 25 1600 * * * * MAX 0.25 1 0.015 0.06 25 120 300 * * PGA202/203BG (1) MIN TYP * 0.08 * * * * * * * * * * * * * * * * * (1 + 12/G) (12 + 120/G) 50 + 450/G * * * * * * * * * * * * * * * MAX 0.15 0.5 0.012 0.04 15 60 150 * * PGA202/203KP (1) MIN TYP * * * * * * * * 10 * * * * MAX * * * * UNITS % % % % ppm/C ppm/C ppm/C V V mA V V G || pF G || pF mV V/C * V/Month V/V
RATED OUTPUT Voltage Over Specified Temperature Current Impedance ANALOG INPUTS Common-Mode Range Absolute Max Voltage (3) Impedance, Differential Common-Mode OFFSET VOLTAGE (RTI) Initial Offset at 25C (4) vs Temperature Offset vs Time Offset vs Supply INPUT BIAS CURRENT Initial Bias Current: at 25C at 85C Initial Offset Current: at 25C at 85C
10 No Damage
VCC
*
*
10 VCC 15
* * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * *
* * * *
pA pA pA pA dB dB dB dB Vp-p nV/Hz Vp-p nV/Hz kHz kHz kHz kHz V/s s s s s
COMMON-MODE REJECTION RATIO
15
*
* *
* * * *
* *
* * * * * *
V V A V A V V mA C C C C/W
6
18
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PGA202/203
2
PIN CONFIGURATION
Top View
A0 A1 +VCC VREF Filter A VOS Adjust -V IN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Digital Common -VCC V OUT V OUT Sense Filter B VOS Adjust +V IN
ABSOLUTE MAXIMUM RATINGS
DIP Supply Voltage ................................................................................... 18V Internal Power Dissipation ............................................................. 750mW Analog and Digital Inputs ..................................................... (VCC + 0.5V) Operating Temperature Range: G Package ............................................................... -55C to +125C P Package ............................................................... -40C to +100C Lead Temperature (soldering, 10s) .................................................. 300C Output Short Circuit Duration ................................................... Continuous Junction Temperature ...................................................................... 175C
PACKAGE INFORMATION
MODEL PGA202KP PGA202AG PGA202BG PGA203KP PGA203AG PGA203BG PACKAGE 14-Pin Plastic DIP 14-Pin Ceramic DIP 14-Pin Ceramic DIP 14-Pin Plastic DIP 14-Pin Ceramic DIP 14-Pin Ceramic DIP PACKAGE DRAWING NUMBER(1) 010 169 169 010 169 169
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.
ORDERING INFORMATION
TEMPERATURE MODEL PGA202KP PGA202AG PGA202BG PGA203KP PGA203AG PGA203BG GAINS 1, 10, 100, 1000 1, 10, 100, 1000 1, 10, 100, 1000 1, 2, 4, 8 1, 2, 4, 8 1, 2, 4, 8 PACKAGE Plastic DIP Ceramic DIP Ceramic DIP Plastic DIP Ceramic DIP Ceramic DIP RANGE 0C to +70C -25C to +85C -25C to +85C 0C to +70C -25C to +85C -25C to +85C OFFSET VOLTAGE MAX (mV) (2 + 24/G) (2 + 24/G) (1 + 12/G) (2 + 24/G) (2 + 24/G) (1 + 12/G)
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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3
PGA202/203
TYPICAL PERFORMANCE CURVES
TA = +25C, VS = 15V unless otherwise noted.
GAIN vs FREQUENCY 80 60 1 40 Gain (dB) 20 0 -20 -40 1 10 10
2
GAIN ERROR vs FREQUENCY 10
G = 1000
Gain Error (%)
10-1 G=1 10-2
10-3 10
3
10
4
10
5
10
6
10
7
1
10
102
103
104
105
Frequency (Hz)
Frequency (Hz)
CMRR vs FREQUENCY 160 G = 100, 1000 120 120 160
PSRR vs FREQUENCY
G = 100
G = 1000
CMRR (dB)
G = 10 40 G=1
PSRR (dB)
80
80 G = 10 40 G=1
0
0
-40 1 10 102 103 Frequency (Hz) 104 105 106
-40 1 10 102 103 Frequency (Hz) 104 105 106
INPUT NOISE vs FREQUENCY 104 104
OUTPUT NOISE vs FREQUENCY
103
Noise (nV/Hz)
103
Noise (nV/Hz)
102 103 104 105
102
102
10
10
1 1 10 Frequency (Hz)
1 1 10 102 103 104 105 Frequency (Hz)
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PGA202/203
4
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25C, VS = 15V unless otherwise noted.
QUIESCENT CURRENT vs POWER SUPPLY 10
INPUT BIAS CURRENT vs POWER SUPPLY 12 11 Input Bias Current (pA) 10 9 8 7 0
8
IQ (mA)
6
4
2
0 6 9 12 Power Supply (V) 15 18
6
9
12 Power Supply (V)
15
18
INPUT RANGE vs POWER SUPPLY 16 15
OUTPUT SWING vs POWER SUPPLY TA = +25C
12 10 8
VOUT (V)
V IN (V)
TA = -25C 5
4
0 6 9 12 Power Supply (V) 15 18
0 6 9 12 Power Supply (V) 15 18
OUTPUT SWING vs LOAD 15
SETTLING TIME vs FILTER CAPACITOR 10
8
Settling Time (s)
0 500 1000 Load ( ) 1500 2000 10
VOUT (V)
6
4
5
2
0
-4 0 10 20 30 Filter Capacitor (pF)
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5
PGA202/203
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25C, VS = 15V unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE 10 103
INPUT BIAS CURRENT vs TEMPERATURE
Input Bias Current (pA)
8
102
IQ (mA)
6
4
10
2
0 -50 -25 0 25 50 75 100 Temperature (C)
1 -50 -25 0 25 50 75 100 Temperature (C)
CURRENT LIMIT vs TEMPERATURE 25
SLEW RATE vs TEMPERATURE 25
Slew Rate (V/s)
20
20
ILIM (mA)
15
15
10 -50 -25 0 25 50 75 100 Temperature (C)
10 -50
-25
0
25
50
75
100
Temperature (C)
OUTPUT SWING vs TEMPERATURE 14
LARGE SIGNAL RESPONSE
12
V OUT (V)
10
5V/Div
G = 10
8
6 -50 -25 0 25 50 75 100 1s/Div Temperature (C)
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PGA202/203
6
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25C, VCC = 15V unless otherwise noted.
DIN
1 2 8+ VIN 7 - 13 3 14 11 PGA202 4 12 VOUT
SMALL SIGNAL RESPONSE
5mV/Div
G = 10
+VCC -VCC
RL
1s/Div
FIGURE 1. Basic Circuit Connections.
DISCUSSION OF PERFORMANCE
A simplified diagram of the PGA202/203 is shown on the first page. The design consists of a digitally controlled, differential transconductance front end stage using precision FET buffers and the classical transimpedance output stage. Gain switching is accomplished with a novel current steering technique that allows for fast settling when changing gains. The result is a high performance, programmable instrumentation amplifier with excellent speed and gain accuracy. The input stage uses a new circuit topology that includes FET buffers to give extremely low input bias currents. The differential input voltage is converted into a differential output current with the transconductance gain selected by steering the input stage bias current between four identical input stages differing only in the value of the gain setting resistor. Each input stage is individually laser-trimmed for input offset, offset drift, and gain. The output stage is a differential transimpedance amplifier. Unlike the classical difference amplifier output stage, the common-mode rejection is not limited by the resistor matching. However, the output resistors are laser-trimmed to help minimize the output offset and drift. BASIC CONNECTIONS Figure 1 shows the proper connections for power supply and signal. The power supplies should be decoupled with 1F tantalum capacitors placed as close to the amplifier as possible for maximum performance. To avoid gain and CMR errors introduced by the external components, you should connect the grounds as indicated. Any resistance in the sense line (pin 11) or the VREF line (pin 4) will lead to a gain error, so these lines should be kept as short as possible. To also maintain stability, avoid capacitance from the output to the input or the offset adjust pins.
OFFSET ADJUSTMENT Figure 2 shows the offset adjustment circuits for the PGA202/ 203. The input offset and the output offset are both separately adjustable. Notice that because the PGA202/203 change between four different input stages to change gain, the input offset voltage will change slightly with gain. For systems using computer autozeroing techniques, neither offset nor drift is a major concern, but it should be noted that since the input offset does change with gain, these systems should perform an autozero cycle after each gain change for optimum performance. In the output offset adjustment circuit, the choice of the buffering op amp is very important. The op amp needs to have low output impedance and a wide bandwidth to maintain full accuracy over the entire frequency range of the PGA202/203. For these reasons we recommend the OPA602 as an excellent choice for this application.
+VCC
50k 6 8 VIN 7 + 9 11 12 VOUT 10k 100k + 100 - OPA602 -VCC +VCC
PGA202 - 4
FIGURE 2. Offset Adjustment Circuits.
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PGA202/203
GAIN SELECTION Gain selection is accomplished by the application of a 2-bit digital word to the gain select inputs. Table I shows the gains for the different possible values of the digital input word. The logic inputs are referred to their own separate digital common pin, which can be connected to any voltage between the minus supply and 8V below the positive supply. The gains are all internally trimmed to an initial accuracy of better than 0.1%, so no external gain adjustment is required. However, if necessary the gains can be increased by the use of an external attenuator around the output stage as shown in Figure 3. Recommended resistor values for certain selected output gains are given in Table II.
PGA202 A1 0 0 1 1 A0 0 1 0 1 GAIN 1 10 100 1000 ERROR 0.05% 0.05% 0.05% 0.10% GAIN 1 2 4 8 PGA203 ERROR 0.05% 0.05% 0.05% 0.05%
OUTPUT SENSE An output sense has been provided to allow greater accuracy in connecting the load. By attaching this feedback point to the load at the load site, IR drops due to the load currents are eliminated since they are inside the feedback loop. Proper connection is shown in Figure 1. When more current is required, a power booster can be placed in the feedback loop as shown in Figure 4. Buffer errors are minimized by the loop gain of the output amplifier.
8+ VIN 7
14 11 12 4 2 1 RL
OPA633
PGA202 -
VOUT
TABLE I. Software Gain Selection.
OUTPUT GAIN 2 5 10 R1 5k 2k 1k R2 5k 8k 9k
A0
A1
FIGURE 4. Current Boosting the Output. OUTPUT FILTERING The summing nodes of the output amplifier have also been made available to allow for output filtering. By placing matched capacitors in parallel with the existing internal capacitors as shown in Figure 5, you can lower the frequency response of the output amplifier. This will reduce the noise of the amplifier, at the cost of a slower response. The nominal frequency responses for some selected values of capacitor are shown in Table III.
TABLE II. Output Stage Gain Control.
8+ VIN 7 PGA202 - 4
11 12
VOUT R1
+
OPA602
- R2
CEXT
10 8 + 11 PGA202 7 - 5 4 12 VOUT
FIGURE 3. Gain Increase with Buffered Attenuator. COMMON-MODE INPUT RANGE Unlike the classical three op amp type of circuit, the input common-mode range of the PGA202/203 does not depend on the differential input and the gain. In the standard three op amp circuit, the input common-mode signal must be kept below the maximum output voltage of the input amplifier minus 1/2 the final output voltage. If, for example, these amplifiers can swing 12V, then to get 12V at the output you must restrict the input common-mode voltage to only 6V. The circuitry of the PGA202/203 is such that the commonmode input range applies to either input pin regardless of the output voltage.
VIN
CEXT
FIGURE 5. Output Filtering.
CUTOFF FREQUENCY 1MHz 100kHz 10kHz C1 AND C2 None 47pF 525pF
TABLE III. Output Frequency vs Filter Capacitors.
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PGA202/203
8
INPUT CHARACTERISTICS Because the PGA202/203 have FET inputs, the bias currents drawn through input source resistors have a negligible effect on DC accuracy. The picoamp currents produce no more than microvolts through megohm sources. The inputs are also internally diode clamped to the supplies. Thus, input filtering and input series protection are easily achievable. A return path for the input bias currents must always be provided to prevent the charging of any stray capacitance. Otherwise, the amplifier could wander and saturate. A 1M to 10M resistor from the input to common will return floating sources such as thermocouples and AC-coupled inputs (see Applications Section, Figures 8 and 9.) DYNAMIC PERFORMANCE The PGA202 and the PGA203 are fast-settling FET input programmable gain instrumentation amplifiers. Careful attention to minimize stray capacitance is necessary to achieve specified performance. High source resistance will interact with the input capacitance to reduce speed and overall bandwidth. Also, to maintain stability, avoid capacitance from the output to the input or the offset adjust pins. Applications with balanced source impedance will provide the best performance. In some applications, mismatched source impedances may be required. If the impedance in the negative input exceeds that in the positive input, stray capacitance from the output will create a net negative feedback and improve the stability of the circuit. If, however, the impedance in the positive input is greater, then the feedback due to stray capacitance will be positive and instability may result. The degree of positive feedback will, of course, depend on the source impedance imbalance as well as the board layout and the operating gain. The addition of a small bypass capacitor of about 5 to 50pF directly across the input terminals of the PGIA will generally eliminate any instability arising from these stray capacitances. CMR errors due to the source imbalance will also be reduced by the addition of this capacitor. The PGA202 and the PGA203 are designed for fast settling in response to changes in either the input voltage or the gain. The bandwidth and the settling times are mostly determined by the output stage and are therefore independent of gain, except at the highest gain of the PGA202 where other factors in the input stage begin to dominate.
8
14 + PGA203 11 12 ISO 4 2 1 102 VOUT
7
-
+5
RL Digital OptoCoupler DIN
FIGURE 6. Isolated Programmable Gain Instrumentation Amplifier.
8 VIN 7
14 + PGA202 - 2 1 4 11 12 VOUT
Down
+ - V REF 10V R1 10k
2-Bit Up/Down Counter OSC Up
Dual Comparator - +
R2 1k
FIGURE 7. Auto Gain Ranging.
1F
APPLICATIONS
In addition to general purpose applications, the PGA202/203 are designed to handle two important and demanding classes of applications: inputs with high source impedances, and rapid scanning data acquisition systems requiring fast settling time. Because the user has access to output sense and output common pins, current sources can also be constructed with a minimum of external components. Some basic application circuits are shown in Figures 6 through 12.
8+ VIN 1F 7
14 11 12 4 2 1 VOUT
PGA202 -
1M
1M
Gain Control
FIGURE 8. AC-Coupled Differential Amplifier for Frequencies Above 0.16Hz.
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9
PGA202/203
8
14 11 12 4 2 1 1M VOUT
+ PGA202
11 12 4 2 1 A0 VOUT A1 1
VIN 7
8+ 7
-
PGA203 -
8
Gain Control
+
2 11 12 4
VOUT = 2G VIN
PGA202 7 -
FIGURE 9. Floating Source Programmable Gain Instrumentation Amplifier.
FIGURE 11. Programmable Differential In/Differential Out Amplifier.
+
OPA27
-
+VCC
10k VIN 200 10k
8+ 7
14 11 12 4 2 1 VOUT
8+ 7
14 11 12 4 2 1 R IOUT 10k R
PGA203 -
PGA203 -
-
OPA27
+ Gain Control
Gain Control
RL
FIGURE 10. Low Noise Differential Amplifier with Gains of 100, 200, 400, 800. FIGURE 12. Programmable Current Source.
A3
8+ VIN 7 14 11 12 4 2 1 7 8 + PGA203 - 1 4 2 14 11 12 VOUT
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
GAIN 1 2 4 8 10 20 40 80 100 200 400 800 1000 2000 4000 8000
PGA202 -
A2 A3 A0 A1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FIGURE 13. Cascaded Amplifiers.
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PGA202/203
10

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