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Features
* All-in-one Design
- MIDI Control Processor - Synthesis - Compatible Effects: Reverb and Chorus - Microphone Echo Processing (Two Channels) - Programmable Spatializer or Four-channel Surround - 4-band Stereo Equalizer High-quality Synthesis - Maximum 48-voice Polyphony and Reverb/Chorus (34 if all features on) - 24 dB Resonant Filter per Voice - 16-bit Samples - Alternate Loop - Internal Computations on 28 Bits Crisp MIDI Response: Built-in 16-bit Processor Runs at 38.4 MHz High-quality Sound Post-processing - 13 Delay Lines for Stereo Reverb - Programmable Stereo Echo for Microphone - Spatializer/Surround Allows Wide Stereo Image for Strong Sound Presence Top Technology - Synthesizer Chip Set: SAM9703 + 32-Mbit ROM + 32K x 8 RAM + DAC or Codec - Single 9.6 MHz Crystal with Built-in PLL - 100-lead TQFP Space Saver Package Standard Firmware includes Top-quality CleanWave(R) Sound Set and Other Sample Sets under Special Conditions Typical Applications: Karaokes, Musical instruments, Battery-operated Instruments Pin- and Function-compatible with SAM9503, with Additional Features: - Lower Consumption - 3.3V Core Supply, 3V to 5.5V Periphery Supply - Up to 8 Channels Audio-in Pin-to-pin replacement for SAM9503 requires 3.3V core supply VC3.
*
* *
Professional Integrated Synthesizer SAM9703
*
* * *
Note:
Description
The highly-integrated architecture of the SAM9703 device combines a specialized high-performance RISC digital signal processor and a general-purpose 16-bit CISC control processor on a single chip. An on-chip memory management unit allows the digital signal processor and the control processor to share external ROM and RAM devices. The ROM bus width should be 16 bits, while the SRAM can be selected to be 8 or 16 bits wide. When using an 8-bit SRAM, fast type (static cache) should be selected as two SRAM cycles will be done in one ROM cycle duration. Running at 300 million operations per second (MOPS), the digital signal processor supports high-quality PCM synthesis as well as most important functions like reverb, chorus, surround effect and equalizer. By adding an additional stereo DAC, fourchannel audio surround can be obtained as well. Computer karaoke manufacturers will enjoy the built-in high-quality dual-microphone echo processing. Dream (R) licenses a 32-Mbit jumper-configurable firmware ROM, CleanWave32 (R) , which includes high-quality General MIDI-compliant synthesis with many additional sounds and drumsets. Please refer to the corresponding CleanWave32(R) datasheet. Other sample sets are available under special conditions. More information, including licensing, can be obtained from any Atmel sales office. Smaller capacity firmwares are also available for more cost-sensitive or portable applications.
Rev. 1710A-10/00
1
The firmware can also be modified to fit customer specifications. A SAM9703-based development/prototyping board is available and includes the SAM9703, 32 Mbits of EPROM memory, 32K words of SRAM, a codec and one DAC, providing four channels of audio out and a stereo line input (ref. 9703DVB). The SAM9703 internal sound definition format is compatible with the SAM9407 sound studio IC. Therefore it is possible to develop specific sounds for the SAM9703 by using the development tools of the SAM9407. The SAM9703 operates from a "low" frequency 9.6 MHz typical crystal. A built-in PLL raises this frequency to a 38.4 Figure 1. Typical Hardware Configuration
MHz internal clock which controls the two processors. Care has been taken that output pin signals change only when necessary. This minimizes RFI (radio frequency interferences) and power consumption. Minimizing RFI is mostly important in order to comply with standards such as FCC, CSA and CE. The core power supply for the SAM9703 should be 3.3V 10%, while the periphery supports supply from 3V to 5.5V (5V 10% for TTL-compatible applications). Therefore, by selecting 3.3V ROM, SRAM and DAC, it is possible to develop low-power/low-voltage portable applications.
CleanWave ROM
RAM
MIDI IN
SAM9703
CODEC
Audio Out Microphone Microphone
2
SAM9703
SAM9703
Pin Description
Pins by Function
Table 1. Power Supply Group
Pin Name GND Pin Number 2, 6, 8, 16, 20, 22, 26, 28, 38, 46, 49, 53, 59, 71, 75, 82, 83, 94 1, 7, 15, 21, 27, 37, 48, 52, 58, 70, 74, 81, 95 9, 19, 24, 77 Type PWR Function Digital Ground All pins should be connected to a ground plane. Power Supply, 3V to 5.5V All pins should be connected to a VCC plane. Core Power Supply, 3.3V 10 %. All pins should be connected to +3.3V. If 3.3V is not available, then it can be derived from 5V by two 1N41418 diodes in series.
VCC
PWR
VC3
PWR
Table 2. Serial MIDI
Pin Name MIDI IN Pin Number 17 Type IN Function Serial TTL MIDI IN. All controls are received by this pin.
Table 3. External ROM/RAM Group
Pin Name WA0_WA24 Pin Number 47, 50, 51, 54 - 57, 60 - 69, 72, 73, 76, 78 - 80, 84, 85 86 - 93, 96 -100, 3 - 5 34 35 36 33 25 Type OUT Function External ROM/RAM address for up to 32M words (64 MB) of memory. ROM memory holds firmware and PCM data. RAM memory holds working variables and effect delay lines. External ROM/RAM data. Holds read data from ROM or RAM when WOE is low, write data to RAM when WWE is low. External ROM chip select, active low. External RAM chip select, active low. External ROM/RAM output enable, active low. External RAM write, active low RAM byte select. Used as lower address from RAM when 8-bit wide RAM is connected.
WD0_WD15 WCS0 WCS1 WOE WWE RBS
I/O OUT OUT OUT OUT OUT
Table 4. Digital Audio Group
Pin Name CLBD WSBD DABD0 DABD1 DAAD Pin Number 23 32 30 31 29 Type OUT OUT OUT OUT IN Function Digital audio bit clock Digital audio left/right select Digital audio main stereo output Auxiliary digital stereo output. Reserved for surround effects. Digital audio two channels input. Up to eight channels of audio can be input to the chip by using pins P1 to P3 alternate function.
3
Table 5. Miscellaneous Group
Pin Name X1-X2 LFT RESET PDWN Pin Number 12, 11 10 13 14 Type - - IN IN Function 9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (3.3V input). X2 cannot be used to drive external circuits. PLL external RC network. Reset input, active low. This is a Schmidt trigger input, allowing direct connection of an RC network. Power down, active low. When power down is active, then all output pins will be floated. The crystal oscillator will be stopped. To exit from power down, PDWN should be high and RESET applied. Test pins. Should be grounded. General-purpose I/O pins. As inputs, can be used to configure the software. P1 to P3 can also be used as three additional stereo serial inputs (six audio channels). When high, indicates that the synthesizer is up and running. May be used as a RESET input for an external DAC.
TEST0-TEST2 P0-P3
43, 44, 45 39, 40, 41, 42
IN I/O
RUN
18
OUT
4
SAM9703
SAM9703
Pinout
Figure 2. SAM9703 Pinout in 100-lead TQFP Package
VCC GND WD13 WD14 WD15 GND VCC GND VC3 LFT X2 X1 RESET PDWN VCC GMD MIDI IN RUN VC3 GND VCC GND CBD VC3 RBS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
WD12 WD11 WD10 WD9 WD8 VCC GND WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 WA25 WA23 GND GND VCC WA22 WA21 WA20 VC3 WA19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND VCC WA18 WA17 GND VCC WA16 WA15 WA14 WA13 WA12 WA11 WA10 WA9 WA8 WA7 GND VCC WA6 WA5 WA4 WA3 GND VCC WA2
GND VCC GND DAAD DABD0 DABD1 WSBD WWE WCS0 WCS1 WOE VCC GND P0 P1 P2 P3 TEST0 TEST1 TEST2 GND WA0 VCC GND WA1
5
Mechanical Dimensions
Figure 3. 100-lead Thin Plastic Quad Flat Pack
16.10(0.634) 15.90(0.626) PIN 1 ID 0.27(0.011) 0.17(0.007)
0.50(0.02)
14.10(0.555) 13.90(0.547)
1.45(0.057) 1.35(0.053)
0.75(0.030) 0.45(0.018)
0.15(0.006) 0.05(0.002)
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SAM9703
SAM9703
Absolute Maximum Ratings
Table 6. Absolute Maximum Ratings
Symbol Parameter/Condition Ambient Temperature (Power applied) Storage Temperature Voltage on any pin (except X1) Supply Voltage VC3 Note: Supply Voltage Maximum IOL per I/O pin All voltages with respect to 0V, GND = 0V) Min -40 -6.5 -0.5 -0.5 -0.5 Typ Max +85 +150 VCC + 0.5 6.5 4.5 10 Unit C C V V V mA
Recommended Operating Conditions
Table 7. Recommended Operating Conditions
Symbol VCC VC3 Note: Parameter/Condition Supply Voltage Supply Voltage
(1)
Min 3 3
Typ 3.3/5.0 3.3
Max 5.5 3.6
Unit V V C
TA Operating Ambient Temperature 0 70 1. When using 3.3V supply in a 5V environment, care must be taken that pin voltage does not exceed VCC + 0.5V.
DC Characteristics
Table 8. DC Characteristics (TA = 25C, VC3 = 3.3V 10%)
Symbol VIL VIH VOL VOH ICC Parameter/Condition Low Level Input Voltage High Level Input Voltage Low Level Output Voltage (IOL = -3.2 mA) High Level Output Voltage (IOH = 0.8 mA) Power Supply Current (Crystal Freq. = 9.6 MHz) Power Down Supply Current VCC 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 2.8 4.5 70 25 70 90 35 100 Min -0.5 -0.5 2.3 3.3 Typ Max 1.0 1.7 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V V mA mA A
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Timings
All timing conditions: TA = 25C, VCC = 5V, VC = 3.3V, all outputs exept X2 and LFT load capacitance = 30 pF, crystal frequency or external clock at X1 = 9.6 MHz.
External ROM Timing
Figure 4. ROM Read Cycle
tRC WCS0 tCSOE WA0WA24 tPOE WOE tOE WD0WD15 tACE tDF
Table 9. Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tDF Parameter Read Cycle Time Chip Select Low/Address Valid to WOE low Output Enable Pulse Width Chip Select/Address Access Time Output Enable Access Time Chip select or WOE High to Input Data High-Z 125 70 0 50 Min 130 45 78 80 Typ Max Unit ns ns ns ns ns ns
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SAM9703
SAM9703
External RAM Timing
Figure 5. 16-bit SRAM Read Cycle
tRC WCS1 tCSOE WA0WA24 tPOE WOE WWE tOE WD0WD15 tACE tDF
Figure 6. 16-bit SRAM Write Cycle
tWC WCS1 tCSWE WA0WA24 WOE WWE tDW WD0WD15 tDH
tWP
Table 10. Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE Parameter Read Cycle Time Chip Select Low/Address Valid to WOE Low Output Enable Pulse Width Chip Select/Address Access Time Output Enable Access Time 125 70 Min 130 45 78 80 Typ Max Unit ns ns ns ns ns
9
Table 10. Timing Parameters (Continued)
Symbol tDF tWC tCSWE tWP tDW tDH Parameter Chip Select or WOE High to Input Data High-Z Write Cycle Time Write enable Low from CS or Address or WOE Write Pulse Width Data Out Setup Time Data Out Hold Time 95 10 Min 0 130 40 104 Typ Max 50 Unit ns ns ns ns ns ns
Figure 7. 8-bit SRAM Read Cycle
tRC WCS1 tCSOE WA0WA24 tPOE WOE WWE tACE RBS tOE WD0WD7 LOW tACH tDF HIGH tORB
10
SAM9703
SAM9703
Figure 8. 8-bit SRAM Write Cycle
tWC WCS1 tCSWE WA0WA24 WOE tWP WWE RBS tDW1 WD0WD7 tDH1 tDW2 HIGH tDH2 tAS tWP
LOW
Table 11. Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tORB tACH tDF tWC tCSWE tWP tDW1 tDH1 tAS tDW tDH2 Parameter Word Read Cycle Time Chip Select Low/Address Valid to WOE Low Output Enable Pulse Width Chip Select/Address Low Byte Access Time Output Enable Low Byte Access Time Output Enable Low Byte Select High Byte Select High Byte access Time Chip select or WOE High to Input High-Z Word Write Cycle Time 1st WWE Low from CS or Address or WOE Write (Low and High Byte) Pulse Width Data Out Low Byte Setup Time Data Out Low Byte Hold Time RBS High to Second Write Pulse Data Out High Byte Setup Time Data Out High Byte Hold Time 45 0 130 40 20 25 20 8 40 10 50 70 20 26 Min 130 45 78 80 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Digital Audio
Figure 9. Digital Audio Timing
tCW WSBD CLBD
tCW
tCLBD
tSOD DABD0 DABD1 DAAD P1, P2, P3(*)
tSOD
(*) when used as alternate audio in
Table 12. Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD Rising to WSBD Change DABD Valid Prior/After CLBD Rising CLBD Cycle Time Min 200 200 416.67 Typ Max Unit ns ns ns
Digital Audio Frame
Figure 10. Digital Audio Frame Format
WSBD (I2S) WSBD (Japanese) CLBD
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
DABD0 DABD1 DAAD P1,P2,P3(*)
MSB
LSB (16 bits)
LSB (20 bits) LSB (18 bits)
MSB
(*) when used as alternate audio in
Notes:
1. Selection between I2S and Japanese format is a firmware option. 2. DAAD, P1, P2, P3 are 16 bits only. 3. When connected to codecs such as CS4216 or CS4218, D0 - D11 can be used to hold independent auxiliary information on left and right words. Refer to the corresponding codec data sheets for details. Auxiliary information is available on DABD0 and DAAD.
12
SAM9703
SAM9703
Reset and Power-down
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which can take about 20 ms. A typical RC/diode power-up network can be used. After the low-to-high transition of RESET, the following occurs: * The synthesis enters an idle state. * The RUN output is set to zero. * Firmware execution starts from address 0100H in ROM space (WCS0 low). If PDWN is asserted low, then all I/Os and outputs will be floated and the crystal oscillator and PLL will be stopped. The chip enters a deep power-down sleep mode. To exit power-down, PDWN has to be asserted high, then RESET applied.
Recommended Board Layout
As for all HCMOS high-integration ICs, some rules of board layout should be followed for reliable operation: * GND, VCC, VC3 distribution, decouplings All GND, VCC, VC3 pins should be connected. GND + VCC planes are strongly recommended below the SAM9703. The board GND + VCC distribution should be in grid form. For 5V VCC operation, if 3.3V is not available, then VC3 can be connected to VCC by two 1N4148 diodes in serial. This guarantees a minimum voltage drop of 1.2V. Recommended VCC decoupling is 0.1 F at each corner of the IC with an additional 10 F decoupling close to the crystal. VC3 requires a single 0.1 F decoupling close to the IC. * Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-R and the SAM9703 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from SAM9703. * Analog Section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the codec vendor recommended layout for correct implementation of the analog section. * Unused Inputs Unused inputs should always be connected. A floating input can cause internal oscillation inside the IC, which can destroy the device by dramatically increasing the power consumption. If the power-down feature is to be used, care should be taken that no pin is left floating during power down. Usually, a 1 M ground return is sufficient.
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Recommended Crystal Compensation and LFT Filter
Figure 11. Crystal Compensation and LFT Filter
C1 GND 22 pF X1 9.6 MHz GND C4 22 pF 10 C2 2.2 nF R1 100 VCC C3 10 nF GND 14 PDWN/ LFT 11 X2 12 X1
DABD1
31
18
23
32
29
Note:
The X2 output cannot be used to drive another circuit.
14
SAM9703
DABD0
30
WSBD
DAAD
CLBD
RUN
SAM9703
CleanWave32TM ROM Firmware (Ref. GMS973201)
* ROM includes Firmware and PCM Data * Full GM implementation with Top-quality Additional
Sounds - 128 General MIDI Sounds - 189 Variation Sounds including Sound Effects - 9 Drum Sets + 1 SFX Set
* Powerful MIDI implementation * Built-in Compatible Reverb and Chorus * Built-in Four-band Parametric Equalizer, Fully Controllable
by MIDI
* Built-in Spatializer Effect with MIDI Control * Microphone Echo Processing
MIDI Reverb ROM CleanWave32 (GMS973201)
Synthesizer
RAM 32k x 16 Chorus Front EQ CODEC PCM3001 or Equivalent Surround Back
SAM9503
MIKE 1
Echo Processor
MIKE 2
(option, requires additional DAC)
HARDWARE
FUNCTION
For detailed information about sound list and MIDI implementation, please request the CleanWave32 user's manual.
Reference Design: 9703DVB
SAM9703 + 2 x 16-Mbit EPROMs + 2 x 32k x 8 SRAMs + Codec + DAC 9703DVB can be used for CleanWave32 evaluation or other specific applications requiring not more than 4 Mb of PCM data.
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1710A-10/00/0M
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