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| HM538123B Series 1 M VRAM (128-kword x 8-bit) ADE-203-231D (Z) Rev. 4.0 Nov. 1997 Description The HM538123B is a 1-Mbit multiport video RAM equipped with a 128-kword x 8-bit dynamic RAM and a 256-word x 8-bit SAM (serial access memory). Its RAM and SAM operate independently and asynchronously. It can transfer data between RAM and SAM. In addition, it has two modes to realize fast writing in RAM. Block write and flash write modes clear the data of 4-word x 8-bit and the data of one row (256-word x 8-bit) respectively in one cycle of RAM. And the HM538123B makes split transfer cycle possible by dividing SAM into two split buffers equipped with 128-word x 8-bit each. This cycle can transfer data to SAM which is not active, and enables a continuous serial access. Features * Multiport organization Asynchronous and simultaneous operation of RAM and SAM capability RAM: 128-kword x 8-bit and SAM: 256-word x 8-bit * Access time RAM: 60 ns/70 ns/80 ns/100 ns max SAM: 20 ns/22 ns/25 ns/25 ns max * Cycle time RAM: 125 ns/135 ns/150 ns/180 ns min SAM: 25 ns/25 ns/30 ns/30 ns min * Low power Active RAM: 413 mW max SAM: 275 mW max Standby 38.5 mW max * High-speed page mode capability * Mask write mode capability * Bidirectional data transfer cycle between RAM and SAM capability * Split transfer cycle capability * Block write mode capability * Flash write mode capability HM538123B Series * 3 variations of refresh (8 ms/512 cycles) 5$6-only refresh &$6-before-5$6 refresh Hidden refresh * TTL compatible Ordering Information Type No. HM538123BJ-6 HM538123BJ-7 HM538123BJ-8 HM538123BJ-10 Access Time 60 ns 70 ns 80 ns 100 ns Package 400-mil 40-pin plastic SOJ (CP-40D) 2 HM538123B Series Pin Arrangement HM538123BJ Series SC SI/O0 SI/O1 SI/O2 SI/O3 DT/OE I/O0 I/O1 I/O2 I/O3 VCC WE NC RAS NC A8 A6 A5 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 V SS SI/O7 SI/O6 SI/O5 SI/O4 SE I/O7 I/O6 I/O5 I/O4 VSS DSF NC CAS QSF A0 A1 A2 A3 A7 Pin Description Pin Name A0 - A8 I/O0 - I/O7 SI/O0 - SI/O7 5$6 &$6 :( '7/2( Function Address inputs RAM port data inputs/outputs SAM port data inputs/outputs Row address strobe Column address strobe Write enable Data transfer/Output enable Serial clock SAM port enable Special function input flag Special function output flag Power supply Ground No connection SC 6( DSF QSF VCC VSS NC 3 HM538123B Series Block Diagram A0 - A8 A0 - A7 Column Address Buffer A0 - A8 Row Address Buffer Refresh Counter Row Decoder Serial Address Counter QSF Sense Amplifier & I/O Bus Block Write Flash Write Control Control 511 0 Input Data Control Transfer Gate Data Register Serial Output Buffer Serial Input Buffer Address Mask Register Mask Register Color Resister SI/O0 - SI/O7 Input Buffer Output Buffer Timing Generator I/O0 - I/O7 4 RAS CAS DT/OE WE DSF SC SE SAM Column Decoder Column Decoder Transfer Gate Data Register 0 255 Memory Array SAM I/O Bus HM538123B Series Pin Functions 5$6 (input pin): 5$6 is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of 5$6. The input level of these signals determine the operation cycle of the HM538123B. Table 1 Operation Cycles of the HM538123B Input Level At The Falling Edge Of 5$6 &$6 L H H H H H H H H H H H '7 2( :( '7/2( X L L L L L H H H H H H X L L L H H L L L H H H 6( X L H X X X X X X X X X DSF At The Falling Edge Of DSF X L L H L H L L H L L H &$6 -- X X X X X L H X L H X Operation Mode CBR refresh Write transfer Pseudo transfer Split write transfer Read transfer Split read transfer Read/mask write Mask block write Flash write Read/write Block write Color register read/write Note: X; Don't care &$6 (input pin): Column address and DSF signal are fetched into chip at the falling edge of &$6, which determines the operation mode of HM538123B. &$6 controls output impedance of I/O in RAM. A0 - A8 (input pins): Row address (AX0 - AX8) is determined by A0 - A8 level at the falling edge of 5$6. Column address (AY0 - AY7) is determined by A0 - A7 level at the falling edge of &$6. In transfer cycles, row address is the address on the word line which transfers data with SAM data register, and column address is the SAM start address after transfer. pin has two functions at the falling edge of 5$6 and after. When :( is low at the falling edge of 5$6, the HM538123B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. (:( level at the falling edge of 5$6 is don't care in read cycle.) When :( is high at the falling edge of 5$6, a normal write cycle is executed. After that, :( switches read/write cycles as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by :( level at the falling edge of 5$6. When :( is low, data is transferred from SAM to RAM (data is written into RAM), and when :( is high, data is transferred from RAM to SAM (data is read from RAM). :( :( (input pin): 5 HM538123B Series I/O0 - I/O7 (input/output pins): I/O pins function as mask data at the falling edge of 5$6 (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained. After that, they function as input/output pins as those of a standard DRAM. In block write cycle, they function as address mask data at the falling edge of &$6. '7/2( pin functions as '7 (data transfer) pin at the falling edge of 5$6 and as 2( (output enable) pin after that. When '7 is low at the falling edge of 5$6, this cycle becomes a transfer cycle. When '7 is high at the falling edge of 5$6, RAM and SAM operate independently. '7 2( (input pin): '7/2( SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. 6( (input pin): 6( pin activates SAM. When 6( is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. 6( can be used as a mask for serial write because internal pointer is incremented at the rising edge of SC. SI/O0 - SI/O7 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was a pseudo transfer cycle or write transfer cycle, SI/O inputs data. DSF (input pin): DSF is a special function data input flag pin. It is set to high at the falling edge of 5$6 when new functions such as color register read/write, split transfer, and flash write, are used. DSF is set to high at the falling edge of &$6 when block write is executed. QSF (output pin): QSF outputs data of address A7 in SAM. QSF is switched from low to high by accessing address 127 in SAM and from high to low by accessing 255 address in SAM. 6 HM538123B Series Operation of HM538123B RAM Read Cycle ('7/2( high, &$6 high and DSF low at the falling edge of 5$6, DSF low at the falling edge of &$6) Row address is entered at the 5$6 falling edge and column address at the &$6 falling edge to the device as in standard DRAM. Then, when :( is high and '7/2( is low while &$6 is low, the selected address data outputs through I/O pin. At the falling edge of 5$6, '7/2( and &$6 become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address access time (tAA) and 5$6 to column address delay time (tRAD) specifications are added to enable high-speed page mode. RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) ('7/2( high, &$6 high and DSF low at the falling edge of 5$6, DSF low at the falling edge of &$6) * Normal Mode Write Cycle (:( high at the falling edge of 5$6) When &$6 and :( are set low after driving 5$6 low, a write cycle is executed and I/O data is written in the selected addresses. When all 8 I/Os are written, :( should be high at the falling edge of 5$6 to distinguish normal mode from mask write mode. If :( is set low before the &$6 falling edge, this cycle becomes an early write cycle and I/O becomes in high impedance. Data is entered at the &$6 falling edge. If :( is set low after the &$6 falling edge, this cycle becomes a delayed write cycle. Data is input at the :( falling. I/O does not become high impedance in this cycle, so data should be entered with 2( in high. If :( is set low after tCWD (min) and tAWD (min) after the &$6 falling edge, this cycle becomes a readmodify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O contention, data should be input after reading data and driving 2( high. * Mask Write Mode (:( low at the falling edge of 5$6) If :( is set low at the falling edge of 5$6, the cycle becomes a mask write mode which writes only to selected I/O. Whether or not an I/O is written depends on I/O level (mask data) at the falling edge of 5$6. Then the data is written in high I/O pins and masked in low ones and internal data is retained. This mask data is effective during the 5$6 cycle. So, in high-speed page mode, the mask data is retained during the page access. 7 HM538123B Series High-Speed Page Mode Cycle ('7/2( high, &$6 high and DSF low at the falling edge of 5$6) High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling &$6 while 5$6 is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and block write cycles can be mixed. Note that address access time (tAA), 5$6 to column address delay time (tRAD), and access time from &$6 precharge (tACP) are added. In one 5$6 cycle, 256-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within t RASP max (100 s). Color Register Set/Read Cycle (&$6 high, 5$6) '7/2( high, : ( high and DSF high at the falling edge of In color register set cycle, color data is set to the internal color register used in flash write cycle or block write cycle. 8 bits of internal color register are provided at each I/O. This register is composed of static circuits, so once it is set, it retains the data until reset. Color register set cycle is just as same as the usual write cycle except that DSF is set high at the falling edge of 5$6, and read, early write and delayed write cycle can be executed. In this cycle, HM538123B refreshs the row address fetched at the falling edge of 5$6. Flash Write Cycle (&$6 high, '7/2( high, :( low and DSF high at the falling edge of 5$6) In a flash write cycle, a row of data (256-word x 8-bit) is cleared to 0 or 1 at each I/O according to the data of color register mentioned before. It is also necessary to mask I/O in this cycle. When &$6and '7/2( is set high, :( is low, and DSF is high at the falling edge of 5$6, this cycle starts. Then, the row address to clear is given to row address and mask data is given to I/O. Mask data is as same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. Cycle time is the same as those of RAM read/write cycles, so all bits can be cleared in 1/256 of the usual cycle time. (See figure 1.) 8 HM538123B Series Color Register Set Cycle RAS CAS Address WE DT/OE DSF I/O Color Data Set color register *1 *1 Execute flash write into each I/O on row address Xi using color resister. Execute flash write into each I/O on row address Xj using color resister. Row Xi Xj Flash Write Cycle Flash Write Cycle Figure 1 Use of Flash Write Block Write Cycle (&$6 high, falling edge of &$6) '7/2( high and DSF low at the falling edge of 5$6, DSF high at the In a block write cycle, 4 columns of data (4-word x 8-bit) is cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are disregarded. The data on I/Os and addresses can be masked. I/O level at the falling edge of &$6 determines the address to be cleared. (See figure 2.) * Normal Mode Block Write Cycle (:( high at the falling edge of 5$6) The data on 8 I/Os are all cleared when :( is high at the falling edge of 5$6. * Mask Block Write Mode (:( low at the falling edge of 5$6) When :( is low at the falling edge of 5$6, HM538123B starts mask block write mode to clear the data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. The mask data is available in the 5$6 cycle. In page mode block write cycle, the mask data is retained during the page access. 9 HM538123B Series Color Register Set Cycle RAS CAS Address WE DT/OE DSF I/O *1 WE Low High I/O I/O Mask Data Don't care Mode Mask Non mask Color Data *1 Address Mask Block Write Cycle Block Write Cycle Row Row *1 Column A2-A7 Row *1 Column A2-A7 *1 Address Mask I/O Mask Data Low: Mask High: Non Mask Address Mask Data I/O0 I/O1 I/O2 I/O3 Column0 (A0 = 0, A1 = 0) Mask Data Column1 (A0 = 1, A1 = 0) Mask Data Column2 (A0 = 0, A1 = 1) Mask Data Column3 (A0 = 1, A1 = 1) Mask Data Low: Mask High: Non Mask Figure 2 Use of Block Write Transfer Operation The HM538123B provides the read transfer cycle, split read transfer cycle, pseudo transfer cycle, write transfer cycle and split write transfer cycle as data transfer cycles. These transfer cycles are set by driving &$6 high and '7/2( low at the falling edge of 5$6. They have following functions: (1) Transfer data between row address and SAM data register (except for pseudo transfer cycle) Read transfer cycle and split read transfer cycle: RAM to SAM Write transfer cycle and split write transfer cycle: SAM to RAM (2) Determine SI/O state (except for split read transfer cycle and split write transfer cycle) Read transfer cycle: SI/O output Pseudo transfer cycle and write transfer cycle: SI/O input (3) Determine first SAM address to access after transferring at column address (SAM start address). SAM start address must be determined by read transfer cycle or pseudo transfer cycle (split transfer cycle isn't available) before SAM access, after power on, and determined for each transfer cycle. 10 HM538123B Series Read Transfer Cycle (&$6 high, '7/2( low, :( high and DSF low at the falling edge of 5$6) This cycle becomes read transfer cycle by driving '7/2( low, :( high and DSF low at the falling edge of The row address data (256 x 8-bit) determined by this cycle is transferred to SAM data register synchronously at the rising edge of '7/2(. After the rising edge of '7/2(, the new address data outputs from SAM start address determined by column address. In read transfer cycle, '7/2( must be risen to transfer data from RAM to SAM. 5$6. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min) specified between the last SAM access before transfer and '7/2( rising edge and tSDH (min) specified between the first SAM access and '7/2( rising edge must be satisfied. (See figure 3.) When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high impedance before tSZS (min) of the first SAM access to avoid data contention. RAS CAS Address DT/OE DSF SC SI/O SAM Data before Transfer Yj Yj + 1 L Xi Yj t SDD t SDH SAM Data after Transfer Figure 3 Pseudo Transfer Cycle (&$6 high, 5$6) '7/2( Real Time Read Transfer low, :( low, 6( high and DSF low at the falling edge of Pseudo transfer cycle switches SI/O to input state and set SAM start address without data transfer to RAM. This cycle starts when &$6 is high, '7/2( low, :( low, 6( high and DSF low at the falling edge of 5$6. Data should be input to SI/O later than tSID (min) after 5$6 becomes low to avoid data contention. SAM access becomes enabled after tSRD (min) after 5$6 becomes high. In this cycle, SAM access is inhibited during 5$6 low, therefore, SC must not be risen. 11 HM538123B Series Write Transfer Cycle (&$6 high, '7/2( low, :( low, 6( low and DSF low at the falling edge of 5$6) Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data transferred into RAM is determined by the address at the falling edge of 5$6. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after tSRD (min) after 5$6 becomes high. SAM access is inhibited during 5$6 low. In this period, SC must not be risen. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by write transfer cycle. However, the address to write data must be the same as that of the read transfer cycle or the split read transfer cycle (row address AX8). Figure 4 shows the example of row bit data transfer. In case AX8 is 0, data cannot be transferred RAM address within the range of 100000000 to 111111111. Same as the case of AX8 = 1. Split Read Transfer Cycle (&$6 high, '7/2( low, :( high and DSF high at the falling edge of 5$6) To execute a continuous serial read by real time read transfer, HM538123B must satisfy SC and '7/2( timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it possible to execute a continuous serial read without the above timing limitation. Figure 5 shows the block diagram for a split transfer. SAM data register (DR) consists of 2 split buffers, whose organizations are 128-word x 8-bit each. Let us suppose that data is read from upper data register DR1 (The row address AX8 is 0 and SAM address A7 is 1.). When split read transfer is executed setting row address AX8 0 and SAM start addresses A0 to A6, 128-word x 8-bit data are transferred from RAM to the lower data register DR0 (SAM address A7 is 0) automatically. After data are read from data register DR1, data start to be read from SAM start addresses of data register DR0. If the next split read transfer isn't executed while data are read from data register DR0, data start to be read from SAM start address 0 of DR1 after data are read from data register DR0. If split read transfer is executed setting row address AX8 1 and SAM start addresses A0 to A6 while data are read from data register DR1, 128-word x 8-bit data are transferred to data register DR2. After data are read from data register DR1, data start to be read from SAM start addresses of data register DR2. If the next split read transfer isn't executed while data is read from data register DR2, data start to be read from SAM start address 0 of data register DR3 after data are read from data register DR2. In this time, SAM data is the one transferred to data register DR3 finally while row address AX8 is 1. In split read data transfer, the SAM start address A7 is automatically set in the data register which isn't used. The data on SAM address A7, which will be accessed next, outputs to QSF, QSF is switched from low to high by accessing SAM last address 127 and from high to low by accessing address 255. Split read transfer cycle is set when &$6 is high, '7/2( is low, :( is high and DSF is high at the falling edge of 5$6. The cycle can be executed asyncronously with SC. However, HM538123B must be satisfied tSTS (min) timing specified between SC rising and 5$6 falling. SAM start address must be accessed, satisfying tRST (min), tCST (min) and tAST (min) timings specified between 5$6 or &$6 falling and column address. (See figure 6.) In split read transfer, SI/O isn't switched to output state. Therefore, read transfer must be executed to switch SI/O to output state when the previous transfer cycle is pseudo transfer or write transfer cycle. 12 HM538123B Series (Row address) A8 ........ A0 000000000 011111111 100000000 RAM 111111111 SAM (Read transfer cycle) (Write transfer cycle) 111111111 SAM SAM ........ RAM 011111111 100000000 (Row address) A8 ........A0 000000000 SAM Possible RAM Impossible RAM Figure 4 Example of Row Bit Data Transfer SAM Column Decoder DR1 SAM I/O Bus AX8 = 0 SAM I/O Bus Memory Array DR3 Memory Array AX8 = 1 DR0 SAM I/O Buffer SI/O Figure 5 Block Diagram for Split Transfer Split Write Transfer Cycle (&$6 high, '7/2( low, :( low and DSF high at the falling edge of 5$6) A continuous serial write cannot be executed because accessing SAM is inhibited during 5$6 low in write transfer. Split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST (min) and tAST (min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input state in this cycle. If SI/O is in output state, pseudo transfer cycle should be executed to switch SI/O into input state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by split write transfer cycle. However, pseudo transfer cycle must be executed before split write transfer cycle. And the MSB of row address (AX8) to write data must be the same as that of the read transfer cycle or the split read transfer cycle. DR2 13 HM538123B Series RAS tSTS (min) CAS t CST (min) Address Xi t AST (min) DT/OE DSF SC 255 (127) n (n + 127) 127 (255) 127 + Yj (Yj) Yj tRST (min) Figure 6 Limitation in Split Transfer SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When 6( is set high, SI/O becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 255), the internal pointer indicates address 0 at the next access. Serial Write Cycle If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode. In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If 6( is high, SI/O data isn't fetched into data register. Internal pointer is incremented by the SC rising, so 6( high can be used as mask data for SAM. After indicating the last address (address 255), the internal pointer indicates address 0 at the next access. 14 HM538123B Series Refresh RAM Refresh RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) 5$6-only refresh cycle, (2) &$6-before-5$6 (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate 5$6 such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. (1) 5$6-Only Refresh Cycle: 5$6-only refresh cycle is executed by activating only 5$6 cycle with &$6 fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this cycle from data transfer cycle, '7/2( must be high at the falling edge of 5$6. (2) CBR Refresh Cycle: CBR refresh cycle is set by activating &$6 before 5$6. In this cycled, refresh address needs not to be input through external circuits because it is input through an internal refresh counter. In this cycle, output is in high impedance and power dissipation is lowered because &$6 circuits don't operate. (3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating 5$6 when '7/2( and &$6 keep low in normal RAM read cycles. SAM Refresh SAM parts (data register, shift register and selector), organized as fully static circuitry, require no refresh. Absolute Maximum Ratings Parameter Terminal voltage *1 *1 Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -0.5 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Power supply voltage Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Relative to VSS. 15 HM538123B Series Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage *1 *1 Symbol VCC VIH VIL *1 Min 4.5 2.4 -0.5 *2 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Input high voltage Input low voltage Notes: 1. All voltages referred to VSS 2. -3.0 V for pulse width 10 ns DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM538123B -6 Parameter Operating current Symbol ICC1 -7 -8 -10 Test Conditions SAM Port SC = VIL, 6( = VIH 6( = VIL, SC cycling tSCC = Min 5$6, &$6 Min Max Min Max Min Max Min Max Unit RAM Port -- 75 -- 70 -- 60 -- 55 mA 5$6, &$6 cycling tRC = Min ICC7 -- 125 -- 120 -- 100 -- 95 mA Standby current ICC2 ICC8 -- -- 7 50 -- -- 7 50 -- -- 7 40 -- -- 7 40 mA mA = VIH SC = VIL, 6( = VIH 6( = VIL, SC cycling tSCC = Min 5$6-only ICC3 -- 75 -- 70 -- 60 -- 55 mA 5$6 &$6 refresh current ICC9 -- 125 -- 120 -- 100 -- 95 mA cycling = VIH tRC = Min SC = VIL, 6( = VIH 6( = VIL, SC cycling tSCC = Min Page mode current ICC4 -- 80 -- 80 -- 70 -- 65 mA &$6 5$6= cycling VIL tPC = Min SC = VIL, 6( = VIH 6( = VIL, SC cycling tSCC = Min ICC10 -- 130 -- 130 -- 110 -- 105 mA 16 HM538123B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont) HM538123B -6 Parameter &$6-before- -7 -8 -10 Test Conditions SAM Port SC = VIL, 6( = VIH 6( = VIL, SC cycling tSCC = Min 5$6, &$6 Symbol ICC5 Min Max Min Max Min Max Min Max Unit RAM Port -- 50 -- 45 -- 40 -- 35 mA cycling tRC = Min 5$6 refresh current 5$6 ICC11 -- 100 -- 95 -- 80 -- 75 mA Data transfer ICC6 current ICC12 -- 80 -- 75 -- 65 -- 60 mA cycling tRC = Min -- 130 -- 125 -- 105 -- 100 mA SC = VIL, 6( = VIH 6( = VIL, SC cycling tSCC = Min Input leakage ILI current Output leakage current Output high voltage Output low voltage ILO -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 A A VOH VOL 2.4 -- -- 0.4 2.4 -- -- 0.4 2.4 -- -- 0.4 2.4 -- -- 0.4 V V IOH = -2 mA IOL = 4.2 mA Notes: 1. ICC depends on output loading condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once while 5$6 is low and &$6 is high. Capacitance (Ta = 25C, VCC = 5 V, f = 1 MHz, Bias: Clock, I/O = VCC, address = VSS) Parameter Address Clock I/O, SI/O, QSF Symbol CI1 CI2 CI/O Min -- -- -- Typ -- -- -- Max 5 5 7 Unit pF pF pF 17 HM538123B Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1,*16 Test Conditions * * * * * Input rise and fall time : 5 ns Output load : See figures Input pulse levels: VSS to 3.0 V Input timing reference levels : 0.8 V, 2.4 V Output timing reference levels : 0.8 V, 2.0 V +5V +5V I OH = - 2 mA I OL = 4.2 mA I/O I OH = - 2 mA I OL = 4.2 mA SI / O *1 100 pF *1 50 pF Output Load (A) Output Load (B) Note: 1. Including scope & jig 18 HM538123B Series Common Parameter HM538123B -6 Parameter Random read or write cycle time 5$6 5$6 &$6 -7 Min Max 135 -- 55 -- -8 Min Max 150 -- 60 -- -10 Min Max 180 -- 70 -- Uni Note t s ns ns Symbol Min Max tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRSH tCSH tCRP tT tREF tDTS tDTH tFSR tRFH tFSC tCFH tDZC tDZO tOFF1 tOFF2 125 -- 55 60 20 0 10 0 15 20 20 60 10 3 -- 0 10 0 10 0 15 0 0 -- -- -- precharge time pulse width pulse width 10000 70 -- -- -- -- -- 40 -- -- -- 50 8 -- -- -- -- -- -- -- -- 20 20 20 0 10 0 15 20 20 70 10 3 -- 0 10 0 10 0 15 0 0 -- -- 10000 80 -- -- -- -- -- 50 -- -- -- 50 8 -- -- -- -- -- -- -- -- 20 20 20 0 10 0 15 20 20 80 10 3 -- 0 10 0 10 0 15 0 0 -- -- 10000 100 10000 ns -- -- -- -- -- 60 -- -- -- 50 8 -- -- -- -- -- -- -- -- 20 20 25 0 10 0 15 20 25 -- -- -- -- -- 75 -- ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns 4 4 5 5 3 2 Row address setup time Row address hold time Column address setup time Column address hold time 5$6 5$6 &$6 &$6 5$6 &$6 to &$6 delay time hold time referenced to hold time referenced to to 5$6 precharge time 100 -- 10 3 -- 0 10 0 10 0 15 0 0 -- -- -- 50 8 -- -- -- -- -- -- -- -- 20 20 Transition time (rise to fall) Refresh period '7 '7 to 5$6 setup time to 5$6 hold time DSF to 5$6 setup time DSF to 5$6 hold time DSF to &$6 setup time DSF to &$6 hold time Data-in to &$6 delay time Data-in to 2( delay time Output buffer turn-off delay referred to &$6 Output buffer turn-off delay referred to 2( 19 HM538123B Series Read Cycle (RAM), Page Mode Read Cycle HM538123B -6 Parameter Access time from 5$6 Access time from &$6 Access time from 2( Address access time Read command setup time Read command hold time Read command hold time referenced to 5$6 5$6 -7 Min Max -- -- -- -- 0 0 10 15 35 35 45 10 -- 70 20 20 35 -- -- -- 35 -- -- -- -- 40 -8 Min Max -- -- -- -- 0 0 10 15 40 40 50 10 -- 80 20 20 40 -- -- -- 40 -- -- -- -- 45 -10 Min Max -- -- -- -- 0 0 10 15 45 45 55 10 -- 100 25 25 45 -- -- -- 55 -- -- -- -- 50 Uni Note t s ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 2 6, 7 7, 8 7 7, 9 Symbol Min Max tRAC tCAC tOAC tAA tRCS tRCH tRRH -- -- -- -- 0 0 10 15 35 35 45 10 -- 60 60 20 20 35 -- -- -- 25 -- -- -- -- 40 to column address delay tRAD tRAL tCAL tPC tCP tACP tRASP time Column address to 5$6lead time Column address to &$6lead time Page mode cycle time &$6 precharge time Access time from &$6 precharge Page mode 5$6 pulse width 100000 70 100000 80 100000 100 100000 ns 20 HM538123B Series Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle HM538123B -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to 5$6lead time Write command to &$6lead time Data-in setup time Data-in hold time :( :( -7 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 45 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -8 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 50 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -10 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 55 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Uni Note t s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 12 12 11 Symbol Min Max tWCS tWCH tWP tRWL tCWL tDS tDH tWS tWH tMS tMH tOEH tPC tCP tCDD tRASP 0 15 15 20 20 0 15 0 10 0 10 20 45 10 20 60 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- to 5$6 setup time to 5$6 hold time Mask data to 5$6 setup time Mask data to 5$6 hold time 2( hold time referred to :( Page mode cycle time &$6 &$6 precharge time to data-in delay time Page mode 5$6 pulse width 100000 70 100000 80 100000 100 100000 ns 21 HM538123B Series Read-Modify-Write Cycle HM538123B -6 Parameter Read-modify-write cycle time 5$6 -7 Min Max 185 -- -8 Min Max 200 -- -10 Min Max 230 -- Uni Note t s ns Symbol Min Max tRWC 175 -- pulse width (read-modify- tRWS write cycle) &$6 110 10000 120 10000 130 10000 150 10000 ns 45 60 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 60 20 20 35 25 -- -- -- -- -- -- -- 45 60 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 70 20 20 35 35 -- -- -- -- -- -- -- 45 65 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 80 20 20 40 40 -- -- -- -- -- -- -- 50 70 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 100 25 25 45 55 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 14 14 12 6, 7 7, 8 7 7, 9 to :( delay time tCWD tAWD tODD tRAC tCAC tOAC tAA Column address to :( delay time 2( to data-in delay time Access time from 5$6 Access time from &$6 Access time from 2( Address access time 5$6 to column address delay tRAD tRCS tRWL tCWL tWP tDS tDH tOEH time Read command setup time Write command to 5$6 lead time Write command to &$6 lead time Write command pulse width Data-in setup time Data-in hold time 2( hold time referred to :( Refresh Cycle HM538123B -6 Parameter &$6 -7 Min Max 10 10 10 -- -- -- -8 Min Max 10 10 10 -- -- -- -10 Min Max 10 10 10 -- -- -- Uni Note t s ns ns ns Symbol Min Max tCSR tCHR tRPC 10 10 10 -- -- -- setup time (&$6-before-5$6 refresh) hold time (&$6-before-5$6 refresh) &$6 5$6 &$6 precharge to hold time 22 HM538123B Series Flash Write Cycle, Block Write Cycle HM538123B -6 Parameter &$6 2( -7 Min Max 20 20 -- -- -8 Min Max 20 20 -- -- -10 Min Max 20 20 -- -- Uni Note t s ns ns 13 13 Symbol Min Max tCDD tODD 20 20 -- -- to data-in delay time to data-in delay time Read Transfer Cycle HM538123B -6 Parameter % % % -7 Max 10000 -- -- -- -- -- -- -- -- -- -- -- 65 35 35 -- -- -- -- -- Min 60 20 25 20 65 25 70 25 40 5 25 10 -- -- -- 20 5 5 0 25 Max 10000 -- -- -- -- -- -- -- -- -- -- -- 70 35 35 -- -- -- -- -- -8 Min 65 20 30 20 70 30 80 25 45 5 25 15 -- -- -- 20 5 5 0 30 Max 10000 -- -- -- -- -- -- -- -- -- -- -- 75 40 35 -- -- -- -- -- -10 Min 80 25 30 30 80 30 100 25 50 5 25 15 -- -- -- 25 5 5 0 30 Max 10000 -- -- -- -- -- -- -- -- -- -- -- 85 40 35 -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 15 17 Symbol tRDH tCDH Min 50 20 25 20 65 25 60 25 40 5 25 10 -- -- -- 20 5 5 0 25 hold time referenced to #$ hold time referenced to $ hold time referenced to column tADH address % % precharge time to #$ delay time tDTP tDRD tSRS tSRH tSCH SC to #$ setup time 1st SC to #$ hold time 1st SC to $ hold time 1st SC to column address hold time tSAH Last SC to % delay time Last SC to % delay time 1st SC to % hold time #$ $ % tSDD tSDD2 tSDH tRQD tCQD tDQD tRQH tCQH tDQH tSZS tSCC to QSF delay time to QSF delay time to QSF delay time QSF hold time referred to #$ QSF hold time referred to $ QSF hold time referred to % Serial data-in to 1st SC delay time Serial clock cycle time 23 HM538123B Series Read Transfer Cycle (cont) HM538123B -6 Parameter SC pulse width SC precharge time SC access time Serial data-out hold time Serial data-in setup time Serial data-in hold time 5$6 -7 Min Max 5 10 -- 5 0 15 15 35 10 -- -- 22 -- -- -- 35 -- -- -8 Min Max 10 10 -- 5 0 15 15 40 10 -- -- 25 -- -- -- 40 -- -- -10 Min Max 10 10 -- 5 0 15 15 45 10 -- -- 25 -- -- -- 55 -- -- Uni Note t s ns ns ns ns ns ns ns ns ns 15 Symbol Min Max tSC tSCP tSCA tSOH tSIS tSIH 5 10 -- 5 0 15 15 35 10 -- -- 20 -- -- -- 25 -- -- to column address delay tRAD tRAL tDTHH time Column address to 5$6 lead time precharge to '7 high hold time 5$6 24 HM538123B Series Pseudo Transfer Cycle, Write Transfer Cycle HM538123B -6 Parameter 6( 6( -7 Min Max 0 10 25 20 10 40 -- -- 20 5 25 5 10 -- -- 5 5 0 15 -- -- -- -- 40 -- 70 35 -- -- -- -- -- 22 22 -- -- -- -- -8 Min Max 0 10 30 25 10 45 -- -- 20 5 30 10 10 -- -- 5 5 0 15 -- -- -- -- 45 -- 75 40 -- -- -- -- -- 25 25 -- -- -- -- -10 Min Max 0 10 30 25 10 50 -- -- 25 5 30 10 10 -- -- 5 5 0 15 -- -- -- -- 50 -- 85 40 -- -- -- -- -- 25 25 -- -- -- -- Uni Note t s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 15 15 Symbol Min Max 0 10 25 20 10 40 -- -- 20 5 25 5 10 -- -- 5 5 0 15 -- -- -- -- 40 -- 65 35 -- -- -- -- -- 20 20 -- -- -- -- setup time referred to 5$6 tES hold time referred to 5$6 tEH tSRD tSRZ tSID tRQD tCQD tRQH tCQH tSCC tSC tSCP tSCA tSEA tSOH tSIS tSIH SC setup time referred to 5$6 tSRS 5$6 to SC delay time Serial output buffer turn-off time referred to 5$6 5$6 to serial data-in delay to QSF delay time to QSF delay time time 5$6 &$6 QSF hold time referred to 5$6 QSF hold time referred to &$6 Serial clock cycle time SC pulse width SC precharge time SC access time 6( access time Serial data-out hold time Serial write enable setup time tSWS Serial data-in setup time Serial data-in hold time 25 HM538123B Series Split Read Transfer Cycle, Split Write Transfer Cycle HM538123B -6 Parameter Split transfer setup time Split transfer hold time referenced to 5$6 Split transfer hold time referenced to &$6 Symbol Min Max tSTS tRST tCST 20 60 20 35 -- 5 25 5 10 -- 5 0 15 15 35 -- -- -- -- 30 -- -- -- -- 20 -- -- -- 25 -- -7 Min Max 20 70 20 35 -- 5 25 5 10 -- 5 0 15 15 35 -- -- -- -- 30 -- -- -- -- 22 -- -- -- 35 -- -8 Min Max 20 80 20 40 -- 5 30 10 10 -- 5 0 15 15 40 -- -- -- -- 30 -- -- -- -- 25 -- -- -- 40 -- -10 Min Max 25 -- Uni Note t s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 100 -- 25 45 -- 5 30 10 10 -- 5 0 15 15 45 -- -- 30 -- -- -- -- 25 -- -- -- 55 -- Split transfer hold time tAST referenced to column address SC to QSF delay time QSF hold time referred to SC Serial clock cycle time SC pulse width SC precharge time SC access time Serial data-out hold time Serial data-in setup time Serial data-in hold time 5$6 tSQD tSQH tSCC tSC tSCP tSCA tSOH tSIS tSIH to column address delay tRAD tRAL time Column address to 5$6 lead time 26 HM538123B Series Serial Read Cycle, Serial Write Cycle HM538123B -6 Parameter Serial clock cycle time SC pulse width SC precharge width Access time from SC Access time from 6( Serial data-out hold time Serial output buffer turn-off time referred to 6( Serial data-in setup time Serial data-in hold time Symbol Min Max tSCC tSC tSCP tSCA tSEA tSOH tSEZ tSIS tSIH tSWH tSWIH 25 5 10 -- -- 5 -- 0 15 5 15 5 15 -- -- -- 20 20 -- 20 -- -- -- -- -- -- -7 Min Max 25 5 10 -- -- 5 -- 0 15 5 15 5 15 -- -- -- 22 22 -- 20 -- -- -- -- -- -- -8 Min Max 30 10 10 -- -- 5 -- 0 15 5 15 5 15 -- -- -- 25 25 -- 20 -- -- -- -- -- -- -10 Min Max 30 10 10 -- -- 5 -- 0 15 5 15 5 15 -- -- -- 25 25 -- 20 -- -- -- -- -- -- Uni Note t s ns ns ns ns ns ns ns ns ns ns ns ns ns 5 15 15 Serial write enable setup time tSWS Serial write enable hold time Serial write disable setup time tSWIS Serial write disable hold time Notes: 1. AC measurements assume tT = 5 ns. 2. When tRCD > tRCD (max) or tRAD > tRAD (max), access time is specified by tCAC or tAA. 3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT is measured between VIH and VIL. 4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied. 5. tOFF1 (max), tOFF2 (max) and tSEZ (max) are defined as the time at which the output achieves the open circuit condition (VOH - 100 mV, VOL + 100 mV). 6. Assume that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. When tRCD tRCD (max) and tRAD tRAD (max), access time is specified by tCAC. 9. When tRCD tRCD (max) and tRAD tRAD (max), access time is specified by tAA. 10. If either tRCH of tRRH is satisfied, operation is guaranteed. 11. When tWCS tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 12. These parameters are specified by the later falling edge of &$6 or :(. 13. Either tCDD (min) or tODD (min) must be satisfied because output buffer must be turned off by &$6 or 2( prior to applying data to the device when output buffer is on. 14. When tAWD tAWD (min) and tCWD tCWD (min) in read-modify-write cycle, the data of the selected address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be satisfied because output buffer must be turned off by 2( prior to applying data to the device. 15. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. 27 HM538123B Series 16. After power-up, pause for 100 s or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. 17. After read transfer cycle, if split read transfer cycle is executed without SC access and SC address is 126 or 254, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is effective and satisfied 5 ns. 18. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout Timing Waveforms*18 Read Cycle t RC t RAS RAS t CSH t RCD CAS t ASR Address Row t RSH t CAS t RAL t ASC Column t RCS t CAC t AA t RAC t DZC t DZO t DTS DT/OE t FSR DSF t RFH t FSC t CFH t DTH t OAC t OFF1 Valid Dout t OFF2 t CAH t RRH t CAL t CRP t RP t RAD t RAH t RCH t CDD WE I/O (Output) I/O (Input) 28 HM538123B Series Early Write Cycle t RC t RAS RAS t CSH t RCD CAS Address t ASR Row t WS WE I/O (Output) I/O (Input) DT/OE t FSR DSF t RFH t FSC t CFH *1 High-Z t MS t MH t DS t DH t WH t RAH t RSH t CAS t CAH t RP t CRP t ASC Column t WCS t WCH Mask Data t DTS t DTH Valid Din Note: 1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. Delayed Write Cycle t RC t RAS RAS t RCD CAS Address t ASR t RAH Row t WS WE I/O (Output) I/O (Input) *1 t WH t ASC Columun t RWL t WP t CWL t CSH t RSH t CAS t CAH t RP t CRP t MS t MH t DZC t OFF2 t ODD t FSC t CFH t DS t DH Mask Data t DTH t DTS t FSR t RFH Valid Din t OEH DT/OE DSF Note: 1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. 29 HM538123B Series Read-Modify-Write Cycle t RWC t RWS RAS t RCD CAS t RAD t ASR Address t WS WE I/O (Output) I/O (Input) DT/OE t FSR DSF t RFH t FSC t CFH *1 t RAH t ASC t CAH t AWD t CWD t CAC t AA t RAC Valid Dout t MS t MH t DZC t DZO t OAC t OFF2 t ODD Mask Data t DTS t DTH t DS t DH t RWL t CWL t WP t CRP t RP Row t WH Column tRCS Valid Din t OEH Note: 1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. Page Mode Read Cycle t RC t RASP RAS t CSH t RCD t CAS t RAD t ASR Address t RAH t ASC Row t CAL t CAH t PC t CP t CAS t CAL t CAH t RAL t ASC t RCS t OFF1 Valid Dout t RP t RSH t CAS t CAL t CAH Column t RRH t RCH t AA t ACP t CAC Valid Dout t CP t CRP CAS t ASC Column t RCS Column t RCH t RCS t AA t ACP t CAC t DZC t OAC t RCH WE t RAC t OFF1 t AA t CAC t DZC t CDD t OAC t OFF2 Valid Dout t OFF1 I/O (Output) t CDD t OFF2 t DZC t OAC t CDD I/O (Input) t DTS DT/OE t FSR DSF t DZO t DTH t RFH t FSC t CFH t FSC t CFH t FSC t CFH 30 HM538123B Series Page Mode Write Cycle (Early Write) t RC t RASP RAS t CSH t RCD CAS Address t ASR t RAH t ASC t CAS t CP t PC t CAS t CP t RSH t CAS t CAH Column t WCS t WCH t CRP t RP t CAH t ASC Column t CAH t ASC Row Column t WS t WH t WCS t WCH *1 t WCS t WCH WE I/O (Output) I/O (Input) t DTS DT/OE t FSR DSF t MS High-Z t MH t DS t DH t DS t DH Valid Din t DS t DH Valid Din Mask Data Valid Din t DTH t RFH t CFH t FSC t FSC t CFH t FSC t CFH Note: 1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. Page Mode Write Cycle (Delayed Write) t RC t RASP RAS t CSH t RCD CAS Address t ASR t RAH t ASC Row t WS WE I/O (Output) I/O (Input) t DTS DT/OE t FSR DSF t RFH t FSC t CFH t FSC t CFH t FSC t CFH t MS *1 t MH t DS t DH t DS t DH t DS t DH t WH Column t CWL t WP t CAS t CAH t CP t ASC Column t CWL t WP t PC t CAS t CAH t CP t RSH t CAS t CAH t RWL t WP t CRP t RP t ASC Column t CWL Mask Data Valid Din Valid Din Valid Din t OEH Note: 1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. 31 HM538123B Series 5$6 5$6-Only Refresh Cycle t RC t RAS RAS CAS Address t OFF1 I/O (Output) t CDD I/O (Input) t OFF2 t ODD t DTS DT/OE t FSR DSF t RFH t DTH t CRP t ASR t RAH t RPC t RP Row &$6 &$6-Before-5$6 Refresh Cycle 5$6 t RC t RP RAS t RPC t CP t RAS t RPC t CSR t CHR Inhibit Falling Transition CAS Address t RP t CSR WE I/O (Output) DT/OE t OFF1 High-Z DSF 32 HM538123B Series Hidden Refresh Cycle t RC t RAS RAS t RCD CAS t ASR Address Row t RCS WE t CAC t AA t RAC I/O (Output) I/O (Input) t DTS DT/OE t FSR Valid Dout t DZC t DZO t DTH t RFH t OAC t OFF2 t OFF1 t RSH t CHR t CRP t RP t RAS t RC t RP t RAD t RAL t RAH t ASC t CAH Column t RRH t FSC t CFH DSF Color Register Set Cycle (Early Write) t RC t RAS RAS t CSH t RCD CAS Address t WS WE I/O (Output) I/O (Input) t DTS DT/OE t FSR DSF t RFH t DTH High-Z t DS t DH t ASR Row t WH t WCS t WCH t RAH t RSH t CAS t CRP t RP Color Data 33 HM538123B Series Color Register Set Cycle (Delayed Write) t RC t RAS RAS t CSH t RCD CAS t ASR Address t WS t WP WE I/O (Output) I/O (Input) t DTS DT/OE DSF t FSR t RFH High-Z t DS t DH t RAH t RSH t CAS t CRP t RP Row t RWL t CWL Color Data t OEH Color Register Read Cycle tRC t RAS RAS t CSH t RCD CAS Address t WS WE t RAC I/O (Output) t DZC I/O (Input) t DTS DT/OE DSF t FSR t RFH t DZO t DTH t OAC Valid Out t OFF2 t ODD t ASR t RAH t RSH t CAS tCRP tRP Row t WH t RCS t CAC tRRH t RCH t CDD t OFF1 34 HM538123B Series Flash Write Cycle t RC t RAS RAS t CRP CAS Address t ASR Row t WS WE t OFF1 I/O (Output) I/O (Input) DT/OE DSF t OFF2 t CDD High-Z t ODD t DTS t MS t MH t WH t RCD t RAH t RP Mask Data t DTH t FSR t RFH Block Write Cycle t RC t RAS RAS t CRP CAS Address t WS WE t OFF1 I/O (Output) I/O (Input) DT/OE t FSR DSF t RFH t FSC t CFH t OFF2 t CDD High-Z t ODD t DTS t MS t MH t DS t DH t ASR t RAH t RCD t ASC t CAH t RSH t CSH t RP t CRP Row t WH *1 Column A2-A8 I/O Mask Data t DTH Address Mask Data Note: 1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. 35 HM538123B Series Page Mode Block Write Cycle t RC t RASP RAS t RCD CAS t ASR t RAH Address t WS WE I/O (Output) I/O (Input) t DTS DT/OE t FSR DSF t RFH t FSC t CFH t FSC t CFH t FSC t CFH *1 High-Z t MS I/O Mask t RP t CSH t CAS t CP t PC t CAS t CAH t CP t RSH t CAS t ASC Column A2-A8 t CRP t ASC Column A2-A8 t CAH t ASC Column A2-A8 t CAH Row t WH t MH t DS Address Mask t DH t DS Address Mask t DH t DS Address Mask t DH t DTH Note: 1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. 36 HM538123B Series Read Transfer Cycle (1) tRC t RAS RAS t CSH t RCD CAS t ASR Address Row t WS WE I/O (Output) t DTS DT/OE t FSR DSF t SCC t SCC t SDD t SDD2* 3 t SCA t SOH Valid Sout t SCC t SDH t SC t SCA t SOH Valid Sout Previous Row t DQD t DQH QSF *1 t RP t CRP t RSH t CAS t RAL t ASC t CAH SAM Start Address t RAD t RAH t WH High-Z t CDH t ADH t RDH t RFH t DTP t DRD t DTHH t SCC t SCP SC t SCA t SOH Valid Sout t SCA t SOH Valid Sout t SOH Valid Sout New Row SI/O (Output) SI/O (Input) SAM Address MSB t RQD t RQH t CQH t CQD QSF *2 SAM Address MSB Notes: 1. This QSF timing is referred when SC is risen once or more between the previous transfer cycle and &$6 falling edge of this cycle (QSF is switched by '7 rising). 2. This QSF timing is referred when SC isn't risen between the previous transfer cycle and &$6 falling edge of this cycle (QSF is switched by 5$6 or &$6 falling). 3. After read transfer cycle, if split read transfer cycle is executed without SC access and SC address is 126 or 254, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is effective and satisfied 5 ns. 37 HM538123B Series Read Transfer Cycle (2) t RC t RAS RAS t CSH t RCD CAS t ASR Address t WS WE t DTHH I/O (Output) DT/OE t FSR DSF t SRS t SC SC Inhibit Rising Transition t SCH t SAH t SRH SI/O (Output) SI/O (Input) t SIS t SIH t SZS t SCA t SOH Valid Sout t SDH t SCP t SC t SCC t SCP t SCA t RFH High-Z t DTS t DTH t DRD t DTP t RAD t RAH t ASC t CAH t RSH t CAS t RAL Sam Start Address t RP t CRP Row t WH Valid Sin t DQD t DQH QSF SAM Address MSB t CQD t CQH t RQD t RQH 38 HM538123B Series Pseudo Transfer Cycle t RC t RAS t RP RAS t CSH t RCD t RSH t CAS t ASR t RAH t ASC t CAH t CRP CAS Address t WS Row t WH SAM Start Address WE I/O (Output) DT/OE t FSR t RFH High - Z t DTS t DTH DSF t ES t SEZ t EH t SWS SE t SRS t SC t SRD t SCP t SCC t SC t SCP SC Inhibit Rising Transition t SCA t SOH t SRZ SI/O (Output) SI/O (Input) Valid Sout Valid Sout t SID t SIS t SIH t SIS t SIH t CQD t RQD t RQH t CQH Valid Sin Valid Sin QSF SAM Address MSB 39 HM538123B Series Write Transfer Cycle t RC t RAS t RP RAS t RCD t CSH t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address t WS Row t WH SAM Start Address WE I/O (Output) DT/OE t FSR t RFH High-Z t DTS t DTH DSF t ES t EH t SWS SE t SRS t SWS t SC t SRD t SCP t SC t SCC t SCP SC Inhibit Rising Transition SI/O (Output) SI/O (Input) t SIS t SIH t SIS t SIH t SIS t SIH Valid Sin t CQD t RQD t RQH t CQH Valid Sin Valid Sin QSF SAM Address MSB 40 HM538123B Series Split Read Transfer Cycle t RC t RAS t RP t CSH t CRP t RCD t RSH t CAS t CRP RAS CAS t ASR t RAD t RAH t ASC t CAH t RAL SAM Start Address Yi Address Row t WS t WH WE t OFF1 I/O (Output) t DTS t DTH High-Z DT/OE t FSR t RFH DSF t CST t AST t RST t SCC t STS t SC n (n+255) t SCP n+2 (n+257) 253 (509) 254 (510) 255 (511) Yi+255 (Yi) Low SE SC 511 (255) t SCA t SOH Valid Sout n+1 (n+256) t SCA t SOH Valid Sout SI/O (Output) SI/O (Input) Valid Sout Valid Sout Valid Sout Valid Sout t SQD t SQH t SQD t SQH QSF SAM Address MSB 41 HM538123B Series Split Write Transfer Cycle t RC t RAS t RP t CSH t RCD t RSH t CAS RAS CAS t ASR t RAH t RAL t ASC t CAH SAM Start Address Yi Address Row t WS t WH WE t OFF1 I/O (Output) t DTS t DTH High-Z DT/OE t FSR t RFH DSF t CST t AST t RST t SCC t STS t SC n (n+255) n+1 (n+256) t SCP n+2 (n+257) n+3 (n+258) 254 (510) 255 (511) Yi+255 (Yi) Low SE SC 511 (255) SI/O (Output) SI/O (Input) t SIS t SIH Valid Sin t SIS t SIH Valid Sin t SIS t SIH Valid Sin t SQD t SQH Valid Sin t SQD t SQH Valid Sin Valid Sin Valid Sin QSF SAM Address MSB 42 HM538123B Series Serial Read Cycle SE tSCC SC tSC tSCA tSOH SI/O (Output) Valid Sout tSEZ Valid Sout tSCP tSC tSCC tSCP tSC tSEA tSCA tSCP tSCC tSC tSCA tSOH Valid Sout Valid Sout Serial Write Cycle tSWH SE tSCC tSC SC tSIS SI/O (Input) tSIH tSCP tSCC tSC tSCP tSIS tSIH tSCC tSC tSCP tSIS tSIH tSC tSWIS tSWIH tSWS Valid Sin Valid Sin Valid Sin 43 HM538123B Series Package Dimensions HM538123BJ Series (CP-40D) Unit: mm 25.80 26.16 Max 40 21 10.16 0.13 11.18 0.13 0.74 3.50 0.26 1 20 1.30 Max 0.25 0.80 + 0.17 - 0.43 0.10 0.41 0.08 1.27 9.40 0.25 0.10 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) CP-40D -- Conforms 1.73 g 44 0.31 2.30 + 0.14 - HM538123B Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. 45 HM538123B Series Revision Record Rev. 1 2.0 Date Mar.18, 1994 Dec.8, 1994 Contents of Modification Initial issue Addition of figure 4: Example of row bit data transfer Addition of description about figure 4 for write transfer cycle 3.0 Apr. 24, 1995 AC Chracteristics Addition of tSDD2 (min): 25/25/25/25 ns Addition of notes 17 Timing waveforms Read transfer cycle Addition of tSDD2 timing Addition of notes 3 Change of Subtitle M. Takahashi T. Kizaki Drawn by Approved by M. Takahashi T. Kizaki M. Takahashi T. Kizaki 4.0 Nov. 1997 46 |
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