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IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
FEATURES: DESCRIPTION:
IDT74ALVC32
* 0.5 MICRON CMOS Technology * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SOIC, SSOP, and TSSOP packages
This quadruple 2-input positive-OR gate is built using advanced dual metal CMOS technology. The ALVC32 performs the Boolean function Y = A * B or Y = A + B in positive logic. The ALVC32 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for Heavy Loads
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
14 13 12 11 10 9 8
1A
1 2 3 4 5 6 7
VCC
4B 4A 4Y 3B 3A 3Y
A Y B
1B 1Y 2A 2B 2Y
GND
SOIC/ SSOP/ TSSOP TOP VIEW
PIN DESCRIPTION
Pin Names xA, xB xY Data Inputs Data Outputs Description
FUNCTION TABLE (EACH GATE)(1)
Inputs xA H X L
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care
Output xB X H L xY H H L
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c)2000 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-4638/1
IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT IIK IOK ICC ISS Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100
CAPACITANCE (TA = +25C, F = 1.0MHz)
Unit V V C mA mA mA mA Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1. As applicable to the device type.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL VIK VH ICCL ICCH ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VI = VCC VI = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -0.7 100 0.1 -- Max. -- -- 0.7 0.8 5 5 -1.2 -- 10 750 A A V mV A A V Unit V
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
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IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD Parameter Power Dissipation Capacitance per Gate Test Conditions CL = 0pF, f = 10Mhz Typical 24 VCC = 3.3V 0.3V Typical 26 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol tPLH tPHL Parameter Propagation Delay xA or xB to xY Min. 1 Max. 3.1 VCC = 2.7V Min. 1 Max. 3.4 VCC = 3.3V 0.3V Min. 1 Max. 3.3 Unit ns
NOTE: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C.
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IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse Generator
(1, 2)
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
6 2.7 1.5 300 300 50
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Quad Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VOL + VLZ VOL VOH VOH - VHZ 0V
ALVC Quad Link
VIN D.U.T. RT
VOUT
500 CL
ALVC Quad Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Quad Link
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2
ALVC Quad Link
tSU
tH
tSU
tH
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
OUTPUT 1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
OUTPUT 2
VT
ALVC Quad Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Pulse Width
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX XXX XX ALVC Package Device Type Temp. Range
DC PY PG 32 74
Small Outline IC Shrink Small Outline Package Thin Shrink Small Outline Package Quadruple 2-Input Positive-OR Gate, 24mA - 40C to +85C
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for Tech Support: logichelp@idt.com (408) 654-6459
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