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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCD221TS/D
MCD221
Technical Summary
CD Interface and Audio Processor (CIAP)
This technical summary provides a brief description of the MCD221 CD-Interface and Audio Processor. A complete data sheet for the MCD221 is available and can be ordered from your local Motorola sales office. The order number is MCD221/D. The MCD221 has two main functions. The first is to form an interface between a CD drive unit and a CD-i or Photo-CD player. The connection to the drive is designed for both applications and can be either a Digital Out (EBU standard) interface, or an I2S plus subcode interface. The host interface can be either a 68000 interface for CD-i players, or a serial (SPI) interface for Photo-CD. The second function of the MCD221 is to decode ADPCM (CD-i base case) audio, to perform audio mixing functions as specified in the Green Book, and to be able to add external audio to the base case audio. The MCD221 can also be used for handling the ADPCM decoding for Photo-CD. The main features of the MCD221 are as follows: * Accepts Audio Inputs in I2S Format (MPEG1) for Mixing with CIAP Internal Audio * Output Can Be Either I2S or SONY Format * Data Input Rate Can Be Up to 2 Times Normal Speed * Can Connect to a Host via Either a 68K or Serial Interface * 80-Pin Quad Flat Pack (QFP)
FU SUFFIX QFP PACKAGE CASE 841B-01
ORDERING INFORMATION
MCD221FU QFP
NOTE: Supply of this Video-CD IC does not convey an implied license under any patent right to use this IC in any Video-CD application. CD-i is a registered trademark of Philips Consumer Electronics.
(c) Motorola, Inc. 1995 MOTOROLA
REV 0 2/95
MCD221 2-1
IIIIIIIIIIIIIIII IIII IIIIIII I IIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIII IIIII IIIIIII II I I I II I IIIIIIIIIIIIIIIIII II II I II IIIIIIIIIIIIIIIIII I I II I II IIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIII II II II I IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIII I II II I II I II IIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIII I II II I II II II I IIIIIIIIIIIIIIIIII II IIIIII IIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIII IIIII IIIIIII
SCLK MOSI MISO MODE_1 MODE_0 VDD VSS
MCD221 2-2
D13 D12 D11 D10 VSS VDD D9 D8 D7 D6 D5 D4 D3 D2 VSS VDD D1 D0 TESTMODE RESET
61
80
DAOUT CLOUT WSOUT XDAI XWSI XCLI SUBCODE/EBU EFI CLI WSI DAI VSS V DD
60
1
PIN ASSIGNMENT
41
20
21
40
A13 TDI TDO TMS TCK VDD VSS INT IACK REQ ACK RDY DONE VDD VSS CS ISEL NC SYSCLK2 SYS_CLK_OUT
MOTOROLA
A12 D14 D15 V DD V SS DTACK R/W A1 A2 A3 A4 A5 A6 A7 A8 A9 V DD V SS A10 A11
PIN DESCRIPTIONS
SIGNAL DESCRIPTIONS Host Interface
Mnemonic A[13 ... 1] D[15 ... 0] CS R/W DTACK Type O B I I B Name and Function System Address Bus. The address must be stable before CS is asserted. Active HIGH. System Data Bus. The data lines must be stable when CS is active during a write and before DTACK is asserted during a read. Tri-state. Chip Select. Used to access the CIAP internal registers and buffers. Active LOW. Read/Write. Indicates the direction of the data transfer. When LOW, the transfer is to the CIAP. Data Transfer Acknowledge. Active LOW. During normal host access, DTACK is an output indicating that data has been put on (read cycles) or read from (write cycles) the data bus. (Active pullup.) During DMA, DTACK is an input indicating that the memory has put data on the data bus. Interrupt. Released when the interrupt status register is read. Active LOW. Interrupt Acknowledge. Active LOW. DMA Request. Active LOW. Acknowledge. DMA handshake signal indicating that the bus is available for data transfer. Active LOW. Ready. DMA handshake signal indicating that the CIAP has completed the data transfer. Tri-state. Active LOW. When released by the CIAP, the output is forced high for a few nanoseconds before it is made tri-state. Done. Indicates the last transfer of a DMA burst. Active LOW.
INT IACK REQ ACK RDY
O I O I O
DONE
I
Serial Interface
Mnemonic SCLK MOSI MISO Type I I Serial Clock. Name and Function
Data Input
CLI
External Audio Interface
Mnemonic
MOTOROLA
I I IIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIII I II II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIII I I I IIIIIIII IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIII
Serial Data. Master out, slave in. Serial Data. Master in, slave out. Serial Interface MODE bits. 00 = Write selected register 01 = Read selected register 10 = Write address 11 = No action O I MODE_0, MODE_1 Mnemonic Type I I I I I Name and Function Serial Bit Clock Input. Word Clock Input. Serial Data Input. Error Flag Input. WSI DAI EFI SUBCODE/EBU Subcode (P ... W) serial data input or EBU input for both main channel and subchannel. Type I I I Name and Function XCLI External Audio Serial Bit Clock Input. When not used, the pin must be connected to VCC or VSS. External Audio Word Clock Input. When not used, the pin must be connected to VCC or VSS. XWSI XDAI External Audio Data Input. When not used, the pin must be connected to VCC or VSS.
MCD221 2-3
Audio Output Interface
General
MCD221 2-4
I I I II I I IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIII IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIII II
CLOUT O O O Audio Output Serial Clock. Audio Output Word Clock. Audio Output Serial Data. WSOUT DAOUT Mnemonic Type O I I I Name and Function SYS_CLK_OUT SYSCLK2 RESET ISEL 16.9344 MHz System Clock Output. Double System Clock Frequency Input. Input for an oscillator with a frequency of 33.8688 MHz. Reset. Global reset for the CIAP. Active LOW. Interface Select. 0 = Serial interface (no parallel access possible) 1 = 68000 interface (no serial access possible) Test Data Input. (Boundary scan input pin.) TDI I TDO TCK O I I Test Data Output. (Boundary scan output pin.) Test Clock. (Boundary scan input pin.) TMS Test Mode Select. (Boundary scan input pin.) TESTMODE O When 0, the CIAP is operational. When 1, the CIAP is in test mode.
Mnemonic
Type
Name and Function
MOTOROLA
FUNCTIONAL DESCRIPTION
DATA FLOW DIAGRAM
MCD221 CIAP
CD DATA IN
DATA INPUT (DI)
HOST INTERFACE (HI)
68xxx HOST INTERFACE
EXTERNAL AUDIO IN AUDIO OUT
AUDIO PROCESSOR (AP)
CONTROLLER (MC)
The MCD221 Data Flow Diagram should be used in conjunction with the following notes which outline the function of the various blocks within the device: * The data input module consists of two parts; a main channel decoder and a subchannel decoder. Both decoders can be active at the same time. The main channel decoder can be in different modes; CD-DA mode, CD-ROM mode, or CD-i mode.
* The audio processor module accepts an external audio input and, after processing, generates an audio output. * The microcode controller interface takes care of accepting commands and passing data to the different parts of the audio processing unit. * The host interface takes care of addressing the internal registers and buffers. The CIAP can interface with two possible hosts; a 68000 type host or a microcontroller that interfaces via a serial link.
MOTOROLA
MCD221 2-5
I I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIII
Address (HEX) 1BC2 1B8C 1B2C 25AA 24EE 1B2E 25FE 25C2 25C0 258C 08FE 25A8 25A6 25A4 25A2 25A0 259A 258E 258A 254E 24E6 24E4 1B24 1B22 11FE 24F0 2596 2594 2592 2590 2588 2586 2584 1200 0900 0000 A_SHDW AP_Right DMACTL Register AP_Left ACONF DLOAD AP_Vol ASTAT BMAN APCR ACM2 ACM1 TCM1 AACS TACS CCR FILE ICR ISR IER -- -- -- -- -- -- -- --
MCD221 2-6
Table 1. Registers and Buffers
REGISTER MEMORY MAP
Download register
DMA control register
Interrupt control register
Audio processor status register
Audio configuration register
Audio processor control register
Audio processor unit volume register
Audio processor unit right register
Audio processor unit left register
ADPCM shadow register
CIAP control register
Buffer management register
File selection register
Actual channel mask register 2
Actual channel mask register 1
Temporal channel mask register
Actual audio channel select register
Temporal audio channel select register
Interrupt status register
Interrupt enable register
R ... W buffer 1
Q-buffer 1
DATA buffer 1
R ... W buffer 0
Q-buffer 0
DATA buffer 0
ADPCM buffer 1
ADPCM buffer 0
Description
MOTOROLA
ELECTRICAL SPECIFICATIONS
OPERATING RANGE The limits for operating the device are as follows: Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . 0C to 70C Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V 10% Voltage, VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V ABSOLUTE MAXIMUM RATINGS* (Voltages Referenced to VSS, Unless Otherwise Noted)
Symbol VDD VI Parameter Min Max Unit V V V Supply Voltage Input Voltage - 0.5 - 1.5 - 0.5 -- -- + 7.0 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit.
II I III I I I II I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I I II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I II
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VDD + 1.5 VDD + 0.5 25 VO IO Output Voltage Output Current mA Pd Power Dissipation 1200 mW C Tstg Storage Temperature - 65 + 150 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. Parameter Symbol IDD VIH VIL Operating Supply Current Input Voltage (TTL Input) Output Voltage (8 mA) VOH VOL VOH VOL Output Voltage (16 mA) Power Dissipation
DC ELECTRICAL CHARACTERISTICS (VDD = 5 V 10%, VSS = 0 V, TA = 0 to + 70C, Unless Otherwise Noted)
Conditions Min -- Max tba Unit mA V
33.8688 MHz -- -- -- -- -- -- --
2.0 -- 3.5 -- 3.5 -- --
-- 0.8 -- 0.4 -- 0.4
V
V
tba
mW
MOTOROLA
MCD221 2-7
APPLICATION EXAMPLES
CIAP/CD-DRIVE ARCHITECTURE In conjunction with a suitable microcontroller, MC68HC05 (IKAT), the MCD221 provides the functionality to connect an MC68xxx host processor to a CD-Drive. The MCD221 decodes both main and subchannel CD data and plays both ADPCM and CDDA audio. External I2S format audio (e.g., MPEG1) may be input and mixed with the CIAP audio. CIAP audio output can be in either I2S or Sony formats.
68xxx HOST INTERFACE MC68HC05 (IKAT) BIDIRECTIONAL CONTROL INTERFACE
CD DRIVE
I2S MAIN CHANNEL DATA SUBCHANNEL DATA MCD221 CIAP (CD INTERFACE PLUS AUDIO PROCESSOR) I2S
EXTERNAL AUDIO SOURCE (e.g., MCD270 MPEG DECODER)
EXTERNAL AUDIO IN
AUDIO OUT
DAC
L R
MCD221 2-8
MOTOROLA
PACKAGE DIMENSIONS
FU SUFFIX CASE 841B-01
L
60 61 41 40 S S
D
D
B B
S
S
-AL
-BB
0.20 (0.008) M C A-B 0.05 (0.002) A-B
V
0.20 (0.008)
M
H A-B
P
-A,B,DDETAIL A
DETAIL A
80 1 20
21
F
-DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B 0.20 (0.008)
M S
D
S
S H A-B
J
S
N
D
S
E C -CSEATING PLANE
M DETAIL C
DATUM PLANE
D 0.20 (0.008)
M
C A-B
S
D
S
SECTION B-B
-HH M G
0.01 (0.004)
U
T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 14.10 13.90 14.10 13.90 2.45 2.15 0.38 0.22 2.40 2.00 0.33 0.22 0.65 BSC 0.25 -- 0.23 0.13 0.95 0.65 12.35 BSC 10 5 0.13 0.17 0.325 BSC 0 7 0.30 0.13 16.95 17.45 -- 0.13 0 -- 16.95 17.45 0.35 0.45 1.6 REF
INCHES MIN MAX 0.547 0.555 0.547 0.555 0.084 0.096 0.009 0.015 0.079 0.094 0.009 0.013 0.026 BSC 0.010 -- 0.005 0.009 0.026 0.037 0.486 BSC 10 5 0.005 0.007 0.013 BSC 0 7 0.005 0.012 0.667 0.687 0.005 -- 0 -- 0.667 0.687 0.014 0.018 0.06 REF
MOTOROLA
MCD221 2-9
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCD221 2-10
*MCD221TS/D*
MCD221TS/D MOTOROLA

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