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ML2003, ML2004
Logarithmic Gain/Attenuator
Features
Low noise: 0 dBrnc max with +24dB gain Low harmonic distortion: -60dB max Gain range: -24 to +24dB Resolution: 0.1dB steps Flat frequency response: 0.05dB from .3-4 kHz 0.10dB from .1-20 kHz * Low supply current 4mA max from 5V supplies * TTL/CMOS compatible digital interface * ML2003 has pin selectable serial or parallel interface; ML2004 serial interface only * * * * *
General Description
The ML2003 and ML2004 are digitally controlled logarithmic gain/attenuators with a range of -24 to +24 dB in 0.1 dB steps. The gain settings are selected by a 9-bit digital word. The ML2003 digital interface is either parallel or serial. The ML2004 is packaged in a 14-pin DIP with a serial interface only. Absolute gain accuracy is 0.05dB max over supply tolerance of 10% and temperature range. These CMOS logarithmic gain/attenuators are designed for a wide variety of applications in telecom, audio, sonar, or general purpose function generation. One specific intended application is analog telephone lines.
Block Diagram
VCC PDN A GND VSS GND
Pin Connections
ML2003 18-PIN DIP
C3 + FINE - + BUFFER - VOUT (LATI)C2 (SID)C1 (LATO)C0 PDN F3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 TOP VIEW ATTEN/GAIN VCC VOUT VSS A GND VIN NC F0 (SOD) SER/PAR C0 (LATO) NC PDN F3 F2 (SCK) 4 5 6 7 8 9 10 11 12 13 F1 GND SER/PAR
VIN
+ COURSE -
ML2003 20-Pin PCC
C1 (SID) C2 (LATI) C3 ATTEN/GAIN
RESISTORS/ SWITCHES 16
RESISTORS/ SWITCHES 16
(SCK)F2 F1 GND
3 2 1 20 19 18 17 16 15 14 VOUT VSS A GND NC NC
DECODER/MODE SELECTOR C0 C1 C2 C2 (LATI) C1 (SID) F0 F2 9
SER/PAR
ML2004 14-PIN DIP
C0 (LATO) F0 (SOD) LATI SID LATO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 TOP VIEW VCC VOUT VSS A GND VIN NC SOD
9-BIT LATCH & SHIFT REGISTER
TOP VIEW
ATTEN/ GAIN
C3
F1
F3
F2 (SCK)
PDN SCK
NOTE: SERIAL MODE FUNCTIONS INDICATED BY PARENTHESES.
NC GND
REV. 1.1.1 3/19/01
F0 (SOD) VIN
VCC
ML2003, ML2004
PRODUCT SPECIFICATION
Pin Description
Name C3 (LATI) C2 (SID) C1 (LATO) C0 PDN F3 (SCK) F2 Function In serial mode, pin is unused. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. In serial mode, input latch clock which loads the data from the shift register into the latch. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. In serial mode, serial data input that contains serial 9 bit data word which controls the gain setting. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. In serial mode, output latch clock which loads the 9 bit data word back into the shift register from the latch. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. Powerdown input. When PDN = 1, device is in powerdown mode. When PDN = 0, device is in normal operation. Pin has internal pulldown resistor to GND. In serial mode, pin is unused. In parallel mode, fine gain select bit. Pin has internal pulldown resistor to GND. In serial mode, shift register clock which shifts the serial data on SID into the shift register on rising edges and out on SOD on falling edges. In parallel mode, fine gain select bit. Pin has internal pulldown resistor to GND. In serial mode, pin is unused. In parallel mode, fine gain select bit. Pin has internal pulldown resistor to GND. Digital ground. 0 volts. All digital inputs and outputs are referenced to this ground. Serial or parallel select input. When SER/PAR = 1, device is in serial mode. When SER/PAR = 0, device is in parallel mode. Pin has internal pullup resistor to VCC. In serial mode, serial output data which is the output of the shift register. In parallel mode, fine gain select bit. Pin has internal pulldown resistor to GND. Analog input. Analog ground. 0 volts. Analog input and output are referenced to this ground. Negative supply. -5 volts 10%. Analog output. Positive supply. +5 volts 10%. In serial mode, pin is unused. In parallel mode, attenuation/gain select bit. Pin has internal pulldown resistor to GND.
F1 GND SER/PAR (SOD) F0 VIN AGND VSS VOUT VCC ATTEN/GAIN
Absolute Maximum Ratings1
Parameter Supply Voltage VCC VSS AGND with respect to GND Analog Input and Output Digital Input and Outputs Input Current Per Pin Power Dissipation Storage Temperature Range Lead Temeperature (Soldering, 10 sec) -65 VSS -0.3V GND -0.3 Min. Max. +6.5 -6.5 0.5 VCC +0.3 VCC +0.3 25 750 +150 300 Units V V V V V mA mW C C
2
REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2003, ML2004
Operating Conditions
Parameter Temperature ML2003CX, ML2004CX ML2003IX, ML2004IX Supply Voltage VCC VSS Range2 Min. 0 -40 4 -4 Max. 70 85 6 -6 Units C C V V
Electrical Characteristics
Unless otherwise specified TA = TMIN to TMAX, VCC = 5V 10%, VSS = -5V 10%, Data Word: ATTEN/GAIN = 1, Other Bits = 0(0dB Ideal Gain), CL = 100pF, RL = 600, SCK = LATI = LATO = 0, dBm measurements use 600 as reference load, digital timing measured at 1.4 V, CL = 100pF or SOD. Symbol Analog AG RG Absolute gain accuracy Relative gain accuracy 4 4 VIN=8dBm, 1 kHz 100000001 000000000 000000001 All other gain settings All values referenced to 100000000 gain when ATTEN/GAIN = 1, VIN =8dBm when ATTEN//GAIN =0 VIN =(8dBm - Ideal Gain) in dB 300-4000 Hz 100-20,000 Hz Relative to 1 kHz VIN = 0, +24dB gain VIN = 0, +24dB gain, C msg. Weighted VIN = 0, +24dB gain, 1kHz VIN = 8dBm gain, 1kHz Measure 2nd, 3rd harmonic relative to fundamental VIN = 8dBm, 1 kHz C msg. weighted 200mVp-p, 1 kHz sine, VIN = 0 on VCC on VSS 1 3.0 3.0 0.8 2.0 IOL = 2mA 0.4 +60 -6 450 -0.05 -0.05 -0.05 -0.05 -0.1 +0.05 +0.05 +0.05 +0.05 +0.1 dB dB dB dB dB Parameter Notes Conditions Min. Typ.3 Max. Units
FR
Frequency response
4
-0.05 -0.1
+0.05 +0.1 100
dB dB mV
VOS ICN HD SD PSRR
Output Offset Voltage Idle Channel Noise Harmonic Distortion Signal to Distortion Power Supply Rejection Input impedance, VIN Input Voltage Range Output Voltage Swing Digital Input Low Voltage Digital Input High Voltage Digital Output Low Voltage
4 4 5 4 4 4
0 dBrnc 900 nv/Hz -60 dB dB
-60 -60
-40 -40
dB dB Meg V V V V V
ZIN VINR VOSW VIL VIH VOL
4 4 4 4 4 4
Digital and DC
REV. 1.1.1 3/19/01
3
ML2003, ML2004
PRODUCT SPECIFICATION
Electrical Characteristics (continued) Unless otherwise specified TA = TMIN to TMAX, VCC = 5V 10%, VSS = -5V 10%, Data Word: ATTEN/GAIN = 1, Other Bits = 0(0dB Ideal Gain), CL = 100pF, RL = 600, SCK = LATI = LATO = 0, dBm measurements use 600 as reference load, digital timing measured at 1.4 V, CL = 100pF or SOD.
Symbol VOH INS IND Parameter Digital Output High Voltage Input Current, SER/ PAR Input Current, All Digital Inputs Except SER/PER VCC Supply Current VSS Supply Current VCC Supply Current, Powerdown Mode VSS Supply Current Powerdown Mode VOUT Settling Time Notes 4 4 4 IOH = -1mA VIH = GND VIH = VCC Conditions Min. Typ.3 Max. 4.0 -5 5 -100 100 Units V A A
ICC ISS ICCP ISSP
4 4 4 4
No output load, VIL = GND, VIH = VCC, VIN = 0 No output load, VIL = GND, VIH = VCC, VIN = 0 No output load, VIL = GND, VIH = VCC No output load, VIL = GND, VIH = VCC VIN = 0.185V. Change gain from -24 to +24dB. Measure from LATI rising edge to when VOUT settles to within 0.05dB of final value. Gain = +24dB. VIN = -0.185 to +0.185V step. Measure when VOUT settles to within 0.05dB of final value. 250 50 50 0 50 50 50 50 0
4 -4 0.5 -0.1
mA mA mA mA
AC Characteristics tSET 4 20 s
tSTEP
VOUT Step Response
4
20
s
tSCK tS tH tD tIPW tOPW
SCK On/Off Period SID Data Setup Time SID Data Hold Time SOD Data Delay LATI Pulse Width LATO Pulse Width
4 4 4 4 4 4 4 5 4
ns ns ns 125 ns ns ns ns ns 125 ns
tIS, tOS LATI, LATO Setup Time tIH, tOH tPLD LATI, LATO Hold Time SOD Parallel Load Delay
Notes: 1. Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. 2. 0C to +70C and -40C to +85C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-case test conditions. 3. Typicals are parametric norm at 25C. 4. Parameter guaranteed and 100% production tested. 5. Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
4
REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2003, ML2004
Timing Diagram
tSCK SCK tS SID tD SOD tH tSCK
SCK tIS LATI tIPW LATO tPLD SOD tOPW tIH tOS tOH
TIMING PARAMETERS ARE REFERENCED TO THE 1.4 VOLT MIDPOINT.
Figure 1. Serial Mode Timing Diagram
Typical Performance Curves
0 -0.5 -0.10 GAIN = +24dB AMPLITUDE (dB) GAIN = +18dB -0.20 GAIN = +12dB -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 100 1K 10K FREQUENCY (Hz) 100K GAIN = +0, -24dB AMPLITUDE (dB) -0.15 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 100 1K 10K FREQUENCY (Hz) 100K GAIN = 0dB GAIN = -24dB ATTEN: VIN = 0.5VRMS GAIN: VIN = 0.5VRMS/GAIN SETTING 0 -0.5 -0.10 ATTEN: VIN = 2VRMS GAIN: VIN = 2VRMS/GAIN SETTING GAIN = +24dB
Figure 2. Amplitude vs Frequency (VIN/VOUT = .5VRMS)
Figure 3. Amplitude vs Frequency (VIN/VOUT = 2VRMS)
REV. 1.1.1 3/19/01
5
ML2003, ML2004
PRODUCT SPECIFICATION
Typical Performance Curves (continued)
2.0 1.8 OUTPUT NOISE VOLTAGE (V/Hz) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 10 100 1K FREQUENCY (Hz) 10K GAIN = +24dB GAIN = +12dB GAIN = -24dB CMSG OUTPUT (NOISE) (dBmc) -2 -3 -4 -5 -6 -7 -8 -9 -10 -24 VIN = 6
-18
-12
-6 -0 6 GAIN SETTING (dB)
12
18
24
Figure 4. Output Noise Voltage vs Frequency
Figure 5. CMSG Output Noise vs Gain Settings
100 90 80
ATTEN: VIN = 8dBm GAIN: VIN = 8dBm/GAIN SETTING 1KHz GAIN ERROR (dB) -18 -12 -6 -0 6 GAIN SETTING (dB) 12 18 24
0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08
CMSG S/N (dB)
70 60
50 40 -24
-1.0 -24
-18
-12
-6 -0 6 GAIN SETTING (dB)
12
18
24
Figure 6. CMSG S/N vs Gain Setting
Figure 7. Gain Error vs Gain Setting
80 VIN = 1kHz 70
80 VIN = 1kHz VIN = 20kHz S/N + D (dB) 60 VIN = 50kHz
70 60 S/N + D (dB) 50 40 30 20 10 -24 VIN = 50kHz ATTEN: VIN = 2VRMS GAIN: VIN = 2VRMS/GAIN SETTING -18 -12 -6 0 6 GAIN SETTING (dB) 12 18 24 30 VIN = 20kHz
50 40
ATTEN: VIN = 0.5VRMS GAIN: VIN = 0.5VRMS/GAIN SETTING 20 -24 -18 -12 -6 0 6 GAIN SETTING (dB)
12
18
24
Figure 8. S/N + D vs Gain Setting (VIN/VOUT = 2VRMS)
Figure 9. S/N + D vs Gain Setting (VIN/VOUT = 0.5VRMS)
6
REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2003, ML2004
Functional Description
The ML2003 consists of a coarse gain stage, a fine gain stage, an output buffer, and a serial/parallel digital interface.
Powerdown Mode
A powerdown mode can be selected with pin PDN. When PDN = 1, the device is powered down. In this state, the power consumption is reduced by removing power from the analog section and forcing the analog output,VOUT, to a high impedance state. While the device is in powerdown mode, the digital section is still functional and the current data word remains stored in the latch when in serial mode. When PDN = 0, the device is in normal operation.
Gain Stages
The analog input, VIN, goes directly into the op amp input in the coarse gain stage. The coarse gain stage has a gain range of 0 to 22.5dB in 1.5dB steps. The fine gain stage is cascaded onto the coarse section. The fine gain stage has a gain range of 0 to 1.5dB in 0.1dB steps. In addition, both sections can be programmed for either gain or attenuation, thus doubling the effective gain range. The logarithmic steps in each gain stage are generated by placing the input signal across a resistor string of 16 series resistors. Analog switches allow the voltage to be tapped from the resistor string at 16 points. The resistors are sized such that each output voltage is at the proper logarithimic ratio relative to the input signal at the top of the string. Attenuation is implemented by using the resistor string as a simple voltage divider, and gain is implemented by using the resistor string as a feedback resistor around an internal op amp.
Digital Section
The ML2003 can be operated with a serial or parallel interface. The SER/PAR pin selects the desired interface. When SER/PAR = 1, the serial mode is selected. When SER/PAR = 0, the parallel mode is selected. The ML2004 digital interface is serial only.
Serial Mode
Serial mode is selected by setting SER/PAR pin high. The serial interface allows the gain settings to be set from a serial data word. The timing for the serial mode is shown in Figure 10. The serial input data, SID, is loaded into a shift register on rising edges of the shift clock, SCK. The data can be parallel loaded into a latch when the input latch signal, LATI, is high. The LATI pulse must occur when SCK is low. In this way, a new data word can be loaded into the shift register without disturbing the existing data word in the latch. The parallel outputs of the latch control the attenuation/gain setting. The order of the data word bits in the latch is shown in Figure 11. Note that bit 0 is the first bit of the data word clocked into the shift register. Tables 1 and 2 describe how the data word programs the gain.
Table 1. Fine Gain Settings (C3-C0 = 0)
Gain Settings
Since the coarse and fine gain stages are cascaded, their gains can be summed logarithmically. Thus, any gain from -24dB to +24dB in 0.1dB steps can be obtained by combining the coarse and fine gain settings to yield the desired gain setting. The relationship between the digital select bits and the corresponding analog gain values is shown in Tables 1 and 2. Note that C3-C0 selects the coarse gain, F3-F0 selects the fine gain, and ATTEN/GAIN selects either attenuation or gain.
Output Buffer
The final analog stage is the output buffer. This amplifier has internal gain of 1 and is designed to drive 600 ohms and 100pF loads. Thus, it is suitable for driving a telephone hybrid circuit directly without any external amplifier.
Ideal Gain (dB) F3 F2 F1 F0 ATTEN/GAIN = 1 ATTEN/GAIN = 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -.1 -.2 -.3 -.4 -.5 -.6 -.7 -.8 -.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 1.1 1.2 1.3 1.4 1.5
Power Supplies
The digital section is powered between VCC and GND, or 5 volts. The analog section is powered between VCC and VSS and uses AGND as the reference point, or 5 volts. GND and AGND are totally isolated inside the device to minimize coupling from the digital section into the analog section. However, AGND and GND should be tied together physically near the device and ideally close to the common power supply ground connection. Typically, the power supply rejection of VCC and VSS to the analog output is greater than -60dB at 1 kHz. If decoupling of the power supplies is still necessary in a system, VCC and VSS should be decoupled with respect to AGND.
REV. 1.1.1 3/19/01
7
ML2003, ML2004
PRODUCT SPECIFICATION
Table 2. Coarse Gain Settings (F3-F0 = 0)
Ideal Gain (dB) C3 C2 C1 C0 ATTEN/GAIN = 1 ATTEN/GAIN = 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 18.0 19.5 21.0 22.5
The loading and reading of the data word can be done continuously or in burst. Since the shift register and latch circuitry inside the device is static, there are no minimum frequency requirements on the clocks or data pulses. However, there is coupling (typically less than 100V) of the digital signals into the analog section. This coupling can be minimized by clocking the data bursts in during noncritical intervals or at a frequency outside the analog frequency range.
Parallel Mode
The parallel mode is selected by setting SER/PAR pin low. The parallel interface allows the gain settings to be set with external switches or from a parallel microprocessor interface. In parallel mode, the shift register and latch are bypassed and connections are made directly to the gain select bits with external pins ATTEN/GAIN, C3-C0, and F3-F0. Tables 1 and 2 describe how these pins program the gain. The pins ATTEN/GAIN, C3-C0, and F3-F0 have internal pulldown resistors to GND. The typical value of these pulldown resistors is 100k.
The device also has the capability to read out the data word stored in the latch. This can be done by parallel loading the data from the latch back into the shift register when the latch signal, LATO, is high. The LATO pulse must occur when SCK is low. Then, the data word can be shifted out of the shift register serially to the output, SOD, on falling edges of the shift clock, SCK.
SCK
0
1
2
3
4
5
6
7
8
SID
F0
F1
F2
F3
C0
C1
C2
C3
ATT/ GAIN
LATI
LATO
SOD
a) LOAD
SCK
0
1
2
3
4
5
6
7
8
SID
LATI
LATO
SOD
F0
F1
F2
F3
C0
C1
C2
C3
ATT/ GAIN
b) READ
Figure 10. Serial Mode Timing
8
REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2003, ML2004
ATTEN/GAIN 8 MSB
C3 7
C2 6
C1 5
C0 4
F3 3
F2 2
F1 1
F0 0 LSB
FUNCTION BIT NUMBER
Figure 11. 9-Bit Latch
Applications
ML2004 LOG GAIN/ATTEN ML2021 EQUALIZER
ML2003
VIN
VOUT
VIN
VOUT
VIN
VOUT ATTEN/GAIN C3-C0 F3-F1
SCK
SCK
LATI
LATI
SID
SID
8-BIT LATCH P
P
Figure 12. Typical Serial Interface
ML2004 ML2004
Figure 13. Typical P Parallel Interface
ML2004
VIN SCK LATI SID
VOUT SOD
VIN SCK LATI SID
VOUT SOD
VIN SCK LATI SID
VOUT SOD
P
Figure 14. Controlling Multiple ML2004 with Only 3 Digital Lines Using One Long Data Word
ML2003
VIN
VOUT ATTEN/GAIN C3-C0 F3-F1
VIN A/D
VIN
P OR DSP
8-BIT LATCH
Figure 15. AGC for DSP or Modem Front End
REV. 1.1.1 3/19/01
9
ML2003, ML2004
PRODUCT SPECIFICATION
ML2003
ML2003
VIN
VOUT ATTEN/GAIN C3-C0 F3-F1
VIN
VOUT ATTEN/GAIN C3-C0 F3-F1 +5 -
UP/DOWN 8-BIT CTR
U/D
UP/DOWN 8-BIT COUNTER
U/D
COMPARATOR
+5 R2
+ CLOCK R1
CLOCK
R3
DOWN UP
R1, R2, R3 SETS AGC THRESHOLD AND HYSTERESIS
FROM P OR SWITCHES
Figure 16. Analog AGC
Figure 17. Digitally Controlled Volume Control
ML2003 VPEAK VREF VIN VOUT ATTEN/GAIN C3-C0 F3-F1 VOUT
- UP/DOWN 8-BIT COUNTER U/D
COMPARATOR
VPEAK VIN
+
CLK1
CLK2
fCLK1 DETERMINES PEAK ACQUIRE TIME fCLK2 DETERMINES PEAK HOLD TIME
Figure 18. Precision Peak Detector (1%) with Controllable Acquire and Hold Time
10
REV. 1.1.1 3/19/01
ML2003, ML2004
PRODUCT SPECIFICATION
Ordering Information
Part Number ML2003IQ ML2003CP ML2003CQ ML2004IP ML2004CP Temperature Range -40C to 85C 0C to 70C 0C to 70C -40C to 85C 0C to 70C Package Molded PCC (Q20) Molded DIP (P18) Molded PCC (Q20) Molded DIP (P14) Molded DIP (P14)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 3/19/01 0.0m 003 Stock#DS300042003 2001 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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