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| PACSZ1284 IEEE 1284 Parallel Port ESD/EMI/Termination Network Features * * * * * 17 EMI filters 17 ESD protectors yielding protection to 30kV contact discharge, per IEC 61000-4-2 specification 17 terminators with choice of resistor values 28-pin QSOP package Lead-free version available Product Description The PACSZ1284 combines EMI filtering, ESD protection, and signal termination in a single QSOP package for parallel port interfaces complying to the IEEE 1284 standard. The PACSZ1284 provides a complete parallel port termination solution. It integrates the equivalent of 60 discrete components, making it ideal for space critical applications. The pins of the device which connect to the parallel port are protected to 30kV contact discharge, well beyond Level 4 of the IEC 61000-4-2 specification. All other pins are ESD-protected for contact discharges up to 8kV per IEC 61000-4-2. There are three available values for pull-up resistor R1. For the PACSZ1284-01, R1 = 1k; for the PACSZ128402, R1 = 2.2k; for the PACSZ1284-04, R1 = 4.7k . P/Active(R) technology provides high reliability and low cost through manufacturing efficiency. the PACSZ1284 is silicon-based and has the same reliability characteristics as today's integrated circuits. Applications * Parallel Ports of PCs, printers, peripherals, and Set-Top Boxes Electrical Schematic PACSZ1284-01 R1 = 1k R2 = 33 C = 150pF PACSZ1284-02 R1 = 2.2k R2 = 33 C = 150pF PACSZ1284-04 R1 = 4.7k R2 = 33 C = 150pF 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R1 R1 R1 R1 R1 R2 R1 R2 R1 R2 R1 R2 R1 R2 R1 R1 R2 R1 R1 R2 R1 R1 R2 R1 R2 R1 C C C C C C C C C C C C C C C C C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (c) 2003 California Micro Devices Corp. All rights reserved. 09/15/03 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 1 PACSZ1284 PACKAGE / PINOUT DIAGRAM CAP-FILTERED CAP-FILTERED SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED CAP-FILTERED SUPERCHIP SIDE SERIES-TERMINATED CAP-FILTERED SUPERCHIP SIDE SERIES-TERMINATED CAP-FILTERED SUPERCHIP SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CAP-FILTERED CAP-FILTERED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED GND CONNECTOR SIDE SERIES-TERMINATED VCC CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CAP-FILTERED Note: This drawing is not to scale. 28-pin QSOP PIN DESCRIPTIONS LEADS 1,2,8,10, 12,15, 27,28 3-7, 9,11, 13,14 16-19, 21, 23-26 20 22 NAME Capacitor-filtered Super I/O Chip side series-terminated Parallel Port connector side series-terminated VCC GND DESCRIPTION IEEE 1284 signals which require no series termination. IEEE 1284 signals on the Super I/O Chip side which require series termination. IEEE 1284 signals on the Parallel Port Connector side which require series termination. Supply rail for the device Ground reference for the device Ordering Information STANDARD VALUES RC Code 01 02 04 R1 () 1.0k 2.2k 4.7k R2 () 33 33 33 C (pF) 150 150 150 PART NUMBERING INFORMATION Standard Finish RC Code 01 02 04 Ordering Part Pins 28 28 28 Package QSOP QSOP QSOP Number1 PACSZ128401Q PACSZ128402Q PACSZ128404Q Part Marking PACSZ128401Q PACSZ128402Q PACSZ128404Q Lead-free Finish Ordering Part Number1 PACSZ128401QR PACSZ128402QR PACSZ128404QR Part Marking PACSZ128401QR PACSZ128402QR PACSZ128404QR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. (c) 2003 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 09/15/03 PACSZ1284 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER VCC Voltage Input Voltage Range, no clamping Storage Temperature Range Power Dissipation per Resistor Package Power Dissipation RATING 5.5 -0.4 to 5.5 -40 to +150 0.1 1.0 UNITS V V C W W STANDARD OPERATING CONDITIONS PARAMETER VCC Voltage Operating Temperature RATING 5.0 -40 to +85 UNITS V C ELECTRICAL OPERATING CHARACTERISTICS SYMBOL TOLR TOLC ILEAK VESDi PARAMETER Absolute Resistance Tolerance Absolute Capacitance Tolerance Leakage current to GND ESD protection, input pins CONDITIONS Measured at TA=25C Measured at 1MHz, 2.5VDC, TA=25C Measured at 5.0VDC, TA=25C Pins 3,4,5,6,7,9,11,13, & 14, per IEC 61000-4-2 specification, Notes 1,2,3 Pins 1,2,8,10,12,15,16,17,18,19, 21,23,24,25,26,27, & 28, per IEC 61000-4-2 specification Notes 1,2,4 ESD applied to connector pin, measured at corresponding input pin; +8kV discharge, Human Body Model Notes 1,2 ESD applied to connector pin, measured at corresponding input pin; -8kV discharge, Human Body Model; Notes 1,2 Note 1: Note 2: Note 3: Note 4: Guaranteed by design and characterization. ESD voltage applied between Input/Connector pins and ground, one pin at a time. Pins 3-7, 9, 11, 13, and 14 typically connect to the I/O pins of a Super I/O chip. Pins 1, 2, 8, 10, 12, 15-19, 21, and 23-28 typically connect to the Parallel Port connector. MIN TYP MAX +20 +20 UNITS % % A kV 1 +8 10 VESD ESD protection, connector pins +30 kV VCLAMP Clamping voltage under ESD discharge 8.3 V -2.7 V (c) 2003 California Micro Devices Corp. All rights reserved. 09/15/03 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 3 PACSZ1284 Performance Information Filter Capacitors The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 lines. Basic filtering is provided through the presence of a capacitor on all signal lines. The filter capacitor is the junction capacitance of an ESD diode. The typical capacitance at a reverse voltage of 2.5V is 150pF. This diode capacitance is somewhat voltage dependent. See Figure 1. Filter Insertion Loss Figure 2 shows the typical Insertion Loss graphs of the PACSZ1284 for Data and Strobe signals. The curves are dependent on the physical location of the filter elements with respect to the ground terminal of this device. These graphs are measured in a 50 environment on a Hewlett Packard HP 8753C Analyzer. The signal source is introduced at the resistor input and the output is measured at the corresponding protection diode. The actual pins measured are labeled in the Figure 2 graph. Figure 1. Diode Capacitance vs. Reverse Voltage The higher speed Data and Strobe lines (9 in total) require an additional series resistor termination for proper operation, while the eight (8) Status lines do not. See Table 1 on page 5. Frequency (MHz) Figure 2. Typical Filter Insertion Loss (c) 2003 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 09/15/03 PACSZ1284 Application Information Termination Considerations The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 signal lines. Control and Status lines (8 in total) only require a pull-up resistor and a filter capacitor. The Data lines and Strobe also require a series termination resistor in addition to the pull-up resistors and filter capacitors. See Table 1, in conjunction with the schematic diagram on page 1. Table 1: IEEE 1284 Termination Requirements Interfacing to IEEE 1284 Connectors IEEE 1284 defines three interface connectors: * 1284 A is a 25-pin DB series connector which is the de facto PC standard for the host connection. * 1284 B is a 36-pin, 0.085 inch centerline connector used on the peripheral device. * 1284 C is a new 36-pin, 0.050 inch centerline connector which can be used for both host and peripheral. Figure 3A shows a possible hook-up between the 1284-A connector on a PC motherboard and the PACSZ1284, illustrating how the pin configuration of the PACSZ1284 allows for easy interconnect between the two. The dotted I/O signals of the PACSZ1284 will typically be connected to a Super I/O chip on the motherboard. Figure 3B shows a possible hook-up between the 1284-B connector on a peripheral and the PACSZ1284. Figure 3C shows a possible hook-up between the 1284-C connector and the PACSZ1284. SIGNAL TERMINATION REQUIREMENTS Signal Name Data1 - Data8 Strobe Init AutoFeedXT Selectin ACK Busy Paper Empty Select Fault Series Termination Yes Yes Not Required Not Required Not Required Not Required Not Required Not Required Not Required Not Required Figure 3A: 1284-A Connector Host 14 25 19 13 Figure 3B: 1284-B Connector Peripheral 36 19 20 2 1 18 1 Figure 3C: 1284-C Connector Host/Peripheral 36 18 1 PACSZ1284 SUPER 1284 1 PACSZ1284 SUPER 1284 = GND = VCC = FLOW THROUGH SIGNALS 1 = GND = VCC PACSZ1284 SUPER 1284 1 Figure 3. Example Connections of IEEE 1284 Connectors with PACSZ1284 (c) 2003 California Micro Devices Corp. All rights reserved. 09/15/03 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 5 PACSZ1284 Application Information (continued) Table 2 provides the IEEE 1284 signal assignments for the three connectors, and example PACSZ1284 pin connections. When connecting a 1284-A host to a 1284-B peripheral, the "Peripheral Logic High" signal is not used. Similarly, when a 1284-A host is connected to a 1284C peripheral, the "Peripheral Logic High" and "Host Logic High" are not used. These two signals are optionally used to detect a "Power Off" or "Cable Disconnect" state for host and peripheral, respectively. Table 2: IEEE 1284 Connector Pinouts and PACSZ1284 Connection Guidelines PACSZ1284 PIN TYPE P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn. side, series-terminated (16-19, 21, or 23-26) Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) 1284-A 25-PIN DSUB SIGNAL STROBE Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 ACK BUSY PError Select AUTOFD FAULT INIT Selectin Ground Ground Ground Ground Ground Ground Ground Ground PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1284-B 36-PIN CHAMP SIGNAL STROBE Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 ACK BUSY PError Select AUTOFD FAULT INIT Selectin Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Not Defined Not Defined Not Defined Not Defined Logic Ground Chassis GND Peripheral Logic PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 31 36 19 20 21 22 23 24 25 26 27 28 29 30 33 34 35 15 16 17 18 1284-C 36-PIN HIGH DENSITY SIGNAL STROBE Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 ACK BUSY PError Select AUTOFD FAULT INIT Selectin Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Not Required Host Logic High PIN 15 6 7 8 9 10 11 12 13 3 1 5 2 17 4 14 16 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 18 (c) 2003 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 09/15/03 PACSZ1284 Mechanical Details QSOP Mechanical Specifications: PACSZ1284 devices are packaged in 28-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-28 package, see the California Micro Devices QSOP Package Information document. 28 27 26 Mechanical Package Diagrams TOP VIEW D 25 24 23 22 21 20 19 18 17 16 15 PACKAGE DIMENSIONS Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.20 0.18 9.80 3.81 5.79 0.40 Max 1.75 0.25 0.30 0.25 9.98 3.98 6.20 1.27 Min 0.053 0.004 0.008 0.007 0.386 0.150 0.228 0.016 QSOP (JEDEC name is SSOP) 28 Inches Max 0.069 0.010 0.012 0.010 0.393 0.157 0.244 0.050 END VIEW SEATING PLANE SIDE VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 H Pin 1 Marking E A A1 B e 0.64 BSC 0.025 BSC 50 pieces* 2500 pieces Controlling Dimensions: inches C L * This is an approximate amount which may vary. Package Dimensions for QSOP-28 (c) 2003 California Micro Devices Corp. All rights reserved. 09/15/03 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 7 |
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