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| Ordering number : EN*4434 CMOS IC LC58E76 On-Chip EPROM Microcomputer 4-Bit Single Chip Microprocessor with LCD Driver, 12 Kbytes of EPROM and 1 Kbit of RAM On-Chip Overview The LC58E76 is an on-chip EPROM microcontroller in the LC587X series of CMOS 4-bit single chip microcontrollers. The LC58E76 provides the same functionality as the LC5876 mask ROM version, and has the same pin layout. The LC58E76 has a 16-kbyte EPROM capacity, and corresponds to the LC5872, LC5873, LC58E74 and LC5876. The LC58E76 is provided in an 80-pin ceramic window package, and programs can be written and erased repeatedly. Thus it is optimal for use during program development. Applications The LC58E76 can be used for program and function evaluation in the following applications. * System control of consumer products that use LCD displays, such as cameras, CD players and tuners * Remote controllers for products such as VCRs or tuners * System control of instruments that use LCD displays, such as miniature test equipment and medical equipment. * The LC58E76 is optimal for products that use LCD displays, in particular, battery operated products. functional and operational testing in the actual PC board used in the mass-produced end product. * On-chip 16 kbyte program EPROM The on-chip 16 kbyte program EPROM allows the LC58E76 to be used to evaluate all four members of the LC587X series. (See the series structure table on the next page.) * Program and option data read/write The program and option data can be read and written with a standard commercial EPROM writer by using a dedicated EPROM writing board. (256K equivalent) (Either a Sanyo or an Advanced EPROM writer should be used.) * Pin correspondence The LC58E76 is pin compatible with the mask ROM versions. (There is no chip correspondence.) Package Dimensions unit: mm 3152A-QFC80 [LC58E76] Features * Optional functions can be switched by EPROM data settings. The LC58E76 includes both program and option selection EPROM on-chip. The option selection EPROM can be used to specify almost all of the LC587X options, including crystal/ceramic oscillator specifications, port hold transistor selection and segment PLA specifications. These option specifications allow SANYO: QFC80 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O3098HA (OT)/42194TH (OT) No. 4434-1/17 LC58E76 Series Structure Type No. Item ROM capacity RAM capacity Package LC5872 2 k x 16 bits 256 x 4 bits QIP80 LC5873 3 k x 16 bits 256 x 4 bits QIP80 LC5874 4 k x 16 bits 256x 4 bits QIP80 LC5876 6 k x 16 bits 256 x 4 bits QIP80 LC58E76 EPROM: 16 kbytes 256 x 4 bits QFC80 ceramic window package The on-chip EPROM window version will be available shortly. Notes Available in quantity Available in quantity Available in quantity Available in quantity Usage Notes The LC58E76 is designed for use in developing and evaluating programs for the microprocessors in the LC587X series. However, there are differences between the LC58E76 and the mask ROM versions. Keep the following points in mind when using the LC58E76. 1. Notes on Reset When the RES pin input changes from high to low, the reset state is cleared after the prescribed oscillator stabilization period has elapsed. The options and the segment PLA are set up during the first 256 cycles following the clearing of the reset state. Instructions are executed starting at location 0 after this setup phase has completed. (The options are undefined and the segment outputs are held at the VSS level when the RES pin is high and during the first 256 cycles following the clearing of the reset state.) 2. Cover the LC58E76's window with an opaque seal when writing data to EPROM. 3. The LC58E76 and the mask ROM versions differ in the following points. Item Operating temperature Operating supply voltage 10 to 40C 2.8 to 5.5 V 5 A typ. (3 V, 32 kHz crystal) 20 A typ. (5 V, 32 kHz crystal) 400 A typ. (5 V, 400 kHz ceramic) 500 A typ. (5 V, 2 MHz ceramic) 700 A typ. (5 V, 4 MHz ceramic) Segment pins: VSS level (CMOS output) Common pins: N-channel open drain Off state LC58E76 Mask ROM versions (LC587X) -30 to 70C 2.0 to 6.0 V 4 A typ. (3 V, 32 kHz crystal) 15 A typ. (5 V, 32 kHz crystal) 400 A typ. (5 V, 400 kHz ceramic) 500 A typ. (5 V, 2 MHz ceramic) 700 A typ. (5 V, 4 MHz ceramic) Static operation (LCD drive output) Off state/lit state CF/Xtal/CF + Xtal RC/RC+Xtal/EXT/EXT+Xtal 32K/38K/65K Open (reset on high) Open (reset on low) Pull-up (reset on low) Pull-down (reset on high) Open drain output/CMOS output Static 1/2 bias, 1/2 duty 1/2 bias, 1/3 duty 1/2 bias, 1/4 duty 1/3 bias, 1/3 duty 1/3 bias, 1/4 duty (Substitute static when the LCD driver is not used.) 00 - 1E However, 0E and 0F cannot be used with the 4 MHz specifications. Note Operating supply currents Hold mode Common segment output states at reset Segment output states after the reset state is cleared Oscillator circuit specifications Crystal oscillator circuit CF/Xtal/CF + Xtal 32K/38K/65K (Note that this is 65K in the reset state) * Option switching in the EPROM version is performed by writing data to the option EPROM. * Option switching in mask ROM versions is performed by specifying mask options. RES pin specifications Open (reset on high) N ports Open drain output Static 1/2 bias, 1/2 duty 1/2 bias, 1/3 duty 1/2 bias, 1/4 duty 1/3 bias, 1/3 duty 1/3 bias, 1/4 duty (Substitute static when the LCD driver is not used.) 00 - 1E However, 0E and 0F cannot be used with the 4 MHz specifications. LCD drive specifications Number of specifiable strobes Note: Although the strobes number 00 to 1E can be used with CF 2 MHz and lower specifications, strobes number 0E, 0F and 1E cannot be used with the CF 4 MHz specifications. No. 4434-2/17 LC58E76 Pin Assignments PIn No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol COM2 COM1 CUP1 CUP2 RES INT SO1 SO2 SO3 SO4 A1 A2 A3 A4 P1 P2 P3 P4 XTOUT XTIN PIn No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol VDD2 VDD1 VSS VDD CFIN CFOUT S1 S2 Input ports S3 S4 K1 K2 I/O ports K3 K4 M1 M2 I/O ports M3 M4 N1 Output ports N2 PIn No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol N3 Output ports N4 TST Seg1 Seg2 Seg3 Seg4 Seg5 Seg6 Seg7 Seg8 Seg9 Seg10 Seg11 Seg12 Seg13 Seg14 Seg15 Seg16 Seg17 PIn No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Seg18 Seg19 Seg20 Seg21 Seg22 Seg23 Seg24 Seg25 Seg26 Seg27 Seg28 Seg29 Seg30 Seg31 Seg32 Seg33 Seg34 Seg35 COM4 COM3 Symbol I/O, serial I/O ports I/O ports I/O ports Note: 1. The TST pin must be connected to VSS in normal operation. 2. When mounting the LC58E76, do not use solder dip techniques. System Block Diagram LC58E76 System Block Diagram RAM ROM DP BNK APG AC ALU : Data memory : Program memory : Data pointer register : Bank register : RAM page flag : Accumulator : Arithmetic and logic unit B OPG PC IR STS1 STS2 STS3 : B register : ROM page flag : Program counter : Instruction register : Status register 1 : Status register 2 : Status register 3 : Status register 4 : Status register 5 : Program logic for segment data and strobes WAIT.C : Wait time counter STS4 STS5 PLA No. 4434-3/17 LC58E76 Pin Functions Pin VDD VSS I/O -- -- QFC-80 Pin No. 24 23 Power supply LCD drive power supply NON VDD1 VDD2 -- -- 22 21 VDD VDD1 VDD2 VSS Switching pin used to supply the LCD drive voltage to the VDD1 and VDD2 pins * Connect a nonpolar capacitor between CUP1 and CUP2 when 1/2 or 1/3 bias is used. * Leave open when a bias other than 1/2 or 1/3 is used. System clock oscillator connections * Ceramic resonator connection (CF specifications) * RC component connection (RC specifications) * External signal input pin (CFOUT is left open) This oscillator is stopped by the execution of a STOP or SLOW instruction. Reference calculation (clock specifications, LCD alternation frequency), system clock oscillator * 32 kHz crystal resonator connection * 65 kHz crystal resonator connection This oscillator is stopped by the execution of a STOP instruction. Input-only ports * Input pins used to read data into RAM * Built-in 7.8 ms and 1.95 ms chatter exclusion circuits * Built-in pull-up/pull-down resistors Note: The 7.8 ms and 1.95 ms times are the times when o0 is 32.768 kHz. 1/1 bias 1/2 bias 1/3 bias Function Option At reset CUP1 CUP2 -- -- 3 4 CFIN Input 25 * CF specifications * Not used CFOUT Output 26 XTIN Input 20 XTOUT Output 19 * * * * 32k specifications 65k specifications 38k specifications Not used * The pull-up or pulldown resistors are on. Note: These pins go to the floating state when reset is cleared. * The pull-up or pulldown resistors are on. Note: These pins go to the floating state when reset is cleared. * Input mode * Output latch data is set high. S1 S2 S3 S4 Input 27 28 29 30 * Transistors to hold a low or high level * Selection of either pull-up or pulldown resistors K1 K2 K3 K4 I/O 31 32 33 34 I/O ports * Input pins used to read data into RAM * Output pins used to output data from RAM * Built-in 7.8 ms and 1.95 ms input-mode chatter exclusion circuits. The selection of 7.8 or 1.95 ms is linked to that for the S ports. Note: The 7.8 ms and 1.95 ms times are the times when o0 is 32.768 kHz. I/O ports * Input pins used to read data into RAM * Output pins used to output data from RAM * M4 is used as the external clock input pin in TM2 mode 3. * The minimum period for the external clock is twice the cycle time. * Built-in pull-up/pull-down resistors I/O ports * Input pins used to read data into RAM * Output pins used to output data from RAM * Built-in pull-up/pull-down resistors I/O ports Function: The same as pins A1 to A4 * Transistors to hold a low or high level * Selection of either pull-up or pulldown resistors M1 M2 M3 M4 A1 A2 A3 A4 P1 P2 P3 P4 I/O 35 36 37 38 11 12 13 14 15 16 17 18 The same as K1 to K4 The same as K1 to K4 I/O The same as K1 to K4 The same as K1 to K4 I/O The same as K1 to K4 The same as K1 to K4 Continued on next page. No. 4434-4/17 LC58E76 Continued from preceding page. QFC-80 Pin No. Pin I/O Function I/O ports Function: The same as pins A1 to A4 Pins SO1 to SO3 area also used for the serial interface. * Use of these pins in serial mode can be selected under program control. * Pin functions: SO1: Serial input pin SO2: Serial output pin SO3: Serial clock pin The serial clock pin can be switched between internal and external, and between rising edge output and falling edge output. Output-only ports * Output pins used to output data from RAM * An alarm signal can be output from pin N4. (Note that this is only when the N4 output latch is low.) * An alarm signal modulated at 1, 2 or 4 kHz can be output. (These frequencies are output when o0 is 32.768 kHz.) * A carrier signal can be output from N3. (Note that this is only when the N3 output latch is low.) Option * Transistors to hold a low or high level * Selection of either pull-up or pulldown resistors * Internal serial clock divisor selection I 1/1 II 1/2 III 1/4 * Pin N1 to N4 output circuit type: I N-channel open drain * Pin N1 to N4 output level I High level II Low level * Transistors to hold a low or high level * Selection of either pull-up or pulldown resistors * Signal conversion (rising/falling) selection * Only when the input resistor open specification is selected At reset SO1 SO2 SO3 SO4 I/O 7 8 9 10 The same as K1 to K4 N1 N2 N3 N4 Output 39 40 41 42 The output levels on pins N1 to N4 can be specified as an option. INT Input 6 Input ports * External interrupt request inputs * Input pins used to read data into RAM * Input detection can be performed on either rising or falling edges. * Built-in pull-up/pull-down resistors LSI reset input * The LC58E7008 resets on a high level input Note: * An external resistor is required. * The reset pulse must be at least 200 s. Test input Connect to VSS in normal operation. RES Input 5 TST Input 43 Seg1, Seg2 to Seg35 Output 44, 45 to 78 * LCD panel drive/general-purpose output -- LCD panel drive I STATIC II 1/2 bias - 1/2 duty III 1/2 bias - 1/3 duty IV 1/2 bias - 1/4 duty V 1/3 bias - 1/3 duty VI 1/3 bias - 1/4 duty Types I to V can be specified as mask options. -- General-purpose output mode I CMOS II P-channel open drain III N-channel open drain Types I to III can be specified as mask options. * LCD/general-purpose output control is handled by the segment PLA, and thus program control is not required. * These pins support output latch control on reset and in standby states when the oscillators are stopped. * Arbitrary combinations of LCD drive and general-purpose outputs can be used. * LCD driver/ general-purpose output switching * LCD drive type switching -- STATIC -- 1/2 bias - 1/2 duty -- 1/2 bias - 1/3 duty -- 1/2 bias - 1/4 duty -- 1/3 bias - 1/3 duty -- 1/3 bias - 1/4 duty * General-purpose output circuit switching -- CMOS -- P-channel open drain -- N-channel open drain * Output latch control in standby modes * LCD drive All segments off * General-purpose outputs Low level Note: When a combination of LCD drive and general- purpose outputs, the output state is either all segments off or low level. * These pins go to the VSS level during the reset period. Continued on next page. No. 4434-5/17 LC58E76 Continued from preceding page. QFC-80 Pin No. Pin I/O Function LCD panel drive common polarity outputs The table below shows how these pins are used depending on the duty used. (Values for alternation frequency reflect a typical specification of 32.768 MHz for o0) Option At reset COM1 COM2 COM3 COM4 Output 2 1 80 79 Static duty COM1 COM2 COM3 COM4 Alternation frequency r 1/2 duty r r 1/3 duty r r r 1/4 duty r r r r 32 Hz x x x x x x These pins are nchannel open-drain outputs during the reset period. 32 Hz 32 Hz 42.7 Hz Note: A cross ( x ) indicates that the pin is not used with that duty type. Usage Notes The following tools and software are required when the LC58E76 is used. The LC5870 Series Software Development Tools: For creating programs and option data. Note that only MS-DOS machines are supported as the development host machine. See the LC5870 Series Software Development Tools manuals for details on the use of these tools. EC5876.EXE: This is a program that converts and merges program and option data for the LC5870 series so that it can be written to the LC58E76 EPROM. EPROM writing board (adapter socket: W58E68Q): This is a socket adapter that allows a general-purpose PROM writer to be used to write program data to the LC58E76. General-purpose PROM writer: The EVA-520 programmer that comes with the LC5870 Series Software Development Tools cannot be used. A general-purpose PROM writer must be used. This section describes the procedures used with the LC58E76 and the EC5876.EXE program, which is one of the tools mentioned above. More details on LC5870 Series program development are available in LC5870 Series Users Manual and the manuals for the LC5870 Series Development Tools and the general-purpose PROM writer. No. 4434-6/17 LC58E76 1. Procedure (This flowchart describes the procedure used.) Specification determination Mask option specification Use the SU5870.EXE program to create the option specification data. Program creation and debugging Use the LC5870S.EXE cross assembler to create the program. Use the dedicated development tools for debugging. Data conversion and merging for the LC58E76 Use the EC5876.EXE program to convert and merge the program and option data. This creates the data to be written to the LC58E76 EPROM. (See "Using the EC5876.EXE Program".) PROM writer setup Setup the PROM writer ROM type, the start and stop addresses, and other states. (See "Use of the EPROM Writing Board".) Transfer the LC58E76 EPROM data created with the EC5876.EXE program to the PROM writer. Write data transfer EPROM writing board setup Mount the PROM writer in the LC58E76 EPROM writing board. Write Mount the LC58E76 in the EPROM writing board, and write the data. Apply an opaque seal to the LC58E76 window at the point that the data is written. Mount the LC58E76 in the socket in the application circuit, and check that the program functions correctly. Mounted configuration program testing Note: There are differences in function and characteristics between the LC58E76 and the LC5870 series mask ROM versions. Be sure to take these differences into account when testing the programmed LC58E76. See the "Usage Notes" section for details on the differences. 2. Using the EC5876.EXE Program (Operation) As shown in the figures below, the data to be written to the LC58E76 consists of a program data area (instruction code area) and an option data area. The EC5876.EXE program applies a special conversion process to the option specification data to create the option data area data. The EC5876.EXE program converts and merges program data and option data to create the data to be written to the LC58E76. * Start-up procedure A:>EC5876 ROMSAMP.HEX PLASAMP.HEX EP-SAMP.HEX No. 4434-7/17 LC58E76 * Error messages Error ON filename.HEX, FILE NOT FOUND...............The file "filename.HEX" was not found. The filename "filename.HEX" was incorrect. Error ON MAKE LC5876, 5874, 5873, 5872.............The ROM data and the option data object microprocessor type did not agree. The ROM data must be created with a cross assembler and option specification software designed for the same microprocessor type. Error ON filename.HEX, EOF NOT DETECTED ..........A hexadecimal record end marker was not found in the file "filename.HEX". Error ON filename.HEX, ILLEGAL CHARACTER........A character other than 0 to 9 or A to F was found in a hexadecimal context while reading the file "filename.HEX". Error ON filename.HEX, ADDRESS OVER....................An address in the file "filename.HEX" exceeded the allowed range. Error ON filename.HEX, ILLEGAL FILEHDR.............The header in the file "filename.HEX" is not for the LC5870 series. There was an error in the hexadecimal file specification. Error ON command line input, INVALID NUMBER OF PARAMETERS...............The number of parameters in the command line was inappropriate. Error ON ILLEGAL, MASK OPTION DATA ......................There was an error in the mask option data. * EPROM data structure Cross assembler and mask option data (1) Cross assembler data EPROM Data (2) Mask option data No. 4434-8/17 LC58E76 3. Use of the W58E68Q EPROM Writing Board (Board used with both the LC58E68 and the LC58E76) The EPROM writing board is a socket adapter that fits the LC58E76 to the device socket in a general-purpose PROM writer. * EPROM Writing Board Appearance * PROM writer settings -- ROM type: -- Start and stop addresses: 256 K, VPP = 21 V mode Set these to 0000H and 40FFH. 4. Erasing LC58E76 EPROM Data Use a general-purpose EPROM eraser to erase data written to an LC58E76. 5. Notes On Order Mask ROM * The following methods cannot be used to order LC5870 Series mask ROM products. -- Use of ".HEX" files that were converted and merged for use in an LC58E76 -- Use of an LC58E76 itself * Ordering mask ROM -- Use the program hexadecimal data generated by the cross assembler. -- Use the option hexadecimal data generated by the option specification software. -- Provide three EPROMs to which the program hexadecimal data has been written using a general-purpose EPROM writer. -- Provide three EPROMs to which the option hexadecimal data has been written using a general-purpose EPROM writer. No. 4434-9/17 LC58E76 Specifications The electrical characteristics listed here are provisional values and are subject to change. Absolute Maximum Ratings at VSS = 0 V, TA = 25C Ratings Parameter Symbol VDD Maximum supply voltage VDD1 VDD2 VI (1) Maximum input voltage VI (2) As allowed in the specified circuit (Figure 1) XTIN, CFIN S1 - 4, K1 - 4, P1 - 4, SO1 - 4, A1 - 4, RES, INT, TST (K, P, M, SO and A ports in input mode) As allowed in the specified circuit (Figure 1) XTOUT, CFOUT K1 -4, P1 - 4, SO1 - 4, A1 - 4, N1 - 4, CUP1, CUP2, Seg1 - 35, COM1 - 4, (K, P, M, SO and A ports in output mode) Open drain specifications Per pin Per pin Per pin Per pin N1 - 4 K1 - 4, P1 - 4, M1 - 4, SO1 - 4, A1 - 4 K1 - 4, P1 - 4, M1 - 4, SO1 - 4, A1 -4, N1 - 4, Seg1 - 35 N1 to N4 (n-channel) Conditions/Pin min -0.3 -0.3 -0.3 typ max +6.0 VDD VDD Unit V V V Allowed up to the voltage that appears VDD +0.3 -0.3 V VO (1) Maximum output voltage VO (2) Allowed up to the voltage that appears VDD +0.3 +13 15 0 5 0 70 -70 500 10 -55 40 +125 -0.3 V VO (3) IO (1) IO (2) IO (3) Output pin current IO (4) IO (1) IO (2) Allowable power dissipation Operating temperature Storage temperature Pdmax Topr Tstg -0.3 0 -10 0 -5 V mA mA mA mA mA mA mW C C Total (summed) pin current Total (summed) pin current For the QFC80 window ceramic flat package No. 4434-10/17 LC58E76 Allowable Operating Ranges at VSS = 0 V, Ta = 25C Ratings Parameter Symbol Conditions/Pin No LCD specifications: VDD1 = VDD2 = VDD Static drive specifications: VDD1 = VDD2 = VDD Supply voltage VDD 1/2 bias specifications: VDD1 = VDD2 1/2VDD 1/3 bias specifications: VDD1 2 x 1/3VDD VDD2 1/3VDD Data retention supply voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Operating frequency 1 Operating frequency 2 Operating frequency 3 Operating frequency 4 Operating frequency 5 Operating frequency 6 VHD VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 fopg1 fopg2 fopg3 fopg4 fopg5 fopg6 RAM and register contents retention voltage* S1 - 4, K1 - 4, P1 - 4, M1 - 4, SO1 - 4, A1 - 4, INT (K, P, M, SO and A ports in input mode) min 2.8 2.8 2.8 2.8 2.8 0.7 VDD 0 0.75 VDD 0 0.75 VDD 0 XTIN/XTOUT crystal oscillator 32 37 60 190 CFIN/CFOUT CF specifications Pins SO1 and SO3 (in serial mode) The rising and falling edges of input signal and clock waveforms must be 10 s. 190 190 typ max 5.5 5.5 5.5 5.5 VDD VDD 0.3 VDD VDD 0.25 VDD VDD 0.25 VDD 33 39 70 1200 2300 4200 Unit V V V V V V V V V V V kHz kHz kHz kHz kHz kHz RES pin CFIN pin VDD = 2.8 to 5.5 V, 32 kHz VDD = 2.8 to 5.5 V, 38 kHz VDD = 2.8 to 5.5 V, 65 kHz VDD = 2.8 to 5.5 V VDD = 3.0 to 5.5 V VDD = 4.5 to 5.5 V Operating frequency 7 fopg7 VDD = 3.0 to 5.5 V DC 200 kHz Note: * In a state with the CF/RC oscillator and the crystal oscillator completely stopped, and all internal circuits stopped Electrical Characteristics at VDD = 2.8 to 3.2 V, VSS = 0 V, Ta = 25C Ratings Parameter Symbol RIN1 A RIN1 B RIN1 C Input resistance RIN1 D RIN2 A RIN2 B RIN2 C RIN2 D RIN3 Output low-level voltage Output high-level voltage Output low-level voltage Output off leakage current Segment port output impedance * When CMOS output ports are used Output high-level voltage Output low-level voltage VOH (3) VOL (3) IOH = -100 A IOL = 100 A Seg 1 to 35 VDD - 0.5 0.5 V V VOL (1) VOH (2) VOL (2) | I OFF | Conditions/Pin VIN = 0.2 VDD, Low-level hold transistor *, Figure 2 VIN = VDD, Pull-down resistor *, Figure 2 VIN = 0.8 VDD, High-level hold transistor *, Figure 2 VIN = VSS, Pull-up resistor *, Figure 2 VIN = 0.2 VDD, INT low-level hold transistor VIN = VDD, INT pull-down resistor VIN = 0.8 VDD, INT high-level hold transistor VIN = VSS, INT pull-up resistor VIN = VDD, With a pull-down resistor on the TST pin IOL = 1.0 mA IOH = -400 A IOL = 400 A VOH = 10.5 V N1 - 4 K1 - 4, P1 - 4, M1 - 4, SO1 - 4, A1 - 4 (K, P, M, SO and A ports in output mode) N1 - 4, Figure 10 VDD - 0.5 0.5 1.0 min 60 30 60 30 60 300 60 300 20 typ 300 150 300 150 300 1500 300 1500 70 max 1200 500 1200 500 1200 5000 1200 5000 300 0.5 Unit k k k k k k k k k V V V A Note: * The 24 pins S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4 and A1 to A4. Continued on next page. No. 4434-11/17 LC58E76 Continued from preceding page. Ratings Parameter Symbol Conditions/Pin min typ max Unit * When p-channel open-drain output ports are used (See Figure 11.) Output high-level voltage Output off leakage current VOH (3) | I OFF | VOL (3) | I OFF | VOH (4) VOL (4) VOH (5) VOL (5) VOH (4) VOL (4) VOH (6) VOM2-1 VOL (6) VOH (4) VOM1-1 VOM1-2 VOL (4) ILEK (1) IOH = -100 A VOL = VSS IOL = 100 A VOH = VDD IOH = -20 A IOL = 20 A IOH = -100 A IOL = 100 A IOH = -20 A IOL = 20 A IOH = -100 A IOH = -100 A IOL = 100 A IOL = 100 A IOH = -20 A IOH = -20 A IOL = 20 A IOL = 20 A VDD = 3.0 V VDD = 3.0 V Input leakage current IOFF VIN = VDD VIN = VSS Output voltage 1 VDD1-(1) VDD2-(1) VDD2-(2) Ta = 25C, STOP mode, Figure 3 S1 - 4, K1 - 4, P1 - 4, M1 - 4, SO1 - 4, A1 - 4, INT, RES (K, P, M, SO and A ports in input mode, INT and RES pin open specifications) VDD1 = V0 1.0 Seg 1 to 35 VDD - 0.2 2VDD/3 - 0.2 VDD/3 - 0.2 2VDD/3 + 0.2 VDD/3 + 0.2 0.2 COM1 - 4 VDD - 0.2 0.2 VDD - 0.2 VDD/2 - 0.2 VDD/2 + 0.2 0.2 COM1 VDD - 0.2 0.2 Seg 1 to 35 VDD - 0.5 1.0 V A * When n-channel open-drain output ports are used (See Figure 11.) Output low-level voltage Output off leakage current * Static drive Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage * 1/2 bias Output high-level voltage Output low-level voltage Output high-level voltage Output middle-level voltage Output low-level voltage * 1/3 bias Output high-level voltage Output middle-level voltage Output low-level voltage Supply leakage current V V V V A Seg 1 to 35 V V V V V Seg 1 to 35 VDD - 0.2 0.2 V V V V Seg 1 to 35 0.5 1.0 V A 1.0 -1.0 1.5 2.0 1.0 A A V V V VDD = 3.0 V, C1 = C2 = 0.1 F 1/2 bias, fopg = 32.768 kHz, Figure 4 VDD = 3.0 V, C1 = C2 = 0.1 F 1/3 bias, fopg = 32.768 kHz, Figure 4 Output voltage 2 VDD1 = V0 VDD2 = V0 Supply current 1 | IDD | 1 VDD = 3.0 V Ta = 25C, Crystal oscillator specifications, Crystal: 32 kHz, Cg = 20 pF, CI = 25 k Halt mode, LCD at 1/3 bias, Figure 6 Ta = 25C, Crystal oscillator specifications, Crystal: 38 kHz or 65 kHz, Cg = 10 pF, CI = 25 k, Halt mode, LCD at 1/3 bias, Figure 6 Ta = 25C, CF oscillator specifications, CF: 400 kHz, Ccg = Ccd = 330 pF Halt mode, LCD at 1/3 bias, Figure 8 Ta = 25C, CF oscillator specifications, CF: 1 MHz, Ccg = Ccd = 100 pF, Halt mode, LCD at 1/3 bias, Figure 8 5.0 A Supply current 2 | IDD | 2 VDD = 3.0 V 10.0 A Supply current 3 | IDD | 3 VDD = 3.0 V 150 A Supply current 4 | IDD | 4 VDD = 3.0 V 200 A Continued on next page. No. 4434-12/17 LC58E76 Continued from preceding page. Ratings Parameter Symbol VDD = 2.8 V Oscillator start time | TSTT | VDD = 2.95 to 3.05 V Conditions/Pin Crystal oscillator specifications, with a 32 kHz crystal CI 25 k, Cg = 20 pF Figure 6 Crystal oscillator specifications, with a 38 or 65 kHz crystal XCg = 10 pF, CI 25 k Figure 6 CF oscillator specifications, with a 400 kHz CF used Ccg = Ccd = 330 pF, Figure 7 CF oscillator specifications, with an 800 kHz CF used Ccg = Ccd = 220 pF or 100 pF Figure 7 XTOUT pin (built-in) 20 min typ max 5 Unit s Oscillator stabilization degree f 3 ppm Oscillator start time | TSTT | VDD = 2.8 V 5 s Oscillator start time | TSTT | VDD = 2.8 V 30 ms Oscillator start time | TSTT | VDD = 2.8 V 30 ms Oscillator compensation capacitance Cd VDD = 3.0 V pF Electrical Characteristics at VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = 25C Ratings Parameter Symbol RIN1 A RIN1 B RIN1 C Input resistance RIN1 D RIN2 A RIN2 B RIN2 C RIN2 D RIN3 Output low-level voltage Output high-level voltage Output low-level voltage Output off leakage current Segment port output impedance * When CMOS output ports are used Output high-level voltage Output low-level voltage VOH (3) VOL (3) VOH (4) | I OFF | VOL (4) | I OFF | VOH (4) VOL (4) VOH (6) VOL (6) IOH = -500 A IOL = 500 A Seg 1 to 35 VDD - 0.5 VDD - 0.2 0.5 V V VOL (1) VOH (2) VOL (2) | I OFF | Conditions/Pin VIN = 0.2 VDD, Low-level hold transistor *, Figure 2 VIN = VDD, Pull-down resistor *, Figure 2 VIN = 0.8 VDD, High-level hold transistor *, Figure 2 VIN = VSS, Pull-up resistor *, Figure 2 VIN = 0.2 VDD, INT low-level hold transistor VIN = VDD, INT pull-down resistor VIN = 0.8 VDD, INT high-level hold transistor VIN = VSS, INT pull-up resistor VIN = VDD, With a pull-down resistor on the TST pin IOL = 10.0 mA IOH = -1.0 mA IOL = 2.0 mA VOH = 10.5 V N1 - 4 K1 - 4, P1 - 4, M1 - 4, SO1 - 4, A1 - 4 (K, P, M, SO and A ports in output mode) N1 - 4, Figure 10 VDD - 0.5 VDD - 0.2 0.2 0.5 1.0 min 30 10 30 10 30 100 30 100 20 typ 120 50 120 50 120 500 120 500 70 max 500 200 500 200 500 2000 500 2000 300 0.5 Unit k k k k k k k k k V V V A * When p-channel open drain output ports are used (See Figure 11.) Output high-level voltage Output off leakage current IOH = -500 A VOL = VSS IOL = 500 A VOH = VDD IOH = -40 A IOL = 40 A IOH = -400 A IOL = 400 A Seg 1 to 35 VDD - 0.5 VDD - 0.2 1.0 V A * When n-channel open-drain output ports are used (See Figure 11.) Output low-level voltage Output off leakage current * Static drive Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Seg 1 to 35 VDD - 0.2 0.2 VDD - 0.2 0.2 V V V V Seg 1 to 35 0.2 0.5 1.0 V A COM1 Note: * The 24 pins S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4 and A1 to A4. Continued on next page. No. 4434-13/17 LC58E76 Continued from preceding page. Ratings Parameter * 1/2 bias Output high-level voltage Output low-level voltage Output high-level voltage Output middle-level voltage Output low-level voltage * 1/3 bias Output high-level voltage Output middle-level voltage Output low-level voltage Output high-level voltage Output middle-level voltage Output low-level voltage Supply leakage current VOH (4) VOM1-1 VOM1-2 VOL (4) VOH (6) VOM2-1 VOM2-2 VOL (6) ILEK (1) IOH = -40 A IOH = -40 A IOL = 40 A IOL = 40 A IOH = -400 A IOH = -400 A IOL = 400 A IOL = 400 A VDD = 5.5 V VDD = 5.5 V Input leakage current IOFF VIN = VDD VIN = VSS Output voltage 1 VDD1-(1) VDD2-(1) VDD2-(2) Ta = 25C, Stop mode, Figure 3 S1 - 4, K1 - 4, M1 - 4, SO1 - 4, A1 - 4, INT, RES (K, P, M, SO and A ports in input mode, INT and RES pin open specifications) VDD1 = V0 Figure 4 VDD1 = V0 VDD2 = V0 Figure 4 1.0 COM1 - 4 Seg 1 to 35 VDD - 0.2 2VDD/3 - 0.2 VDD/3 - 0.2 VDD - 0.2 2VDD/3 - 0.2 VDD/3 - 0.2 2VDD/3 + 0.2 VDD/3 + 0.2 0.2 2VDD/3 + 0.2 VDD/3 + 0.2 0.2 V V V V V V V V A VOH (4) VOL (4) VOH (6) VOM2-1 VOL (6) IOH = -40 A IOL = 40 A IOH = -400 A IOH = -400 A IOL = 400 A IOL = 400 A COM1 - 4 Seg 1 to 35 VDD - 0.2 0.2 VDD - 0.2 VDD/2 - 0.2 VDD/2 + 0.2 0.2 V V V V V Symbol Conditions/Pin min typ max Unit 1.0 -1.0 2.5 3.33 1.67 A A V V V VDD = 5.0 V, C1 = C2 = 0.1 F, 1/2 bias, fopg = 32.768 kHz VDD = 5.0 V, C1 = C2 = 0.1 F, 1/3 bias, fopg = 32.768 kHz Output voltage 2 Supply current 1 | IDD | 1 VDD = 5.0 V Ta = 25C, Crystal oscillator specifications, Crystal: 32 kHz, Cg = 20 pF, CI = 25 k Halt mode, LCD at 1/3 bias, Figure 6 Ta = 25C, Crystal oscillator specifications, Crystal: 38 kHz or 65 kHz, Cg = 10 pF, CI = 25 k, Halt mode, LCD at 1/3 bias, Figure 6 Ta = 25C, CF oscillator specifications, CF: 400 kHz, Ccg = Ccd = 330 pF Halt mode, LCD at 1/3 bias, Figure 7 Ta = 25C, CF oscillator specifications, CF: 1 MHz, Ccg = Ccd = 100 pF, Halt mode, LCD at 1/3 bias, Figure 8 Ta = 25C, CF oscillator specifications, CF: 2 MHZ, Ccg = Ccd = 33 pF, Halt mode, LCD at 1/3 bias, Figure 8 Ta = 25C, CF oscillator specifications, CF: 4 MHz, Ccg = Ccd = 33 pF, Halt mode, LCD at 1/3 bias, Figure 8 XTOUT pin (built-in) 20 A Supply current 2 | IDD | 2 VDD = 5.0 V 30 A Supply current 3 | IDD | 3 VDD = 5.0 V 400 A Supply current 4 | IDD | 4 VDD = 5.0 V 450 A Supply current 5 | IDD | 5-1 VDD = 5.0 V 500 A Supply current 6 | IDD | 6-1 VDD = 5.0 V 700 A Oscillator compensation capacitance Cd VDD = 5.0 V 20 pF No. 4434-14/17 LC58E76 Xtal 32 k: 32.768 kHz 65 k: 65.536 kHz 38 k: 38.2293 kHz Figure 1-(1) Specified Oscillator Circuit (XT pin) Figure 1-(2) Specified Oscillator Circuit (CF pin) Figure 2 S, K, P, M, SO and A Port Input Circuit (Reference) Recommended Ceramic Resonators for Mask ROM Versions Manufacturer Item Frequency 400 kHz 800 kHZ 1 MHz 2 MHz 4 MHz CSB400P CSB800J CSB1000J CSA2.00MG, CST2.00MG CSA4.00MG, CST4.00MG Murata Mfg. Co., Ltd. Type No. Ccg (pF) 330 220 220 33 33 Ccd (pF) 330 220 220 33 33 KBR-400B KBR-800H KBR-1000H KBR-2.00MS KBR-4.00MS Kyocera Corporation Type No. Ccg (pF) 330 100 100 33 33 Ccd (pF) 330 100 100 33 33 Figure 14 Timer 2 External Clock Input Timing (in external clock mode: pin M4) Figure 13 Serial I/O Timing (in external clock mode) No. 4434-15/17 LC58E76 Figure 3 * In the stop state * With the S-port input resistors on * With the I/O ports in output mode with high-level data values * With the INT pin built-in resistor connected and in the open state * With an external pull-down resistor on the RES pin * The LCD-port values do not include the external component currents. * With a crystal frequency between 32 and 65 kHz * With CF between 200 kHz and 4 MHz Figures 4 and 5 * With a crystal frequency of 32 kHz * C1, C2, and C3 are 0.1 F capacitors. * With the LCD ports open * With CD between 200 kHz and 4 MHz Figure 3 Supply Leakage Current Test Circuit Figure 4 Output Voltage Test Circuit Figure 5 Output Voltage Test Circuit Figure 6: Supply Current Test Circuit Figure 7: Supply Current Test Circuit Figure 8 Supply Current Test Circuit Figure 10 Pin N1 to Pin N4 Circuits No. 4434-16/17 LC58E76 Figure 11: Segment Pin Open-Drain Circuits Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 4434-17/17 |
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