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19-4771; Rev 1; 10/98
NUAL KIT MA UATION TA SHEET EVAL WS DA FOLLO
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC
____________________________Features
o Regulated Step-Up/Step-Down Operation o 80mA Output from 3 Cells o 85% Efficiency o 13A Idle ModeTM (coast) Current o Selectable Low-Noise PWM or Low-Current PFM Operation o PWM Operating Frequency Synchronized to Seven Times an External Clock Source o Operates at 270kHz with No External Clock o Automatic Backup-Battery Switchover
________________General Description
The MAX769 is a complete buck/boost power supply and monitoring system for two-way pagers or other lowpower digital communications devices. Few external components are required. Included on-chip are: * An 80mA output, synchronous-rectified, buck/boost DC-DC converter with a digitally controlled +1.8V to +4.9V output. The DC-DC converter is unique, since it provides a regulated output for battery inputs that are both less than and greater than the output voltage, without using transformers. * Three low-noise linear-regulator outputs * Three DAC-controlled comparators for softwaredriven, 3-channel A/D conversion * SPITM-compatible serial interface * Reset and low-battery (LBO) warning outputs * Charger for NiCd/NiMH, lithium battery, or storage capacitor for RF PA power or system backup * Two 1.8 (typical), serial-controlled, open-drain MOSFET switches for beeper or vibrator drive An evaluation kit for the MAX769 (MAX769EVKIT) is available to aid in design and prototyping.
Pin Configuration appears at end of data sheet.
MAX769
Ordering Information
PART MAX769EEI TEMP. RANGE -40C to +85C PIN-PACKAGE 28 QSOP
________________________Applications
Two-Way Pagers GPS Receivers 2 or 3-Cell Powered, Hand-Held Equipment
___________________________________________________Typical Operating Circuit
INPUT 2 OR 3 AA ALKALINE BATTERIES 1.5V TO 5.5V LOW-BATTERY IN/OUT REJECT IN/OUT LBI LBO RSIN RSO CS SCL SD1 SD03 DR1 DR2 DR2IN DRGND
BATT
LX1 LX2 OUT PGND REG2IN
SERIAL I/O
MAX769
OFS OUTPUT 2 2.85V ANALOG OUTPUT 1 3V LOGIC OUTPUT 3 1V RECEIVER TO RF PA NiCd STORAGE BATTERY OR CAPACITOR STACK
1.8 DRIVERS
REG2 REG1
A/D INPUT OPTIONAL
CH0 SYNC
REG3 NICD
FILT
REF
AGND
Idle Mode is a trademark of Maxim Integrated Products. SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769
ABSOLUTE MAXIMUM RATINGS
BATT, OUT, NICD, LBO, RSO to AGND...................-0.3V to +6V REG1, REG2, OFS, REF, R2IN to AGND .....-0.3V to (OUT + 0.3V) SCL, SDO, SDI, CS, SYNC, FILT, DR2IN, CH0, LBI, RSIN to AGND......................-0.3V to (REG1 + 0.3V) REG3 .......................................................-0.3V to (REG2 + 0.3V) DR1, DR2 to DRGND ...............................-0.3V to (BATT + 0.3V) PGND, DRGND to AGND ......................................-0.3V to +0.3V LX1 to PGND .............................................-0.3V to (OUT + 0.3V) LX2 to PGND ............................................-0.3V to (BATT + 0.3V) Continuous Power Dissipation (TA = +70C) QSOP (derate 8mW/C above +70C) ..........................640mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(OUT = 3.0V, BATT = 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER GENERAL PERFORMANCE BATT Typical Operating Range (Note 2) BATT Minimum Start-Up Voltage (Note 3) Coast Mode Supply Current (Note 4) Run Mode Supply Current (Note 4) BATT Supply Current (Note 5) NICD Input Current, Standby (Note 6) NICD Input Supply Current, Backup (Note 7) NICD Input Current, Power Fail (Note 8) REG2 Supply Current (Note 4) REG3 Supply Current (Note 4) CH DAC Supply Current (Note 4) Reference Voltage DR1, DR2 On-Resistance DR1, DR2 Leakage Current SDO Output Low SDO Output High Logic Input Level Low Logic Input Level High Logic Input Current Run or Coast Mode TA = +25C REG2, REG3 and CH DAC off, VOUT = 2.8V REG2, REG3 and CH DAC on Coast Mode Charger and Backup Modes off, NICD = 3.6V Backup Mode, NICD = 3.6V, OUT = 3V Charger and Backup Modes off, BATT = 0V, OUT = 0V Incremental supply current when on Incremental supply current when on Incremental supply current when on IREF = 0 to 20A, OUT = 1.8V to 4.9V TA = +25C IDR = 120mA TA = -40C to +85C VDR = 5V ISDO = 100A ISDO = -100A, from REG1 Includes CS, SDI, SCL, DR2IN, and SYNC Includes CS, SDI, SCL, DR2IN, and SYNC Logic Input = 0 to 3.3V; includes CS, SDI, SCL, DR2IN, and SYNC -1 VREG1 - 0.2 0.4 VREG1 - 0.4 1 -1.5% 1.5 1.6 13 875 4 1.2 20 1.2 50 20 30 1.28 1.8 1 1.5% 2.8 3.6 250 200 5.5 2.0 25 1350 10 3 40 3 V V A A A A A A A A A V nA mV V V V A CONDITIONS MIN TYP MAX UNITS
2
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SCL Maximum Clock Rate SDI Setup Time (tDS) SDI Hold Time (tDH) SCL to SDO Output Valid (tDO) CS to SDO Output Valid (tDV) CS to SDO Disable (tTR) CS to SCL Setup Time (tCSS) CS to SCL Hold Time (tCSH) CS Pulse Width High (tCSW) SCL Pulse Width High or Low (tCH, tCL) DC-DC CONVERTER Output Current, Run Mode (Note 10) Output Current, Coast Mode (Note 10) OUT Error, Coast Mode (Note 11) OUT Error, Run Mode (Note 12) OUT DAC Step Size (Note 13) OUT Load Regulation OUT Line Regulation Maximum LX Duty Cycle OUT Voltage Ripple LX Switch Current Limit LX On-Resistance (Note 14) PHASE-LOCKED LOOP (PLL) Frequency, Free-Run Frequency, Locked Jitter (Note 15) Capture Time (Note 15) NICD CHARGER Current High Current Low OUT Error, Backup Regulator Backup-Regulator On-Resistance (Note 16) 0.2V < (OUT - NICD) < 2V, 15mA_CHG = 1 0.2V < (OUT - NICD) < 2V, 1mA_CHG = 1 OUT = 2.8V, IOUT = 20mA, NICD = 3.3V Backup Mode, NICD = 3.3V 7 0.45 -3.5 5 25 1.5 3.5 10 mA mA % TA = +25C, FILT connected to REF fSYNC = 38.4kHz fSYNC = 38.4kHz, FILT Network = 1nF (22nF + 10k) fSYNC = 38.4kHz, FILT Network = 1nF (22nF + 10k) 210 270 268.8 15 1 25 325 kHz kHz kHz ms Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V Coast Mode, OUT = 1.8V to 4.9V Run Mode, OUT = 1.8V to 4.9V Coast or Run Mode, OUT = 1.8V to 4.9V IOUT = 1mA to 80mA, Run Mode BATT = 1.6V to 4.5V OUT = 3.0V IOUT = 80mA, COUT = 47F with ESR < 0.25 During the inductor charge cycle LX1, LX2, BATT = 3.0V NMOS PMOS 76 300 80 15 -3.5 -3.5 30 100 25 25 83 70 350 0.9 1.3 400 1.8 2.6 115 40 3.5 3.5 170 mA mA % % mV mV mV % mVp-p mA 50 50 100 50 50% duty cycle CONDITIONS MIN 5 100 50 70 70 70 TYP MAX UNITS MHz ns ns ns ns ns ns ns ns ns SERIAL-INTERFACE TIMING SPECIFICATIONS (Note 9)
MAX769
3
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER LINEAR REGULATORS REG1 PMOS On-Resistance REG1 Supply Rejection (Note 16) REG1 Clamp Voltage REG2 Voltage Drop REG2 Load Regulation REG2 Supply Rejection (Note 16) REG3 Output Voltage REG3 Supply Rejection (Note 16) LBI/RSIN Input Threshold LBI/RSIN Input Hysteresis (Note 16) LBI/RSIN Input Current LBO/RSO Output Low LBO/RSO Output Leakage LBO/RSO Response Time (Note 16) CH0 Threshold Range (Note 16) CH1 Threshold Range (Note 16) CH2 Threshold Range (Note 16) CH0 Threshold Resolution (Note 16) CH1 Threshold Resolution (Note 16) CH2 Threshold Resolution (Note 16) CH0 Error CH1 Error CH2 Error CH0 Input Hysteresis (Note 16) CH1 Input Hysteresis (Note 16) Measures NICD Measures BATT At thresholds of 200mV, 800mV, and 1270mV At thresholds of 1200mV, 3200mV, and 5080mV At thresholds of 1200mV, 3200mV, and 5080mV -2.0 - 15mV -3.0 - 60mV -3.0 - 60mV 1 4 2 8 Measures NICD Measures BATT IOUT = 1mA Output = 5.5V 10mV overdrive 0.2 1.2 1.2 10 40 40 2.0 + 15mV 3.0 + 60mV 3.0 + 60mV 4 16 OUT = 3.0V, IREG1 = 65mA f = 268.8kHz, CREG1 = 10F ceramic IOUT = 1mA, OUT = 4.9V TA = +25C TA = -40C to +85C IREG2 = 0 to 24mA, OUT = 3.0V, ROFS = 15k IREG2 = 0.1mA to 24mA f = 268.8kHz, CREG1 = 10F, ceramic, ROFS = 15k, COFS = 0.1F, IREG2 = 15mA IREG3 = 0 to 2mA f = 268.8kHz, CREG1 = 1F ceramic Falling input 30 0.96 40 0.58 7.5 -50 15 3.2 3.15 120 155 9 40 1.0 50 0.60 16 -3 30 1 15 0.63 30 50 400 250 50 1.27 5.08 5.08 1.04 1.5 25 3.3 3.4 3.45 190 3.1 dB V V mV mV dB V dB V mV nA mV nA s V V V mV mV mV % % % mV mV CONDITIONS MIN TYP MAX UNITS
DATA-ACQUISITION AND VOLTAGE MONITORS
4
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER CH2 Input Hysteresis (Note 16) CH0 Input Current CH Comparator Response Time (Note 16) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: CH0 = 0.2V to 1.27V 10mV overdrive CONDITIONS MIN 4 -100 0.6 TYP 8 MAX 16 100 1.0 UNITS mV nA s
Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16:
Specifications to -40C are guaranteed by design, not production tested. This is not a tested parameter, since the IC is powered from OUT, not BATT. Minimum start-up voltage is tested by determining when the LX pins can draw at least 15mA for 0.5s (min) at a 285kHz (min) repetition rate. This guarantees that the IC will deliver at least 200A at the OUT pin. This supply current is drawn from the OUT pin. Current drain from the battery depends on voltages at BATT and OUT and on the DC-to-DC converter's efficiency. Current into BATT pin in addition to the supply current at OUT. This current is roughly constant from Coast to Run Mode. Current into NICD pin when NICD isn't being charged and isn't regulating OUT. Current into NICD pin when NICD is regulating OUT. Doesn't include current drawn from OUT by the rest of the circuit. Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V. Current into the NICD pin when BATT and OUT are both at 0V. This test guarantees that NICD won't draw significant current when the main battery is removed and backup is not activated. Serial-interface timing specifications are not tested and are provided for design guidance only. Serial-interface functionality is tested by clocking data in at 5MHz with a 50% duty-cycle clock and checking for proper operation. With OUT set below 2.5V, the serial-interface clock frequency should be reduced to 1MHz to ensure proper operation. This specification is not directly tested but is guaranteed by correlation to LX on-resistance and current-limit tests. Measured by using the internal feedback network and Coast-Mode error comparator to regulate OUT. Doesn't include ripple voltage due to inductor currents. Measured by using the internal feedback network and Run-Mode error comparator to regulate OUT. Doesn't include ripple voltage due to inductor currents. Uses the OUT measurement techniques described for the OUT error, Coast Mode, and OUT error Run Mode specifications. The on-resistance is for either LX1 or LX2. PLL acquisition characteristics depend on the impedance at the FILT pin. The specification is not tested and is provided for design guidance only. The limits in this specification are not guaranteed and are provided for design guidance only.
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT (RUN MODE, VOUT = 3.0V)
MAX769-01
EFFICIENCY vs. LOAD CURRENT (COAST MODE, VOUT = 3.0V)
MAX769-02
EFFICIENCY vs. LOAD CURRENT (COAST MODE, VOUT = 2.4V)
MAX769-03
100 VIN = 1.5V VIN = 2.0V 90 EFFICIENCY (%)
100 VIN = 5.0V VIN = 3.5V VIN = 2.5V VIN = 2.0V VIN = 1.5V
100 VIN = 5.0V VIN = 3.5V VIN = 2.5V VIN = 2.0V VIN = 1.5V
90 EFFICIENCY (%)
90 EFFICIENCY (%)
80
80
80
70
VIN = 5.0V VIN = 3.5V VIN = 2.5V
70
70
60
60
60
50 1 10 LOAD CURRENT (mA) 100
50 0.01 0.1 1 LOAD CURRENT (mA) 10 100
50 0.01 0.1 1 LOAD CURRENT (mA) 10 100
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5
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
NO-LOAD BATTERY CURRENT vs. BATTERY VOLTAGE
VOUT = 3.0V COAST MODE BATTERY CURRENT (A)
MAX769-04
MAXIMUM LOAD CURRENT vs. BATTERY VOLTAGE
140 120 100 80 60 40 20 COAST MODE VOUT = 3.0V RUN MODE
MAX769-05
START-UP BATTERY VOLTAGE vs. LOAD CURRENT
VOUT = 3.0V COAST MODE 5
MAX769-06
100
160 MAXIMUM LOAD CURRENT (mA)
6
START-UP BATTERY VOLTAGE (V)
4
3
2
10 1 2 3 4 5 6 BATTERY VOLTAGE (V)
0 1 2 3 4 5 6 BATTERY VOLTAGE (V)
1 1 10 LOAD CURRENT (mA) 100
NICD CHARGING CURRENT vs. NICD VOLTAGE
MAX769-07
DR1 OR DR2 ON-RESISTANCE vs. VOUT
MAX769-08
25 NICD CHARGING CURRENT (mA)
3
20 2 RON () 1 5 15mA MODE VOUT = 4.9V 0 0 1 2 3 4 5 6 NICD VOLTAGE (V) 0 0 1 2 3 4 5 VOUT VOLTAGE (V) 15
10
LX NOISE SPECTRUM (RUN MODE, SYNC OPERATION)
MAX769-09
REG2 NOISE SPECTRUM (RUN MODE)
MAX769-10
20
100
0 NOISE (dBV) NOISE (dBV)
80
-20
60
-40
40
-60 -80 100 200 300 400 500 600 FREQUENCY (kHz)
20
0 0.1 1 10 100 1000 10,000 FREQUENCY (kHz)
6
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME LX1 SDI SDO PGND SCL LBO RSO REF CH0 RSIN LBI FILT SYNC OFS AGND DRGND DR1 DR2IN DR2 REG3 REG2 R2IN NICD REG1 OUT BATT CS LX2 FUNCTION Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET that switches to OUT. Serial Data Input for SPI Interface Serial Data Output for SPI Interface Power Ground. Source of LX1 and LX2 NFETs. Serial Clock for SPI Interface Open-Drain Output for LBI Comparator Reset Output. Open drain goes low when RSIN drops below 0.6V. All serial registers are reset (or set) to POR state as well. 1.28V Reference. Bypass with a 1F capacitor. CH0 is compared to a 7-bit DAC that adjusts from 0.2V to 1.27V. The comparison result is sent to the CH0 OUT register. Reset Input. Triggers RSO and resets IC when input is below 0.6V. Comparator with hysteresis (18mV). Low-Battery Input. Triggers LBO and internal serial bit. An external RC network sets the PLL loop response to adjust frequency lock time versus jitter: 1nF || (22nF + 10k). Sync Input for PWM Switch Rate. A 38.4kHz input results in a 268.8kHz PWM rate (seven times the SYNC frequency). Resistor sets offset between OUT (or REG1 or any other point) and REG2. ROFS = 15k results in 150mV. Analog Ground Ground for DR1 and DR2 FET Sources Open-Drain FET Switch. Activated via the serial-interface bit. Logic Input. ANDed with the DR2ON bit to control the DR2 switch. Open-Drain FET Switch. On via AND of the DR2ON bit and the DR2IN pin. 1V, 2mA Regulator Output. On via the serial interface. Low noise. 24mA REG2 Output. Linearly regulated to the voltage at the OFS pin (voltage difference = 10A x ROFS). REG2 isolates noise. REG2 Input. Connect to OUT, REG1, or another voltage source. 15mA or 1mA Settable Charge Current from OUT to 3-Cell NiCd Stack. When the NICD_REG_ON bit is set (Table 1), NICD becomes an input to the linear regulator at OUT, and the DC-DC converter is off. PFET Output Connected to OUT. Output is clamped such that it cannot rise above 3.3V, regardless of the voltage set at OUT. DC-DC Converter Output and Feedback Point. Digitally controlled from 1.8V to 4.9V in 100mV steps (Table 5). Positive Connection to Battery. The IC is powered from OUT. Chip Select for SPI Serial Interface Connect LX2 to the other inductor terminal. LX2 is internally connected to an NFET that switches to PGND and a PFET that switches to BATT.
MAX769
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7
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769
2- OR 3-CELL BATTERY IN SCL 5 N LBO 6 SDI 2 SDO 3 CS 27 26 BATT P N 4 N X7 PLL P SERIAL I/O CH1 OV0-OV4 S2 TO S1 AND S2 + CP2 - CH2 7 DAC0-DAC7 RESET CONTROL 7-BIT CH DAC BACKUP REGULATOR 5 AOUT + V FEEDBACK 1.28V REFERENCE CHG/REG CHARGE NICD OR BACKUP REGULATOR 1mA/15mA 14 22 + CPRS - 10A 3.3V REG2 ON RSO 7 N REG3 ON 1.0V - AR3 + - AR2 + P REG2 21 10F OFS R2IN COFS 0.1F ROFS 15k 23 NICD 5 CLAMP ON WHEN OV4 = 1 25 3.3V CLAMP - AR1 + P REG1 24 10F 47F 12 13 SYNC OUT FILT 22nF 10k 1nF 1 LX1 PGND L1 68H 28 LX2 22F
MAX769
LBI 11 - 0.6V CPLB + LB0 CH0 9 FROM NICD S1 FROM BATTERY + CP0 - + CP1 - CH0 RUN/ COAST
PWM (PFM IN COAST)
REF 1F
8
0.6V RSIN 10
P REG3 20 1.0V 1F
1.8 N N
1.8
17 DR1
18 DR2IN
19 DR2
16 DRGND
15 AGND
Figure 1. MAX769 Block Diagram
8 _______________________________________________________________________________________
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC
_______________Detailed Description
The MAX769 contains several functional blocks that simplify the integration of power-supply and monitoring functions within a 2 or 3-cell powered system. They are described in the following subsections. REG1 output clamps at 3.3V. This arrangement limits VREG1 to an acceptable voltage for logic when OUT is programmed to a higher voltage (typically >4V) for charging (see Charger Circuit and Backup Linear Regulator sections).
MAX769
Voltage Regulators
Regulator outputs include the following: * OUT: Main switch-mode buck/boost output * REG1: 1.5 switch and output voltage clamp. Switches REG1 to OUT and clamps REG1 at 3.3V when OUT is set to 3.4V or more. * REG2: Linear-regulated, 24mA low-noise output that regulates so that VOUT - VREG2 is a set difference voltage (10A x ROFS). Output peak-to-peak ripple is typically 2mV with a 10F bypass capacitor at REG2. REG2 clamps the output at 3.3V when OUT is set to 3.4V or more. * REG3: Low-noise, 1V linear regulator that supplies 2mA.
Low-Noise Analog Supply (REG2) REG2 is a linear, 24mA low-dropout regulating circuit whose input is R2IN. The REG2 output (VREG2) is set by ROFS. ROFS does not set an absolute voltage, but rather an offset level from R2IN (Figure 2). VREG2 is set by: VREG2 = VR2IN - 10A x ROFS
Typically R2IN and R OFS are tied to OUT, in which case: VOUT - VREG2 = 10A x ROFS ROFS adjusts V REG1 - V REG2 to allow REG2 noise rejection to be traded for voltage drop and consequent efficiency loss. A 15k (typical) R OFS value sets a 150mV voltage difference. R2IN is typically supplied from OUT or REG1, but can be connected elsewhere as long as the voltage applied to R2IN does not exceed VOUT. For lowest output noise on REG2, connect R2IN to REG1. Note that the REG2 output also clamps at 3.3V when OUT is set to 3.4V or higher.
Main DC-DC Boost Converter (OUT) OUT is the main DC-DC converter's output. It supplies current from the internal synchronous-rectified buck/ boost regulator and needs no external FETs or voltagesetting resistors. The output voltage (VOUT) is adjusted from 1.8V to 4.9V in 100mV steps (Tables 1 and 5) by internal DAC control using a serial-data command. OUT can supply up to 80mA, less the current supplied to the other regulators (REG1, REG2, and REG3).
OUT can also be put into a low-current, pulse-skipping Coast Mode (13A typical quiescent current) by resetting the RUN/COAST serial input bit. OUT supplies up to 40mA in Coast Mode. Typically, when changing from Run to Coast Mode, a lower OUT voltage is also set (Table 4) to further reduce system operating current. The extent of this reduction depends on the minimum operating voltage of the system components when they are in standby or sleep states. OUT can be set as low as 1.8V; however, some Run Mode functions are limited when VOUT is below 2.5V: * The allowed serial-interface clock rate is reduced. * Internal LX FET and DR1 and DR2 on-resistance increases.
Low-Noise, 1V Analog Supply (REG3) REG3 is a 1V, low-noise linear regulator that supplies up to 2mA. REG3's input is internally connected to REG2.
PWM Frequency Synchronization
The DC-DC converter switching frequency in pulsewidth-modulation (PWM) mode is nominally 270kHz if no synchronization clock is supplied and FILT is tied to REF. If the PLL is used, a filter network is connected to FILT, a clock is applied to SYNC, and the internal oscillator locks to seven times the input clock rate. The MAX769 is designed for a 38.4kHz SYNC input and hence a 268.8kHz operating frequency. PWM switching frequency is unaffected by the serial-data clock rate.
Voltage Detectors (LBO and Reset)
The MAX769 contains two voltage-detector inputs: LBI and RSIN. The LBI and RSIN comparator outputs are open-drain pins (LBO and RSO) for a real-time hardware output. LBO is also readable via the serial interface. Both LBI and RSIN trigger at a 0.6V input threshold and have about 18mV hysteresis. RSO also triggers the MAX769 internal power-on reset (POR).
Logic Supply (REG1) REG1 is not a regulator in the conventional sense, but rather a 1.5 PFET that acts as either a switch or a voltage clamp, depending on the programmed OUT voltage. When OUT is set to 3.3V or less, REG1 operates as a switch. When OUT is set to 3.4V or more, the
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9
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769
2 OR 3-CELL AA ALKALINE BATTERY
C5 22F 26 BATT 1 LX1 LX2 OUT PGND 28 25 4 24
L1 68H
D1 MBR0520L
R1 1M 11 REG1 R5 270k 6 A/D IN 9 27 5 2 3 17 19 18 16 LBO CH0 CS SCL SDI SDO DR1 DR2 DR2IN DRGND R2 250k LBI
C1 47F 3.0V LOGIC
C6 0.1F
REG1
MAX769
R2IN OFS
C2 10F 22 14 COFS 0.1F 21 C3 10F ROFS, 15k
SERIAL I/O
1.8 DRIVERS
REG2
2.85V ANALOG 1V RCVR R3 1.3M
REG3
20 C4 1F 10 7 23 TO RF PA TO C RESET 3-CELL NiCd 100k
38.4kHz C10 22nF 10k
13 12 C9 1nF 8 C8 1F
SYNC FILT
RSIN RSO NICD
R4 470k
REF AGND 15
Figure 2. Standard Application Circuit
7-Bit ADC (CH0 Input and CH1, CH2)
Three analog channels are compared to a 7-bit, serially programmed digital-to-analog converter (CH DAC). The CH DAC voltage can be varied in 10mV steps from 200mV to VREF - 1LSB (or 1.27V) (Table 1). CH0 is an external input, while CH1 and CH2 are signals internally generated from the NICD and BATT pins. NICD and BATT are internally divided by four before being compared to CH DAC. The comparison threshold voltages for each channel are described in the following equations: VTH (CH0: pin 9) = D x 10mV VTH (CH1: NICD) = D x 40mV VTH (CH2: BATT) = D x 40mV
where D is the decimal equivalent of the binary code DAC0-DAC6 (Table 1). DAC0 is the LSB. A DAC code of 1111111 equates to D = 127. When all zeros are programmed, the CH DAC and CH_ comparators turn off. CH0, CH1, and CH2 comparison results reside in the three MSB locations of the output serial data (Table 4). The CH_ OUT data is delayed by one read cycle. In other words, each CH_ OUT bit is the result of the comparison made against the CH DAC voltage programmed during the previous serial-write operation. An analog-to-digital (A/D) conversion can be performed on a channel by using the system software to step through a successive-approximation routine or, if the input is partially known, by setting the CH DAC to a voltage near the estimated point and checking successive CH_ OUT bits.
10
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC
A faster A/D shortcut can be used for battery measurements when the goal is a "go, no go" determination. For this type of test, the CH DAC can simply be set to the desired limit, and CH_ OUT supplies the result on the next serial-write operation. One instance in which this shortcut saves time is during a battery-impedance check. The unloaded battery voltage can first be measured, if time allows, using one of the techniques described in the previous paragraph. Then the magnitude of the loaded voltage drop can be quickly checked with a single comparison to see if it is within the desired limit. The A/D circuitry can be invoked in both Run and Coast Modes. Functions that can be programmed on or off in Coast Mode are (Table 1): * DR1 and DR2 * REG2 and REG3 * NICD charger (Note: This may overload OUT if turned on in Coast Mode when other loads are present) * Backup regulator * CH0, CH1, CH2, and CH DAC Functions that always turn off in Coast Mode are: * SYNC and PLL circuits * DC-DC PWM control circuits
MAX769
Open-Drain Drivers
Two open-drain drivers (DR1 and DR2) are activated via the serial interface. DR1 and DR2 are grounded 1.8 (typical) NFETs that can sink up to 120mA. The maximum sink current is limited by on-resistance and package dissipation to about 240mA total sink current for both switches. Note that DR1 and DR2 are designed to sink current only from the main battery (BATT) and cannot be pulled above BATT. DR2 is controlled by an external input (DR2IN) as well as a serial input bit. DR2IN is ANDed with the DR2ON serialcontrol bit, allowing DR2 to drive an audio beeper. The audio-frequency clock is applied to DR2IN, and ON/OFF gating is applied to DR2ON. Both DR2IN (pin 18) and DR2ON (serial bit) must be high for DR2 to switch on.
Power-On Reset
The MAX769 has an internal POR circuit (VOUT < 1.6V) to ensure an orderly power-up when a battery is first applied. This feature is separate from the RSO comparator; however, if RSO goes low during operation, all serial registers are set to the same predetermined states as on power-up. The POR states for each register are listed in Table 2. Note that the MAX769 always comes out of reset in Coast Mode; consequently, it cannot supply full power until Run Mode is selected by serial command. System software cannot exercise full load current until Run Mode is enabled.
Charger Circuit
A charger current source from OUT to NICD is activated via a serial bit (Table 1). The current source can charge a small 3-cell NiCd or NiMH battery (typically a coin cell) or a 1-cell lithium battery. The charge current can be set to either 15mA or 1mA. OUT sets the maximum charge (or float) voltage. When charging is implemented, VOUT must also be set high enough to allow sufficient headroom for the charger current source. The VOUT - VNICD difference should normally be between 0.2V and 0.5V. Charger current vs. NICD voltage is graphed in the Typical Operating Characteristics. Note also that charging current reduces the OUT current available for other loads.
Coast Mode/Voltage Selection
Reduce the operating current by setting the RUN/COAST bit low via the serial input. This shifts the DC-DC boost converter from low-noise PWM operation (Run Mode) to a very low operating current mode (Coast Mode) in which switching pulses are only provided as needed to satisfy the load. To further reduce operating current in Coast Mode, lower VOUT using the OV0-OV4 serial bits. The MAX769 starts up in Coast Mode. Select Run Mode with the serial interface after power-up. Various circuit functions can be disabled as follows: Functions that always remain on in Coast Mode are: * * * * * Serial I/O Reference (REF) OUT REG1 LBI, RSIN (and LBO, RSO)
Backup Linear Regulator
The BACKUP serial input bit turns on the backup regulator, which sources current from NICD to OUT. This regulator backs up OUT by using the rechargeable battery (at NICD) when the main battery (at BATT) is depleted or removed. The backup regulator pass device's resistance is typically 5, so it can typically supply 20mA with only 100mV of dropout.
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11
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769
Table 1. Serial-Bit Assignments
R2 (MSB) 0 0 0 0 1 R1 0 0 1 1 DAC6 R0 0 1 0 1 DAC5 D4 DR2_ON X OV4 X DAC4 D3 DR1_ON LBO_Sets_ BACKUP OV3 X DAC3 D2 REG3_ON BACKUP OV2 X DAC2 D1 REG2_ON 15mA_CHG OV1 X DAC1 D0 RUN/ COAST 1mA_CHG OV0 X DAC0
Table 2. Serial-Bit Power-On Reset (POR) States
R2 0 0 0 0 1 R1 0 0 1 1 POR = 0 R0 0 1 0 1 POR = 0 D4 POR = 0 X POR = 0 X POR = 0 D3 POR = 0 POR = 0 POR = 1 X POR = 0 D2 POR = 0 POR = 0 POR = 1 X POR = 0 D1 POR = 0 POR = 0 POR = 0 X POR = 0 D0 POR = 0 POR = 0 POR = 0 X POR = 0
Table 3. Input-Bit Function Description
INPUT BIT RUN/COAST REG2_ON, REG3_ON DR1, DR2 1mA_CHG, 15mA_CHG FUNCTION 1 = Run Mode, 0 = Coast Mode (POR state is Coast Mode). 1 = Turns on the selected regulator (POR state is off). 1 = Turns on the selected switch (POR state is off). 1 = Turns on the selected charge current to NICD. If both are set, the charge current is 15mA (POR state is off). 1 = Turns on the backup linear regulator from NICD to OUT and disables the DC-DC converter (POR state is BACKUP off). Setting this bit overrides 1mA_CHG, 15mA_CHG, and LBO_Sets_BACKUP (Figure 1). 1 = Allows LBO to turn on the backup regulator and disable the DC-DC converter (POR state is no connection between LBO and BACKUP). Sets OUT Output Voltage (POR state is VOUT = 3.0V). Sets 7-bit CH DAC voltage for A/D conversion (POR state is all zeros with DAC and comparators off).
BACKUP
LBO_Sets_BACKUP OV0-OV4 DAC0-DAC6
Table 4. Serial Output Data
D7 (MSB) D6 D5 D4 D3-D0 FUNCTION CH_OUT and LBO output bits. A 1 indicates that the selected channel (CH_) voltage is greater than the CH DAC voltage or that LBI is less than 0.6V.
CH2_OUT
CH1_OUT
CH0_OUT
LBO
X
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC
Table 5. VOUT Output Voltage
SERIAL-DATA BIT OV4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OV3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OV2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
LBO LBO_SETS_BACKUP TO BACKUP REGULATOR BACKUP 1mA_CHG 15mA_CHG TO CHARGER CONTROL
VOUT (V)
All DC-DC converter and charging circuitry is disabled when the backup regulator is turned on, but all other functions remain active. Activate BACKUP manually or by serial command, or set it to trigger automatically via LBO.
MAX769
Automatic Backup
Setting the LBO_Sets_BACKUP serial bit (Table 1) programs the IC so that when LBO goes low, the backup regulator automatically turns on without instructions from the microprocessor (P). When the LBO_Sets_BACKUP bit is 0, the backup regulator is turned on only by setting the BACKUP bit. The BACKUP bit also overrides the LBO_Sets_BACKUP bit. Figure 3 shows the logic for this function. If the main battery is depleted and the NiCd battery is drained during backup, RSO goes low while the backup regulator is supplying OUT (if RSI is used to monitor OUT or REG1). When RSO falls, the serial registers reset to their POR states (with the DC-DC converter on in Coast Mode and the backup regulator off, see Tables 1, 2, and 3). This prevents the IC from getting hung up with the DC-DC converter off when a new main battery is inserted. This sequence is required because if the MAX769 did not default to "DC-DC converter on" when coming out of reset, the P (still reset by RSO) would not be able to provide the device with serial instructions to turn on.
Serial Interface
The MAX769 has an SPI-compatible serial interface. The serial-interface lines are Chip Select (CS), Serial Clock (SCL), Serial Data In (SDI), and Serial Data Out (SDO). Serial input data is arranged in 8-bit bytes. Most bytes contain a 3-bit address pointer (R2, R1, R0) along with 5 bits of input data (D4-D0). For common operations such as selecting Run or Coast Mode, activating REG2 or REG3, or turning on DR1 or DR2, only the 000 (R2, R1, R0) address register needs to be written. The serial input data format for all MAX769 operations is outlined in Tables 1, 2, and 3.
Figure 3. Logic for Charger Control and BACKUP and for LBO_Sets_BACKUP Serial Input Bits
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC
Serial data is clocked in and out MSB first. Input data is latched on the CLK rising edge, and output data is shifted out on the CLK falling edge. When CS goes low, DO immediately contains the MSB output bit (D7). D6 is not clocked out until the falling clock edge that follows the first rising clock edge after a Chip Select. See the timing diagrams in Figures 4 and 5. SPI writes and reads concurrently, so it may be necessary to perform dummy writes in order to read output data. Four output data bits (D7-D4, Table 4) are sent from SDO each time a serial operation occurs.
MAX769
When R2 = 0, R0 and R1 are address pointers. However, when R2 = 1, the 7 remaining bits (R1, R0 and D4-D0) become DAC programming bits. This violation of programming etiquette (R1 and R0 are sometimes address bits and other times data bits) allows the CH DAC to be loaded with only one write operation. Writing all zeros to the CH DAC turns it, the CH0, CH1, and CH2 comparators, and the NICD and BATT voltage-sensing resistors off to minimize current consumption. This reduces current drain from OUT by about 30A.
CS
***
tCSH SCLK
tCSS
tCL
tCH
tCSH
*** tDS tDH
DIN tDV DOUT
*** tDO *** tTR
Figure 4. Detailed Serial-Interface Timing
CS
SCL
SCO
D7
D6
D5
D4
0
0
0
0
SDI
R2
R1
R0
D4
D3
D2
D1
D0
Figure 5. CS, SCL, SDO, and SDI Serial Timing
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC
Applications Information
Component Selection
The MAX769 requires minimal design calculation and is optimized for the component values shown in Figure 2. However, some flexibility in component selection is still allowed, as described in the following text. A list of suitable components is provided in Table 6. Inductor L1 is nominally 68H, but values from 47H to 100H should be satisfactory. The inductor current rating should be 300mA or more if full output current (80mA) is needed. If less output current is required, the inductor current rating can be reduced proportionally but should never be less than 150mA. Inductor resistance should be minimized for best efficiency, but since the MAX769 N-channel switch resistance is typically 0.9, efficiency does not improve significantly for coil resistances below 0.4. Filter capacitors C1-C4 should be low-ESR types (tantalum or ceramic) for lowest ripple and best noise rejection. The values shown in Figure 2 are optimized for each output's rated current. Lower required output current allows smaller capacitance values. Resistors at the LBI and RSIN inputs set the voltage at which the LBO and RSO outputs trigger. The voltage threshold for both LBI and RSI is 0.6V. The resistors required to set a desired trip voltage, (Figure 2) VTRIP, are calculated by: R1 = R2[(VTRIP(LBO) / 0.6) - 1] R3 = R4[(VTRIP(LBO) / 0.6) - 1] To minimize battery drain, use large values for R2 and R4 (>100k) in the above equations; 470k is a good starting value. See the Low-Noise Analog Supply (REG2) section for information on selecting ROFS. Since LBO and RSO are open-drain outputs, pull-up resistors are usually required. Normally these will be pulled up to REG1. 100k is recommended as a compromise between response time and current drain, although other values can be used. Since LBI and RSO are high (open circuit) during normal operation, current normally does not flow in the pull-up resistors until a low-battery or reset event occurs. from external logic (or a P) powered from REG1, or by open-drain logic devices that are pulled up to REG1.
MAX769
Board Layout and Noise Reduction
The MAX769 makes every effort in its internal design to minimize noise and EMI. Nevertheless, prudent layout practices are still suggested for best performance. Recommendations are as follows: 1) Keep trace lengths at L1, LX1, and LX2, as well as at PGND, as short and wide as possible. Since LX1 and LX2 toggle between VBATT and VOUT at a fast rate, minimizing the trace length serves to reduce excess PC board area that might act as an antenna. 2) Place the filter capacitors at OUT, REG1, REG2, and REG3 as close to their respective pins as possible (no more than 0.5mm away). 3) Consider using an inductor at L1. A shielded inductor at L1 will minimize radiated noise, but may not be essential. Toroids will also exhibit EMI performance similar to that of shielded coils. 4) Keep the power components at the uppermost part of the IC to minimize coupling to other parts of the circuit. The LX1, LX2, OUT, and PGND pins are located at the uppermost part of the IC to facilitate PC board layout. Other pins in this area are digital and are not affected by close proximity to switching nodes. 5) Use a separate short, wide ground trace for PGND and the ground side of the BATT and OUT filter capacitors. Tie this trace to the ground plane.
Table 6. External Components
SUPPLIER INDUCTORS (68H) Coilcraft Murata DT1608C-223, DT1608C-683 LQH4N680K CD54-680 Sumida CDR74B-680 CD73-680 CAPACITORS AVX Marcon Sprague TDK Polystor TPS series THCR series 595D series C3216 series A-10300 Tantalum Ceramic Tantalum Ceramic 1.5 Farads 15 0.58, 3.18mm high, shielded 1.9, 2.6mm high, low current, low cost 0.46, 4.5mm high 0.33, 4.5mm high, shielded 0.33, 3.5mm high PART NO. COMMENTS
Logic Levels
Note that since the MAX769's internal logic is powered from REG1, the input logic levels at the digital inputs (DR2IN, RUN, SYNC, CS, and SDI) as well as the logic output level of SDO are governed by the voltage at REG1. Logic-high inputs at these pins should not exceed VREG1. Digital inputs should either be driven
STORAGE CAPACITOR (optional at NICD pin)
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2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769
Pin Configuration
TOP VIEW
LX1 1 SDI 2 SDO 3 PGND 4 SCL 5 LBO 6 RSO 7 REF 8 CH0 9 RSIN 10 LBI 11 FILT 12 SYNC 13 OFS 14 28 LX2 27 CS 26 BATT 25 OUT 24 REG1
MAX769
23 NICD 22 R2IN 21 REG2 20 REG3 19 DR2 18 DR2IN 17 DR1 16 DRGND 15 AGND
QSOP
________________________________________________________Package Information
QSOP.EPS
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