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| S3C72N8/P72N8/C72N5/P72N5 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C72N8/C72N5 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C72N8/C72N5 offer an excellent design solution for a wide variety of applications that require LCD functions. Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to internal and external events. In addition, the S3C72N8/C72N5's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C72N8/C72N5 microcontroller is also available in OTP (One Time Programmable) version, S3P72N8/P72N5. S3P72N8/P72N5 microcontroller has an on-chip 8/16-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P72N8/P72N5 is comparable to S3C72N8/C72N5, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C72N8/P72N8/C72N5/P72N5 FEATURES Memory - - - 512 x 4-bit RAM 8 K x 8-bit ROM (S3C72N8/P72N8) 16 K x 8-bit ROM (S3C72N5/P72N5) Bit Sequential Carrier - Support 16-bit serial data transfer in arbitrary format Interrupts - - - Three internal vectored interrupts Three external vectored interrupts Two quasi-interrupts I/O Pins - - - Input only: 8 pins I/O: 24 pins Output: 8 pins sharing with segment driver outputs Memory-Mapped I/O Structure - Data memory bank 15 LCD Controller/Driver - - - Maximum 16-digit LCD direct drive capability 32 segment, 4 common pins Display modes: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) Two Power-Down Modes - - Idle mode (only CPU clock stops) Stop mode (main or sub system oscillation stops) 8-Bit Basic Timer - - Programmable interval timer Watchdog timer Oscillation Sources - - - - - Crystal, ceramic, or RC for main system clock Crystal or external oscillator for subsystem clock Main system clock frequency: 4.19 MHz (typical) Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8, or 64) 8-Bit Timer/Counter 0 - - - - Programmable 8-bit timer External event counter Arbitrary clock frequency output Serial I/O interface clock generator Instruction Execution Times - - 0.95, 1.91, 15.3 s at 4.19 MHz (main) 122 s at 32.768 kHz (subsystem) Watch Timer - - - Real-time and interval time measurement Four frequency outputs to BUZ pin Clock source generation for LCD Operating Temperature - - 40 C to 85 C 8-Bit Serial I/O Interface - - - - 8-bit transmit/receive mode 8-bit receive only mode LSB-first or MSB-first transmission selectable Internal or external clock source Operating Voltage Range - 1.8 V to 5.5 V Package Type - 80-pin QFP 1-2 S3C72N8/P72N8/C72N5/P72N5 PRODUCT OVERVIEW BLOCK DIAGRAM Watchdog Timer Basic Timer Watch Timer P2.3/BUZ INT0, INT1, INT2 P1.3/TCL0 P2.0/TCLO0 8-Bit Timer/ Counter 0 RESET XIN XOUT XTIN XTOUT LCD Driver/ Controller Interrupt Control Block I/O Port 4 I/O Port 5 Internal Interrupts Clock Instruction Register 4-Bit Accumulator Program Counter Program Status Word Flags Bias VLC0-VLC2 LCDCK/P3.0 LCDSY/P3.1 COM0-COM3 SEG0-SEG23 P8.0-P8.7/ SEG24-SEG31 P0.0/INT4 P0.1/SCK P0.2/SO P0.3/SI P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 P3.3 P4.0-P4.3 P5.0-P5.3 I/O Port 0 P6.0-P6.3/ KS0-KS3 P7.0-P7.3/ KS4-KS7 I/O Port 6 I/O Port 7 Instruction Decoder Arithmetic and Logic Unit I/O Port 1 I/O Port 2 Stack Pointer I/O Port 3 P8.0-P8.7/ SEG24-SEG31 I/O Port 8 512 x 4-Bit Data Memory 8/16-Kbyte Program Memory Serial I/O Port P0.1 P0.2 P0.3 /SCK /SO /SI Figure 1-1. S3C72N8/C72N5 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C72N8/P72N8/C72N5/P72N5 PIN ASSIGNMENTS SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SEG19 SEG20 SEG21 SEG22 SEG23 P8.0/SEG24 P8.1/SEG25 P8.2/SEG26 P8.3/SEG27 P8.4/SEG28 P8.5/SEG29 P8.6/SEG30 P8.7/SEG31 P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0.0/INT4 P0.1/SCK P0.2/SO P0.3/SI P1.0/INT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3C72N8/C72N5 (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Figure 1-2. S3C72N8/C72N5 80-QFP Pin Assignment Diagram 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P5.0 P4.3 P4.2 P4.1 P4.0 P3.3 P3.2 P3.1/LCDSY P3.0/LCDCK P2.3/BUZ P2.2/CLO P2.1 P2.0/TCLO0 P1.3/TCL0 P1.2/INT2 P1.1/INT1 1-4 S3C72N8/P72N8/C72N5/P72N5 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C72N8/C72N5 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0- P4.3 P5.0- P5.3 P6.0- P6.3 P7.0- P7.3 Pin Type I I/O I/O I I Description 4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable. 4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. 4-bit I/O ports. N-channel open-drain output up to 5 V. 1-, 4-, and 8-bit read/write and test are possible. Ports 4 and 5 can be paired to support 8-bit data transfer. 4-bit pull-up resistors are software assignable. 4-bit I/O ports. Port 6 pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable. Ports 6 and 7 can be paired to enable 8-bit data transfer. Output port for 1-bit data (for use as CMOS driver only) LCD segment signal output LCD segment signal output LCD common signal output LCD power supply. Voltage dividing resistors are assignable by mask option LCD power control LCD clock output for display expansion Number 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-43 Share Pin INT4 SCK Reset Value Input Circuit Type A-1 D* D* A-1 A-1 SO SI INT0 INT1 INT2 TCL0 TCLO0 - CLO BUZ LCDCK LCDSY Input I/O Input D I/O Input D I/O - Input E I/O 44-51 KS0-KS3 KS4-KS7 Input D* P8.0- P8.7 SEG0- SEG23 SEG24- SEG31 COM0- COM3 VLC0-VLC2 BIAS LCDCK O O O O - - I/O 59-52 3-1, 80-60 59-52 4-7 9-11 8 32 SEG24- SEG31 - P8.0-P8.7 - SCLK SDAT - P3.0 Output Output Output Output - - Input H-16 H-15 H-16 H-15 - - D 1-5 PRODUCT OVERVIEW S3C72N8/P72N8/C72N5/P72N5 Table 1-1. S3C72N8/C72N5 Pin Descriptions (Continued) Pin Name LCDSY TCL0 TCLO0 SI SO SCK Pin Type I/O I/O I/O I I/O I/O I Description LCD synchronization clock output for LCD display expansion External clock input for timer/counter 0 Timer/counter 0 clock output Serial interface data input Serial interface data output Serial I/O interface clock signal External interrupts. The triggering edge for INT0 and INT1 is selectable. Only INT0 is synchronized with the system clock. Quasi-interrupt with detection of rising edge signals. External interrupt input with detection of rising or falling edge Quasi-interrupt inputs with falling edge detection. CPU clock output 2, 4, 8 or 16 kHz frequency output for buzzer sound with 4.19 MHz main system clock or 32.768 kHz subsystem clock. Crystal, ceramic or RC oscillator pins for main system clock. (For external clock input, use XIN and input XIN`s reverse phase to XOUT) Crystal oscillator pins for subsystem clock. (For external clock input, use XTIN and input XTIN's reverse phase to XTOUT) Main power supply Ground Reset signal Test signal input (must be connected to VSS) Number 33 27 28 23 22 21 24 25 26 20 44-51 30 31 Share Pin P3.1 P1.3 P2.0 P0.3 P0.2 P0.1 P1.0 P1.1 P1.2 P0.0 P6.0-P7.3 P2.2 P2.3 Reset Value Input Input Input Input Input Input Input Circuit Type D A-1 D A-1 D* D* A-1 INT0 INT1 INT2 INT4 KS0-KS7 CLO BUZ I I I/O I/O I/O Input Input Input Input Input A-1 A-1 D* D D XIN, XOUT XTIN, XTOUT VDD VSS RESET - 15,14 - - - - 17,18 - - - - - - - 12 13 19 16 - - - - - - Input - - - B - TEST NOTES: 1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode. 2. D * Type has a schmitt trigger circuit at input. 1-6 S3C72N8/P72N8/C72N5/P72N5 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD Pull-Up Resistor In P-Channel In N-Channel Schmitt Trigger Figure 1-3. Pin Circuit Type A Figure 1-5. Pin Circuit Type B (RESET RESET) VDD Pull-Up Resistor P-Channel Pull-Up Resistor Enable Data VDD P-Channel Out In Schmitt Trigger Output Disable N-Channel Figure 1-4. Pin Circuit Type A-1 (P1, P0.0, P0.3) Figure 1-6. Pin Circuit Type C 1-7 PRODUCT OVERVIEW S3C72N8/P72N8/C72N5/P72N5 VDD Pull-up Resistor Resistor Enable Data Output Disable P-Channel Circuit Type C I/O Circuit Type A Figure 1-7. Pin Circuit Type D (P0.1, P0.2, P2, P3, P6, P7) VDD PNE Pull-up Resistor Resistor Enable P-CH Data Output Enable N-CH I/O VDD Circuit Type A Figure 1-8. Pin Circuit Type E (P4, P5) 1-8 S3C72N8/P72N8/C72N5/P72N5 PRODUCT OVERVIEW VLC0 VLC1 LCD Segment / Common Data Out VLC2 Figure 1-9. Pin Circuit Type H-15 (SEG/COM) VDD VLC0 VLC1 LCD Segment & Port 8 Data Out VLC2 Figure 1-10. Pin Circuit Type H-16 (P8) 1-9 PRODUCT OVERVIEW S3C72N8/P72N8/C72N5/P72N5 NOTES 1-10 S3C72N8/P72N8/C72N5/P72N5 ELECTRICAL DATA 14 OVERVIEW ELECTRICAL DATA In this section, information on S3C72N8/C72N5 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request 14-1 ELECTRICAL DATA S3C72N8/P72N8/C72N5/P72N5 Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL All I/O ports - One I/O pin active All I/O ports active Output Current Low One I/O pin active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 (Peak value) + 15 (note) Total value for ports 0, 2, 3, and 5 Total value for ports 4, 6, and 7 Operating Temperature Storage Temperature TA Tstg - - + 100 (Peak value) + 60 (note) + 100 + 60 (note) - 40 to + 85 - 65 to + 150 Duty . C Units V mA NOTE: The values for Output Current Low (IOL) are calculated as Peak Value x Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions All input pins except those specified below for VIH2, VIH3 Ports 0, 1, 6, 7 and RESET XIN, XOUT, XTIN and XTOUT Ports 2, 3, 4 and 5 Ports 0, 1, 6, 7 and RESET XIN, XOUT, XTIN and XTOUT VDD = 4.5 V to 5.5 V Ports 0, 2, 3, 4, 5, 6, 7 and BIAS IOH = - 1 mA VDD = 4.5 V to 5.5 V Port 8 ONLY IOH = - 100 A Min 0.7 VDD 0.8 VDD VDD - 0.1 - - - VDD - 1.0 Typ - - - - - - - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V VOH2 VDD - 2.0 - - 14-2 S3C72N8/P72N8/C72N5/P72N5 ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output low voltage Symbol VOL1 VOL2 Input high leakage current ILIH1 Conditions VDD = 4.5 V to 5.5 V, Ports 0, 2-7 IOL = 15 mA VDD = 4.5 V to 5.5 V, Port 8 only IOL = 100 A VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT, XTIN and XTOUT VIN = 0 V All input pins except XIN, XOUT, XTIN and XTOUT VIN = 0 V XIN, XOUT, XTIN and XTOUT VOUT = VDD All output pins VOUT = 0 V All output pins Ports 0-7 VIN = 0 V; VDD = 5 V VDD = 3 V RL2 RLCD VIN = 0 V; VDD = 5 V, RESET VDD = 3 V LCD voltage dividing resistor COM output impedance SEG output impedance COM output voltage deviation SEG output voltage deviation VDC RSEG TA = 25 C 25 50 100 200 50 47 95 220 450 93 - - Min - - - Typ 0.4 - - Max 2 1 3 A Units V ILIH2 Input low leakage current ILIL1 - - - - 20 -3 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH1 - 20 3 A ILOL -3 RL1 100 200 400 800 140 K RCOM VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V (VLC0 - COMi) Io = 15uA (I = 0-3) - 3 5 3 5 45 6 15 6 15 90 mV - VDS VDD = 5 V (VLC0-SEGi) Io = 15A (I = 0-31) - n 45 n 90 mV 14-3 ELECTRICAL DATA S3C72N8/P72N8/C72N5/P72N5 Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter VLC0 Output voltage VLC1 Output voltage VLC2 Output voltage Supply Current (1) Symbol VLC0 VLC1 VLC2 IDD1 (2) TA = 25 oC TA = 25 oC TA = 25 oC Main operating: VDD = 5 V 10% CPU = fx/4 SCMOD = 0000B crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% Main Idle mode; VDD = 5 V 10% CPU = fx/4 SCMOD = 0000B crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% 6.0 MHz 4.19 MHz Conditions Min 0.6 VDD - 0.2 0.4 VDD - 0.2 0.2 VDD - 0.2 - Typ 0.6 VDD 0.4 VDD 0.2 VDD 3.5 2.5 Max 0.6 VDD + 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2 8 5.5 Units V mA IDD2 (2) 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz - 1.6 1.2 1.0 0.9 4 3 2.5 2.0 6.0 MHz 4.19 MHz - IDD3 IDD4 IDD5 IDD6 (3) Sub operating: VDD = 3 V 10% CPU = fxt/4 SCMOD = 1001B 32 kHz crystal oscillator Sub Idle mode; VDD = 3 V 10% CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Stop mode; VDD = 5 V 10%, XTIN = 0 V CPU = fxt/4, SCMOD = 0000B Stop mode; VDD = 5 V 10% CPU = fx/4, SCMOD = 0100B 0.5 0.4 15 1.0 0.8 30 A - 6 15 - 2.5 5 - 0.5 3 NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors and through LCD voltage dividing resistors. 2. Data includes the power consumption for sub-system clock oscillation. 3. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The main-system clock oscillation stops by the STOP instruction. 14-4 S3C72N8/P72N8/C72N5/P72N5 ELECTRICAL DATA Table 14-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT Parameter Oscillation frequency (1) Test Condition - Min 0.4 Typ - Max 6.0 Units MHz C1 C2 Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range. - - - 4 ms Crystal Oscillator XIN XOUT Oscillation frequency (1) 0.4 - 6.0 MHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V - - 0.4 - - - 10 30 6.0 ms External Clock XIN XOUT XIN input frequency (1) - MHz XIN input high and low level width (tXH, tXL) RC Oscillator XIN R XOUT - VDD = 5 V R = 20 K, VDD = 5 V R = 38 K, VDD = 3 V 83.3 0.4 - - 2.0 1.0 - 2 ns MHz Frequency (1) NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 14-5 ELECTRICAL DATA S3C72N8/P72N8/C72N5/P72N5 Table 14-4. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillato r Crystal Oscillator Clock Configuration XTIN XTOUT Parameter Oscillation frequency (1) Test Condition - Min 32 Typ 32.768 Max 35 Units kHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V - - 32 1.0 - - 2 10 100 s External Clock XTIN XTOUT XTIN input frequency (1) - kHz XTIN input high and low level width (tXTL, tXTH) - 5 - 15 s NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs. Table 14-5. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF 14-6 S3C72N8/P72N8/C72N5/P72N5 ELECTRICAL DATA Table 14-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) TCL0 input frequency TCL0 input high, low width SCK cycle time Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V With subsystem clock (fxt) VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5V VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source Min 0.67 0.95 114 0 0.48 1.8 800 650 3200 3800 400 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 400 400 - Typ - - 122 - - - Max 64 64 125 1.5 1 - - Units s f TI0 tTIH0, tTIL0 tKCY MHz MHz s ns SCK high, low tKH, tKL - - ns width SI setup time to SCK high tSIK tKSI tKSO External SCK source Internal SCK source External SCK source Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source INT0 INT1, INT2, INT4, KS0-KS7 Input - - - - - 300 250 1000 1000 ns ns ns SI hold time to SCK high Output delay for SCK to SO Interrupt input high, low width RESET Input Low tINTH, tINTL tRSL (2) - - - - s s 10 10 Width NOTES: 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting. 14-7 ELECTRICAL DATA S3C72N8/P72N8/C72N5/P72N5 CPU Clock 1.5 MHz 1.0475 MHz 1.00 MHz 750 kHZ 500 kHZ 250 kHZ Main Oscillator Frequency 6 MHz 4.19 MHz 3 MHz 15.6 kHz 1 2 1.8 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8, 64) 3 4 5 6 7 Figure 14-1. Standard Operating Voltage Range Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions Normal operation VDDDR = 1.8 V Normal operation Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx (2) Max 6.5 10 - - - Unit V A s ms NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 14-8 S3C72N8/P72N8/C72N5/P72N5 ELECTRICAL DATA TIMING WAVEFORMS Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Normal Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instrction RESET tWAIT tSREL Figure 14-2. Stop Mode Release Timing When Initiated By RESET Idle Mode ~ ~ ~ ~ Stop Mode Data Retention Mode Normal Mode VDD VDDDR Execution of STOP Instrction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request 14-9 ELECTRICAL DATA S3C72N8/P72N8/C72N5/P72N5 0.8 VDD Measurement Points 0.2 VDD 0.8 VDD 0.2 VDD Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 14-5. Clock Timing Measurement at XIN 1/fxt tXTL tXTH XTIN VDD - 0.1 V 0.1 V Figure 14-6. Clock Timing Measurement at XTIN 14-10 S3C72N8/P72N8/C72N5/P72N5 ELECTRICAL DATA 1/fTI0 tTIL0 tTIH0 TCL0 0.8 VDD 0.2 VDD Figure 14-7. TCL0 Timing tRSL RESET 0.2 VDD Figure 14-8. Input Timing for RESET Signal tINTL tINTH INT0, 1, 2, 4, K0 to K7 0.8 VDD 0.2 VDD Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts 14-11 ELECTRICAL DATA S3C72N8/P72N8/C72N5/P72N5 tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO tKH SO Output Data Figure 14-10. Serial Data Transfer Timing 14-12 S3C72N8/P72N8/C72N5/P72N5 MECHANICAL DATA 15 OVERVIEW -- Pad diagram MECHANICAL DATA This section contains the following information about the device package: -- Package dimensions in millimeters -- Pad/pin coordinate data table 15-1 MECHANICAL DATA S3C72N8/P72N8/C72N5/P72N5 23.90 0.30 20.00 0.20 0-8 + 0.10 0.15 - 0.05 14.00 0.20 17.90 0.30 80-QFP-1420C 0.80 0.20 #1 0.80 0.35 0.10 0.15 MAX (1.00) 0.10 MAX #80 0.05 MIN (0.80) 2.65 0.10 3.00 MAX 0.80 0.20 NOTE: Dimensions are in millimeters. Figure 15-1. 80-QFP-1420C Package Dimensions 15-2 S3C72N8/P72N8/C72N5/P72N5 S3P72N8/P72N5 OTP 16 OVERVIEW S3P72N8/P72N5 OTP The S3P72N8/P72N5 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72N8/C72N5 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The S3P72N8/P72N5 is fully compatible with the S3C72N8/C72N5, both in function and in pin configuration. Because of its simple programming requirements, the S3P72N8/P72N5 is ideal for use as an evaluation chip for the S3C72N8/C72N5. 16-1 S3P72N8/P72N5 OTP S3C72N8/P72N8/C72N5/P72N5 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SEG19 SEG20 SEG21 SEG22 SEG23 P8.0/SEG24 P8.1/SEG25 P8.2/SEG26 P8.3/SEG27 P8.4/SEG28 P8.5/SEG29 P8.6/SEG30 P8.7/SEG31 P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 BIAS VLC0 SDAT/VLC1 SCLK/VLC2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET P0.0/INT4 P0.1/SCK P0.2/SO P0.3/SI P1.0/INT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3P72N8 S3P72N5 (80-QFP-1420C) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Figure 16-1. S3P72N8/P72N5 Pin Assignments (80-QFP) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P5.0 P4.3 P4.2 P4.1 P4.0 P3.3 P3.2 P3.1/LCDSY P3.0/LCDCK P2.3/BUZ P2.2/CLO P2.1 P2.0/TCLO0 P1.3/TCL0 P1.2/INT2 P1.1/INT1 16-2 S3C72N8/P72N8/C72N5/P72N5 S3P72N8/P72N5 OTP Table 16-1. Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name VLC1 Pin Name SDAT Pin No. 10 I/O I/O During Programming Function Serial data pin. Output port when reading and input port when writing can be assigned as Input/push-pull output port respectively. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. VLC2 TEST SCLK VPP (TEST) 11 16 I/O I RESET VDD / VSS RESET VDD / VSS 19 12/13 I I Table 16-2. Comparison of S3P72N8/P72N5 and S3C72N8/C72N5 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P72N8/P72N5 8 K/16 K-byte EPROM 1.8 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 80 QFP User Program 1 time 80 QFP Programmed at the factory S3C72N8/C72N5 8 K/16-Kbyte mask ROM 1.8 V to 5.5 V - OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P72N8/P72N5, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5V 12.5V 12.5V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means low level; "1" means high level. 16-3 S3P72N8/P72N5 OTP S3C72N8/P72N8/C72N5/P72N5 Table 16-4. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL All I/O ports - One I/O pin active All I/O ports active Output Current Low One I/O pin active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 (Peak value) + 15 (note) Total value for ports 0, 2, 3, and 5 Total value for ports 4, 6, and 7 Operating Temperature Storage Temperature TA Tstg - - + 100 (Peak value) + 60 (note) + 100 + 60 (note) - 40 to + 85 - 65 to + 150 Duty . C Units V mA NOTE: The values for Output Current Low (IOL) are calculated as Peak Value x Table 16-5. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions All input pins except those specified below for VIH2, VIH3 Ports 0, 1, 6, 7 and RESET XIN, XOUT, XTIN and XTOUT Ports 2, 3, 4 and 5 Ports 0, 1, 6, 7 and RESET XIN, XOUT, XTIN and XTOUT VDD = 4.5 V to 5.5 V Ports 0, 2, 3, 4, 5, 6, 7 and BIAS IOH = - 1 mA VDD = 4.5 V to 5.5 V Port 8 ONLY IOH = - 100 A Min 0.7 VDD 0.8 VDD VDD - 0.1 - - - VDD - 1.0 Typ - - - - - - - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V VOH2 VDD - 2.0 - - 16-4 S3C72N8/P72N8/C72N5/P72N5 S3P72N8/P72N5 OTP Table 16-5. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output low voltage Symbol VOL1 VOL2 Input high leakage current ILIH1 Conditions VDD = 4.5 V to 5.5 V, Ports 0, 2-7 IOL = 15 mA VDD = 4.5 V to 5.5 V, Port 8 only IOL = 100 A VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT, XTIN and XTOUT VIN = 0 V All input pins except XIN, XOUT, XTIN and XTOUT VIN = 0 V XIN, XOUT, XTIN and XTOUT VOUT = VDD All output pins VOUT = 0 V All output pins Ports 0-7 VIN = 0 V; VDD = 5 V VDD = 3 V RL2 LCD voltage dividing resistor COM output impedance SEG output impedance COM output voltage deviation SEG output voltage deviation VDC RSEG RLCD VIN = 0 V; VDD = 5 V, RESET VDD = 3 V TA = 25 C VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V (VLC0-COMi) Io = 15uA (I = 0-3) VDS VDD = 5 V (VLC0-SEGi) Io = 15A (I = 0-31) - n 45 n 90 mV - 25 50 100 200 50 47 95 220 450 93 - - Min - - - Typ 0.4 - - Max 2 1 3 A Units V ILIH2 Input low leakage current ILIL1 - - - - 20 -3 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH1 - 20 3 A ILOL -3 RL1 100 200 400 800 140 K RCOM - 3 5 3 5 45 6 15 6 15 90 mV 16-5 S3P72N8/P72N5 OTP S3C72N8/P72N8/C72N5/P72N5 Table 16-5. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter VLC0 Output voltage VLC1 Output voltage VLC2 Output voltage Supply Current (1) Symbol VLC0 VLC1 VLC2 IDD1 (2) TA = 25 oC TA = 25 oC TA = 25 oC Main operating: VDD = 5 V 10% CPU = fx/4 SCMOD = 0000B crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% Main Idle mode; VDD = 5 V 10% CPU = fx/4 SCMOD = 0000B crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% 6.0 MHz 4.19 MHz Conditions Min 0.6 VDD - 0.2 0.4 VDD - 0.2 0.2 VDD - 0.2 - Typ 0.6 VDD 0.4 VDD 0.2 VDD 3.5 2.5 Max 0.6 VDD + 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2 8 5.5 Units V mA IDD2 (2) 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz - 1.6 1.2 1.0 0.9 4 3 2.5 2.0 6.0 MHz 4.19 MHz - IDD3 IDD4 IDD5 IDD6 (3) Sub operating: VDD = 3 V 10% CPU = fxt/4 SCMOD = 1001B 32 kHz crystal oscillator Sub Idle mode; VDD = 3 V 10% CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Stop mode; VDD = 5 V 10%, XTIN = 0 V CPU = fxt/4, SCMOD = 0000B Stop mode; VDD = 5 V 10% CPU = fx/4, SCMOD = 0100B 0.5 0.4 15 1.0 0.8 30 A - 6 15 - 2.5 5 - 0.5 3 NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors and 2. 3. through LCD voltage dividing resistors. Data includes the power consumption for sub-system clock oscillation. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The main-system clock oscillation stops by the STOP instruction. 16-6 S3C72N8/P72N8/C72N5/P72N5 S3P72N8/P72N5 OTP Table 16-6. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT Parameter Oscillation frequency (1) Test Condition - Min 0.4 Typ - Max 6.0 Units MHz C1 C2 Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range. - - - 4 ms Crystal Oscillator XIN XOUT Oscillation frequency (1) 0.4 - 6.0 MHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V - - 0.4 - - - 10 30 6.0 ms External Clock XIN XOUT XIN input frequency (1) - MHz XIN input high and low level width (tXH, tXL) RC Oscillator XIN R XOUT - VDD = 5 V R = 20 K, VDD = 5 V R = 38 K, VDD = 3 V 83.3 0.4 - - 2.0 1.0 - 2 ns MHz Frequency (1) NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 16-7 S3P72N8/P72N5 OTP S3C72N8/P72N8/C72N5/P72N5 Table 16-7. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration XTIN XTOUT Parameter Oscillation frequency (1) Test Condition - Min 32 Typ 32.768 Max 35 Units kHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V - - 32 1.0 - - 2 10 100 s External Clock XTIN XTOUT XTIN input frequency (1) - kHz XTIN input high and low level width (tXTL, tXTH) - 5 - 15 s NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs. Table 16-8. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF 16-8 S3C72N8/P72N8/C72N5/P72N5 S3P72N8/P72N5 OTP Table 16-9. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V With subsystem clock (fxt) Min 0.67 0.95 114 0 0.48 1.8 800 650 3200 3800 400 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 400 400 - Typ - - 122 - - - Max 64 64 125 1.5 1 - - Units s TCL0 input frequency TCL0 input high, low width SCK cycle time f TI0 tTIH0, tTIL0 tKCY VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5V VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source MHz MHz s ns SCK high, low tKH, tKL VDD = 1.8 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source - - ns width SI setup time to SCK high tSIK tKSI tKSO External SCK source Internal SCK source External SCK source Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source - - - - - 300 250 1000 1000 ns ns ns SI hold time to SCK high Output delay for SCK to SO Interrupt input high, low width RESET Input Low tINTH, tINTL tRSL INT0 INT1, INT2, INT4, KS0-KS7 Input (2) - - - - s s 10 10 Width NOTES: 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting. 16-9 S3P72N8/P72N5 OTP S3C72N8/P72N8/C72N5/P72N5 CPU Clock 1.5 MHz 1.0475 MHz 1.00 MHz 750 kHZ 500 kHZ 250 kHZ Main Oscillator Frequency 6 MHz 4.19 MHz 3 MHz 15.6 kHz 1 2 1.8 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8, 64) 3 4 5 6 7 Figure 16-2. Standard Operating Voltage Range Table 16-10. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions Normal operation VDDDR = 1.8 V Normal operation Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx (2) Max 6.5 10 - - - Unit V s s ms NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 16-10 S3C72N8/P72N8/C72N5/P72N5 S3P72N8/P72N5 OTP TIMING WAVEFORMS Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Normal Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instrction RESET tWAIT tSREL Figure 16-3. Stop Mode Release Timing When Initiated By RESET Idle Mode ~ ~ ~ ~ Stop Mode Data Retention Mode Normal Mode VDD VDDDR Execution of STOP Instrction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 16-4. Stop Mode Release Timing When Initiated By Interrupt Request 16-11 S3P72N8/P72N5 OTP S3C72N8/P72N8/C72N5/P72N5 0.8 VDD Measurement Points 0.2 VDD 0.8 VDD 0.2 VDD Figure 16-5. A.C. Timing Measurement Points (Except for XIN and XTIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 16-6. Clock Timing Measurement at XIN 1/fxt tXTL tXTH XTIN VDD - 0.1 V 0.1 V Figure 16-7. Clock Timing Measurement at XTIN 16-12 S3C72N8/P72N8/C72N5/P72N5 S3P72N8/P72N5 OTP 1/fTI0 tTIL0 tTIH0 TCL0 0.8 VDD 0.2 VDD Figure 16-8. TCL0 Timing tRSL RESET 0.2 VDD Figure 16-9. Input Timing for RESET Signal tINTL tINTH INT0, 1, 2, 4, K0 to K7 0.8 VDD 0.2 VDD Figure 16-10. Input Timing for External Interrupts and Quasi-Interrupts 16-13 S3P72N8/P72N5 OTP S3C72N8/P72N8/C72N5/P72N5 tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO tKH SO Output Data Figure 16-11. Serial Data Transfer Timing 16-14 S3C72N8/P72N8/C72N5/P72N5 S3P72N8/P72N5 OTP Start Address = First Location VDD = 5 V, VPP = 12.5 V x=0 Program One 1 ms Pulse Increment X Yes x = 10 No Fail Verify Byte Verify 1 Byte Fail Last Address No Increment Address VDD = VPP = 5 V Fail Compare All Byte Pass Device Faild Device Passed Figure 16-12. OTP Programming Algorithm 16-15 S3P72N8/P72N5 OTP S3C72N8/P72N8/C72N5/P72N5 NOTES 16-16 |
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