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19-2511; Rev 2; 10/02
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
General Description
The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device selects one of the two differential HSTL or LVECL/LVPECL inputs and repeats them at eight differential outputs. Outputs are compatible with LVECL and LVPECL, and can directly drive 50 terminated transmission lines. The differential inputs can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output voltage VBB. All inputs have internal pulldown resistors to V EE. The internal pulldowns and a fail-safe circuit ensure differential low default outputs when the inputs are left open or at VEE. The MAX9325 operates over a 2.375V to 3.8V supply range for interfacing to differential HSTL and LVPECL signals. This allows high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For LVECL operation, the device operates with a -2.375V to -3.8V supply. The MAX9325 is offered in 28-lead PLCC and spacesaving 28-lead QFN packages. The MAX9325 is specified for operation from -40C to +85C. o 50ps (max) Output-to-Output Skew o 1.5psRMS (max) Random Jitter o Guaranteed 300mV Differential Output at 700MHz o +2.375V to +3.8V Supplies for Differential HSTL/LVPECL o -2.375V to -3.8V Supplies for Differential LVECL o Two Selectable Differential Inputs o On-Chip Reference for Single-Ended Inputs o Outputs Low for Inputs Open or at VEE o Pin Compatible with MC100LVE310
Features
MAX9325
Ordering Information
PART MAX9325EQI MAX9325EGI TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 PLCC 28 QFN 5mm x 5mm
Applications
Precision Clock Distribution Low-Jitter Data Repeaters
Functional Diagram appears at end of data sheet.
Pin Configurations
VCC Q0 Q0 Q1
Q1 Q2 Q2
VCC
TOP VIEW
Q0
Q0
Q1
Q1
Q2
Q2
INPUT SELECT TRUTH TABLE CLK_SEL INPUT CLOCK CLK0, CLK0 SELECTED CLK1, CLK1 SELECTED
28
27
26
25
24
23
22
25 24
23 22 21
20
19
*
*
L
VEE CLK_SEL CLKO VCC CLKO VBB CLK1
26 27 28 1 2 3 4
18 17 16
Q3 Q3 Q4 VCC Q4 Q5 Q5 VEE CLK_SEL CLKO VCC CLKO VBB CLK1 1 2 3 4 5 6 7
*
21 20 19
Q3 Q3 Q4 VCC Q4 Q5 Q5
H
MAX9325
15 14 13 12
MAX9325
18 17 16 15
*
5
6
7
Q7
8
9
10
Q6
11
Q6
CLK1
N.C.
VCC
Q7
10
11
12
13
Q6
CLK1
Q7
Q7
N.C.
QFN
*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO VEE.
________________________________________________________________ Maxim Integrated Products
VCC
Q6
PLCC
14
8
9
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325
ABSOLUTE MAXIMUM RATINGS
VCC - VEE ...............................................................-0.3V to +4.1V Inputs (CLK_, CLK_, CLK_SEL) to VEE ......-0.3V to (VCC + 0.3V) CLK_ to CLK_ .....................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current................................................0.65mA Continuous Power Dissipation (TA = +70C) 28-Lead PLCC (derate 10.5mW/C above +70C) .....842mW JA in Still Air .............................................................+95C/W JC .............................................................................+25C/W 28-Lead QFN (derate 20.8mW/C above +70C) ....1667mW JA in Still Air ............................................................+48C/W JC ..............................................................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (CLK_, CLK_, Q_, Q_)....................2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
((VCC - VEE) = 2.375V to 3.8V, RL = 50 1% to VCC - 2V. Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Notes 1-4)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
SINGLE-ENDED INPUT (CLK_SEL) Single-Ended Input High Voltage Single-Ended Input Low Voltage Input Current VIH Figure 1 VCC - 1.165 VCC VCC - 1.165 VCC VCC - 1.165 VCC V
VIL IIN
Figure 1 VIH, VIL
VEE -10.0
VCC - 1.475 +150
VEE -10.0
VCC - 1.475 +150
VEE -10.0
VCC - 1.475 +150
V A
DIFFERENTIAL INPUT (CLK_, CLK_) Single-Ended Input High Voltage Single-Ended Input Low Voltage Differential Input High Voltage VIH Figure 1 VCC - 1.165 VCC VCC - 1.165 VCC VCC - 1.165 VCC V
VIL
Figure 1
VEE VEE + 1.2
VCC - 1.475 VCC
VEE VEE + 1.2
VCC - 1.475 VCC
VEE VEE + 1.2
VCC - 1.475 VCC
V
VIHD
Figure 1
V
2
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2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)
((VCC - VEE) = 2.375V to 3.8V, RL = 50 1% to VCC - 2V. Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Notes 1-4)
PARAMETER Differential Input Low Voltage SYMBOL VILD CONDITIONS Figure 1 (VCC - VEE) < 3.0V, Figure 1 (VCC - VEE) 3.0V, Figure 1 VIH, VIL, VIHD, VILD -40C MIN VEE 0.095 0.095 -10.0 TYP MAX VCC - 0.095 VCC - VEE 3.0 +150.0 MIN VEE 0.095 0.095 -10.0 +25C TYP MAX VCC - 0.095 VCC - VEE 3.0 +150.0 MIN VEE 0.095 0.095 -10.0 +85C TYP MAX VCC - 0.095 VCC - VEE V 3.0 +150.0 A UNITS V
MAX9325
Differential Input Voltage
VIHD VILD
Input Current OUTPUT (Q_, Q_) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage
IIN
VOH
Figure 2
VCC VCC VCC VCC VCC VCC VCC VCC VCC - 1.085 - 0.977 - 0.880 - 1.025 - 0.949 - 0.88 - 1.025 - 0.929 - 0.88
V
VOL
Figure 2
VCC VCC VCC VCC VCC VCC VCC VCC VCC - 1.810 - 1.695 - 1.620 - 1.810 - 1.697 - 1.62 - 1.810 - 1.698 - 1.62 535 718 595 749 595 769
V
VOH - VOL Figure 2
mV
REFERENCE VOLTAGE OUTPUT (VBB) Reference Voltage Output SUPPLY Supply Current IEE (Note 6) 35 50 39 55 42 65 mA VBB IBB = 0.5mA (Note 5) VCC VCC - 1.38 - 1.318 VCC - 1.26 VCC VCC VCC - 1.38 - 1.325 - 1.26 VCC VCC VCC - 1.38 - 1.328 - 1.26 V
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3
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325
AC ELECTRICAL CHARACTERISTICS--PLCC Package
((VCC - VEE) = 2.375V to 3.8V, RL = 50 1% to VCC - 2V, fIN 500MHz, input transition time = 125ps (20% to 80%). Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Note 7)
PARAMETER Differential Input-to-Output Delay Single-Ended Input-to-Output Delay Output-toOutput Skew Part-to-Part Skew Added Random Jitter Added Deterministic Jitter Switching Frequency Output Rise/Fall Time (20% to 80%) SYMBOL tPLHD tPHLD tPLH tPHL tSKOO tSKPP CONDITIONS -40C MIN 475 TYP MAX 650 MIN 460 +25C TYP MAX 710 MIN 490 +85C TYP MAX 740 UNITS
Figure 2
ps
Figure 3 (Note 8)
440
780
430
790
450
800
ps
(Note 9) Differential input (Note 10) fIN = 0.5GHz clock pattern (Note 11) fIN = 1.0Gbps, 2E23 - 1 PRBS pattern (Note 11) VOH - VOL 300mV clock pattern
50 160
50 190
50 225
ps ps
tRJ
1.5
1.5
1.5
psRMS
tDJ
100
100
100
psP-P
fMAX
1.5
1.5
1.5
GHz
tR, tF
Figure 2
140
440
140
440
140
440
ps
4
_______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325
AC ELECTRICAL CHARACTERISTICS--QFN Package
((VCC - VEE) = 2.375V to 3.8V, RL = 50 1% to VCC - 2V, fIN 500MHz, input transition time = 125ps (20% to 80%). Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Note 7)
PARAMETER Differential Input-to-Output Delay Single-Ended Input-to-Output Delay Output-toOutput Skew Part-to-Part Skew Added Random Jitter Added Deterministic Jitter Switching Frequency Output Rise/Fall Time (20% to 80%) SYMBOL tPLHD tPHLD tPLH tPHL tSKOO tSKPP CONDITIONS -40C MIN 250 TYP MAX 575 MIN 298 +25C TYP MAX 553 MIN 309 +85C TYP MAX 576 UNITS
Figure 2
ps
Figure 3 (Note 8)
253
581
310
586
324
606
ps
(Note 9) Differential input (Note 10) fIN = 0.5GHz clock pattern (Note 11) fIN = 1.0Gbps, 2E23 - 1 PRBS pattern (Note 11) VOH - VOL 300mV clock pattern
50 192
50 215
50 218
ps ps
tRJ
1.5
1.5
1.5
psRMS
tDJ
95
95
95
psP-P
fMAX
1.5
1.5
1.5
GHz
tR, tF
Figure 2
97
411
104
210
111
232
ps
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11:
Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. DC parameters production tested at TA = +25C and guaranteed by design over the full operating temperature range. Single-ended input operation using VBB is limited to (VCC - VEE) = 3.0V to 3.8V. Use VBB only for inputs that are on the same device as the VBB reference. All pins open except VCC and VEE. Guaranteed by design and characterization. Limits are set at 6 sigma. Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal. Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal. Measured between outputs of different parts under identical condition for same-edge transition. Device jitter added to the input signal. Differential input signal.
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5
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325
Typical Operating Characteristics
(PLCC package, typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V), RL = 50 1% to VCC - 2V, fIN = 500MHz, input transition time = 125ps (20% to 80%).)
SUPPLY CURRENT (IEE) vs. TEMPERATURE
MAX9325 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
MAX9325 toc02
50 45 SUPPLY CURRENT (mA) 40 35 30 25 20 -40 -15 10 35 60
800
700 OUTPUT VOLTAGE (V)
600
500
400
300 85 0 500 1000 1500 TEMPERATURE (C) FREQUENCY (MHz)
TRANSITION TIME vs. TEMPERATURE
MAX9325 toc03
PROPAGATION DELAY vs. TEMPERATURE
MAX9325 toc05
400 360 TRANSITION TIME (ps) 320 280 240 200 160 -40 -15 10 35 60 tF
750
PROPAGATION DELAY (ps)
650 tPHLD 550 tPLHD 450
tR
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
6
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2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
Pin Description
PIN PLCC 1, 8, 15, 22 2 3 4 5 6 7 9 10 11 12 13 14 16 17 18 19 20 21 23 24 25 26 27 28 Exposed QFN 4, 11, 18, 25 5 6 7 8 9 10 12 13 14 15 16 17 19 20 21 22 23 24 26 27 28 1 2 3 Exposed Pad NAME FUNCTION Positive Supply Voltage. Bypass each VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible, with the smaller value capacitor closest to the device. Inverting Differential Clock Input 0. Internal 105k pulldown to VEE. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass VBB to VCC with a 0.01F ceramic capacitor. Otherwise leave open. Noninverting Differential Clock Input 1. Internal 105k pulldown to VEE. Inverting Differential Clock Input 1. Internal 105k pulldown to VEE. Not Connected Inverting Q7 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q7 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q6 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q6 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q5 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q5 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q4 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q4 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q3 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q3 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q2 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q2 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Negative Supply Voltage Clock Select Input. When driven low, the CLK0 input is selected. Drive high to select the CLK1 Input. The CLK_SEL threshold is equal to VBB. Internal 75k pulldown to VEE. Noninverting Differential Clock Input 0. Internal 105k pulldown to VEE. Internally Connected to VEE
MAX9325
VCC CLK0 VBB CLK1 CLK1 N.C. Q7 Q7 Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 VEE CLK_SEL CLK0 --
_______________________________________________________________________________________
7
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325
VCC VIHD (MAX) VIHD - VILD VIH VILD (MAX) VBB VIL VIHD (MIN) VIHD - VILD VILD (MIN) VCC
VEE
VEE
DIFFERENTIAL INPUT VOLTAGE DEFINITION
SINGLE-ENDED INPUT VOLTAGE DEFINITION
Figure 1. Input Voltage Definitions
CLK
VIHD VIHD - VILD
CLK tPLHD Q_ tPHLD
VILD
VOH VOH - VOL
Q_
VOL
80% VOH - VOL
80%
0V (DIFFERENTIAL)
VOH - VOL DIFFERENTIAL OUTPUT WAVEFORM Q_ - Q_ tR tF 20% 20%
Figure 2. Differential Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram
8
_______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325
CLK_ WHEN CLK_ = VBB VIH
VBB
VBB
OR
VIL
VIH VBB CLK_ WHEN CLK_ = VBB VBB
VIL tPLH tPHL
Q_
VOH
VOH - VOL Q_ VOL
Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram
Detailed Description
The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device selects one of the two differential HSTL or LVECL/LVPECL inputs, and repeats them at eight differential outputs. Outputs are compatible with LVECL and LVPECL, and can directly drive 50 terminated transmission lines. A 2:1 mux selects between the two differential inputs, CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched by the single-ended CLK_SEL input. A logic low selects the CLK0, CLK0 input. A logic high selects the CLK1, CLK1 input. The logic threshold for CLK_SEL is set by an internal VBB voltage reference. The selected input is reproduced at eight differential outputs at speeds up to 700MHz. The differential inputs can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output voltage (VBB). A single-ended input of at least VBB 95mV or a differential input of at least 95mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics. The maximum magnitude of the differential input from CLK_ to CLK_ is 3.0V or
(VCC - VEE), whichever is less. This limit also applies to the difference between a single-ended input and any reference voltage input. The single-ended CLK_SEL input has a 75k pulldown to VEE that selects the default input, CLK0, CLK0, when CLK_SEL is left open or at VEE. All the differential inputs have 105k pulldowns to VEE. Internal pulldowns and a fail-safe circuit ensure differential low default outputs when the inputs are left open or at VEE. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.375V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.375V to -3.8V supply.
Single-Ended Operation
CLK_SEL is a single-ended input with the input threshold internally set to VBB, and can be driven to VCC or VEE or by a single-ended LVPECL/LVECL signal. The CLK_, CLK_ are differential inputs but can be configured to accept single-ended inputs when operating at supply voltages greater than 2.58V. The recommended supply voltage for single-ended operation is 3.0V to 3.8V. A dif9
_______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
ferential input is configured for single-ended operation by connecting the on-chip reference voltage, VBB, to an unused complementary input as a reference. For example, the differential CLK0, CLK0 input is converted to a noninverting, single-ended input by connecting VBB to CLK0 and connecting the single-ended input to CLK0. Similarly, an inverting input is obtained by connecting VBB to CLK0 and connecting the single-ended input to CLK0. With a differential input configured as singleended (using VBB), the single-ended input can be driven to VCC or VEE or with a single-ended LVPECL/LVECL signal. When configuring a differential input as a single-ended input, a user must ensure that the supply voltage (VCC VEE) is greater than 2.58V. This is because the input high minimum level must be at (VEE + 1.2V) or higher for proper operation. The reference voltage VBB must be at least (VEE + 1.2V) or higher for the same reason because it becomes the high-level input when the other single-ended input swings below it. The minimum VBB output for the MAX9325 is (VCC - 1.38V). Substituting the minimum VBB output for (VBB = VEE + 1.2V) results in a minimum supply (VCC - VEE) of 2.58V. Rounding up to standard supplies gives the single-ended operating supply ranges (V CC - V EE ) of 3.0V to 3.8V for the MAX9325. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If not used, leave it open. The VBB reference can source or sink 0.5mA, which is sufficient to drive two inputs.
MAX9325
Traces
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
Exposed-Pad Package
The 28-lead QFN package (MAX9325EGI) has the exposed paddle on the bottom of the package that provides the primary heat removal path from the IC to the PC board, as well as excellent electrical grounding to the PC board. The MAX9325EGI's exposed pad is internally connected to V EE . Do not connect the exposed pad to a separate circuit ground plane unless VEE and the circuit ground are the same.
Chip Information
TRANSISTOR COUNT: 1030 PROCESS: Bipolar
Functional Diagram
Q0 MAX9325 CLK0 CLK0 105k Q2 VEE 0 1 CLK1 CLK1 105k VEE CLK_SEL 75k Q7 VEE Q7 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q0 Q1 Q1 Q2
Applications Information
Output Termination
Terminate the outputs through 50 to (VCC - 2V) or use equivalent Thevenin terminations. Terminate each Q and Q output with identical termination on each for low output distortion. When a single-ended signal is taken from the differential output, terminate both Q_ and Q_. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device's total thermal limits should be observed.
Supply Bypassing
Bypass each VCC to VEE with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors. Place the capacitors as close to the device as possible with the 0.01F capacitor closest to the device pins. Use multiple vias when connecting the bypass capacitors to ground. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If the VBB reference is not used, it can be left open.
10
______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9325
e
INCHES MIN MAX 0.165 0.180 0.090 0.120 0.145 0.156 0.020 --0.013 0.021 0.026 0.032 0.009 0.011 0.050 INCHES MIN MAX 0.385 0.395 0.350 0.356 0.290 0.330 0.200 REF 0.495 0.456 0.430 REF 0.695 0.656 0.630 REF
D D1 D3
N
A A1 A2 A3 B B1 C e
MIN MAX 4.20 4.57 3.04 2.29 3.96 3.69 --0.51 0.53 0.33 0.81 0.66 0.28 0.23 1.27
D D1 D2 D3
MIN 9.78 8.89 7.37 5.08 12.32 11.43 9.91 7.62 17.40 16.51 14.99 12.70
MAX N 10.03 20 AA 9.04 8.38 REF 12.57 28 AB 11.58 10.92 REF 17.65 44 AC 16.66 16.00 REF 20.19 19.20 18.54 REF 25.27 24.33 23.62 REF 52 AD
D 0.485 D1 0.450 D2 0.390 D3 0.300 D 0.685 D1 0.650 D2 0.590 D3 0.500 D 0.785 D1 0.750 D2 0.690 D3 0.600 D 0.985 D1 0.950 D2 0.890 D3 0.800
D3 D1 D
A
A2 A1 B1 B A3 D2
0.795 19.94 0.756 19.05 0.730 17.53 REF 15.24 0.995 25.02 0.958 24.13 0.930 22.61 REF 20.32
68 AE
C
NOTES:
1. D1 DOES NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .20mm (.008") PER SIDE. 3. LEADS TO BE COPLANAR WITHIN .10mm. 4. CONTROLLING DIMENSION: MILLIMETER 5. MEETS JEDEC MO047-XX AS SHOWN IN TABLE. 6. N = NUMBER OF PINS.
PROPRIETARY INFORMATION TITLE:
FAMILY PACKAGE OUTLINE: 20L, 28L, 44L, 52L, 68L PLCC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0049
D
1 1
______________________________________________________________________________________
PLCC.EPS
11
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L QFN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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