IC42S16102 Document Title 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM Revision History Revision No 0A 0B History Initial Draft This device improves output driving strength Draft Date August 28,2004 January 18,2005 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 1 IC42S16102 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES * Driver Strength for High capacitive bus loading * Clock frequency: 200, 166, 143 MHz * Fully synchronous; all signals referenced to a positive clock edge * Two banks can be operated simultaneously and independently * Dual internal bank controlled by A11 (bank select) * Single 3.3V power supply * LVTTL interface * Programmable burst length - (1, 2, 4, 8, full page) * Programmable burst sequence: Sequential/Interleave * Auto refresh, self refresh * 4096 refresh cycles every 64 ms * Random column address every clock cycle * Programmable CAS latency (2, 3 clocks) * Burst read/write and burst read/single write operations capability * Burst termination by burst stop and precharge command * Byte controlled by LDQM and UDQM * Package 400mil 50-pin TSOP-2 and 60ball(16M) VF-BGA * Pb(lead)-free package is available DESCRIPTION ICSI's 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 50-Pin TSOP-2 VCC DQ0 DQ1 GNDQ DQ2 DQ3 VCCQ DQ4 DQ5 GNDQ DQ6 DQ7 VCCQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GND DQ15 DQ14 GNDQ DQ13 DQ12 VCCQ DQ11 DQ10 GNDQ DQ9 DQ8 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 60-BALL VF-BGA ( 16M SDRAM ) 7 6 5 4 3 2 1 VDD A1 A2 A10 NC CS CAS WE NC DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VDD A3 A0 NC NC RAS LDQM NC NC VSSQ VDDQ DQ4 VSSQ VDDQ DQ0 A4 A5 A7 A9 NC CLK UDQM NC NC VDDQ VSSQ DQ11 VDDQ VSSQ DQ15 VSS A6 A8 A11 CKE NC NC NC DQ8 DQ9 DQ10 DQ12 DQ13 DQ14 VSS R P N M L K J H G F E D C B A PIN DESCRIPTIONS A0 - A10 A11 DQ0 - DQ15 CLK CKE CS RAS CAS WE LDQM,UDQM VDD/VSS VDDQ/VSSQ NC Address Bank Address Data Input/Output Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Power Supply/Ground Data Output Power/Ground No Connection Row Address : RA0 - RA11, Column Address : CA0 - CA7 Auto-precharge flag : A10 Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Multiplexed data input / output pin The system clock input.All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated,the SDRAM will be one of the states among power down,suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM RAS,CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Power supply for internal circuits and input buffers Power supply for output buffers No Connection Integrated Circuit Solution Inc. DR042-0A 01/18/2005 3 IC42S16102 FUNCTIONAL BLOCK DIAGRAM COMMAND DECODER & CLOCK GENERATOR ROW DECODER CLK CKE CS RAS CAS WE A11 MODE REGISTER 11 11 ROW ADDRESS BUFFER MEMORY CELL ARRAY 2048 11 BANK 0 DQM SENSE AMP I/O GATE A10 8 COLUMN ADDRESS BUFFER BURST COUNTER COLUMN ADDRESS LATCH DATA IN BUFFER 16 16 256 COLUMN DECODER ROW DECODER MULTIPLEXER A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 REFRESH CONTROLLER SELF REFRESH CONTROLLER I/O 0-15 8 256 SENSE AMP I/O GATE REFRESH COUNTER DATA OUT BUFFER 16 16 11 ROW ADDRESS LATCH 11 ROW ADDRESS BUFFER 2048 MEMORY CELL ARRAY Vcc/VccQ GND/GNDQ BANK 1 11 S16BLK.eps 4 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC MAX VCCQ MAX VIN VOUT PD MAX ICS TOPR TSTG Parameters Maximum Supply Voltage Maximum Supply Voltage for Output Buffer Input Voltage Output Voltage Allowable Power Dissipation Output Shorted Current Operating Temperature Storage Temperature Rating -1.0 to +4.6 -1.0 to +4.6 -1.0 to +4.6 -1.0 to +4.6 1 50 0 to +70 -55 to +150 Unit V V V V W mA C C DC RECOMMENDED OPERATING CONDITIONS(2) (At TA = 0 to +70C) Symbol VCC, VCCQ VIH VIL Parameter Supply Voltage Input High Voltage(3) Input Low Voltage(4) Min. 3.0 2.0 -0.3 Typ. 3.3 -- -- Max. 3.6 VDD + 0.3 +0.8 Unit V V V CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25C, Vcc = VccQ = 3.3 0.3V, f = 1 MHz) Symbol CIN1 CIN2 CI/O Parameter Input Capacitance: A0-A11 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) Data Input/Output Capacitance: I/O0-I/O15 Typ. -- -- -- Max. 4 4 5 Unit pF pF pF Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to GND. 3. VIH (max) = VCCQ + 2.0V with a pulse width 3 ns. 4. VIL (min) = GND - 2.0V with a pulse < 3 ns and -1.5V with a pulse < 5ns. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 5 IC42S16102 DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter IIL IOL VOH VOL ICC1 Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Operating Current(1,2) Test Condition 0V VIN VCC, with pins other than the tested pin at 0V Output is disabled 0V VOUT VCC IOUT = -2 mA IOUT = +2 mA One Bank Operation, Burst Length=1 tRC tRC (min.) IOUT = 0mA CKE VIL (MAX) CKE VIH (MIN) CAS latency = 3 -5 -6 -7 -- -- -- -- -5 -6 -7 -5 -6 -7 -- Speed Min. -5 -10 2.4 -- -- -- -- -- --5 --6 --7 -- -- -- -- -- -- -- Max. 5 10 -- 0.4 150 145 140 2 50 45 40 150 140 130 100 90 80 1 Unit A A V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA ICC2 ICC3 Precharge Standby Current (In Power-Down Mode) Active Standby Current (In Non Power-Down Mode) Operating Current (In Burst Mode)(1) Auto-Refresh Current tCK = tCK (MIN) tCK = tCK (MIN) ICC4 tCK = tCK (MIN) IOUT = 0mA tRC = tRC (MIN) ICC5 ICC6 Self-Refresh Current CKE 0.2V Notes: 1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 F should be inserted between Vcc and GND for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Icc1 and Icc4 depend on the output load. 6 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 AC CHARACTERISTICS(1,2,3) -5 Symbol tCK3 tCK2 tAC3 tAC2 tCHI tCL tOH tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKA tCS tCH tRC tRAS tRP tRCD tRRD tDPL Parameter Clock Cycle Time Access Time From CLK(4) CLK HIGH Level Width CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time Output HIGH Impedance Time(5) CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 Min. Max. Min. 5 -- 7 -- -- 4.5 -- 5 2 -- 2 -- 2 -- 0 -- -- 4.5 -- 5 2 -- 1 -- 2 -- 1 -- 2 -- 1 -- 1CLK+3 -- 2 -- 1 -- 50 -- 30 100,000 15 -- 15 -- 10 -- 2CLK -- 2CLK+tRP -- 1 -- 10 64 -6 Max. Min. 6 -- 8 -- -- 5.5 -- 6 2 -- 2 -- 2 -- 0 -- -- 5.5 -- 6 2 -- 1 -- 2 -- 1 -- 2 -- 1 -- 1CLK+3 -- 2 -- 1 -- 60 -- 36 100,000 18 -- 18 -- 12 -- 2CLK -- 2CLK+tRP -- 1 -- 10 64 -7 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 -- 8.6 -- -- 6 -- 6 2.5 -- 2.5 -- 2 -- 0 -- -- 6 -- 6 2 -- 1 -- 2 -- 1 -- 2 -- 1 -- 1CLK+3 -- 2 -- 1 -- 70 -- 42 100,000 21 -- 21 -- 14 -- 2CLK -- 2CLK+tRP -- 1 -- 10 64 CAS Latency = 3 CAS Latency = 2 Input Data Setup Time Input Data Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time CKE to CLK Recovery Delay Time Command Setup Time (CS, RAS, CAS, WE, DQM) Command Hold Time (CS, RAS, CAS, WE, DQM) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Active Command To Read / Write Command Delay Time Command Period (ACT [0] to ACT[1]) Input Data To Precharge Command Delay time Input Data To Active / Refresh tDAL Command Delay time (During Auto-Precharge) tTTransition Time tREF Refresh Cycle Time (4096) Notes: 1. When power is first applied, memory operation should be started 100 s after Vcc and VccQ reach their stipulated voltages. Also note that the power-on sequence must be executed before starting memory operation. 2. Measured with tT = 1 ns. 3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.). 4. Access time is measured at 1.4V with the load shown in the figure below. 5. The time tHZ (max.) is defined as the time required for the output voltage to transition by 200 mV from VOH (min.) or VOL (max.) when the output is in the high impedance state. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 7 IC42S16102 OPERATING FREQUENCY / LATENCY RELATIONSHIPS Symbol Parameter -- -- tCAC tRCD tRAC tRC tRAS tRP tRRD tCCD tDPL tDAL tRBD tWBD tRQL tWDL tPQL tQMD tDMD tMCD Clock Cycle Time Operating Frequency CAS Latency Active Command To Read/Write Command Delay Time RAS Latency (tRCD + tCAC) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Command Period (ACT[0] to ACT [1]) Column Command Delay Time (READ, READA, WRIT, WRITA) Input Data To Precharge Command Delay Time Input Data To Active/Refresh Command Delay Time (During Auto-Precharge) Burst Stop Command To Output in HIGH-Z Delay Time (Read) Burst Stop Command To Input in Invalid Delay Time (Write) Precharge Command To Output in HIGH-Z Delay Time (Read) Precharge Command To Input in Invalid Delay Time (Write) Last Output To Auto-Precharge Start Time (Read) DQM To Output Delay Time (Read) DQM To Input Delay Time (Write) Mode Register Set To Command Delay Time -5 5 200 3 3 6 10 6 3 2 1 2 5 3 0 3 0 -2 2 0 2 -6 6 166 3 3 6 10 6 3 2 1 2 5 3 0 3 0 -2 2 0 2 -7 7 143 3 3 6 10 6 3 2 1 2 5 3 0 3 0 -2 2 0 2 Units ns MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle AC TEST CONDITIONS (Input/Output Reference Level: 1.4V) Input tCHI 2.4V tCK tCL CLK 1.4V 0.4V tCS 2.4V tCH INPUT 1.4V 0.4V tOH OUTPUT 1.4V tAC 1.4V Output Load I/O ZO = 50 50 +1.4V 50 pF 8 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 COMMANDS Active Command CLK CKE HIGH CS RAS CAS WE A0-A9 A10 ROW Read Command CLK CKE HIGH CS RAS CAS WE A0-A9 A10 NO PRECHARGE BANK 1 COLUMN (1) AUTO PRECHARGE ROW BANK 1 A11 BANK 0 A11 BANK 0 Write Command CLK CKE HIGH CS RAS CAS WE A0-A9 A10 NO PRECHARGE BANK 1 COLUMN(1) AUTO PRECHARGE Precharge Command CLK CKE HIGH CS RAS CAS WE A0-A9 BANK 0 AND BANK 1 A10 BANK 0 OR BANK 1 BANK 1 A11 BANK 0 A11 BANK 0 No-Operation Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 HIGH Device Deselect Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 HIGH Notes: 1. A8-A9 = Don't Care. Don't Care Integrated Circuit Solution Inc. DR042-0A 01/18/2005 9 IC42S16102 COMMANDS (cont.) Mode Register Set Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 OP-CODE HIGH Auto-Refresh Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 HIGH OP-CODE OP-CODE Self-Refresh Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 Power Down Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 NOP ALL BANKS IDLE NOP NOP NOP Clock Suspend Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 NOP BANK(S) ACTIVE Burst Stop Command CLK CKE HIGH NOP CS RAS CAS WE A0-A9 A10 A11 NOP NOP Don't Care 10 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Mode Register Set Command (CS, RAS, CAS, WE = LOW) The IC42S16102 product incorporates a register that defines the device operating mode. This command functions as a data input pin that loads this register from the pins A0 to A11. When power is first applied, the stipulated power-on sequence should be executed and then the IC42S16102 should be initialized by executing a mode register set command. Note that the mode register set command can be executed only when both banks are in the idle state (i.e. deactivated). Another command cannot be executed after a mode register set command until after the passage of the period tMCD, which is the period required for mode register set command execution. When the A10 pin is HIGH, this command functions as a read with auto-precharge command. After the burst read completes, the bank selected by pin A11 is precharged. When the A10 pin is LOW, the bank selected by the A11 pin remains in the activated state after the burst read completes. Write Command (CS, CAS, WE = LOW, RAS = HIGH) When burst write mode has been selected with the mode register set command, this command selects the bank specified by the A11 pin and starts a burst write operation at the start address specified by pins A0 to A9. This first data must be input to the I/O pins in the cycle in which this command. The selected bank must be activated before executing this command. When A10 pin is HIGH, this command functions as a write with auto-precharge command. After the burst write completes, the bank selected by pin A11 is precharged. When the A10 pin is low, the bank selected by the A11 pin remains in the activated state after the burst write completes. After the input of the last burst write data, the application must wait for the write recovery period (tDPL, tDAL) to elapse according to CAS latency. Active Command (CS, RAS = LOW, CAS, WE= HIGH) The IC42S16102 includes two banks of 4096 rows each. This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs. Precharge Command (CS, RAS, WE = LOW, CAS = HIGH) This command starts precharging the bank selected by pins A10 and A11. When A10 is HIGH, both banks are precharged at the same time. When A10 is LOW, the bank selected by A11 is precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period tRP, which is the period required for bank precharging. This command corresponds to the RAS signal from LOW to HIGH in conventional DRAMs Auto-Refresh Command (CS, RAS, CAS = LOW, WE, CKE = HIGH) This command executes the auto-refresh operation. The row address and bank to be refreshed are automatically generated during this operation. Both banks must be placed in the idle state before executing this command. The stipulated period (tRC) is required for a single refresh operation, and no other commands can be executed during this period. The device goes to the idle state after the internal refresh operation completes. This command must be executed at least 4096 times every 64 ms. This command corresponds to CBR auto-refresh in conventional DRAMs. Read Command (CS, CAS = LOW, RAS, WE = HIGH) This command selects the bank specified by the A11 pin and starts a burst read operation at the start address specified by pins A0 to A9. Data is output following CAS latency. The selected bank must be activated before executing this command. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 11 IC42S16102 Self-Refresh Command (CS, RAS, CAS, CKE = LOW, WE = HIGH) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh operation is started by dropping the CKE pin from HIGH to LOW. The self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins. The selfrefresh operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the device internal recovery period (tRC) has elapsed. After the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an auto-refresh should immediately be performed for all addresses (4096 cycles). Both banks must be placed in the idle state before executing this command. Power-Down Command (CKE = LOW) When both banks are in the idle (inactive) state, or when at least one of the banks is not in the idle (inactive) state, this command can be used to suppress device power dissipation by reducing device internal operations to the absolute minimum. Power-down mode is started by dropping the CKE pin from HIGH to LOW. Power-down mode continues as long as the CKE pin is held low. All pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. The powerdown operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the recovery period (tCKA) has elapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tREF). Thus the maximum time that power-down mode can be held is just under the refresh cycle time. Burst Stop Command (CS, WE, = LOW, RAS, CAS = HIGH) The command forcibly terminates burst read and write operations. When this command is executed during a burst read operation, data output stops after the CAS latency period has elapsed. Clock Suspend (CKE = LOW) This command can be used to stop the device internal clock temporarily during a read or write cycle. Clock suspend mode is started by dropping the CKE pin from HIGH to LOW. Clock suspend mode continues as long as the CKE pin is held LOW. All input pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. Also note that the device internal state is maintained. Clock suspend mode is terminated by raising the CKE pin from LOW to HIGH, at which point device operation restarts. The next command cannot be executed until the recovery period (tCKA) has elapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tREF). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. No Operation (CS, = LOW, RAS, CAS, WE = HIGH) This command has no effect on the device. Device Deselect Command (CS = HIGH) This command does not select the device for an object of operation. In other words, it performs no operation with respect to the device. 12 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 COMMAND TRUTH TABLE(1,2) Symbol MRS REF SREF PRE PALL ACT WRIT WRITA READ READA BST NOP DESL SBY ENB MASK Command Mode Register Set Auto-Refresh(5) Self-Refresh(5,6) Precharge Selected Bank Precharge Both Banks Bank Activate(7) Write Write With Auto-Precharge(8) Read(8) Read With Auto-Precharge(8) Burst Stop(9) No Operation Device Deselect Clock Suspend / Standby Mode Data Write / Output Enable Data Mask / Output Disable (3,4) CKE n-1 n H H H H H H H H H H H H H L H H X H L X X X X X X X X X X X X X CS RAS CAS WE DQM L L L L L L L L L L L L H X X X L L L L L L H H H H H H X X X X L L L H H H L L L L H H X X X X L H H L L H L L H H L H X X X X X X X X X X X X X X X X X X L H A11 A10 X X BS X BS BS BS BS BS X X X X X X A9-A0 I/On X HIGH-Z HIGH-Z X X X X X X X X X X X Active HIGH-Z OP CODE X X X X L X H X Row Row L Column(18) H Column(18) L Column(18) H Column(18) X X X X X X X X X X X X DQM TRUTH TABLE(1,2) Symbol ENB MASK ENBU ENBL MASKU MASKL Command Data Write / Output Enable Data Mask / Output Disable Upper Byte Data Write / Output Enable Lower Byte Data Write / Output Enable Upper Byte Data Mask / Output Disable Lower Byte Data Mask / Output Disable CKE n-1 n H H H H H H X X X X X X DQM UPPER LOWER L H L X H X L H X L X H CKE TRUTH TABLE(1,2) Symbol SPND -- -- REF SELF SELFX PDWN -- Command Start Clock Suspend Mode Clock Suspend Terminate Clock Suspend Mode Auto-Refresh Start Self-Refresh Mode Terminate Self-Refresh Mode Start Power-Down Mode Terminate Power-Down Mode Current State Active Other States Clock Suspend Idle Idle Self-Refresh Idle Power-Down CKE n-1 n H L L H H L L H H L L L H H L H H L L H CS RAS CAS WE X X X L L L H L H X X X X L L H X H X X X X X L L H X H X X X X X H H H X H X X A11 A10 A9-A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Integrated Circuit Solution Inc. DR042-0A 01/18/2005 13 IC42S16102 OPERATION COMMAND TABLE(1,2) Current State Command Idle DESL NOP BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation No Operation or Power-Down(12) No Operation or Power-Down(12) No Operation or Power-Down Illegal Illegal Row Active No Operation Auto-Refresh or Self-Refresh(13) Mode Register Set No Operation No Operation No Operation Read Start(17) Write Start(17) Illegal(10) Precharge(15) Illegal Illegal Burst Read Continues, Row Active When Done Burst Read Continues, Row Active When Done Burst Interrupted, Row Active After Interrupt Burst Interrupted, Read Restart After Interrupt(16) Burst Interrupted Write Start After Interrupt(11,16) Illegal(10) Burst Read Interrupted, Precharge After Interrupt Illegal Illegal Burst Write Continues, Write Recovery When Done Burst Write Continues, Write Recovery When Done Burst Write Interrupted, Row Active After Interrupt Burst Write Interrupted, Read Start After Interrupt(11,16) Burst Write Interrupted, Write Restart After Interrupt(16) Illegal(10) Burst Write Interrupted, Precharge After Interrupt Illegal Illegal Burst Read Continues, Precharge When Done Burst Read Continues, Precharge When Done Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal CS RAS CAS WE H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L A11 A10 A9-A0 X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X V V V V X Row Active Read Write Read With AutoPrecharge 14 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 OPERATION COMMAND TABLE(1,2) Current State Command Write With DESL Auto-Precharge NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Precharge DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Immediately DESL Following NOP Row Active BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Write DESL Recovery NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation Burst Write Continues, Write Recovery And Precharge When Done Burst Write Continues, Write Recovery And Precharge Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal No Operation, Idle State After tRP Has Elapsed No Operation, Idle State After tRP Has Elapsed No Operation, Idle State After tRP Has Elapsed Illegal(10) Illegal(10) Illegal(10) No Operation, Idle State After tRP Has Elapsed(10) Illegal Illegal No Operation, Row Active After tRCD Has Elapsed No Operation, Row Active After tRCD Has Elapsed No Operation, Row Active After tRCD Has Elapsed Illegal(10) Illegal(10) Illegal(10,14) Illegal(10) Illegal Illegal No Operation, Row Active After tDPL Has Elapsed No Operation, Row Active After tDPL Has Elapsed No Operation, Row Active After tDPL Has Elapsed Read Start Write Restart Illegal(10) Illegal(10) Illegal Illegal CS RAS CAS WE H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L A11 A10 A9-A0 X X X V V V V X X X X X X X V V(18) V V(18) V V(18) V X X X OPCODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE Integrated Circuit Solution Inc. DR042-0A 01/18/2005 15 IC42S16102 OPERATION COMMAND TABLE(1,2) Current State Command Write Recovery DESL With AutoNOP Precharge BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Refresh DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Mode Register DESL Set NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation No Operation, Idle State After tDAL Has Elapsed No Operation, Idle State After tDAL Has Elapsed No Operation, Idle State After tDAL Has Elapsed Illegal(10) Illegal(10) Illegal(10) Illegal(10) Illegal Illegal No Operation, Idle State After tRP Has Elapsed No Operation, Idle State After tRP Has Elapsed No Operation, Idle State After tRP Has Elapsed Illegal Illegal Illegal Illegal Illegal Illegal No Operation, Idle State After tMCD Has Elapsed No Operation, Idle State After tMCD Has Elapsed No Operation, Idle State After tMCD Has Elapsed Illegal Illegal Illegal Illegal Illegal Illegal CS RAS CAS WE H L L L L L L L L H L L L L L L L L H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L A11 A10 A9-A0 X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X V V V V X Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input 2. All input signals are latched on the rising edge of the CLK signal. 3. Both banks must be placed in the inactive (idle) state in advance. 4. The state of the A0 to A11 pins is loaded into the mode register as an OP code. 5. The row address is generated automatically internally at this time. The I/O pin and the address pin data is ignored. 6. During a self-refresh operation, all pin data (states) other than CKE is ignored. 7. The selected bank must be placed in the inactive (idle) state in advance. 8. The selected bank must be placed in the active state in advance. 9. This command is valid only when the burst length set to full page. 10. This is possible depending on the state of the bank selected by the A11 pin. 11. Time to switch internal busses is required. 12. The IS42S16102 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 13. The IS42S16102 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 14. Possible if tRRD is satisfied. 15. Illegal if tRAS is not satisfied. 16. The conditions for burst interruption must be observed. Also note that the IS42S16102 will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 17. Command input becomes possible after the period tRCD has elapsed. Also note that the IS42S16102 will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 18. A8,A9 = don't care. 16 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 CKE RELATED COMMAND TRUTH TABLE(1) Current State Self-Refresh Operation Undefined Self-Refresh Recovery(2) Self-Refresh Recovery(2) Illegal(2) Illegal(2) Self-Refresh Idle State After tRC Has Elapsed Idle State After tRC Has Elapsed Illegal Illegal Power-Down on the Next Cycle Power-Down on the Next Cycle Illegal Illegal Clock Suspend Termination on the Next Cycle (2) Clock Suspend Undefined Power-Down Mode Termination, Idle After That Termination(2) Power-Down Mode No Operation See the Operation Command Table Bank Active Or Precharge Auto-Refresh Mode Register Set See the Operation Command Table See the Operation Command Table See the Operation Command Table Self-Refresh(3) See the Operation Command Table Power-Down Mode(3) See the Operation Command Table Clock Suspend on the Next Cycle(4) Clock Suspend Termination on the Next Cycle Clock Suspend Termination on the Next Cycle CKE n-1 n H L L L L L H H H H H H H H L L H L L H H H H H H H H H H L H H L L X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L CS RAS CAS WE X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X X X X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X A11 A10 A9-A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Self-Refresh Recovery Power-Down Both Banks Idle Other States X X X X X X X X X X OP CODE X X X X X X X X X X X X OP CODE X X X X X X X X X X X X X X X Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input 2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The minimum setup time (tCKA) required before all commands other than mode termination must be satisfied. 3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode. 4. The input must be command defined in the operation command table. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 17 IC42S16102 TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2) Operation DESL NOP BST CS RAS CAS WE H L L X H H X H H X H L A11 A10 A9-A0 X X X X X X X X X Previous State BANK 0 BANK 1 Any Any R/W/A I I/A I/A I/A R/W I/A R/W R/W/A A R/W/A A Any Any I/A I/A R/W/A I R/W/A A R/W/A A I/A R/W I/A R/W Next State BANK 0 BANK 1 Any Any A I I/A I/A I/A A I/A A RP RP R R Any Any I/A I/A A I RP RP R R I/A A I/A A READ/READA L H L H H H H H L L L L H H H H L L L L H L X X H H L L X H H L L H H L L CA(3) CA(3) CA(3) CA(3) CA(3) CA(3) CA(3) CA(3) WRIT/WRITA L H L L ACT PRE/PALL L L L L H H H L REF MRS L L L L L L H L H CA(3) H CA(3) L CA(3) L CA(3) H CA(3) H CA(3) L CA(3) L CA(3) RA RA RA RA H X H X L X L X L X L X X X OPCODE I/A R/W/A R/W A I/A R/W/A R/W A R/W/A I/A A R/W R/W/A I/A A R/W Any I I Any R/W/A/I I/A I/A R/W/A/I I/A R/W/A/I R/W/A/I I/A R/W/A/I I/A I/A R/W/A/I I I I I I/A WP A WP I/A W A W WP I/A WP A W I/A W A Any A A Any I I I I I/A I R/W/A/I I I I/A I R/W/A/I I I I I Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address 2. The device state symbols are interpreted as follows: I Idle (inactive state) A Row Active State R Read W Write RP Read With Auto-Precharge WP Write With Auto-Precharge Any Any State 3. CA: A8,A9 = don't care. 18 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation) SELF REFRESH SREF entry SREF exit MODE REGISTER SET MRS IDLE REF AUTO REFRESH CKE_ CKE ACT IDLE POWER DOWN ACTIVE POWER DOWN CKE_ CKE BST BANK ACTIVE WRIT READ BST WRIT WRITA READ READA READ WRITE CKE_ WRIT READ CKE_ CLOCK SUSPEND CKE WRITA CKE_ CKE WRITA READA READA CKE_ CKE CLOCK SUSPEND WRITE WITH AUTO PRECHARGE PRE PRE PRE READ WITH AUTO PRECHARGE CKE POWER APPLIED POWER ON PRE PRECHARGE Automatic transition following the completion of command execution. Transition due to command input. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 19 IC42S16102 Device Initialization At Power-On (Power-On Sequence) As is the case with conventional DRAMs, the IC42S16101 product must be initialized by executing a stipulated poweron sequence after power is applied. After power is applied and VCC and VCCQ reach their stipulated voltages, set and hold the CKE and DQM pins HIGH for 100 s. Then, execute the precharge command to precharge both bank. Next, execute the auto-refresh command twice or more and define the device operation mode by executing a mode register set command. The mode register set command can be also set before auto-refresh command. Burst Length When writing or reading, data can be input or output data continuously. In these operations, an address is input only once and that address is taken as the starting address internally by the device. The device then automatically generates the following address. The burst length field in the mode register stipulates the number of data items input or output in sequence. In the IC42S16102 product, a burst length of 1, 2, 4, 8, or full page can be specified. See the table on the next page for details on setting the mode register. Burst Type The burst data order during a read or write operation is stipulated by the burst type, which can be set by the mode register set command. The IC42S16102 product supports sequential mode and interleaved mode burst type settings. See the table on the next page for details on setting the mode register. See the "Burst Length and Column Address Sequence" item for details on I/O data orders in these modes. Mode Register Settings The mode register set command sets the mode register. When this command is executed, pins A0 to A9, A10, and A11 function as data input pins for setting the register, and this data becomes the device internal OP code. This OP code has four fields as listed in the table below. Input Pin A11, A10, A9, A8 A6, A5, A4 A3 A2, A1, A0 Field Mode Options CAS Latency Burst Type Burst Length Write Mode Burst write or single write mode is selected by the OP code (A11, A10, A9) of the mode register. A burst write operation is enabled by setting the OP code (A11, A10, A9) to (0,0,0). A burst write starts on the same cycle as a write command set. The write start address is specified by the column address and bank select address at the write command set cycle. A single write operation is enabled by setting OP code (A11, A10, A9) to (0,0,1). In a single write operation, data is only written to the column address and bank select address specified by the write command set cycle without regard to the bust length setting. Note that the mode register set command can be executed only when both banks are in the idle (inactive) state. Wait at least two cycles after executing a mode register set command before executing the next command. CAS Latency During a read operation, the between the execution of the read command and data output is stipulated as the CAS latency. This period can be set using the mode register set command. The optimal CAS latency is determined by the clock frequency and device speed grade (-10/12). See the "Operating Frequency / Latency Relationships" item for details on the relationship between the clock frequency and the CAS latency. See the table on the next page for details on setting the mode register. 20 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 MODE REGISTER 11 10 9 8 7 6 5 LT MODE 4 3 BT 2 1 BL 0 WRITE MODE Address Bus Mode Register (Mx) M2 Burst Length 0 0 0 0 1 1 1 1 M3 Burst Type 0 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Type Sequential Interleaved Sequential 1 2 4 8 Reserved Reserved Reserved Full Page Interleaved 1 2 4 8 Reserved Reserved Reserved Reserved M6 Latency Mode 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved M11 0 0 M10 0 0 M9 0 1 others M8 0 0 M7 0 0 Write Mode Burst Read & Burst Write Burst Read & Single Write Reserved Integrated Circuit Solution Inc. DR042-0A 01/18/2005 21 IC42S16102 BURST LENGTH AND COLUMN ADDRESS SEQUENCE Burst Length 2 4 Column Address A2 A1 A0 X X X X X X 0 0 0 0 1 1 1 1 n X X 0 0 1 1 0 0 1 1 0 0 1 1 n 0 1 0 1 0 1 0 1 0 1 0 1 0 1 n Address Sequence Sequential Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4..... ...Cn-1(Cn+255), Cn(Cn+256)..... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 None 8 Full Page (256) Notes: 1. The burst length in full page mode is 256. 22 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 BANK SELECT AND PRECHARGE ADDRESS ALLOCATION Row X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 Column Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 -- -- -- -- -- -- -- -- -- -- 0 1 0 1 -- -- -- -- -- -- -- -- -- -- 0 1 0 1 Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Precharge of the Selected Bank (Precharge Command) Row Address Precharge of Both Banks (Precharge Command) (Active Command) Bank 0 Selected (Precharge and Active Command) Bank 1 Selected (Precharge and Active Command) Column Address Column Address Column Address Column Address Column Address Column Address Column Address Column Address Don't Care Don't Care Auto-Precharge - Disabled Auto-Precharge - Enables Bank 0 Selected (Read and Write Commands) Bank 1 Selected (Read and Write Commands) Integrated Circuit Solution Inc. DR042-0A 01/18/2005 23 IC42S16102 Burst Read The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the clock signal after the CAS latency period. Next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal. The output buffers go to the LOW impedance state CAS latency minus one cycle after the read command, and go to the HIGH impedance state automatically after the last data is output. However, the case where the burst length is a full page is an exception. In this case the output buffers must be set to the high impedance state by executing a burst stop command. Note that upper byte and lower byte output data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tQMD) is fixed at two, regardless of the CAS latency setting, when this function is used. The selected bank must be set to the active state before executing this command. CLK COMMAND UDQM LDQM READ A0 tQMD=2 I/O8-I/O15 I/O0-I/O 7 DOUT A0 HI-Z DOUT A2 DOUT A3 HI-Z DOUT A0 READ (CA=A, BANK 0) DOUT A1 HI-Z CAS latency = 2, burst length = 4 DATA MASK (LOWER BYTE) DATA MASK (UPPER BYTE) Burst Write The write cycle is started by executing the command. The address provided during write command execution is used as the starting address, and at the same time, data for this address is input in synchronization with the clock signal. Next, data is input in other in synchronization with the clock signal. During this operation, data is written to address generated automatically by the device. This cycle terminates automatically after a number of clock cycles determined by the stipulated burst length. However, the case where the burst length is a full page is an exception. In this case the write cycle must be terminated by executing a burst stop command. The latency for I/O pin data input is zero, regardless of the CAS latency setting. However, a wait period (write recovery: tDPL) after the last data input is required for the device to complete the write operation. Note that the upper byte and lower byte input data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tDMD) is fixed at zero, regardless of the CAS latency setting, when this function is used. The selected bank must be set to the active state before executing this command. CLK COMMAND I/O WRITE DIN 0 DIN 1 DIN 2 DIN 3 BURST LENGTH CAS latency = 2,3, burst length = 4 24 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read With Auto-Precharge The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation. During this operation, the delay period (tPQL) between the last burst data output and the start of the precharge operation differs depending on the CAS latency setting. When the CAS latency setting is two, the precharge operation starts on one clock cycle before the last burst data is output (tPQL = -1). When the CAS latency setting is three, the precharge operation starts on two clock cycles before the last burst data is output (tPQL = -2). Therefore, the selected bank can be made active after a delay of tRP from the start position of this precharge operation. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. CAS Latency tPQL 3 -2 2 -1 CLK COMMAND I/O READA 0 tPQL DOUT 0 DOUT 1 DOUT 2 DOUT 3 tRP ACT 0 READ WITH AUTO-PRECHARGE (BANK 0) PRECHARGE START CAS latency = 2, burst length = 4 CLK COMMAND I/O READA 0 tPQL DOUT 0 DOUT 1 DOUT 2 tRP DOUT 3 ACT 0 READ WITH AUTO-PRECHARGE (BANK 0) PRECHARGE START CAS latency = 3, burst length = 4 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 25 IC42S16102 Write With Auto-Precharge The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation. During this operation, the delay period (tDAL) between the last burst data input and the completion of the precharge operation differs depending on the CAS latency setting. The delay (tDAL) is tRP plus one CLK period. That is, the precharge operation starts one clock period after the last burst data input. Therefore, the selected bank can be made active after a delay of tDAL. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. CAS Latency tDAL 3 1CLK +tRP 2 1CLK +tRP CLK COMMAND I/O READA 0 ACT 0 DOUT 0 DOUT 1 DOUT 2 DOUT 3 tRP READ WITH AUTO-PRECHARGE (BANK 0) PRECHARGE START (tPQL=0) CAS latency = 2, burst length = 4 COMMAND I/O READ WITH AUTO-PRECHARGE (BANK 0) CLK READA 0 tPQL DOUT 0 DOUT 1 DOUT 2 DOUT 3 tRP ACT 0 PRECHARGE START CLK COMMAND I/O READA 0 tPQL DOUT 0 DOUT 1 DOUT 2 tRP DOUT 3 ACT 0 READ WITH AUTO-PRECHARGE (BANK 0) PRECHARGE START CAS latency = 3, burst length = 4 26 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Interval Between Read Command A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command. The interval between two read command (tCCD) must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK COMMAND I/O READ A0 READ B0 DOUT A0 tCCD DOUT B0 DOUT B1 DOUT B2 DOUT B3 READ (CA=A, BANK 0) READ (CA=B, BANK 0) CAS latency = 2, burst length = 4 Interval Between Write Command A new command can be executed while a write cycle is in progress, i.e., before that cycle completes. At the point the second write command is executed, data corresponding to the new write command can be input in place of the data for the previous write command. The interval between two write commands (tCCD) must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND I/O WRITE A0 WRITE B0 DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0) CAS latency = 2, burst length = 4 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 27 IC42S16102 Interval Between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The I/On pins must be placed in the HIGH impedance state at least one cycle before data is output during this operation. The interval (tCCD) between command must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND I/O WRITE A0 READ B0 DIN A0 WRITE (CA=A, BANK 0) HI-Z DOUT B0 DOUT B1 DOUT B2 DOUT B3 READ (CA=B, BANK 0) CAS latency = 2, burst length = 4 CLK tCCD COMMAND I/O WRITE A0 READ B0 DIN A0 WRITE (CA=A, BANK 0) HI-Z READ (CA=B, BANK 0) DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS latency = 3, burst length = 4 Don't Care 28 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Interval Between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i. e., before that cycle completes. Data corresponding to the new write command can be input at the point new write command is executed. To prevent collision between input and output data at the I/On pins during this operation, the output data must be masked using the U/LDQM pins. The interval (tCCD) between these commands must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND U/LDQM I/O READ A0 WRITE B0 HI-Z DIN B0 DIN B1 DIN B2 DIN B3 READ (CA=A, BANK 0) WRITE (CA=B, BANK 0) CAS latency = 2, 3, burst length = 4 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 29 IC42S16102 Precharge The precharge command sets the bank selected by pin A11 to the precharged state. This command can be executed at a time tRAS following the execution of an active command to the same bank. The selected bank goes to the idle state at a time tRP following the execution of the precharge command, and an active command can be executed again for that bank. If pin A10 is low when this command is executed, the bank selected by pin A11 will be precharged, and if pin A10 is HIGH, both banks will be precharged at the same time. This input to pin A11 is ignored in the latter case. Read Cycle Interruption Using the Precharge Command A read cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (tRQL) from the execution of the precharge command to the completion of the burst output is the clock cycle of CAS latency. CAS Latency tRQL 3 3 2 2 CLK tRQL COMMAND I/O READ A0 PRE 0 DOUT A0 READ (CA=A, BANK 0) DOUT A1 DOUT A2 HI-Z PRECHARGE (BANK 0) CAS latency = 2, burst length = 4 CLK tRQL COMMAND I/O READ A0 PRE 0 DOUT A0 READ (CA=A, BANK 0) DOUT A1 DOUT A2 HI-Z PRECHARGE (BANK 0) CAS latency = 3, burst length = 4 30 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (tWDL) from the precharge command to the point where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS. To inhibit invalid write, the DQM signal must be asserted HIGH with the precharge command. This precharge command and burst write command must be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual bank operation. Inversely, to write all the burst data to the device, the precharge command must be executed after the write data recovery period (tDPL) has elapsed. Therefore, the precharge command must be executed on one clock cycle that follows the input of the last burst data item. CAS Latency tWDL tDPL 3 0 1 2 0 1 CLK tWDL=0 COMMAND DQM I/O WRITE A0 PRE 0 DIN A0 DIN A1 DIN A2 DIN A3 MASKED BY DQM WRITE (CA=A, BANK 0) PRECHARGE (BANK 0) CAS latency = 2, 3, burst length = 4 CLK tDPL COMMAND I/O WRITE A0 PRE 0 DIN A0 DIN A1 DIN A2 DIN A3 PRECHARGE (BANK 0) WRITE (CA=A, BANK 0) CAS latency = 2, 3, burst length = 4 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 31 IC42S16102 Read Cycle (Full Page) Interruption Using the Burst Stop Command The IC42S16102 can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IC42S16102 repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed within the ACT to PRE command period (tRAS max.) following the burst stop command. After the period (tRBD) required for burst data output to stop following the execution of the burst stop command has elapsed, the outputs go to the HIGH impedance state. This period (tRBD) is two clock cycle when the CAS latency is two and three clock cycle when the CAS latency is three. CAS Latency tRBD 3 3 2 2 CLK tRBD COMMAND I/O READ A0 BST DOUT A0 READ (CA=A, BANK 0) DOUT A0 DOUT A1 DOUT A2 BURST STOP DOUT A3 HI-Z CAS latency = 2, burst length = full page CLK tRBD COMMAND I/O READ A0 BST DOUT A0 READ (CA=A, BANK 0) DOUT A0 DOUT A1 BURST STOP DOUT A2 DOUT A3 HI-Z CAS latency = 3, burst length = full page 32 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle (Full Page) Interruption Using the Burst Stop Command The IC42S16102 can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. The IC42S16102 repeats the operation starting at the 256th cycle with data input returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed with in the ACT to PRE command period (tRAS max.) following the burst stop command. After the period (tWBD) required for burst data input to stop following the execution of the burst stop command has elapsed, the write cycle terminates. This period (tWBD) is zero clock cycles, regardless of the CAS latency. CLK tWBD=0 tRP PRE 0 COMMAND I/O WRITE A0 BST INVALID DATA DIN A0 DIN A1 DIN A DIN A1 DIN A2 BURST STOP PRECHARGE (BANK 0) READ (CA=A, BANK 0) CAS latency = 2, 3, burst length = full page Don't Care Burst Data Interruption Using the U/LDQM Pins (Read Cycle) Burst data output can be temporarily interrupted (masked) during a read cycle using the U/LDQM pins. Regardless of the CAS latency, two clock cycles (tQMD) after one of the U/ LDQM pins goes HIGH, the corresponding outputs go to the HIGH impedance state. Subsequently, the outputs are maintained in the high impedance state as long as that U/ LDQM pin remains HIGH. When the U/LDQM pin goes LOW, output is resumed at a time tQMD later. This output control operates independently on a byte basis with the UDQM pin controlling upper byte output (pins I/O8-I/O15) and the LDQM pin controlling lower byte output (pins I/O0 to I/O7). Since the U/LDQM pins control the device output buffers only, the read cycle continues internally and, in particular, incrementing of the internal burst counter continues. CLK COMMAND UDQM LDQM READ A0 tQMD=2 I/O8-I/O15 I/O0-I/O 7 READ (CA=A, BANK 0) DOUT A0 HI-Z DOUT A2 DOUT A3 HI-Z DOUT A0 DOUT A1 HI-Z DATA MASK (LOWER BYTE) CAS latency = 2, burst length = 4 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 DATA MASK (UPPER BYTE) 33 IC42S16102 Burst Data Interruption U/LDQM Pins (Write Cycle) Burst data input can be temporarily interrupted (muted ) during a write cycle using the U/LDQM pins. Regardless of the CAS latency, as soon as one of the U/LDQM pins goes HIGH, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be muted as long as that U/LDQM pin remains HIGH. The IC42S16102 will revert to accepting input as soon as that pin is dropped to LOW and data will be written to the device. This input control operates independently on a byte basis with the UDQM pin controlling upper byte input (pin I/O8 to I/O15) and the LDQM pin controlling the lower byte input (pins I/O0 to I/O7). Since the U/LDQM pins control the device input buffers only, the cycle continues internally and, inparticular, incrementing of the internal burst counter continues. CLK COMMAND UDQM tDMD=0 WRITE A0 LDQM I/O8-I/O15 I/O0-I/O7 WRITE (CA=A, BANK 0) DIN A1 DIN A2 DIN A3 DIN A0 DATA MASK (LOWER BYTE) DIN A3 CAS latency = 2, burst length = 4 DATA MASK (UPPER BYTE) Don't Care Burst Read and Single Write The burst read and single write mode is set up using the mode register set command. During this operation, the burst read cycle operates normally, but the write cycle only writes a single data item for each write cycle. The CAS latency and DQM latency are the same as in normal mode. CLK COMMAND I/O CAS latency = 2, 3 34 WRITE A0 DIN A0 WRITE (CA=A, BANK 0) Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Bank Active Command Interval When the selected bank is precharged, the period trp has elapsed and the bank has entered the idle state, the bank can be activated by executing the active command. If the other bank is in the idle state at that time, the active command can be executed for that bank after the period tRRD has elapsed. At that point both banks will be in the active state. When a bank active command has been executed, a precharge command must be executed for CLK tRRD that bank within the ACT to PRE command period (tRAS max). Also note that a precharge command cannot be executed for an active bank before tRAS (min) has elapsed. After a bank active command has been executed and the trcd period has elapsed, read write (including autoprecharge) commands can be executed for that bank. COMMAND ACT 0 ACT 1 BANK ACTIVE (BANK 1) BANK ACTIVE (BANK 0) CLK tRCD COMMAND ACT 0 READ 0 BANK ACTIVE (BANK 0) CAS latency = 3 BANK ACTIVE (BANK 0) Clock Suspend When the CKE pin is dropped from HIGH to LOW during a read or write cycle, the IS42S16102 enters clock suspend mode on the next CLK rising edge. This command reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low. In this state, all inputs other than CKE pin are invalid and no other commands can be executed. Also, the device internal states are maintained. When the CKE pin goes from LOW to HIGH clock suspend mode is terminated on the next CLK rising edge and device operation resumes. CLK The next command cannot be executed until the recovery period (tCKA) has elapsed. Since this command differs from the self-refresh command described previously in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. CKE COMMAND I/O READ 0 DOUT 0 READ (BANK 0) DOUT 1 DOUT 2 DOUT 3 CAS latency = 2, burst length = 4 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 CLOCK SUSPEND 35 IC42S16102 OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle T0 CLK tCK tCHI tCL T1 T2 T3 T10 T17 T18 T19 T20 CKE HIGH tCS CS tCH tCS tCH tCH tCH tAS tAH CODE tAS tAH BANK 0 & 1 RAS tCS CAS tCS WE A0-A9 tAS CODE tAS tAH CODE BANK 0 ROW tAH ROW BANK 1 A10 A11 DQM HIGH I/O WAIT TIME T=100 s tRP tRC tRC tMCD tRAS tRC Undefined CAS latency = 2, 3 Don't Care 36 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Power-Down Mode Cycle T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tAS tAH ROW tAS tAH BANK 0 & 1 BANK 0 OR 1 T1 tCHI T2 T3 Tn Tn+1 Tn+2 Tn+3 tCL tCKS tCKH tCKA CKE tCS CS RAS tCS CAS tCS WE A0-A9 A10 A11 DQM I/O tRP POWER DOWN MODE EXIT POWER DOWN MODE Undefined Don't Care ROW BANK 1 BANK 0 BANK 1 BANK 0 tRAS tRC CAS latency = 2, 3 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 37 IC42S16102 Auto-Refresh Cycle T0 CLK tCKS tCK tCHI tCL T1 T2 T3 Tl Tm Tn Tn+1 CKE tCS tCH tCS tCH tCH tCH CS RAS tCS CAS tCS WE A0-A9 tAS tAH BANK 0 & 1 ROW ROW BANK 1 A10 A11 BANK 0 DQM I/O tRP [ tRC ][ tRC ][ tRC ] Undefined Don't Care tRAS tRC CAS latency = 2, 3 38 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Self-Refresh Cycle T0 T1 tCHI T2 T3 Tm Tm+1 Tm+2 Tn CLK tCKS tCK tCKA tCS tCH tCS tCH tCH tCKA tCL tCKS tCKS CKE CS RAS tCS CAS tCS tCH WE A0-A9 tAS tAH BANK 0 & 1 A10 A11 DQM I/O tRP SELF REFRESH MODE EXIT SELF REFRESH tRC tRC Undefined CAS latency = 2, 3 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 39 IC42S16102 Read Cycle T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tQMD tAC tAC tOH DOUT m (1) A0-A9 A10 A11 DQM COLUMN m BANK 0 AND 1 NO PRE BANK 1 BANK 0 OR 1 BANK 1 tCH BANK 0 ROW ROW BANK 1 BANK 0 tAC tOH DOUT m+1 tAC tOH DOUT m+2 tOH DOUT m+3 I/O tRCD tRAS tRC tLZ tCAC tHZ tRQL tRP tRCD tRAS tRC Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 40 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle / Auto-Precharge T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tQMD tAC tAC tOH DOUT m (1) A0-A9 A10 A11 DQM COLUMN m AUTO PRE BANK 1 ROW ROW BANK 1 BANK 0 tCH tAC tOH DOUT m+1 tAC tOH DOUT m+2 tOH DOUT m+3 I/O tLZ tRCD tRAS tRC tCAC tHZ tPQL tRP tRCD tRAS tRC Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 41 IC42S16102 Read Cycle / Full Page T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T260 T261 T262 T263 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tQMD tAC tAC tOH DOUT 0m (1) A0-A9 A10 A11 DQM COLUMN BANK 0 OR 1 BANK 0 tCH tAC tOH DOUT 0m+1 tAC tOH DOUT 0m-1 tAC tOH DOUT 0m tOH DOUT 0m+1 I/O tLZ tRCD tRAS tRC (BANK 0) tHZ tRBD tRP (BANK 0) tCAC (BANK 0)
Undefined CAS latency = 2, burst length = full page Don't Care Note 1: A8,A9 = Don't Care. 42 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle / Ping-Pong Operation (Bank Switching) T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tQMD tAC tAC tOH tOH DOUT 0m+1 DOUT 0m (1) (1) A0-A9 A10 A11 DQM COLUMN AUTO PRE ROW COLUMN AUTO PRE ROW ROW NO PRE BANK 1 BANK 1 BANK 0 OR 1 BANK 0 tCH tAC tAC tOH DOUT 1m ROW BANK 0 OR 1 BANK 0 BANK 1 tOH DOUT 1m+1 I/O tLZ tRRD (BANK 0 TO 1) tHZ tRCD (BANK 1) tLZ tHZ tRCD (BANK 0) tRCD (BANK 0) tCAC (BANK 1) tCAC (BANK 1) tRAS (BANK 0) tRP (BANK 0) tRAS (BANK 0) tRC (BANK 0) tRC (BANK 0) tRAS (BANK 1) tRP (BANK1) tRC (BANK 1)
Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 43 IC42S16102 Write Cycle T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tCH NO PRE BANK 1 BANK 0 OR 1 BANK 1 BANK 0 (1) A0-A9 A10 A11 DQM COLUMN m BANK 0 AND 1 ROW ROW BANK 1 BANK 0 tDS tDH tDS DIN m tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDPL tRP tRCD tRAS tRC Undefined I/O tRCD tRAS tRC
CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 44 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle / Auto-Precharge T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tCH BANK 0 AUTO PRE BANK 1 ROW BANK 1 (1) A0-A9 A10 A11 DQM COLUMN m ROW tDS tDH tDS DIN m tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDAL tRP tRCD tRAS tRC Undefined Don't Care I/O tRCD tRAS tRC
CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 45 IC42S16102 Write Cycle / Full Page T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T258 T259 T260 T261 T262 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tCH BANK 0 OR 1 BANK 0 (1) A0-A9 A10 A11 DQM COLUMN m tDS tDH tDS DIN 0m tDH tDS DIN 0m+1 tDH tDS DIN 0m+2 tDH DIN 0m-1 DIN 0m tDPL tRP I/O tRCD tRAS tRC
Undefined CAS latency = 2, burst length = full page Don't Care Note 1: A8,A9 = Don't Care. 46 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle / Ping-Pong Operation T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 BANK 1 (1) (1) A0-A9 A10 A11 DQM COLUMN AUTO PRE ROW COLUMN AUTO PRE ROW ROW NO PRE BANK 1 BANK 0 OR 1 BANK 0 ROW BANK 0 tCH tDS tDH tDS DIN 0m tDH tDS DIN 0m+1 tDH tDS DIN 0m+2 tDH tDS DIN 0m+3 tDPL tDH tDS DIN 1m tDH tDS DIN 1m+1 tDH tDS DIN 1m+2 tDH DIN 1m+3 tDPL tRCD (BANK 0) I/O tRRD (BANK 0 TO 1) tRCD (BANK 0) tRCD (BANK 1) tRAS (BANK 0) tRP (BANK 0) tRAS (BANK 0) tRC (BANK 0) tRC (BANK 0) tRAS (BANK 1) tRC (BANK 1)
Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 47 IC42S16102 Read Cycle / Page Mode T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 tQMD tAC NO PRE BANK 1 BANK 0 NO PRE BANK 1 tCS BANK 0 tCH tAC tOH DOUT n (1) (1) (1) A0-A9 A10 A11 DQM COLUMN m COLUMN n COLUMN o AUTO PRE BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0 tAC tOH DOUT m tAC tOH DOUT m+1 tAC tOH DOUT n+1 tAC tOH DOUT o tOH DOUT o+1 I/O tLZ tRCD tRAS tRC tCAC tHZ tCAC tCAC tRQL tRP Undefined Don't Care
CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care. 48 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle / Page Mode; Data Masking T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE NO PRE BANK 1 tCS tQMD tAC tCH tAC tOH DOUT m (1) (1) (1) A0-A9 A10 A11 DQM COLUMN m COLUMN n COLUMN o AUTO PRE BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0 BANK 0 tQMD tAC tAC tOH DOUT m+1 tAC tOH DOUT o tOH DOUT n tOH DOUT o+1 I/O tLZ tRCD tRAS tRC tCAC tHZ tCAC tLZ tCAC tRQL tRP tHZ
Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 49 IC42S16102 Write Cycle / Page Mode T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 tCS BANK 0 tCH BANK 0 OR 1 BANK 1 BANK 0 (1) (1) (1) A0-A9 A10 A11 DQM COLUMN m COLUMN n COLUMN o AUTO PRE BANK 0 AND 1 tDS tDH tDS DIN m tDH tDS DIN m+1 tDH tDS DIN n tDH tDS DIN n+1 I/O tRCD tRAS tRC tDH tDS tDH DIN o DIN o+1 tDPL tRP Undefined Don't Care CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care. 50 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle / Page Mode; Data Masking T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 BANK 1OR 0 BANK 1 BANK 0 (1) (1) (1) A0-A9 A10 A11 DQM COLUMN m COLUMN n COLUMN o AUTO PRE BANK 0 AND 1 tCS tCH tDS tDH tDS DIN m tDH tDS DIN m+1 tDH DIN n tDS I/O tRCD tRAS tRC tDH tDS tDH DIN o DIN o+1 tDPL tRP Undefined Don't Care CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 51 IC42S16102 Read Cycle / Clock Suspend T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL tCKS tCKH T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS NO PRE BANK 1 BANK 0 tQMD BANK 0 OR 1 BANK 1 BANK 0 (1) A0-A9 A10 A11 DQM COLUMN m AUTO PRE BANK 0 AND 1 ROW ROW BANK 1 BANK 0 tCH tAC tAC tOH tOH DOUT m+1 DOUT m I/O tLZ tRCD tRAS tRC tCAC tHZ tRP tRAS tRC Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. 52 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle / Clock Suspend T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL tCKS tCKH T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 BANK 0 (1) A0-A9 A10 A11 DQM COLUMN m AUTO PRE BANK 0 AND 1 ROW ROW BANK 1 BANK 0 tCH tDS tDH DIN m tDS DIN m+1 tDH I/O tRCD tRAS tRC tDPL tRP tRAS tRC Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 53 IC42S16102 Read Cycle / Precharge Termination T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tQMD tAC tCH tAC tOH DOUT m (1) (1) A0-A9 A10 A11 DQM COLUMN m ROW ROW BANK 0 OR 1 BANK 0 BANK 0 BANK 1 COLUMN n AUTO PRE NO PRE BANK 1 BANK 0 tAC tOH DOUT m+1 tHZ tOH DOUT m+2 I/O tLZ tRCD tRAS tRC tCAC tRQL tRP tRCD tRAS tRC tCAC
Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 54 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle / Precharge Termination T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tCH BANK 0 OR 1 BANK 0 tCS tCH BANK 0 ROW BANK 1 NO PRE BANK 1 BANK 0 tCS tDH tDS DIN 0m+2 DIN 0n (1) (1) A0-A9 A10 A11 DQM COLUMN m ROW COLUMN n AUTO PRE tDS tDH tDS DIN 0m DIN 0m+1 tDH tDS tDH I/O tRCD tRAS tRC tRCD tRP tRAS tRC Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 55 IC42S16102 Read Cycle / Byte Operation T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 tQMD tQMD tCH BANK 0 BANK 0 (1) A0-A9 A10 A11 UDQM COLUMN m AUTO PRE BANK 0 AND 1 ROW ROW BANK 1 tCS tCS tCH LDQM tAC tLZ tHZ tOH DOUT m tAC tLZ tAC tOH DOUT m+2 tOH DOUT m+3 I/O8-15 tAC tLZ tAC tOH DOUT m tOH DOUT m+1 I/O0-7 tRCD tRAS tRC tCAC tQMD tRQL tRP tRCD tRAS tRC
Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 56 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle / Byte Operation T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 tCH BANK 0 BANK 0 (1) A0-A9 A10 A11 UDQM COLUMN m AUTO PRE BANK 0 AND 1 ROW ROW BANK 1 tCS tCS tCH LDQM tDS tDS tDH DIN m tDS tDH DIN m tRCD tRAS tRC Undefined tDH tDS DIN m+1 tDS DIN m+3 tDPL tRP tRCD tRAS tRC DIN m+3 tDH tDH I/O8-15 I/O0-7 CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 57 IC42S16102 Read Cycle, Write Cycle / Burst Read, Single Write T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tQMD tAC tAC tOH DOUT m (1) (1) A0-A9 A10 A11 DQM COLUMN m NO PRE BANK 1 COLUMN n AUTO PRE NO PRE BANK 1 tCH tAC tOH DOUT m+1 BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0 BANK 0 tAC tOH DOUT m+2 tDS tOH DOUT m+3 DIN n tDH I/O tLZ tRCD tRAS tRC tCAC tHZ tDPL tRP Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 58 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 0 tCS tQMD tAC tAC tOH DOUT m (1) A0-A9 A10 A11 DQM COLUMN m BANK 0 AND 1 NO PRE BANK 1 BANK 0 OR 1 BANK 1 tCH BANK 0 ROW ROW BANK 1 BANK 0 tAC tOH DOUT m+1 tAC tOH DOUT m+2 tOH DOUT m+3 I/O tLZ tRCD tRAS tRC tCAC tHZ tRQL tRP tRCD tRAS tRC Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 59 IC42S16102 Read Cycle / Auto-Precharge T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 0 tCS tQMD tAC tAC tOH DOUT m (1) A0-A9 A10 A11 DQM COLUMN AUTO PRE ROW ROW BANK 1 BANK 1 BANK 0 tCH tAC tOH DOUT m+1 tAC tOH DOUT m+2 tOH DOUT m+3 I/O tLZ tRCD tRAS tRC tCAC tHZ tPQL tRP tRCD tRAS tRC Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 60 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle / Full Page T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T262 T263 T264 T265 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 BANK 0 tCS tCH NO PRE BANK 0 OR 1 BANK 0 (1) A0-A9 A10 A11 DQM COLUMN tAC tAC tOH DOUT 0m tAC tOH DOUT 0m+1 tAC tOH DOUT 0m-1 tAC tOH DOUT 0m tOH DOUT 0m+1 I/O tLZ tRCD (BANK 0) tHZ tRBD tRP (BANK 0) tCAC (BANK 0) tRAS (BANK 0) tRC (BANK 0)
Undefined Don't Care CAS latency = 3, burst length = full page Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 61 IC42S16102 Read Cycle / Ping Pong Operation (Bank Switching) T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 BANK 1 ROW NO PRE BANK 0 tCS tQMD tAC tLZ tAC tOH DOUT 0m (1) (1) A0-A9 A10 A11 DQM ROW COLUMN AUTO PRE COLUMN AUTO PRE ROW ROW NO PRE BANK 1 BANK 0 OR 1 BANK 0 tCH tAC tOH DOUT 0m+1 BANK 0 OR 1 BANK1 BANK 0 tAC tOH DOUT 1m tOH DOUT 1m+1 I/O tRRD (BANK 0 TO 1) tRCD (BANK 1) tCAC (BANK 1) tHZ tRQL (BANK 0) tRCD (BANK 0) tCAC (BANK 0) tRCD (BANK 0) tRAS (BANK 0) tRP (BANK 0) tRAS (BANK 0) tRC (BANK 0) tRC (BANK 0) tRAS (BANK 1) tRP (BANK1) tRC (BANK 1)
Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. 62 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tCH NO PRE BANK 1 BANK 0 OR 1 BANK 1 BANK 0 COLUMN BANK 0 AND 1 ROW BANK 1 BANK 0 (1) A0-A9 A10 A11 DQM ROW tDS tDH tDS DIN m tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDPL tRP tRCD tRAS tRC Undefined I/O tRCD tRAS tRC
CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 63 IC42S16102 Write Cycle / Auto-Precharge T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tCH BANK 0 BANK 1 (1) A0-A9 A10 A11 DQM COLUMN AUTO PRE ROW ROW BANK 1 tDS tDH tDS DIN m tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDAL tRP tRCD tRAS tRC Undefined I/O tRCD tRAS tRC
CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 64 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle / Full Page T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T259 T260 T261 T262 T263 T264 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS BANK 0 tCH NO PRE BANK 0 OR 1 BANK 0 COLUMN (1) A0-A9 A10 A11 DQM tDS tDH tDS DIN 0m tDH tDS DIN 0m+1 tDH tDS DIN 0m+2 tDH DIN 0m-1 DIN 0m tDPL tRP I/O tRCD tRAS tRC
Undefined Don't Care CAS latency = 3, burst length = full page Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 65 IC42S16102 Write Cycle / Ping-Pong Operation (Bank Switching) T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 BANK 1 (1) (1) A0-A9 A10 A11 DQM COLUMN AUTO PRE ROW COLUMN AUTO PRE ROW ROW NO PRE BANK 1 BANK 0 OR 1 BANK 0 ROW BANK 1 BANK 0 tCH tDS tDH tDS DIN 0m tDH tDS DIN 0m+1 tDH tDS DIN 0m+2 tDH tDS DIN 0m+3 tDPL (BANK 0) tDH tDS DIN 1m tDH tDS DIN 1m+1 tDH tDS DIN 1m+2 tDH DIN 1m+3 tDPL tRCD I/O tRRD (BANK 0 TO 1) tRCD (BANK 0) tRCD (BANK 1) tRAS (BANK 0) tRP (BANK 0) tRAS tRC tRC (BANK 0) tRAS (BANK 1) tRC (BANK 1)
Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 66 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle / Page Mode T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 1 BANK 0 tCS tQMD BANK 0 NO PRE NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 BANK 0 (1) (1) (1) A0-A9 A10 A11 DQM COLUMN m COLUMN n COLUMN o AUTO PRE BANK 0 AND 1 tCH tAC tAC tOH DOUT o tAC tLZ tAC tOH DOUT m tAC tOH DOUT m+1 tAC tOH DOUT n tOH DOUT n+1 tOH DOUT o+1 I/O tCAC tRCD tRAS tRC tCAC tCAC tRQL tRP tHZ Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 67 IC42S16102 Read Cycle / Page Mode; Data Masking T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 1 BANK 0 tCS tQMD BANK 1 BANK 0 tCH tAC tLZ tAC tOH DOUT m (1) (1) (1) A0-A9 A10 A11 DQM COLUMN m COLUMN n COLUMN o AUTO PRE BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0 NO PRE NO PRE NO PRE BANK 1 BANK 0 tQMD tAC tOH DOUT m+1 DOUT n tAC tOH tAC tOH DOUT o tOH DOUT o+1 I/O tCAC tRCD tRAS tRC tCAC tCAC tRQL tRP tHZ
Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. 68 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Write Cycle / Page Mode T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS BANK 0 BANK 0 tCH NO PRE BANK 1 NO PRE BANK 1 NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 BANK 0 (1) (1) (1) A0-A9 A10 A11 DQM COLUMN m COLUMN n COLUMN o AUTO PRE BANK 0 AND 1 tDS tDH tDS DIN m tDH tDS DIN m+1 tDH DIN n tDS tDH tDS DIN o tDH DIN o+1 I/O tRCD tRAS tRC tDPL tRP Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 69 IC42S16102 Write Cycle / Page Mode; Data Masking T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 1 BANK 0 NO PRE BANK 1 BANK 0 BANK 1 BANK 0 NO PRE NO PRE BANK 1 BANK 0 BANK 1OR 0 (1) (1) (1) A0-A9 A10 A11 DQM COLUMN m COLUMN n COLUMN o AUTO PRE BANK 0 AND 1 tCS tCH tDS tDH tDS DIN m tDH tDS DIN m+1 tDH DIN n tDS I/O tRCD tRAS tRC tDH tDS tDH DIN o DIN o+1 tDPL tRP Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. 70 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle / Clock Suspend T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL tCKS tCKH T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS NO PRE BANK 1 BANK 0 tQMD BANK 0 OR 1 BANK 1 tCH tAC tAC tOH tOH DOUT m+1 DOUT m (1) A0-A9 A10 A11 DQM COLUMN m AUTO PRE BANK 0 AND 1 BANK 0 I/O tLZ tRCD tRAS tRC tCAC tHZ tRP
Undefined Don't Care CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 71 IC42S16102 Write Cycle / Clock Suspend T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL tCKS tCKH T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 BANK 0 (1) A0-A9 A10 A11 DQM COLUMN m AUTO PRE BANK 0 AND 1 ROW ROW BANK 1 BANK 0 tCH tDS tDH DIN m tDS DIN m+1 tDH I/O tRCD tRAS tRC tDPL tRP tRAS tRC Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don't Care. 72 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle / Precharge Termination T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tQMD tAC BANK 0 OR 1 BANK 0 tCH BANK 0 ROW BANK 1 (1) A0-A9 A10 A11 DQM COLUMN m ROW tAC tOH DOUT m tAC tOH DOUT m+1 tHZ tOH DOUT m+2 I/O tLZ tRCD tRAS tRC tCAC tRQL tRP tRCD tRAS tRP
Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 73 IC42S16102 Write Cycle / Precharge Termination T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tCH BANK 0 OR 1 BANK 0 tCS tCH BANK 0 ROW BANK 1 (1) A0-A9 A10 A11 DQM COLUMN m ROW tDS tDH tDS DIN 0m DIN 0m+1 tDH tDS DIN 0m+2 tDH I/O tRCD tRAS tRC tRCD tRP tRAS tRP Undefined Don't Care CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care. 74 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle / Byte Operation T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 tCS tQMD tQMD tCH BANK 0 OR 1 BANK 1 BANK 0 BANK 0 (1) A0-A9 A10 A11 UDQM COLUMN m AUTO PRE BANK 0 AND 1 ROW ROW BANK 1 tCS tCH LDQM tAC tLZ tHZ tOH DOUT m tAC tLZ tAC DOUT m+2 tHZ tOH DOUT m+3 I/O8-15 tAC tLZ tAC tOH DOUT m tHZ tOH DOUT m+1 I/O0-7 tRCD tRAS tRC tCAC tQMD tRQL tRP tRCD tRAS tRP
Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 75 IC42S16102 Write Cycle / Byte Operation T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 tCH BANK 0 BANK 0 (1) A0-A9 A10 A11 UDQM COLUMN m AUTO PRE BANK 0 AND 1 ROW ROW BANK 1 tCS tCS tCH LDQM tDS tDS tDH DIN m tDS tDH DIN m tRCD tRAS tRC DIN m+1 tDS DIN m+3 tDPL tRP tRCD tRAS tRP tDH tDS DIN m+3 tDH tDH I/O8-15 I/O0-7 Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don't Care. 76 Integrated Circuit Solution Inc. DR042-0A 01/18/2005 IC42S16102 Read Cycle, Write Cycle / Burst Read, Single Write T0 CLK tCKS tCK tCKA tCH tCS tCH tCH tCH tCHI tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CKE tCS CS RAS tCS CAS tCS WE tAS tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 0 tCS tQMD tAC tAC tOH tOH DOUT m+1 DIN n DOUT m (1) (1) A0-A9 A10 A11 DQM COLUMN m NO PRE BANK 1 COLUMN n AUTO PRE NO PRE BANK 1 BANK 0 tCH BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0 tDS tDH I/O tLZ tRC tRAS tRC
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