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C16550 Universal Asynchronous Receiver/Transmitter with FIFOs
October 12, 1998 Product Specification
AllianceCORETM Facts
Device Family CLBs Used IOBs Used Global IOBs System Clock fmax Device Features Used Core Specifics Spartan 493 391 4 34.4 MHz XC4000XL 493 391 4 56.4 MHz
CAST, Inc.
24 White Birch Drive Pomona, New York 10907 USA Phone: +1 914-354-4945 Fax: +1 914-354-0325 E-Mail: info@cast-inc.com URL: www.cast-inc.com
Global Buffers
Features
* * * Capable of running with all existing 16450 and 16550A Software Asynchronous operation In FIFO mode, Transmitter and Receiver are each buffered with 16-byte FIFOs to reduce the number of interrupts of the CPU Programmable data word length (5 - 8 bit), parity and stop bits Parity, overrun and framing error checking Supports up to 1.5 Mbps transmission rates Programmable Baud Rate Generator allows division of any reference clock by 1 to (216-1) and generates an internal 16 X Clock False start bit detection Automatic break generation and detection Internal diagnostic capabilities Peripheral modem control functions
* * * *
* * * *
Provided with Core Documentation Core documentation Design File Formats .ngo, .XNF Netlist; VHDL Source RTL available extra Constraint Files .ncf Verification Tool VHDL Schematic Symbols Viewlogic Evaluation Model None Reference designs & None application notes Additional Items None Design Tool Requirements Xilinx Core Tools Alliance/Foundation 1.4 Entry/Verification VHDL RTL Tool Support Support provided by CAST, Inc.
Note: 1. Assuming all core signals are routed off-chip.
Applications
The C16550 core is used in serial data communications and modem applications.
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C16550 Universal Asynchronous Receiver/Transmitter with FIFOs
DDIS TXRDYn RXRDYn DO[7:0] Chip Select & R/W Control Logic Line Status Register FIFO Control Register Transmitter FIFO
INTERNAL DATA BUS
CLK A[2:0] ADSn CS0 CS1 CS2n RDn WRn MRESETn
TXDATA MUX
Transmitter Holding Buffer Modem Control Register Modem Status Register Interrupt Enable Register Interrupt ID Register Divisor LSB Divisor MSB Baud Generator Rx Buffer Register MUX RX FIFO Modem Control Logic
RTSn DTRn OUT1 OUT2 CTSn DSRn DCDn RIn Interrupt Control Logic
DIN[7:0]
Line Control Register
INTRPT
BOUDOUTn
RCLK RXDATA
Scratchpad Register
X8789
Figure 1: C16550 Asynchronous Receiver/Transmitter with FIFOs Block Diagram
General Description
The C16550 programmable asynchronous communications interface (UART) megafunction provides data formatting and control to a serial communication channel. The megafunction has select, read/write, interrupt and bus interface logic features that allow data transfers over an 8bit bi-directional parallel data bus system. With proper formatting and error checking, the megafunction can transmit and receive serial data, supporting asynchronous operation.
Line Status Register (LSR)
This register provides information on the status of data transfers between the C16550 and the CPU.
Interrupt Enable Register (IER)
The Interrupt Enable Register masks interrupts from the modem status registers, line status, transmitter empty and receiver ready to the INTRPT output pin.
Modem Status Register (MSR)
This register provides the current state of modem control lines.
Functional Description
The C16550 core is partitioned into modules as shown in Figure 1 and described below.
Modem Control (Register & Logic)
This register controls the interface lines with the MODEM (MODEM control logic) and changes the status of the C16550 from normal operating mode and local loop-back mode (diagnostics mode).
Chip Select & R/W Control Logic
The chip select and R/W control logic controls the internal chip addressing.
Line Control Register (LCR)
The Line Control Register is used to specify the data communication format. The break feature, parity, stop bits and word length can be changed by writing to the appropriate bits in LSR.
Transmitter Holding Buffer
The transmitter section is composed of a Transmit Holding Register (THR) and a Transmit Shift Register (TSR). Writing to THR will transfer the contents of the data bus (DIN 70) to the Transmit Holding Register every time that the THR
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CAST, Inc. or TSR is empty. This write operation should be done when Transmit Holding Register Empty (THRE) is set. Table 1: Core Signal Pinout Signal Signal Direction CLK A[2:0] ADSn CS0 CS1 CS2n RDn WRn MRESETn DIN[7:0] Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Input Input Input Input Output Output Input Input
Description Master Clock; uses 1 global IOB pin Register Select Address Strobe Chip Select 0 Chip Select 1 Chip Select 2 Read Control; uses 1 global IOB pin Write Control; uses 1 global IOB pin External Reset Data Input Bus Driver Disable Chip Select Out Transmit ready Receiver ready Data Output Bus Transmit Data Request-to-Send Data Terminal Ready Output 1 Output 2 Clear-to -Send Data Set Ready Data Carrier Detect Ring Indicator Interrupt Baud Out Receive Clock; uses 1 global IOB pin Receive Data
Receiver Buffer & RX FIFO
This register contains the assembled received data. On the falling edge of the start bit, the receiver section starts its operations. The start bit is valid if the RXDATA is still low at the middle sample of Start bit, thus preventing the receiver from assembling a false data character. The receiver buffer is actually a 16-byte FIFO.
Scratchpad Register (SR)
This register stores the temporary byte for variable use.
FIFO Control Register (FCR)
This register is used to control FIFOs' logic (to enable, to clear, to set FIFOs' trigger level and set the type of DMA signaling).
Interrupt Identification Register (IIR)
The Interrupt Identification Register provides the source of interrupt among four levels of prioritized interrupt conditions in order to minimize the CPU overhead during data transfers.
DDIS CSOUT TxRDYn RxRDYn D0[7:0] TXDATA RTSn DTRn OUT1 OUT2 CTSn DSRn DCDn RIn INTRPT BOUDOUT RCLK RXDATA
Interrupt Control Logic
The C16550 contains an interrupt generation and prioritization logic. When an interrupt is generated the IIR indicates that an interrupt is pending and also the type of interrupt between various available. The C16550 provides four prioritized levels of interrupt: * * * * Priority 1 Receiver line status (highest priority) Priority 2 Receiver data ready or receiver character timeout Priority 3 Transmitter holding register empty Priority 4 Modem Status (lowest priority)
Baud Generator & LSB and MSB Divisor Registers
The C16550 contains a programmable baud rate generator that takes any clock input from DC-20MHz and dividing it by any divisor from 1 to (216 -1). The output frequency of the Boudoutn is equal to 16X of the transmission baud rate. The two registers divisor MSB and divisor LSB are used to store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization in order to ensure desired operation of the baud generator. The formula for the divisor is: divisor = CLKIN frequency in / (desired baud rate X 16) * *
Core Modifications
The C16550 core can be customized to include: * Different FIFOs size (separately for Transmitter and Receiver) Removal of internal baud rate generator Different CPU interface
This Material Copyrighted By Its Respective Manufacturer
C16550 Universal Asynchronous Receiver/Transmitter with FIFOs Please contact CAST directly for any required modifications.
Related Information
Data Transmission Circuits 1993 Data Book
Contact: Texas Instruments Literature Response Center P.O. Box 809066 Dallas, Texas 75380-9066 URL: http://www.ti.com
Pinout
The pinout of the C16550 core has not been fixed to specific FPGA I/O, allowing flexibility with a users application. Signal names are shown in the block diagram in Figure 1, and in Table 1.
Core Assumptions
* * * The bi-directional data bus has been split into two separate buses: DIN[7:0] and DO[7:0] The 1_ stop bit mode (for 5 bit word length) is not supported Signals rd2, wr2, xin and xout have been eliminated from the interface
Xilinx Programmable Logic
For information on Xilinx programmable logic or development system software, contact your local Xilinx sales office, or: Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com For general Xilinx literature, contact:
Verification Methods
The C16550 UART core's functionality has been extensively tested with a VHDL testbench and a large number of test patterns.
Recommended Design Experience
The user must be familiar with HDL design methodology as well as instantiation of Xilinx netlists in a hierarchical design environment.
Phone: E-mail:
+1 800-231-3386 (inside the US) +1 408-879-5017 (outside the US) literature@xilinx.com
For AllianceCORETM specific information, contact: Phone: E-mail: URL: +1 408-879-5381 alliancecore@xilinx.com www.xilinx.com/products/logicore/alliance/ tblpart.htm
Ordering Information
This product is available from the AllianceCORE partner listed on the first page. Please contact the partner for pricing and more information. The C16550 core is licensed from Moxsyn S.R.L.
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