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LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP DESCRIPTIO
The LTC(R)2600/LTC2610/LTC2620 are octal 16-, 14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP packages. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, crosstalk and load regulation in singlesupply, voltage-output multiples. The parts use a simple SPI/MICROWIRETM compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisy-chain capability and a hardware CLR function are included. The LTC2600/LTC2610/LTC2620 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; and after power-up, they stay at zero scale until a valid write and update take place.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
FEATURES
s
s s s s s s s s s
Smallest Pin Compatible Octal DACs: LTC2600: 16 Bits LTC2610: 14 Bits LTC2620: 12 Bits Guaranteed 16-Bit Monotonic Over Temperature Tiny 16-Lead Narrow SSOP Package Wide 2.5V to 5.5V Supply Range Low Power Operation: 250A per DAC at 3V Individual Channel Power-Down to 1A, Max Ultralow Crosstalk between DACs (<10V) High Rail-to-Rail Output Drive (15mA, Min) Double-Buffered Digital Inputs Pin-Compatible 10-/8-Bit Versions (LTC1660/LTC1665)
APPLICATIO S
s s s s
Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment
BLOCK DIAGRA
GND 1
16 VCC
REGISTER
REGISTER
REGISTER
REGISTER
VOUT A
2
DAC A
DAC H
15 VOUT H
REGISTER
REGISTER
REGISTER
VOUT B
3
DAC B
REGISTER
DAC G
14 VOUT G
REGISTER
REGISTER
REGISTER
REGISTER
VOUT C
4
DAC C
DAC F
13 VOUT F DNL (LSB)
REGISTER
REGISTER
REGISTER
REGISTER
VOUT D
5
DAC D
DAC E
12 VOUT E
REF
6 CONTROL LOGIC DECODE
11
CLR
CS/LD
7
10
SDO
SCK
8
32-BIT SHIFT REGISTER
9
SDI
2600 BD
U
W
U
Differential Nonlinearity (LTC2600)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2600 G21
VCC = 5V VREF = 4.096V
2600f
1
LTC2600/LTC2610/LTC2620 ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW GND VOUT A VOUT B VOUT C VOUT D REF CS/LD SCK 1 2 3 4 5 6 7 8 16 VCC 15 VOUT H 14 VOUT G 13 VOUT F 12 VOUT E 11 CLR 10 SDO 9 SDI
Any Pin to GND ........................................... - 0.3V to 6V Any Pin to VCC .............................................- 6V to 0.3V Maximum Junction Temperature ......................... 125C Operating Temperature Range LTC2600C/LTC2610C/LTC2620C .......... 0C to 70C LTC2600I/LTC2610I/LTC2620I .......... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................ 300C
LTC2600CGN LTC2600IGN LTC2610CGN LTC2610IGN LTC2620CGN LTC2620IGN GN PART MARKING 2600 2600I 2610 2610I 2620 2620I
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 150C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Resolution Monotonicity DNL INL VCC = 5V, VREF = 4.096V (Note 2) Differential Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) Integral Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) Load Regulation VREF = VCC = 5V, Midscale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.5V, Midscale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking CONDITONS
q q q q q q q q
ELECTRICAL CHARACTERISTICS
MIN 12 12
LTC2620 TYP MAX
MIN 14 14
LTC2610 TYP MAX
MIN 16 16
LTC2600 TYP MAX
UNITS Bits Bits
DC Performance
0.5 0.75 4 3 0.1 0.1 0.2 0.2
1 16 0.5 0.5 1 1 12 0.3 0.3 0.8 0.8
1 64 2 2 4 4
0.025 0.125 0.025 0.125 0.05 0.05 0.25 0.25
LSB/mA LSB/mA LSB/mA LSB/mA
SYMBOL ZSE VOS GE PSR
PARAMETER Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient Power Supply Rejection
CONDITIONS VCC = 5V, VREF = 4.096V Code = 0 VCC = 5V, VREF = 4.096V, (Note 7) VCC = 5V, VREF = 4.096V VCC = 10%
q q
LTC2600/LTC2610/LTC2620 MIN TYP MAX 1 1 1.7
q
UNITS mV mV V/C %FSR ppm/C dB
2600f
DC Performance 9 9 0.7
0.2 6.5 -80
2
U
LSB LSB
W
U
U
WW
W
LTC2600/LTC2610/LTC2620
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL ROUT PARAMETER DC Output Impedance DC Crosstalk (Note 4) CONDITIONS VREF = VCC = 5V, Midscale; -15mA IOUT 15mA q VREF = VCC = 2.5V, Midscale; -7.5mA IOUT 7.5mA q Due to Full Scale Output Change (Note 5) Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V, VREF = 5.6V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND VCC = 2.5V, VREF = 2.6V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND Reference Input Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current, Power Down Mode All DACs Powered Down Positive Supply Voltage Supply Current For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) All DACs Powered Down (Note 3) VCC = 5V All DACs Powered Down (Note 3) VCC = 3V
q q q q q q
ELECTRICAL CHARACTERISTICS
LTC2600/LTC2610/LTC2620 MIN TYP MAX 0.025 0.030 10 3.5 -7.3 15 15 7.5 7.5 0 11 16 90 0.001 2.5 2.6 2.0 0.35 0.10 0.80 1000 1 5.5 4 3.2 1 1 34 34 18 24 60 60 50 50 VCC 20 0.15 0.15
UNITS V V/mA V mA mA mA mA V k pF A V mA mA A A V/s pF nV * s kHz nV/Hz nV/Hz VP-P V V
ISC
Short-Circuit Output Current
Normal Mode
q
Power Supply
q q q q q
AC Performance Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise Digital I/O VIH VIL Digital Input High Voltage Digital Input Low Voltage VCC = 2.5V to 5.5V VCC = 2.5V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VCC = 2.5V to 5.5V Load Current = -100A Load Current = +100A VIN = GND to VCC (Note 6)
q q q q q q q q q
At Midscale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz 2.4 2.0
12 180 120 100 15
0.8 0.6 0.5 VCC - 0.4 0.4 1 8
V V V V V A pF
VOH VOL ILK CIN
Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance
2600f
3
LTC2600/LTC2610/LTC2620
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Figure 1) (Note 6)
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V CONDITONS
q q q q q q q q q q q
TI I G CHARACTERISTICS
VCC = 2.5V to 5.5V 4 4 9 9 10 7 7 20 45 20 7 50 ns ns ns ns ns ns ns ns ns ns ns MHz
t9 t10
Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535.
TYPICAL PERFOR A CE CHARACTERISTICS
Current Limiting
0.10 0.08 0.06 0.04 CODE = MIDSCALE VREF = VCC = 5V VREF = VCC = 3V 1.0 0.8 0.6 0.4
OFFSET ERROR (mV)
VOUT (V)
0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -40 -30 -20 -10 0 10 IOUT (mA) 20 30 40 VREF = VCC = 3V VREF = VCC = 5V
VOUT (mV)
4
UW
UW
MIN
TYP
MAX
UNITS
CLR Pulse Width CS/LD High to SCK Positive Edge SCK Frequency 50% Duty Cycle
q
Note 3: Digital inputs at 0V or VCC. Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the measured DAC at midscale, unless otherwise noted. Note 5: RL = 2k to GND or VCC. Note 6: Guaranteed by design and not production tested. Note 7: Inferred from measurement at code 256 (LTC2600), code 64 (LTC2610) or code 16 (LTC2620).
(LTC2600/LTC2610/LTC2620) Offset Error vs Temperature
3 2 1 0 -1 -2 -3 -50
Load Regulation
CODE = MIDSCALE
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -35 -25 -15 -5 5 IOUT (mA) 15 25 35 VREF = VCC = 3V VREF = VCC = 5V
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2600 G01
2600 G02
2600 G03
2600f
LTC2600/LTC2610/LTC2620 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600/LTC2610/LTC2620
Zero-Scale Error vs Temperature
3 2.5 ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 0 -50 0.4 0.3 OFFSET ERROR (mV) -30 -10 10 30 50 TEMPERATURE (C) 70 90 0.2 0.1 0 -0.1 -0.2 -0.3 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -0.4 -50 -2 -3
Gain Error vs VCC
0.4 0.3 0.2
GAIN ERROR (%FSR) 450 400 350 300 ICC (nA) 250 200 150
0.1 0 -0.1 -0.2 -0.3 -0.4 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
2600 G07
Midscale Glitch Impulse
VOUT 10mV/DIV 12nV-s TYP
VOUT (V)
CS/LD 5V/DIV
2600 G10
2.5s/DIV
UW
2600 G04
Gain Error vs Temperature
3 2 1 0 -1
Offset Error vs VCC
2.5
3
3.5
4 VCC (V)
4.5
5
5.5
2600 G06
2600 G05
ICC Shutdown vs VCC
Large-Signal Settling
VOUT 0.5V/DIV
VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5s/DIV
2600 G09
100 50 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
2600 G08
Power-On Reset Glitch
5.0 4.5 4.0
Headroom at Rails vs Output Current
5V SOURCING
VCC 1V/DIV 4mV PEAK 4mV PEAK VOUT 10mV/DIV 250s/DIV
2600 G11
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 456 IOUT (mA) 7 8 9 10 3V SINKING 5V SINKING 3V SOURCING
2600 G12
2600f
5
LTC2600/LTC2610/LTC2620 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600/LTC2610/LTC2620
Supply Current vs Logic Voltage
2.4 2.3 2.2 2.1 ICC (mA) 2.0 1.9 1.8 1.7 1.6 1.5 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 5 VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC
Multiplying Bandwidth
0 -3 -6 -9 -12 -15
dB
-18 -21 -24 -27 -30 -33 -36 1k VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 10k 100k FREQUENCY (Hz) 1M
2600 G16
10mA/DIV
10mA/DIV
6
UW
2600 G13
Exiting Power-Down to Midscale
VCC = 5V VREF = 2V VOUT 0.5V/DIV
VOUT 1V/DIV
Hardware CLR
CS/LD 5V/DIV
CLR 5V/DIV
2.5s/DIV
2600 G14
1s/DIV
2600 G25
Output Voltage Noise, 0.1Hz to 10Hz
Short-Circuit Output Current vs VOUT (Sinking)
VOUT 10V/DIV
0mA
0
1
2
3
456 SECONDS
7
8
9
10
VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 1V/DIV
2600 G18
2600 G17
Short-Circuit Output Current vs VOUT (Sourcing)
0mA
VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 1V/DIV
2600 G19
2600f
LTC2600/LTC2610/LTC2620 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600
Integral Nonlinearity (INL)
32 24 16 DNL (LSB) INL (LSB) 8 0 -8 -16 -24 -32 0 16384 32768 CODE 49152 65535
2600 G20
VCC = 5V VREF = 4.096V
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2600 G21
INL (LSB)
DNL vs Temperature
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -16 -0.6 -0.8 -1.0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -24 -32 DNL (NEG) VCC = 5V VREF = 4.096V DNL (POS) INL (LSB) 32 24 16
0 -8 INL (NEG)
DNL (LSB)
LTC2610
Integral Nonlinearity (INL)
8 6 4 0.4 DNL (LSB) INL (LSB) 2 0 -2 -4 -0.6 -6 -8 0 4096 8192 CODE 12288 16383
2600 G26
UW
2600 G23
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 16 8 0 -8 -16 -24 VCC = 5V VREF = 4.096V 32 24
INL vs Temperature
VCC = 5V VREF = 4.096V
INL (POS)
INL (NEG)
-32 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2600 G22
INL vs VREF
1.5 VCC = 5.5V 1.0 INL (POS) 0.5
DNL vs VREF
VCC = 5.5V
8
DNL (POS) 0 DNL (NEG) -0.5 -1.0 -1.5
0
1
2 3 VREF (V)
4
5
2600 G24
0
1
2 3 VREF (V)
4
5
2600 G25
Differential Nonlinearity (DNL)
1.0 0.8 0.6 VCC = 5V VREF = 4.096V
VCC = 5V VREF = 4.096V
0.2 0 -0.2 -0.4
-0.8 -1.0 0 4096 8192 CODE 12288 16383
2600 G27
2600f
7
LTC2600/LTC2610/LTC2620 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2620
Integral Nonlinearity (INL)
2.0 1.5 1.0 0.4 DNL (LSB) INL (LSB) 0.5 0 -0.5 -1.0 -0.6 -1.5 -2.0 0 1024 2048 CODE 3072 4095
2600 G28
PIN FUNCTIONS
GND (Pin 1): Analog Ground. VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Voltage Outputs. The output range is 0 - VREF. REF (Pin 6): Reference Voltage Input. 0V VREF VCC. CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 9): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK. The LTC2600 accepts input word lengths of either 24 or 32 bits. SDO (Pin 10): Serial Interface Data Output. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is used for daisy-chain operation. CLR (Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V. CMOS and TTL compatible. VCC (Pin 16): Supply Voltage Input. 2.5V VCC 5.5V.
8
UW
Differential Nonlinearity (DNL)
1.0 0.8 0.6 VCC = 5V VREF = 4.096V
VCC = 5V VREF = 4.096V
0.2 0 -0.2 -0.4
-0.8 -1.0 0 1024 2048 CODE 3072 4095
2600 G29
U
U
U
2600f
LTC2600/LTC2610/LTC2620
BLOCK DIAGRA
GND 1
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
DAC REGISTER
VOUT A
2
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
VOUT B
3
DAC B
DAC REGISTER
DAC REGISTER
INPUT REGISTER
VOUT C
INPUT REGISTER
DAC REGISTER
4
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
VOUT D
5
DAC D
DAC REGISTER
REF
6 CONTROL LOGIC DECODE
CS/LD
7
SCK
8
TI I G DIAGRA
SCK
SDI t5 CS/LD t8 SDO
2600 F01
W
W
16 VCC DAC A DAC H 15 VOUT H DAC G 14 VOUT G DAC C DAC F 13 VOUT F DAC E 12 VOUT E 11 CLR 10 SDO 32-BIT SHIFT REGISTER 9 SDI
2600 BD02
UW
t1 t2 1 t3 2 t4 3 23 t6 24 t10
t7
Figure 1
2600f
9
LTC2600/LTC2610/LTC2620
OPERATIO
Power-On Reset
The LTC2600/LTC2610/LTC2620 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2600/ LTC2610/LTC2620 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. For example, if the power supply is ramped to 5V in 1ms, the analog outputs rise less than 10mV above ground (typ) during power-on. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range - 0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. Transfer Function The transfer function is k VOUT(IDEAL) = N VREF 2
Table 1.
COMMAND C3 C2 C1 C0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Write to Input Register n Update (Power-Up) DAC Register n Write to Input Register n, Update (Power Up) All Write to and Update (Power Up) n Power Down n No Operation ADDRESS (n) A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H All DACs
2600f
10
U
where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6). Serial Interface Referring to Figure 2a: The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering-on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command word, C3C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSB-to-LSB, followed by 0, 2 or 4 don't-care bits (LTC2600, LTC2610 and LTC2620 respectively). Data can only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a; the command (C3-C0) and address (A3-A0) assignments are shown in Table 1. Optionally, the instruction may be extended to 32 bits. To use the 32-bit word width, 8 don't-care bits are transferred to the device first, followed by the 24-bit input word as just described (see Figure 2b). The 32-bit word width is required for daisy-chain operation, and is also available to accommodate microprocessors which have a minimum word width of 2 bytes.
LTC2600/LTC2610/LTC2620
OPERATIO
INPUT WORD (LTC2600)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (16 BITS) D15 D14 D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL01
INPUT WORD (LTC2610)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (14 BITS + 2 DON'T-CARE BITS) D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL02
INPUT WORD (LTC2620)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D11 D10 D9 MSB DATA (12 BITS + 4 DON'T-CARE BITS) D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL03
Daisy-Chain Operation The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a "daisy chain" series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the "no operation" command (1111) for the other devices in the chain.
U
X X
X
X
X
X
Power Down Mode Command 0100b is reserved for the special "power down" instruction (see Table 1). Any or all DACs may be powered down by selecting the appropriate DAC address (n). In this mode, the digital interface stays active while the analog circuits are disabled. The static power consumption of the digital interface is leakage current only. The reference input and analog outputs are set in a high impedance state, although the DAC feedback resistors are still in place loading the DAC outputs with 90k to ground. As shown in Table 1, any or all of the DACs can be powered back up by executing an update command to the selected DAC which will power up that DAC and update its output with the last loaded DAC word. Voltage Outputs Each of the 8 rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA.
2600f
11
LTC2600/LTC2610/LTC2620
OPERATIO
DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers' DC output impedance is 0.025 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25 * 1mA * 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF.
12
U
Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping "signal" and "power" grounds separated internally and by reducing shared internal resistance to just 0.005. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer.
2600f
LTC2600/LTC2610/LTC2620
OPERATIO
The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.025), and will degrade DC crosstalk. Note that the LTC2600/LTC2610/LTC2620 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance.
U
Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
2600f
13
COMMAND WORD
ADDRESS WORD
DATA WORD
24-BIT INPUT WORD
LTC2600/LTC2610/LTC2620
Figure 2a. LTC2600 24-Bit Load Sequence (Minimum Input Word). LTC2610 SDI Data Word: 14-Bit Input Code + 2 Don't-Care Bits; LTC2620 SDI Data Word: 12-Bit Input Code + 4 Don't-Care Bits
CS/LD 6 7 13 14 17 D15 D14 D13 D12 D11 A2 ADDRESS WORD C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 A1 A0 A3 X COMMAND WORD X X X C3 C2 C1 X C3 C2 C1 C0 8 9 10 21 11 12 18 16 20 15 19 X 22 D10 23 D9 24 D8 25 D7 DATA WORD D8 D7 D6 D5 D4 D3 D2 D1 D0 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0
SCK
1
2
3
4
5
SDI
X
X
X
X
X
DON'T CARE
SDO
X
X
X
X
X
PREVIOUS 32-BIT INPUT WORD t1 t2 SCK 17 t3 SDI SDO D15 t8 PREVIOUS D15 PREVIOUS D14 t4 D14 18
CURRENT 32-BIT INPUT WORD
YYYY F02b
Figure 2b. LTC2600 32-Bit Load Sequence (Required for Daisy-Chain Operation). LTC2610 SDI/SDO Data Word: 14-Bit Input Code + 2 Don't-Care Bits; LTC2620 SDI/SDO Data Word: 12-Bit Input Code + 4 Don't-Care Bits
U
OPERATIO
14
2 7 13 14 17 D7
YYYY F02a
CS/LD 3 4 10 21 D3 D2 D1 D0 23 D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 11 12 18 24 22 16 20 C0 A3 A2 A1 A0 D15 5 6 8 9 15 19 C1
SCK
1
SDI
C3
C2
2600f
VREF = VCC
POSITIVE FSE
VREF = VCC
OUTPUT VOLTAGE
OUTPUT VOLTAGE INPUT CODE (c)
OUTPUT VOLTAGE 0 (a) 32, 768 INPUT CODE 65, 535
0V
NEGATIVE OFFSET
INPUT CODE
2600 F03
(b)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
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OPERATIO
LTC2600/LTC2610/LTC2620
15
2600f
LTC2600/LTC2610/LTC2620
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
RELATED PARTS
PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5s/750A, 8s/450A VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2s for 10V Step
2600f
16 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
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GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 TYP .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC
GN16 (SSOP) 0502
LT/TP 0303 2K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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