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Integrated Circuit Systems, Inc.
Preliminary Information
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL1 GND NC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 SEL0 SEL1 SEL2 NC VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19
GENERAL DESCRIPTION
The M1010-01 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for OC-12 and OC-48 optical network systems supporting 622 2,488 MHz rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1010-01 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.
28 29 30 31 32 33 34 35 36
M1010
(Top View)
18 17 16 15 14 13 12 11 10
VCC NC nFOUT FOUT GND NC NC VCC GND
FEATURES
Ideal for OC-12/48 data clock Integrated SAW delay line Output frequencies from 150 to 175 MHz (Specify VCSO output frequency at time of order) Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz) LVPECL clock output Pin-selectable feedback and reference divider ratios, no programming required Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations Using M1010-01-155.5200
Frequency Input (Mfin) Ratio 8 2 1 Input Reference Clock (MHz) 19.44 77.76 155.52 Output Clock MHz 155.52
Table 1: Example I/O Clock Frequency Combinations
SIMPLIFIED BLOCK DIAGRAM
M1010
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL 3 2 0 R Div 1 M Div Mfin Div VCSO Loop Filter
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
SEL2:0 FIN_SEL1:0
Divider LUT Mfin Divider LUT
FOUT nFOUT
Figure 2: Simplified Block Diagram
M1010-01 Datasheet Rev 0.4
M1010-01 VCSO Based Clock Jitter Attenuator
Revised 29Sep2003
Integrated Circuit Systems, Inc.
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Integrated Circuit Systems, Inc.
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information
DETAILED BLOCK DIAGRAM
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP RPOST nOP_OUT nVC VC
External Loop Filter Components
M1010
MUX
OP_IN Phase Detector
nOP_IN
OP_OUT
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL
3
RIN
0
R Div
1
RIN Loop Filter Amplifier
Phase Locked Loop (PLL)
SAW Delay Line
Phase Shifter
VCSO
M Div
Mfin Divider
SEL2:0
Divider LUT Mfin Divider LUT
FOUT nFOUT
FIN_SEL1:0
2
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 18, 19, 33 12, 13, 17, 25, 32 15 16 20 21 22 23 24 27 28 29 30 31 34, 35, 36 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC NC FOUT nFOUT nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 FIN_SEL1 FIN_SEL0 SEL0 SEL1 SEL2 DNC I/O Configuration Description
Ground Input Output Input Power Output Input Input Input Input Input No internal terminator Internal pull-UP resistor1 Internal pull-down resistor
1
Power supply ground connections. External loop filter connections. See Figure 4, External Loop Filter, on pg. 4.
Power supply connection, connect to +3.3V. No internal connection. Clock output pairs. Differential LVPECL. Reference clock input pair. Differential LVPECL or LVDS. Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair. Differential LVPECL or LVDS.
Internal pull-down resistor1 Internal pull-UP resistor1 Internal pull-down resistor
1
Input clock frequency selection. LVCMOS/LVTTL. Internal pull-down resistor1 See Table 3, Mfin (Frequency Input) Divider Look-Up Table (LUT) on pg. 3.
Internal pull-UP resistor1 Do Not Connect.
M and R divider value selection. LVCMOS/ LVTTL. See Table 4, SEL2:0 Look-up Table (LUT) on pg. 3.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-up resistors, see "Inputs with Pull-down" and "Inputs with Pull-up" in Table 8, DC Characteristics, on pg. 6.
M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information SEL2:0 Look-up Table (LUT) The SEL2:0 pins select the feedback and reference divider values M and R to enable adjustment of loop bandwidth and jitter tolerance.
SEL2:0
PLL DIVIDER LOOK-UP TABLES
Mfin (Frequency Input) Divider Look-Up Table (LUT) The FIN_SEL1:0 pins select the feedback divider value ("Mfin").
FIN_SEL1:0
M 236 79 14 239 1 2 4 8
R
Description
Mfin Value 8 2 1 x
0 0 1 1
0 1 0 1
Sample Ref. Freq. (MHz) 1 19.44 77.76 155.52 Test mode. Do not use.
M1010-01-155.5200
0 0 0 0
0 0 1 1
0 1 0 1
100 101 110 111
236 79 14 239 Various divider values to adjust bandwidth 1 and jitter tolerance 2 4 8
Table 4: SEL2:0 Look-up Table (LUT)
Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)
Note 1: Example with M1010-01-155.5200.
FUNCTIONAL DESCRIPTION
The M1010-01 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). A configurable frequency divider (labeled "Mfin Divider") provides the division options to accomodate various reference clock frequencies. In addition, configurable feedback and reference dividers (the "M Divider" and "R Divider") provide divider value options to enable adjustment of loop bandwidth and jitter tolerance. For example, the M1010-01-155.5200 (see "Ordering Information" on pg. 8) has a 155.52MHz VCSO frequency: The Mfin feedback divider allows an input frequency to be the VCSO output frequency divided by 1, 2, or 8. Therefore, for the base input frequency of 155.52MHz, the actual input reference clock frequencies can be: 155.52, 77.76, and 19.44MHz. (See Table 3 on pg. 3.) The PLL The PLL uses a phase detector and configurable dividers to synchronize the output of the VCSO with selected reference clock. The "Mfin Divider" and "M Divider" divide the VCSO frequency, feeding the result into the phase detector. The selected input reference clock is divided by the "R Divider". The result is fed into the other input of the phase detector.
M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
The phase detector compares its two inputs. It then outputs pulses to the loop filter as needed to increase or decrease the VCSO frequency and thereby match and lock the divider output's frequency and phase to those of the input reference clock. Due to the narrow tuning range of the VCSO (+200ppm), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections. Relationship Among Frequencies and Dividers The VCSO center frequency must be specified at time of order. The relationship between the VCSO (Fvcso) frequency, the Mfin divider, the M divider, the R divider, and the input reference frequency (Fin) is: Fvcso = Fin x Mfin x --R Clock Output The M1010-01 provides one differential LVPECL output pair FOUT. PECL and LVDS product options are available; consult factory.
M
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External Loop Filter To provide stable PLL operation, the M1010-01 requires the use of an external loop filter. This is implemented by connecting passive external components to the device as shown in Figure 4 below. The M1010-01 utilizes a differential analog signal path to minimize noise coupling from the system. Because of this, the loop filter implementation requires two identical complementary RC filters as shown here.
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information PLL bandwidth is affected by the "M" value and the "Mfin" value, as well as the VCSO frequency. The various SEL1:0 settings can be used to actively change PLL loop bandwidth in a given application. See "SEL2:0 Look-up Table (LUT)" on pg. 3. See Table 5, Example Loop Filter Component Values for M1010-01-155.5200, on pg. 4. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application.
VC
6 7
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
nOP_IN
Figure 4: External Loop Filter
Example Loop Filter Component Values for M1010-01-155.52001
VCSO Parameters: KVCO = 200kHz/V, RIN = 2050k VCSO Bandwidth = 700kHz. , Device Configuration (MHz) Example External Loop Filter Component Value Nominal Performance Using These Values
FRef
FVCSO
(MHz)
Mfin
M, R R loop Value2 1 2 1 118.0k 118.0k 59.0k 59.0k 118.0k 40.2k 59.0k 76.8k
C loop
R post
C post
19.44
155.52
8
1.0F 22.0F 1.0F 2.2F 2.2F 1.0F 1.0F 2.0F
100k 200k 100k 100k 200k 40.2k 100k 200k
1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF
PLL Loop Damping Passband Peak Bandwidth Factor Amplitude @ Center (dB) Freq. 6.5 0.05 10Hz 270Hz 134Hz 610Hz 267Hz 134Hz 740Hz 267Hz 180Hz 6.8 6.5 6.8 6.8 6.3 6.8 6.3 0.04 0.05 0.04 0.04 0.05 0.04 0.05 4Hz 20Hz 10Hz 10Hz 20Hz 10Hz 8Hz
77.76
155.52
2
2 8 1
155.52
155.52
1
4 8
Table 5: Example Loop Filter Component Values for M1010-01-155.5200
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com. Note 2: For loop timing applications, the recommended value for the product of "Mfin" x "M" is 8 or higher.
M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
oC
-45 to +100
Table 6: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature Commercial Industrial
V
oC oC
0 -40
+70 +85
Table 7: Recommended Conditions of Operation
M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT = 150-175MHz, Outputs terminated with 50 to VCC - 2V TA = -40 oC to +85 oC (industrial)
Symbol Parameter
Min 3.135
Typ 3.3 162
Max 3.465
Unit Conditions
Power Supply VCC ICC Differential Inputs IIH IIL VP-P VCMR LVCMOS / LVTTL Inputs Inputs with Pull-down VIH VIL CIN IIH IIL IIH IIL Rpullup All Inputs Differential Outputs CIN VOH VOL VP-P
Positive Supply Voltage Power Supply Current Input High Current Input Low Current Peak to Peak Input Common Mode Input Input High Voltage Input Low Voltage Input Capacitance Input High Current Input Low Current Input High Current Input Low Current Internal Pull-up Resistor Input Capacitance Output High Voltage Output Low Voltage
FOUT, nFOUT
1
V mA A A A A V
DIF_REF0, DIF_REF1 nDIF_REF0, nDIF_REF1 DIF_REF0, DIF_REF1 nDIF_REF0, nDIF_REF1 DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 REF_SEL, FIN_SEL1, FIN_SEL0, SEL2, SEL1, SEL0 All Inputs except nDIF_REF1:0, SEL2:0 -5 -150 0.15 0.5 2
150 5
Vcc 0.8 4
V V pF A A k
VCC = VIN = 3.456V
Vcc + 0.3 V
-0.3
150 -5
51
Rpulldown Internal Pull-down Resistor Inputs with Pull-up
nDIF_REF1, nDIF_REF0, SEL2, SEL1, SEL0 All Inputs Vcc - 1.4 Vcc - 2.0 0.4
5 -150
51 4
A A k pF
VCC = 3.456V VIN = 0 V
Vcc - 1.0 V Vcc - 1.7 V 0.85
Peak to Peak Output Voltage
V
Note 1: Single-ended measurement. See Figure 5, Output Rise and Fall Time on pg. 7.
Table 8: DC Characteristics
M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT = 150-175MHz, Outputs terminated with 50 to VCC - 2V TA = -40 oC to +85 oC (industrial)
Symbol Parameter
Min DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 FOUT, nFOUT Commercial Industrial 18.75 150
Typ
Max 175 50 175
Unit Conditions
FIN FOUT APR PLL Loop Constants 1 KVCO RIN n Phase Noise and Jitter J(t) odc tR tF
Input Frequency Output Frequency VCSO Pull-Range VCO Gain Internal Loop Resistor Single Side Band Phase Noise @155.52MHz Jitter (rms) @155.52MHz Output Duty Cycle 2 Output Rise Time for FOUT, nFOUT
2
MHz MHz MHz ppm ppm kHz/V k kHz dBc/Hz Fin=19.44_MHz dBc/Hz Mfin=8, M=x, R=x dBc/Hz ps ps % ps ps
20% to 80% 20% to 80%
120 50
200 150
200 2050 700
BWVCSO VCSO Bandwidth
1kHz Offset 10kHz Offset 100kHz Offset 12kHz to 20MHz 50kHz to 80MHz 45 325 325
-72 -94 -123
0.5 0.5 50 450 450 55 500 500
Output Fall Time 2 for FOUT, nFOUT
Table 9: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 5, Example Loop Filter Component Values for M1010-01-155.5200 on pg. 4. Note 2: See Parameter Measurement Information on pg. 7.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time Output Duty Cycle
nFOUT FOUT VP-P Clock Output 20% tR 20% tF odc = tPW tPERIOD tPW (Output Pulse Width) tPERIOD
80%
80%
Figure 5: Output Rise and Fall Time
Figure 6: Output Duty Cycle
M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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Preliminary Information
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Figure 7: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
VCSO Freq (MHz) 155.52 156.25 Temperature Order Part Number M1010-01 - 155.5200 M1010-01I 155.5200 M1010-01 - 156.2500 M1010-01I 156.2500
Table 10: Ordering Information
commercial industrial commercial industrial
Consult ICS for the availability of other VCSO frequencies.
Part Number:
Device Number Temperature " - " = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) VCSO Frequency (MHz) Consult ICS for available VCSO frequencies
M1010- 01 - xxx.xxxx
Figure 8: Part Numbering Scheme
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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