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INTEGRATED CIRCUITS
DATA SHEET
P89LPC932
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM Preliminary data 2002 Oct 21
Philips Semiconductors
Preliminary Datasheet - Subject to Change -
80C51 8-bit microcontroller with two-cycle instructions
8KB Flash with 512 Byte Data EEPROM and 768 Byte RAM
P89LPC932
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Special Function Registers Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Clock Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CPU Clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Low Speed Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Medium Speed Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High Speed Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-Chip RC oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Watchdog Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 External Clock Input Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CPU Clock (CCLK) Wakeup Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CPU Clock (CCLK) Modification: DIVM Register . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Low Power Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Data RAM Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 External interrupt inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Quasi-bidirectional output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Open drain output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input-only configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Push-pull output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Additional Port Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
2002 Oct 21
Philips Semiconductors
Preliminary Datasheet - Subject to Change -
80C51 8-bit microcontroller with two-cycle instructions
8KB Flash with 512 Byte Data EEPROM and 768 Byte RAM
P89LPC932
Power-on Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Timers/Counters 0 and 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timer overflow toggle output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Real-Time Clock/System Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Capture/Compare Unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 CCU clock (CCUCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CCU clock prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Basic timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PWM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Alternating Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PLL operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CCU interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Baud rate generator and selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) . . . . 28 The 9th bit (Bit 8) in double buffering (Modes 1, 2 and 3) . . . . . . . . . . . . . . 28 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Typical SPI configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Comparator interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Comparators and Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . 34 Keypad Interrupt (KBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2002 Oct 21
3
Philips Semiconductors
Preliminary Datasheet - Subject to Change -
80C51 8-bit microcontroller with two-cycle instructions
8KB Flash with 512 Byte Data EEPROM and 768 Byte RAM
P89LPC932
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ISP and IAP capabilities of the LPC932 . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Flash organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Flash programming and erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power-on Reset code execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Hardware activation of the Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 In-Application Programming method (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . 38 User Configuration Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 User Sector Security Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC Characteristics, ISP ENTRY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Licences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2002 Oct 21
4
Philips Semiconductors
Preliminary Datasheet - Subject to Change -
80C51 8-bit microcontroller with two-cycle instructions
8KB Flash with 512 Byte Data EEPROM and 768 Byte RAM
P89LPC932
List of Figures
Logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Block diagram.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 28-pin TSSOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 TSSOP28 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 28-pin PLCC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PLCC28 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Block diagram of oscillator control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Interrupt sources, interrupt enables, and power-down wake-up sources . . . . . . . . .20 Asymmetrical PWM, downcounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Symmetrical PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Alternate output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Capture/Compare Unit interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Baud rate sources for UART (Modes 1, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 I2C-bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 I2C-bus serial interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 SPI single master single slave configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 SPI dual device configuration, where either can be a master or a slave. . . . . . . . . .32 SPI single master multiple slaves configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Comparator input and output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Watchdog timer in Watchdog mode (WDTE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .35 SPI Master timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 SPI Master timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 SPI Slave timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 SPI Slave timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Shift Register Mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 External clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 ISP Entry waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2002 Oct 21
5
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
GENERAL DESCRIPTION
The P89LPC932 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC932 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC932 in order to reduce component count, board space, and system cost.
FEATURES
* A high performance 80C51 CPU provides instruction cycle times of 167-333 ns for all instructions except multiply and divide when executing at 12 MHz. This is 6 times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. * 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). * 8 KB Flash code memory with 1 KB erasable sectors and 64-byte erasable page size. * 256-byte RAM data memory. 512-byte auxiliary on-chip RAM. * 512-byte customer Data EEPROM on chip allows serialization of devices, storage of set-up parameters, etc. * Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output. * Real-Time clock that can also be used as a system timer. * Capture/Compare Unit (CCU) provides PWM, input capture, and output compare functions. * Two analog comparators with selectable inputs and reference source. * Enhanced UART with fractional baudrate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities. * 400 kHz byte-wide I2C communication port. * SPI communication port. * Eight keypad interrupt inputs, plus two additional external interrupt inputs. * Four interrupt priority levels. * Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog time-out time is selectable from 8 values. * Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. * Low voltage reset (Brownout detect) allows a graceful system shut-down when power fails. May optionally be configured as an interrupt. * Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. * Configurable on-chip oscillator with frequency range and RC oscillator options (selected by user programmed Flash configuration bits). The RC oscillator option allows operation without external oscillator components. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 12 MHz. The RC oscillator option is selectable and fine tunable. * Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. * Port "input pattern match" detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. * Second data pointer. * Schmitt trigger port inputs. * LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. * Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. * 23 I/O pins minimum (28-pin package). Up to 26 I/O pins while using on-chip oscillator and reset options. * Only power and ground connections are required to operate the LPC932 when on-chip oscillator and reset options are selected. * Serial Flash programming allows simple in-circuit production coding. Flash security bits prevent reading of sensitive application programs.
2002 Oct 21
6
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
* In-Application Programming of the Flash code memory. This allows changing the code in a running application. * Idle and two different Power down reduced power modes. Improved wakeup from Power down mode (a low interrupt input starts execution). Typical Power down current is 1A (total Power down with voltage comparators disabled). * 28-pin PLCC and TSSOP packages. * Emulation support.
ORDERING INFORMATION
Part Number P89LPC932BA P89LPC932BDH Package PLCC28: plastic leaded chip carrier; 28 leads TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm Temperature Range 0 to +70 C 0 to +70 C Frequency 0-12 MHz 0-12 MHz Drawing Number SOT261-2 SOT361-1
LOGIC SYMBOL
VDD VSS
P89 LPC932
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2 XTAL1
TxD RxD T0 INT0 INT1 RST OCB OCC ICB OCD MOSI MISO SS SPICLK OCA ICA
PORT0
PORT3
Figure 1: Logic symbol.
2002 Oct 21
7
PORT2
PORT1
SCL SDA
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
BLOCK DIAGRAM
High Performance LPC932 CPU
8KB Code Flash UART
Internal Bus
I2C
256 byte Data RAM
512 byte Auxiliary RAM 512 byte Data EEPROM Port 3 Configurable I/Os Port 2 Configurable I/Os Port 1 Configurable I/Os Port 0 Configurable I/Os Keypad Interrupt Programmable Oscillator Divider CPU Clock On-Chip RC Oscillator
SPI
Real-Time Clock/ System Timer
Timer0 Timer1 Watchdog Timer and Oscillator
CCU (Capture/ Compare Unit)
Analog Comparators
Crystal or Resonator
Configurable Oscillator
Power Monitor (Power-On Reset, Brownout Reset)
Figure 2: Block diagram.
2002 Oct 21
8
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
PIN CONFIGURATION
28-pin TSSOP package
ICB/P2.0 OCD/P2.1 KBI0/CMP2/P0.0 OCC/P1.7 OCB/P1.6 RST/P1.5 VSS XTAL1/P3.1 CLKOUT/XTAL2/P3.0 INT1/P1.4 SDA/INT0/P1.3 SCL/T0/P1.2 MOSI/P2.2 MISO/P2.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1 P0.2/CIN2A/KBI2 P0.3/CIN1B/KBI3 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 VDD P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SS
Figure 3: TSSOP28 pin configuration.
28-pin PLCC package
P0.1/CIN2B/KBI1 26 25 24 23 22 21 20 19 12 13 14 15 16 17 18 KBI0/CMP2/P0.0
OCC/P1.7
OCD/P2.1
28
OCB/P1.6 RST/P1.5 VSS XTAL1/P3.1 CLKOUT/XTAL2/P3.0 INT1/P1.4 SDA/INT0/P1.3
5 6 7 8 9 10 11
27
4
3
2
1
P2.6/OCA
P2.7/ICA
ICB/P2.0
P0.2/CIN2A/KBI2 P0.3/CIN1B/KBI3 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 VDD P0.6/CMP1/KBI6 P0.7/T1/KBI7
P1.1/RXD
MOSI/P2.2
SCL/T0/P1.2
MISO/P2.3
Figure 4: PLCC28 pin configuration.
2002 Oct 21
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P2.5/SPICLK
P1.0/TXD
P2.4/SS
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
PIN DESCRIPTIONS
MNEMONIC PIN NO. for TSSOP28/ PLCC28 P0.0 - P0.7 3, 26, 25, 24, 23, 22, 20, 19 TYPE NAME AND FUNCTION
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pullup disabled. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. The Keypad Interrupt feature operates with port 0 pins. All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below. 3 I/O P0.0 Port 0 bit 0. O CMP2 Comparator 2 output. I KBI0 Keyboard Input 0. 26 I/O P0.1 Port 0 bit 1. I CIN2B Comparator 2 positive input B. I KBI1 Keyboard Input 1. 25 I/O P0.2 Port 0 bit 2. I CIN2A Comparator 2 positive input A. I KBI2 Keyboard Input 2. 24 I/O P0.3 Port 0 bit 3. I CIN1B Comparator 1 positive input B. I KBI3 Keyboard Input 3. 23 I/O P0.4 Port 0 bit 4. I CIN1A Comparator 1 positive input A. I KBI4 Keyboard Input 4. 22 I/O P0.5 Port 0 bit 5. I CMPREFComparator reference (negative) input. I KBI5 Keyboard Input 5. 20 I/O P0.6 Port 0 bit 6. O CMP1 Comparator 1 output. I KBI6 Keyboard Input 6. 19 I/O P0.7 Port 0 bit 7. I/O T1 Timer/counter 1 external count input or overflow output. I KBI7 Keyboard Input 7. P1.0 - P1.7 18, 17, 12, I/O (for Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three 11, 10, 6, 5, P1.0-P1.4, pins as noted below. During reset Port 1 latches are configured in the input only mode 4 P1.6-P1.7); with the internal pullup disabled. The operation of the configurable port 1 pins as inputs I (for P1.5) and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. P1.2 - P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. 18 17 I/O O I/O I Port 1 also provides various special functions as described below. P1.0 Port 1 bit 0. TxD Transmitter output for the serial port. P1.1 Port 1 bit 1. RxD Receiver input for the serial port.
2002 Oct 21
10
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM MNEMONIC PIN NO. for TSSOP28/ PLCC28 12 TYPE NAME AND FUNCTION
P89LPC932
I/O I/O I/O I I I/O I I I I
11
10 6
5 4 P2.0 - P2.7 1, 2, 13, 14, 15, 16, 27, 28
I/O O I/O O I/O
Port 1 bit 2. (Open-drain when used as an output) Timer/counter 0 external count input or overflow output. (Open-drain when used as outputs) SCL I2C serial clock input/output. P1.3 Port 1 bit 3. (Open-drain when used as an output) INT0 External interrupt 0 input. SDA I2C serial data input/output. P1.4 Port 1 bit 4. INT1 External interrupt 1 input. P1.5 Port 1 bit 5. (Input only) RST External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode. P1.6 Port 1 bit 6. OCB Output Compare B. P1.7 Port 1 bit 7. OCC Output Compare C. Port 2: Port 2 is a 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pullup disabled. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. This port is not available in 20-pin package and is configured automatically as outputs to conserve power. The alternate functions for these pins must not be enabled. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below. P2.0 Port 2 bit 0. ICB Input capture B. P2.1 Port 2 bit 1. OCD Output compare D. P2.2 Port 2 bit 2. MOSI SPI master out slave in. When configured as master, this pin is output, when configured as slave, this pin is input. P2.3 Port 2 bit 3. MISO SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output. P2.4 Port 2 bit 4. SS SPI Slave select. P2.5 Port 2 bit 5. SPICLK SPI clock. When configured as master, this pin is output, when configured as slave, this pin is input. (Not available in 20-pin package) P2.6 Port 2 bit 6. OCA Output compare A P2.7 Port 2 bit 7. ICA Input capture A
P1.2 T0
1 2 13
I/O I I/O O I/O I/O I/O I/O I/O I I/O I/O I/O O I/O I
14
15 16
27 28
2002 Oct 21
11
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM MNEMONIC PIN NO. for TSSOP28/ PLCC28 P3.0 - P3.1 9, 8 TYPE NAME AND FUNCTION
P89LPC932
I/O
Port 3: Port 3 is an 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pullup disabled. The operation of port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: P3.0 Port 3 bit 0. XTAL2 Output from the oscillator amplifier (when a crystal oscillator option is selected via the FLASH configuration). CLKOUTCPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer. P3.1 Port 3 bit 1. XTAL1 Input to the oscillator circuit and internal clock generator circuits (when selected via the FLASH configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, AND if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/ system timer. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power down modes.
9
I/O O O
8
I/O I
VSS VDD
7 21
I I
SPECIAL FUNCTION REGISTERS
Note: Special Function Registers (SFRs) accesses are restricted in the following ways: 1. User must NOT attempt to access any SFR locations not defined. 2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs. 3. SFR bits labeled '-', '0' or '1' can ONLY be written and read as follows: - '-' Unless otherwise specified, MUST be written with '0', but can return any value when read (even if it was written with '0'). It is a reserved bit and may be used in future derivatives. - '0' MUST be written with '0', and will return a '0' when read. - '1' MUST be written with '1', and will return a '1' when read.
2002 Oct 21
12
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
SPECIAL FUNCTION REGISTERS TABLE
Name Description SFR Address Bit Functions and Addresses MSB LSB Reset Value Hex Binary
E7 ACC* Accumulator E0H
E6
E5
E4
E3
E2
E1
E0 00H 00000000
AUXR1#
Auxiliary Function Register
A2H
CLKLP
EBRR
ENT1
ENT0
SRST
0
-
DPS
00H1
000000x0
F7 B* B Register F0H
F6
F5
F4
F3
F2
F1
F0 00H 00000000
BRGR0# Baud Rate Generator Rate Low BRGR1# Baud Rate Generator Rate High
BEH BFH
00H 00H
00000000 00000000
BRGCON# Baud Rate Generator Control
BDH
-
-
-
-
-
-
SBRGS
BRGEN
00H%
xxxxxx00
CCCRA# CCCRB# CCCRC# CCCRD#
Capture Compare A Control Register Capture Compare B Control Register Capture Compare C Control Register Capture Compare D Control Register
EAH EBH ECH EDH
ICECA2 ICECB2 -
ICECA1 ICECB1 -
ICECA0 ICECB0 -
ICESA ICESB -
ICNFA ICNFB -
FCOA FCOB FCOC FCOD
OCMA1 OCMB1 OCMC1 OCMD1
OCMA0 OCMB0 OCMC0 OCMD0
00H 00H 00H 00H
00000000 00000000 xxxxx000 xxxxx000
CMP1# CMP2#
Comparator 1 Control Register Comparator 2 Control Register
ACH ADH
-
-
CE1 CE2
CP1 CP2
CN1 CN2
OE1 OE2
CO1 CO2
CMF1 CMF2
00H1 00H1
xx000000 xx000000
DEECON# Data EEPROM Control Register DEEDAT# Data EEPROM Data Register DEEADR# Data EEPROM Address Register
F1H F2H F3H
EEIF
HVERR
ECTL1
ECTL0
-
-
-
EADR8
0EH 00H 00H
00001110 00000000 00000000
DIVM#
CPU Clock Divide-by-M Control
95H
00H
00000000
DPTR DPH DPL
Data Pointer (2 bytes) Data Pointer High Data Pointer Low 83H 82H 00H 00H 00000000 00000000
I2ADR#
I2C Slave Address Register
DBH
I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 DF DE I2EN DD STA DC STO DB SI DA AA D9 -
GC D8 CRSEL
00H
00000000
I2CON*# I2DAT# I2SCLH# I2SCLL#
I2C Control Register I2C Data Register Serial Clock Generator/SCL Duty Cycle Register High Serial Clock Generator/SCL Duty Cycle Register Low
D8H DAH DDH DCH
-
00H
x00000x0
00H 00H
00000000 00000000
2002 Oct 21
13
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Name
Description
SFR Address
Bit Functions and Addresses MSB LSB
Reset Value Hex Binary
I2STAT#
I2C Status Register
D9H
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
F8H
11111000
ICRAH# ICRAL# ICRBH# ICRBL#
Input Capture A Register High Input Capture A Register low Input Capture B Register High Input Capture B Register Low
ABH AAH AFH AEH
00H 00H 00H 00H 00000000 00000000 00000000
AF IEN0* Interrupt Enable 0 A8H EA
AE EWDRT
AD EBO
AC ES/ESR
AB ET1
AA EX1
A9 ET0
A8 EX0 00H 00000000
EF IEN1*# Interrupt Enable 1 E8H EIEE
EE EST
ED -
EC ECCU
EB ESPI
EA EC
E9 EKBI
E8 EI2C 00H1 00x00000
BF IP0* Interrupt Priority 0 B8H -
BE PWDRT
BD PBO
BC PS/PSR
BB PT1
BA PX1
B9 PT0
B8 PX0 00H1 x0000000
IP0H#
Interrupt Priority 0 High
B7H
-
PWDRT H
PBOH
PSH/ PSRH
PT1H
PX1H
PT0H
PX0H
00H1
x0000000
FF IP1*# Interrupt Priority 1 F8H PIEE
FE PST
FD -
FC PCCU
FB PSPI
FA PC
F9 PKBI
F8 PI2C 00H1 00x00000
IP1H#
Interrupt Priority 1 High
F7H
PIEEH
PSTH
-
PCCUH
PSPIH
PCH
PKBIH
PI2CH
00H1
00x00000
KBCON#
Keypad Control Register
94H 86H 93H
-
-
-
-
-
-
PATN _SEL
KBIF
00H1 00H FFH
xxxxxx00 00000000 11111111
KBMASK# Keypad Interrupt Mask Register KBPATN# Keypad Pattern Register
OCRAH# OCRAL# OCRBH# OCRBL# OCRCH# OCRCL# OCRDH# OCRDL#
Output Compare A Register High Output Compare A Register Low Output Compare B Register High Output Compare B Register Low Output Compare C Register High Output Compare C Register Low Output Compare D Register High Output Compare D Register Low
EFH EEH FBH FAH FDH FCH FFH FEH
00H 00H 00H 00H 00H 00H 00H 00H
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
87 P0* Port 0 80H T1/KB7
86
85
84 CIN1A/ KB4
83 CIN1B/ KB3
82 CIN2A/ KB2
81 CIN2B/ KB1
80 CMP2/ KB0 Note 1
CMP1/ CMPREF/ KB6 KB5
97 P1* Port 1 90H OCC
96 OCB
95 RST
94 INT1
93 INT0/ SDA
92 T0/SCL
91 RxD
90 TxD Note 1
2002 Oct 21
14
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Name
Description
SFR Address
Bit Functions and Addresses MSB LSB
Reset Value Hex Binary
A7 P2* Port 2 A0H ICA
A6 OCA
A5 SPICLK
A4 SS
A3 MISO
A2 MOSI
A1 OCD
A0 ICB Note 1
B7 P3* Port 3 B0H -
B6 -
B5 -
B4 -
B3 -
B2 -
B1 XTAL1
B0 XTAL2 Note 1
P0M1# P0M2# P1M1# P1M2# P2M1# P2M2# P3M1# P3M2#
Port 0 Output Mode 1 Port 0 Output Mode 2 Port 1 Output Mode 1 Port 1 Output Mode 2 Port 2 Output Mode 1 Port 2 Output Mode 2 Port 3 Output Mode 1 Port 3 Output Mode 2
84H 85H 91H 92H A4H A5H B1H B2H
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) (P1M1.7) (P1M1.6) (P1M2.7) (P1M2.6) -
FFH 00H
11111111 00000000 11x1xx11 00x0xx00 11111111 00000000 xxxxxx11 xxxxxx00
(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3H1 (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00H1 FFH 00H
(P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) -
(P3M1.1) (P3M1.0) 03H1 (P3M2.1) (P3M2.0) 00H1
PCON# PCONA#
Power Control Register Power Control Register A
87H B5H
SMOD1 RTCPD
SMOD0 DEEPD
BOPD VCPD
BOI
GF1 I2PD
GF0 SPPD
PMOD1 SPD
PMOD0 CCUPD
00H 00H1
00000000 00000000
D7 PSW* Program Status Wword D0H CY
D6 AC
D5 F0
D4 RS1
D3 RS0
D2 OV
D1 F1
D0 P 00H 00000000
PT0AD#
Port 0 Digital Input Disable
F6H
-
-
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
-
00H
xx00000x
RSTSRC# Reset Source Register
DFH
-
-
BOF
POF
R_BK
R_WD
R_SF
R_EX
Note 2
RTCCON# Real-Time Clock Control RTCH# RTCL# Real-Time Clock Register High Real-Time Clock Register Low
D1H D2H D3H
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
60H1,5 011xxx00 00H5 00H
5
00000000 00000000
SADDR# SADEN# SBUF
Serial Port Address Register Serial Port Address Enable Serial Port Data Buffer Register
A9H B9H 99H
00H 00H xxH
00000000 00000000 xxxxxxxx
9F SCON* Serial Port Control 98H SM0/FE
9E SM1
9D SM2
9C REN
9B TB8
9A RB8
99 TI
98 RI 00H 00000000
SSTAT#
Serial Port Extended Status Register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00H
00000000
SP
Stack Pointer
81H
07H
00000111
SPCTL#
SPI Control Register
E2H E1H
SSIG SPIF
SPEN WCOL
DORD -
MSTR -
CPOL -
CPHA -
SPR1 -
SPR0 -
04H 00H
00000100 00xxxxxx
SPSTAT# SPI Status Register
2002 Oct 21
15
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Name
Description
SFR Address
Bit Functions and Addresses MSB LSB
Reset Value Hex Binary
SPDAT#
SPI Data Register
E3H
00H
00000000
TAMOD#
Timer 0 and 1 Auxiliary Mode
8FH
-
-
-
T1M2
-
-
-
T0M2
00H
xxx0xxx0
8F TCON* Timer 0 and 1 Control 88H TF1
8E TR1
8D TF0
8C TR0
8B IE1
8A IT1
89 IE0
88 IT0 00H 00000000
TCR20*# TCR21# TH0 TH1 TH2# TICR2# TIFR2# TISE2# TL0 TL1 TL2# TMOD TOR2H# TOR2L#
CCU Control Register 0 CCU Control Register 1 Timer 0 High Timer 1 High CCU Timer High CCU Interrupt Control Register CCU Interrupt Flag Register CCU Interrupt Status Encode Register Timer 0 Low Timer 1 Low CCU Timer Low Timer 0 and 1 Mode CCU Reload Register High CCU Reload Register Low
C8H F9H 8CH 8DH CDH C9H E9H DEH 8AH 8BH CCH 89H CFH CEH CBH CAH
PLEEN TCOU2
HLTRN -
HLTEN -
ALTCD -
ALTAB PLLDV.3
TDIR2 PLLDV.2
TMOD21 PLLDV.1
TMOD20 PLLDV.0
00H 00H 00H 00H 00H
00000000 0xxx0000 00000000 00000000 00000000 00000x00 00000x00 xxxxx000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxx00 0000000
TOIE2 TOIF2 -
TOCIE2D TOCF2D -
TOCIE2C TOCF2C -
TOCIE2B TOCF2B -
TOCIE2A TOCF2A -
-
TICIE2B TICF2B
TICIE2A TICF2A
00H 00H 00H 00H 00H 00H
ENCINT.2 ENCINT.1 ENCINT.0
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
00H 00H 00H
TPCR2H# Prescaler Control Register High TPCR2L# Prescaler Control Register Low
-
-
-
-
-
-
TPCR2H.1 TPCR2H.0
00H 00H
TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0
TRIM#
Internal Oscillator Trim Register
96H
-
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
Notes 4,5
WDCON# Watchdog Control Register WDL# Watchdog Load
A7H C1H C2H C3H
PRE2
PRE1
PRE0
-
-
WDRUN WDTOF
WDCLK
Notes 3,5 FFH 11111111
WFEED1# Watchdog Feed 1 WFEED2# Watchdog Feed 2
Notes:
* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits, must be written with 0's. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is '0'. If any of them is written if BRGEN = 1, result is unpredictable. Unimplemented bits in SFRs (labeled '-' ) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are '0's although they are unknown when read. 1. All ports are in input only (high impendance) state after power-up. 2. The RSTSRC register reflects the cause of the LPC932 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF - the power-on reset value is xx110000. 3. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all 1, WDRUN=1 and WDCLK=1. WDTOF bit is 1 after watchdog reset and is 0 after power-on reset. Other resets will not affect WDTOF. 4. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. 5. The only reset source that affects these SFRs is power-on reset.
2002 Oct 21
16
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
FUNCTIONAL DESCRIPTION
(Please refer to the LPC932 User's Manual for a more detailed functional description).
ENHANCED CPU
The LPC932 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
CLOCKS Clock Definitions
The LPC932 device has several internal clocks as defined below: * OSCCLK - Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 5) and can also be optionally divided to a slower frequency (see section "CPU Clock (CCLK) Modification: DIVM Register").Note: fOSC is defined as the OSCCLK frequency. * CCLK - CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). ). * RCCLK - The internal 7.373 MHz RC oscillator output. * PCLK - Clock for the various peripheral devices and is CCLK/2
CPU Clock (OSCCLK)
The LPC932 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.
Low Speed Oscillator Option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.
Medium Speed Oscillator Option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
High Speed Oscillator Option
This option supports an external crystal in the range of 4 MHz to 12 MHz. Ceramic resonators are also supported in this configuration.
Clock Output
The LPC932 supports a user selectable clock output function on the XTAL2 / CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the LPC932. This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is 1/2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.
ON-CHIP RC OSCILLATOR OPTION
The LPC932 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, 2.5%. End user applications can write to the Trim register to adjust the on-chip RC oscillator to other frequencies.
2002 Oct 21
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Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
WATCHDOG OSCILLATOR OPTION
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.
EXTERNAL CLOCK INPUT OPTION
In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin may be used as a standard port pin or a clock output.
XTAL1 XTAL2
High freq. Med freq. Low freq.
RTC
OSCCLK RCCLK
DIVM
CCLK
CPU
2 PCLK
RC Oscillator
(7.3728M Hz2.5%) Watchdog Oscillator (400KHz+20%-30%)
PCLK
W DT
32x PLL
CCU Timer 0 & 1 I2C SPI UART
Figure 5: Block diagram of oscillator control
CPU CLOCK (CCLK) WAKEUP DELAY
The LPC932 has an internal wakeup timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus 60-100 s. If the clock source is either the internal RC oscillator, watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60-100 s.
CPU CLOCK (CCLK) MODIFICATION: DIVM REGISTER
The OSCCLK frequency can be divided down up to 256 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
2002 Oct 21
18
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
LOW POWER SELECT
The LPC932 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to '1' to lower the power consumption further. On any reset, CLKLP is '0' allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
MEMORY ORGANIZATION
The various LPC932 memory spaces are as follows: DATA IDATA 128 bytes of internal data memory space (00h..7Fh) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. Indirect Data. 256 bytes of internal data memory space (00h.FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it. Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. "External" Data or Auxiliary RAM. Duplicates the classic 80C51 64 KB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The LPC932 has 512 bytes of on-chip XDATA memory. 64 KB of Code memory space, accessed as part of program execution and via the MOVC instruction. The LPC932 has 8 KB of on-chip Code memory.
SFR XDATA
CODE
The LPC932 also has 512 bytes of on-chip Data EEPROM that is accessed via SFRs (see section "Data EEPROM").
DATA RAM ARRANGEMENT
The 768 bytes of on-chip RAM organized as follows: Table 1: On-Chip Data Memory Usages. Type DATA IDATA XDATA Data RAM Memory that can be addressed directly and indirectly Memory that can be addressed indirectly Auxiliary ("External Data") on-chip memory that is accessed using the MOVX instructions Size (Bytes) 128 256 512
INTERRUPTS
The LPC932 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The LPC932 supports 15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog/ realtime clock, I2C, keyboard, comparators 1 and 2, SPI, CCU, data EEPROM write completion. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.
2002 Oct 21
19
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
External interrupt inputs
The LPC932 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode if successive samples of the INTn pin show a high in one cycle and a low in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the LPC932 is put into Power down or Idle mode, the interrupt will cause the processor to wake up and resume operation. Refer to the section on Power Reduction Modes for details.
IE0 EX0 IE1 EX1 BOPD EBO RTCF ERTC (RTCCON.1) WDOVF KBF EKB EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI & RI/RI ES/ESR TI EST SI EI2C SPIF ESPI Any CCU Interrupt (see section "Capture/ Compare Unit (CCU)") ECCU EEIF EIEE Interrupt to CPU Wakeup (if in Power down)
Figure 6: Interrupt sources, interrupt enables, and power-down wake-up sources
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Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
I/O PORTS
The LPC932 has 4 I/O ports: Port 0, Port 1, Port2, and Port 3. Ports 0, 1 and 2 are 8-bit ports and Port 3 is a 2-bit port. The exact number of I/O pins available depend upon the clock and reset options chosen: Table 2: Number of I/O pins available. Number of I/O pins Clock source On-chip oscillator or watchdog oscillator Reset option 28-pin package No external reset(except during power-up) External RST pin supported External clock input No external reset(except during power-up) External RST pin supported Low/medium/high speed oscillator (external crystal or resonator) No external reset(except during power-up) External RST pin supported 26 25 25 24 24 23
Port configurations
All but three I/O port pins on the LPC932 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. P1.5 (RST) can only be an input and cannot be configured. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open drain.
Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. LPC932 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit.
Open drain output configuration
The open drain output configuration turns off all pullups and only drives the pulldown transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. An open drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.
Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt-triggered input that also has a glitch suppression circuit .
Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.
2002 Oct 21
21
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Port 0 analog functions
The LPC932 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high impedance) mode as described in the I/O Ports section. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD1:5 defaults to '0's to enable digital functions.
Additional Port Features
After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices. * After power-up, all I/O pins except P1.5, may be configured by software. * Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only or open drain. Every output on the LPC932 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the section DC Electrical Characteristics for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
POWER MONITORING FUNCTIONS
The LPC932 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout detect.
Brownout detection
The Brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a Brownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt. Brownout detection may be enabled or disabled in software. If Brownout detection is enabled, the operating voltage range for VDD is 2.7 V-3.6 V, and the brownout condition occurs when VDD falls below the brownout trip voltage, VBO (see DC Electrical Characteristics), and is negated when VDD rises above VBO. If brownout detection is disabled, the operating voltage range for VDD is 2.4 V-3.6 V. If the LPC932 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of Brownout detect, the VDD rise and fall times must be observed. Please see the DC Electrical Characteristics section of this datasheet for specifications.
Power-on Detection
The Power-on Detect has a function similar to the Brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where Brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.
POWER REDUCTION MODES
The LPC932 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Powerdown mode. Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode. The Power-down mode stops the oscillator in order to minimize power consumption. The LPC932 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VRAM, therefore it is highly recommended to wake up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited.
2002 Oct 21
22
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during Power-down. These include: Brownout detect, Watchdog Timer, Comparators (Note: Comparators can be powered-down separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled. Total Power down Mode: This is the same as Power down Mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled. If the internal RC oscillator is used to clock the RTC during Power down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the Real-Time Clock running during Power down.
RESET
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. NOTE: During a power-up sequence, the RPE selection is overidden and this pin will always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Reset can be triggered from the following sources : * External reset pin (during power-up or if user configured via UCFG1); * Power-on detect; * Brownout detect; * Watchdog Timer; * Software reset; * UART break character detect reset. For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a '0' to the corresponding bit. More than one flag bit may be set: * During a power-on reset, both POF and BOF are set but the other flag bits are cleared. * For any other reset, previously set flag bits that have not been cleared will remain set.
Reset vector
Following reset, the LPC932 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address =00h. The Boot address will be used if a UART break reset occurs, or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see User's Manual). Otherwise, instructions will be fetched from address 0000H.
TIMERS/COUNTERS 0 AND 1
The LPC932 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer overflow has been added. In the "Timer" function, the register is incremented every machine cycle. In the "Counter" function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle. Timers 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/ Counters. Mode 3 is different.
2002 Oct 21
23
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.
Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.
Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
REAL-TIME CLOCK/SYSTEM TIMER
The LPC932 has a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered down. The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all 0's, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the Real-Time Clock and its associated SFRs to the default state.
CAPTURE/COMPARE UNIT (CCU)
This unit features: * A 16-bit timer with 16-bit reload on overflow * Selectable clock, with prescaler to divide clock source by any integral number between 1 and 1024. * 4 Compare / PWM outputs with selectable polarity * Symmetrical / Asymmetrical PWM selection * 2 Capture inputs with event counter and digital noise rejection filter * 7 interrupts with common interrupt vector (one Overflow, 2XCapture, 4XCompare), * Safe 16-bit read/write via shadow registers
CCU clock (CCUCLK)
The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of a PLL. The PLL is designed to use a clock source between 0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide PCLK into a frequency between 0.5 MHz and 1 MHz.
CCU clock prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented as a 10-bit free-running counter with programmable reload at overflow.
2002 Oct 21
24
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Basic timer operation
The Timer is a free-running up/down counter with a direction control bit. If the timer counting direction is changed while the counter is running, the count sequence will be reversed. The timer can be written or read at any time. When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt generated if enabled. The 16-bit CCU Timer may also be used as an 8-bit up/down timer.
Output compare
There are four output compare channels A, B, C and D. Each output compare channel needs to be enabled in order to operate and the user will have to set the associated I/O pin to the desired output mode to connect the pin. When the contents of the timer matches that of a capture compare control register, the Timer Output Compare Interrupt Flag - TOCFx becomes set. An interrupt will occur if enabled.
Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register. The capture event can be programmed to be either rising or falling edge triggered. A simple noise filter can be enabled on the input capture by enabling the Input Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event. An event counter can be set to delay a capture by a number of capture events.
PWM operation
PWM operation has two main modes, symmetrical and asymmetrical. In asymmetrical PWM operation the CCU Timer operates in downcounting mode regardless of the direction control bit. In symmetrical mode, the timer counts up/down alternately. The main difference from basic timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation. As with basic timer operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However, since bit FCO is used to hold the halt value, only a compare event can change the state of the pin.
TOR2
Compare Value Timer Value 0x0000 Non-Inverted
Inverted
Figure 7: Asymmetrical PWM, downcounting
2002 Oct 21
25
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
TOR2 Compare Value
Timer Value 0 Non-Inverted
Inverted
Figure 8: Symmetrical PWM
Alternating Output Mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle.
TOR2 Compare Value A (or C) Compare Value B (or D) Timer Value 0
PWM Output A (or C)
(P2.6)
PWM Output B (or D)
(P1.6)
Figure 9: Alternate output mode
PLL operation
The PWM module features a Phase Locked Loop that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher. The PLL is fed an input signal of 0.5 - 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor of 1-16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as follows: PLL frequency = PCLK / (N+1) Where: N is the value of PLLDV3:0. Since N ranges in 0 - 15, the CCLK frequency can be in the range of PCLK to PCLK/16.
2002 Oct 21
26
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
EA (IEN0.7) ECCU (IEN1.4) TOIE2 (TICR2.7) TOIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2.1) TICF2B (TIFR2.1) TOCIE2A (TICR2.3) TOCF2A (TIFR2.3) TOCIE2B (TICR2.4) TOCF2B (TIFR2.4) TOCIE2C (TICR2.5) TOCF2C (TIFR2.5) TOCIE2D (TICR2.6) TOCF2D (TIFR2.6) other interrupt sources Interrupt to CPU
ENCINT.0 Priority Encoder ENCINT.1 ENCINT.2
Figure 10: Capture/Compare Unit interrupts
UART
The LPC932 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The LPC932 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options.The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16
Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1/16 of the CPU clock frequency.
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described later in section on "Baud rate generator and selection").
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 1/16 or 1/32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.
2002 Oct 21
27
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described later in section on "Baud rate generator and selection").
Baud rate generator and selection
The LPC932 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 11). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is set. The independent Baud Rate Generator uses OSCCLK.
SMOD1 = 1 Timer 1 Overflow (PCLK-based) /2 SMOD1 = 0 Baud Rate Generator (PCLK-based)
SBRGS = 0 Baud Rate Modes 1 and 3 SBRGS = 1
Figure 11: Baud rate sources for UART (Modes 1, 3)
Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7-6) are set up when SMOD0 is '0'.
Break detect
Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed low. The break detect can be used to reset the device and force the device into ISP mode.
Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e. SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).
Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data.
The 9th bit (Bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt. If double buffering is enabled, TB8 MUST be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.
2002 Oct 21
28
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM I2C SERIAL INTERFACE
P89LPC932
I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features: * Bi-directional data transfer between masters and slaves * Multimaster bus (no central master) * Arbitration between simultaneously transmitting masters without corruption of serial data on the bus * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer * The I2C-bus may be used for test and diagnostic purposes A typical I2C-bus configuration is shown in Figure 12. The LPC932 device provides a byte-oriented I2C interface that supports data transfers up to 400 kHz.
RP
RP
SDA
I2C-bus
SCL
P1.3/SDA
P1.2/SCL
Other Device with I2C Interface
Other Device with I2C Interface
LPC932
Figure 12: I2C-bus configuration
2002 Oct 21
29
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
8
P1.3
Address Register
I2ADR
Input Filter
Comparator
P1.3/SDA
Output Stage
Shift Register
ACK I2DAT
8
Bit Counter / Arbitration & Sync Logic
Output Stage Timer 1 Overflow P1.2 I2CON I2SCLH I2SCLL
Interrupt
Serial Clock Generator
Control Register & SCL Duty Cycle Registers
8
Status Bus
Status Decoder
I2STAT
Status Register
8
Figure 13: I2C-bus serial interface block diagram
2002 Oct 21
30
Internal Bus
P1.2/SCL
Input Filter
CCLK Timing & Control Logic
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
SERIAL PERIPHERAL INTERFACE (SPI)
LPC932 provides another high-speed serial communication interface - the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation mode: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.
C P U c lo c k
8 -B it S h ift R e g is te r D iv id e r by 4, 16, 64, 128 R e a d D a ta B u ffe r
S M M S
M IS O P 2 .3 Pin Control Logic M OSI P 2 .2
c lo c k
S e le c t
SPR1 SPR0
S P I c lo c k (M a s te r)
S P IC L K P 2 .5 SS P 2 .4
C lo c k L o g ic
S M
MSTR DORD MSTR CPHA SPEN CPOL SSIG
S P I C o n tro l
WCOL SPIF
M STR SPEN SPR1 SPR0
S P I C o n tro l R e g is te r S P I S ta tu s R e g is te r SPI in te rru p t re q u e s t In te rn a l D a ta Bus
Figure 14: SPI block diagram The SPI interface has four pins: SPICLK, MOSI, MISO and SS: * SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions. * SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figures 15 - 17.
2002 Oct 21
31
SPEN
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Typical SPI configurations
Master MISO MISO MOSI Slave
8-Bit Shift Register
MOSI
8-Bit Shift Register
SPICLK
SPICLK SS
SPI Clock Generator
Port
Figure 15: SPI single master single slave configuration I
Master MISO MISO MOSI SPICLK Slave
8-Bit Shift Register
MOSI
8-Bit Shift Register
SPICLK
SPI Clock Generator
SS
SPI Clock Generator
SS
Figure 16: SPI dual device configuration, where either can be a master or a slave.
2002 Oct 21
32
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
Master MISO MISO MOSI
Slave
8-Bit Shift Register
MOSI
8-Bit Shift Register
SPICLK
SPICLK SS
SPI Clock Generator
Port
Slave MISO MOSI
8-Bit Shift Register
SPICLK Port SS
Figure 17: SPI single master multiple slaves configuration
ANALOG COMPARATORS
Two analog comparators are provided on the LPC932. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. The overall connections to both comparators are shown in Figure 18. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
Internal reference voltage
An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref, is 1.23 V 10%.
Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.
2002 Oct 21
33
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
CP1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref CN1 Comparator 1 OE1
+
CO1 CMP1 (P0.6)
-
Change Detect CMF1
Interrupt Change Detect CP2 Comparator 2 (P0.2) CIN2A (P0.1) CIN2B CMF2 EC
+
CO2 CMP2 (P0.0)
OE2 CN2
Figure 18: Comparator input and output connections
Comparators and Power Reduction Modes
Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be configured in the pushpull mode in order to obtain fast switching times while in power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.
KEYPAD INTERRUPT (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs.
2002 Oct 21
34
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
WATCHDOG TIMER
The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 40 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 19 shows the watchdog timer in watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a timeout period that ranges from a few s to a few seconds. Please refer to the User's Manual for more details.
WDL (C1H)
MOV WFEED1,#0A5H MOV WFEED2, #05AH
Watchdog Oscillator PCLK
/32
PRESCALER
8-Bit Down Counter
RESET
Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence SHADOW REGISTER FOR WDCON
control register
PRE2
PRE1
PRE0
WDRUN
WDTOF
WDCLK
WDCON(A7H)
Figure 19: Watchdog timer in Watchdog mode (WDTE = 1)
2002 Oct 21
35
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
ADDITIONAL FEATURES Software Reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.
Dual Data Pointers
The dual Data Pointers (DPTR) provides two diferent Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.
DATA EEPROM
The LPC932 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write and fill the memory via SFRs and one interrupt. This Data EEPROM provides 100,000 minimum erase/program cycles for each byte. Byte Mode: In this mode, data can be read and written one byte at a time. Row Fill: In this mode, the addressed row (64 bytes) is filled with a single value. The entire row can be erased by writing 00h. Sector Fill: In this mode, all 512 bytes are filled with a single value. The entire sector can be erased by writing 00h. After the operation finishes, the hardware will set the EEIF bit, which if enabled will generate an interrupt. The flag is cleared by software.
FLASH PROGRAM MEMORY
General description
The LPC932 Flash memory provides in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Sector and Page Erase functions can erase any Flash sector (1 KB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. In-System Programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user-friendly programming interface. The LPC932 Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The LPC932 uses VDD as the supply voltage to perform the Program/Erase algorithms.
Features
* Internal fixed boot ROM, containing low-level In-Application Programming (IAP) routines * User programs can call these routines to perform In-Application Programming (IAP). * Default loader providing In-System Programming via the serial port, located in upper end of user program memory. * Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space, providing flexibility to the user. * Programming and erase over the full operating voltage range * Read/Programming/Erase using ISP/IAP * Any flash program/erase operation in 2 ms * Parallel programming with industry-standard commercial programmers * Programmable security for the code in the Flash for each sector. * 10,000 minimum erase/program cycles for each byte. * 10-year minimum data retention.
2002 Oct 21
36
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
ISP and IAP capabilities of the LPC932 Flash organization
The LPC932 program memory consists of eight 1 KB sectors. Each sector can be further divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. An In-Application Programming (IAP) interface is provided to allow the end user's application to erase and reprogram the user code memory. In addition, erasing and reprogramming of user-programmable bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported. As shipped from the factory, the upper 512 bytes of user code space contains a serial In-System Programming (ISP) routine allowing for the device to be programmed in circuit through the serial port.
Flash programming and erasing
There are three methods of erasing or programming of the Flash memory that may be used. First, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point. Second, the on-chip ISP boot loader may be invoked. This ISP boot loader will, in turn, call low-level routines through the same common entry point that can be used by the end-user application. Third, the Flash may be programmed or erased using the parallel method by using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead this device provides a 32-bit CRC result on either a sector or the entire 8 KB of user code space.
Boot ROM
When the microcontroller programs its own Flash memory, all of the low level details are handled by code that is contained in a Boot ROM that is separate from the Flash memory. A user program simply calls the common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation. The Boot ROM include operations such as erase sector, erase page, program page, CRC, program security bit, etc. The Boot ROM occupies the program memory space at the top of the address space from FF00 to FEFF hex, thereby not conflicting with the user program memory space.
Power-on Reset code execution
The LPC932 contains two special Flash elements: the Boot Vector and the Boot Status Bit. Following reset, the LPC932 examines the contents of the Boot Status Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user's application code. When the Boot Status Bit is set to a value other than zero, the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00H. The factory default setting is 01EH, corresponds to the address 1E00H for the default ISP boot loader. This boot loader is pre-programmed at the factory into this address space and can be erased by the user. Users who wish to use this loader should take cautions to avoid erasing the 1KB sector from 1C00H to 1FFFH. Instead, the page erase function can be used to erase the eight 64-byte pages located from 1C00H to 1DFFH. A custom boot loader can be written with the Boot Vector set to the custom boot loader, if desired.
Hardware activation of the Boot Loader
The boot loader can also be executed by forcing the device into ISP mode during a power-on sequence (see User's Manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. If the factory default setting for the Boot Vector (1EH) is changed, it will no longer point to the factory pre-programmed ISP boot loader code. If this happens, the only way it is possible to change the contents of the Boot Vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Boot Status Bit. After programming the Flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000H.
In-System Programming (ISP)
In-System Programming is performed without removing the microcontroller from the system. The In-System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the LPC932 through the serial port. This firmware is provided by Philips and embedded within each LPC932 device. The Philips In-System Programming facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins. Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.
2002 Oct 21
37
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
In-Application Programming method (IAP)
Several In-Application Programming (IAP) calls are available for use by an application program to permit selective erasing and programming of Flash sectors, pages, security bits, configuration bytes, and device id. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller's registers before making a call to PGM_MTP at FF00H.
USER CONFIGURATION BYTES
A number of user-configurable features of the LPC932 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the Flash byte UCFG1. Please see the User's Manual for additional details.
USER SECTOR SECURITY BYTES
There are eight User Sector Security Bytes each corresponding to one sector. Please see the User's Manual for additional details.
2002 Oct 21
38
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
ABSOLUTE MAXIMUM RATINGS
PARAMETER Temperature under bias Storage temperature range Voltage on Xtal1, Xtal2 pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer, not device power consumption) RATING -55 to +125 -65 to +150 VDD+0.5 -0.5 to +5.5 20 1.5 UNIT C C V V mA W
Notes: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification are not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
2002 Oct 21
39
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
DC ELECTRICAL CHARACTERISTICS
VDD = 2.4 V to 3.6 V unless otherwise specified; Tamb = 0 C to +70 C for commercial, -40 C to +85 C for industrial, unless otherwise specified. SYMBOL IDD IID IPD IPD1 VDDR VDDF VRAM VIL VIL1 VIH VIH1 HYS VOL VOH VOH1 CIO IIL ILI ITL RRST VBO VREF PARAMETER Power supply current, operating Power supply current, Idle mode Power supply current, Power-down mode, voltage comparators powered down Power supply current, Total Power-down mode Vdd rise time Vdd fall time RAM keep-alive voltage Input low voltage (TTL input) Negative going threshold (Schmitt input) Input high voltage (TTL input) Positive going threshold (Schmitt input) Hysteresis voltage (Port 1) Output low voltage all ports 5, 9 Output high voltage, all ports 3 IOL = 20 mA; VDD = 2.4 V IOL = 3.2 mA; VDD = 2.4 V IOH = -20 A; VDD = 2.4 V IOH = -3.2 mA; VDD = 2.4 V VIN = 0.4 V VIN = VIL or VIH
3, 6
TEST CONDITIONS 3.6 V, 12 MHz 11 3.6 V, 12 MHz 11 3.6 V 11 3.6 V 11
LIMITS MIN 1.5 TYP1 15 1 1 0.4VDD 0.6VDD 0.2VDD 1.23 10 MAX 25 4 tbd 5 2 50 0.22VDD0.1 5.5 0.7VDD 1.0 0.3 15 -50 10 -250 225 2.70 1.34 20
UNIT mA mA A A mV/s mV/s V V V V V V V V V V pF A A A kW V V ppm/ C
2.4 V < VDD < 3.6 V
-0.5 0.22VDD 0.7VDD+0.1 VDD-0.2 VDD-0.7 -30 40
Output high voltage, all ports 4 Input/Output pin capacitance 10 Logical 0 input current, all Input leakage current, all ports 8 ports 7
Logical 1-to-0 transition current, all ports Internal reset pull-up resistor Brownout trip voltage with BOV = 1, BOPD = 0 Bandgap reference voltage
VIN = 1.5 V at VDD = 3.6 V
2.4 V < VDD < 3.6 V
2.40 1.11 -
tC (VREF) Bandgap temperature coefficient
Notes: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. 2. Active mode: ICC(MAX) = tbd Idle mode: ICC(MAX) = tbd 3. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open drain pins. 4. Ports in PUSH-PULL mode. Does not apply to open drain pins. 5. In all output modes except high impedance mode. 6. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when VIN is approximately 2 V. 7. Measured with port in high impedance mode. 8. Measured with port in quasi-bidirectional mode.
2002 Oct 21
40
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
9. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 20 mA Maximum IOL per port pin: Maximum total IOL for all outputs: 80 mA Maximum total IOH for all outputs: 5 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10. Pin capacitance is characterized but not tested. 11. The IDD, IID, and IPD specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer.
2002 Oct 21
41
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
AC ELECTRICAL CHARACTERISTICS
Tamb = 0 C to +70 C for commercial, -40 C to +85 C for industrial, unless otherwise specified.1
SYMBOL fRCOSC fWDOSC fOSC tCLCL fLPEP Glitch Filter P1.5(RST) pin glitch rejection P1.5(RST) pin signal acceptance Glitch rejection - any pin except P1.5(RST) Signal acceptance - any pin except P1.5(RST) External Clock tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX tDVXH SPI Interface Operating frequency - 2.0 MHz (Master) fSPI - 2.0 MHz (Slave) - 3.0 MHz (Master) - 3.0 MHz (Slave) Cycle time - 2.0 MHz (Master) tSPICYC 20, 21, 22, 23 - 2.0 MHz (Slave) - 3.0 MHz (Master) - 3.0 MHz (Slave) Enable lead time (Slave) tSPILEAD 22, 23 - 2.0 MHz - 3.0 MHz Enable lag time (Slave) tSPILAG 22, 23 - 2.0 MHz - 3.0 MHz SPICLK high time tSPICLKH 20, 21, 22, 23 - Master - Slave SPICLK low time tSPICLKL 20, 21, 22, 23 20, 21, 22, 23 20, 21, 22, 23 22, 23 - Master - Slave tSPIDSU tSPIDH tSPIA Data set-up time (Master or Slave) Data hold time (Master or Slave) Access time (Slave) 340 190 100 100 0 120 340 190 100 100 0 120 ns ns ns ns 340 190 340 190 ns 250 240 250 240 ns 250 240 250 240 ns 500 333 500 333 ns 0 0 2.0 3.0 0 0 2.0 3.0 MHz 25 25 25 25 High time Low time Rise time Fall Time Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Input data valid to clock rising edge 33 33 16 tCLCL 13 tCLCL 150 tCLCL-tCLCX tCLCL-tCHCX 8 8 tCLCL+20 0 33 33 1333 1083 150 8 8 103 0 ns ns ns ns ns ns ns ns ns 50 125 50 15 50 125 50 15 ns ns ns ns 25 FIGURE (S) Variable Clock PARAMETER MIN Internal RC oscillator frequency Internal watchdog oscillator frequency Oscillator frequency CLock cycle LPEP active frequency 7.189 280 0 83 0 MAX 7.557 480 12 4 fOSC = 12 MHz MIN 7.189 280 MAX 7.557 480 MHz KHz MHz ns MHz UNIT
Shift Register(UART mode 0)
2002 Oct 21
42
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
Variable Clock PARAMETER MIN Disable time (Slave) tSPIDIS 22, 23 - 2.0 MHz - 3.0 MHz Enable to output data valid tSPIDV 20, 21, 22, 23 20, 21, 22, 23 20, 21, 22, 23 - 2.0 MHz - 3.0 MHz tSPIOH Output data hold time Rise time tSPIR - SPI outputs (SPICLK,MOSI, MISO) - SPI inputs (SPICLK,MOSI, MISO, SS) Fall time tSPIF 20, 21, 22, 23 - SPI outputs (SPICLK,MOSI, MISO) - SPI inputs (SPICLK,MOSI, MISO, SS) 100 2000 100 2000 ns 100 2000 100 2000 ns 0 240 167 0 240 167 ns ns 0 0 240 167 240 167 ns MAX fOSC = 12 MHz MIN MAX
P89LPC932
SYMBOL
FIGURE (S)
UNIT
Notes: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
SS tCLCL tSPIF tSPICLKH SPICLK (CPOL = 0) (output) tSPIF SPICLK (CPOL = 1) (output) tSPIDSU tSPIDH tSPICLKL tSPIR tSPICLKH tSPICLKL tSPIR
MISO (input) tSPIDV tSPIF MOSI (output)
MSB/LSB in
LSB/MSB in
tSPIOH
tSPIDV
tSPIR
Master MSB/LSB out
Master LSB/MSB out
Figure 20: SPI Master timing (CPHA = 0)
2002 Oct 21
43
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
SS tCLCL tSPIF SPICLK (CPOL = 0) (output) tSPIF tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU tSPIDH tSPICLKL tSPIR tSPICLKL tSPIR tSPICLKH
MISO (input) tSPIDV tSPIF MOSI (output)
MSB/LSB in
LSB/MSB in tSPIDV tSPIR
tSPIOH
tSPIDV
Master MSB/LSB out
Master LSB/MSB out
Figure 21: SPI Master timing (CPHA = 1)
SS tSPIR tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIA tSPIOH tSPIDV Slave MSB/LSB out tSPIOH tSPIDV tSPIOH tSPIDIS tSPICLKL tSPIR tSPICLKH tCLCL tSPIF tSPICLKH tSPICLKL tSPIR tSPILAG tSPIR
MISO (output)
Slave LSB/MSB out
Not defined
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
Figure 22: SPI Slave timing (CPHA = 0)
2002 Oct 21
44
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
SS tSPIR tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIA tSPIOH tSPIDV Not defined Slave MSB/LSB out tSPIOH tSPIDV tSPIOH tSPIDV Slave LSB/MSB out tSPIDIS tSPICLKL tSPIR tSPICLKH tCLCL tSPIF tSPICLKH tSPICLKL tSPIR tSPILAG tSPIR
MISO (output)
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
Figure 23: SPI Slave timing (CPHA = 1)
2002 Oct 21
45
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
COMPARATOR ELECTRICAL CHARACTERISTICS
VDD = 2.4 V to 3.6 V unless otherwise specified; Tamb = 0 C to +70 C for commercial, -40 C to +85 C for industrial, unless otherwise specified SYMBOL VIO VCR CMRR PARAMETER Offset voltage comparator inputs Common mode range comparator inputs Common mode rejection ratio Response time Comparator enable to output valid Input leakage current, comparator 0 < VIN < VDD
1
TEST CONDITIONS
MIN 0 -
LIMITS TYP 250 -
MAX 20 VDD-0.3 -50 500 10 10
UNIT mV V dB ns s A
IIL
Notes: 1. This parameter is characterized, but not tested in production.
tXLXL
Clock
tXHQX tQVXH
Output Data
0
Write to SBUF
1 tXHDX
2
3
4
5
6
7
Set TI
tXHDV
Input Data
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Clear RI
Set RI
Figure 24: Shift Register Mode timing
VDD - 0.5 0.45V
0.2VDD+0.9 0.2 VDD - 0.1 tCHCX tCHCL tCLCX tC Figure 25: External clock timing tCLCH
2002 Oct 21
46
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
VDD tVR RST tRH
tRL
Figure 26: ISP Entry waveform
AC CHARACTERISTICS, ISP ENTRY MODE
VDD = 2.4 V to 3.6 V unless otherwise specified; Tamb = 0 to +70C for commercial, -40 C to +85 C for industrial, unless otherwise specified SYMBOL tVR tRH tRL PARAMETER RST delay from VDD active RST HIGH time RST LOW time MIN 50 1 1 32 MAX UNIT s s s
2002 Oct 21
47
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
PACKAGE OUTLINE
PLCC28: plastic leaded chip carrier; 28 leads SOT261-2
eD y X
eE
25
19 18 ZE
A
bp b1 wM
26
28
1
pin 1 index e k 5 e D HD 11 ZD B 4 12
E
HE A A4 A1 (A 3) Lp detail X
vM A
vMB
0
5 scale
10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 b1 D(1) E(1) bp e A3 eD eE HD UNIT A max. min.
mm 4.57 4.19 0.51 0.25 0.01 3.05 0.53 0.33 0.81 0.66
HE
k
Lp
1.44 1.02
v
0.18
w
0.18
y
0.1
ZD(1) ZE(1) max. max.
2.16 2.16
10.92 10.92 12.57 12.57 1.22 11.58 11.58 1.27 9.91 9.91 12.32 12.32 1.07 11.43 11.43 0.43 0.39 0.43 0.39
45 o
0.180 inches 0.02 0.165
0.021 0.032 0.456 0.456 0.05 0.12 0.013 0.026 0.450 0.450
0.495 0.495 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.485 0.485 0.042 0.040
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT261-2 REFERENCES IEC 112E08 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 01-11-15
2002 Oct 21
48
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
D
E
A
X
c y HE vMA
Z
28
15
Q A2 pin 1 index A1 (A 3) A
Lp L detail X
1
e bp
14
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27
2002 Oct 21
49
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
DATA SHEET STATUS
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http:// www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
DISCLAIMERS
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
LICENCES
Purchase of Philips I2C components Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 Oct 21
50
Philips Semiconductors
Preliminary data
80C51 8-bit microcontroller with two-clock core
8 KB 3 V low-power Flash with 512-byte data EEPROM
P89LPC932
CONTACT INFORMATION
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002. Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 2002 Oct 22 Document order number: 9397 750 10475
2002 Oct 21
51

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