View CY2254A_286261.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY2254A
PentiumTM Processor Compatible Clock Synthesizer/Driver
Features
* Multiple clock outputs to meet requirements of most PentiumTM motherboards -- Four pin-selectable CPU clocks @ 66.66 MHz, 60.0 MHz, and 50.0 MHz for support of Intel Triton PCIset based PC -- 55.0 MHz pin-selectable CPU clock also available (-2 option only) -- Six PCI clocks at 1/2 CPU Clock frequency -- One I/O clock @ 24 MHz -- One Keyboard Controller clock @ 12 MHz (-1 option) or one Universal Serial Bus clock @ 48 MHz (-2 option) -- Two Ref. clocks @ 14.318 MHz -- Ref. 14.318 MHz Xtal oscillator input * CPU clock jitter < 200 ps cycle-to-cycle * Low skew outputs -- < 250 ps between CPU clocks -- < 250 ps between PCI clocks -- < 500 ps between CPU and PCI clocks (-2 option) -- CPU clock leads PCI clock by +1 ns min. to +4 ns max. (-1 option) Logic Block Diagram
REF0 (14.318 MHz) REF1 (14.318 MHz) SYS PLL XTALIN XTALOUT 14.318 MHz OSC. CPU PLL ROM S0 S1 -1 option only
* * * * *
Freq. stability = 0.01% (max.) Output duty cycle 45% min. to 55% max. Test mode support (-1 option only) 3.3V or 5.0V operation Internal pull-up resistors on S0, S1, and OE inputs
Functional Description
The CY2254A is a Clock Synthesizer/Driver that provides the multiple clocks required for a Pentium based PC. The CY2254A has low-skew outputs (< 250 ps between the CPU Clocks, < 250 ps between the PCI Clocks). In addition, the CY2254A CPU clock outputs have less than 200 ps cycle-to-cycle jitter. Finally, both the PCI and CPU clock outputs meet the 1V/ns slew rate requirement of a Pentium processor-based system. The CY2254A accepts a 14.318 MHz reference signal as its input. The CY2254A has 2 PLLs, one of which generates the CPU and PCI clocks, and the other generates the I/O and Keyboard Controller or USB clocks. The CY2254A runs off either a 3.3V or 5V supply. The CY2254A is available in two options. The -1 option supports the Intel Triton PCIset and provides a 12 MHz keyboard clock on pin 25. The -2 option provides a 48 MHz USB clock on pin 25 and supports the Cyrix M1 processor.
Pin Configuration
Top View SOIC
VDD XTALIN XTALOUT VSS OE CPUCLK0 CPUCLK1 VDD CPUCLK2 CPUCLK3 VSS S1 S0 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 REF0 REF1 VDD SEE BELOW IOCLK VSS PCICLK2 PCICLK3 VDD PCICLK4 PCICLK5 VSS PCICLK1 PCICLK0
/2
/2
KBDCLK (12 MHz) IOCLK (24 MHz) USBCLK (48 MHz) CPUCLK0 CPUCLK1 CPUCLK2 CPUCLK3
/2
DELAY PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5
OPTION -1 -2
PIN 25 KBDCLK 12 MHz USBCLK 48 MHz
OE Intel is a registered trademark of Intel Corporation. Pentium and Triton are trademarks of Intel Corporation. Cyrix is a registered trademark of Cyrix Corporation.
2254-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 February 1996 - Revised June 12, 1997
CY2254A
Pin Summary
Name VDD XTALIN
[1] [1]
-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Description Voltage supply Reference crystal input Reference crystal feedback Ground Output Enable, Active HIGH (internal pull-up resistor to VDD) CPU clock output CPU clock output Voltage supply CPU clock output CPU clock output Ground CPU clock select input, bit 1 (internal pull-up resistor to VDD) CPU clock select input, bit 0 (internal pull-up resistor to VDD) Voltage supply PCI clock output PCI clock output Ground PCI clock output PCI clock output Voltage supply PCI clock output PCI clock output Ground I/O clock output (24 MHz) Keyboard controller clock output (12 MHz)
XTALOUT VSS OE CPUCLK0 CPUCLK1 VDD CPUCLK2 CPUCLK3 VSS S1 S0 VDD PCICLK0 PCICLK1 VSS PCICLK5 PCICLK4 VDD PCICLK3 PCICLK2 VSS IOCLK KBDCLK USBCLK VDD REF1 REF0
25 26 27 28 26 27 28
Universal Serial Bus clock output (48 MHz) Voltage supply Reference clock output (14.318 MHz) Reference clock output (14.318 MHz)
Function Table
Option -1,-2 -1,-2 -1,-2 -1,-2 -1 -2 OE 0 1 1 1 1 1 S0 X 0 0 1 1 1 S1 X 0 1 0 1 1 XTALIN CPUCLK PCICLK High-Z 25.0 MHz 30.0 MHz 33.33 MHz TCLK/4 27.5 MHz Ref. Clock Output High-Z IOCLK High-Z KBDCLK -1 only High-Z 12 MHz 12 MHz 12 MHz TCLK/8 48 MHz USBCLK -2 only High-Z 48 MHz 48 MHz 48 MHz
14.318 MHz High-Z 14.318 MHz 50.0 MHz 14.318 MHz 60.0 MHz 14.318 MHz 66.66 MHz TCLK
[2]
14.318 MHz 24 MHz 14.318 MHz 24 MHz 14.318 MHz 24 MHz TCLK TCLK/4
TCLK/2
14.318 MHz 55.0 MHz
14.318 MHz 24 MHz
Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 17 pF. 2. TCLK is a test clock on XTALIN (pin 2) during test mode.
2
CY2254A
PCI Clock Driver Strength Requirements
* Matched impedances on both rising and falling edges on the output drivers * Output impedance: 25 (typical) measured at 1.5V * Maximum output impedance: 40 measured at 1.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage .......................................................-0.5 to +7.0V Input Voltage................................................... -0.5V to VDD+0.5 Storage Temperature (Non-Condensing).... -65C to +150C Max. Soldering Temperature (10 sec)...................... +260C Junction Temperature .............................................. +150C Package Power Dissipation.............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015)
CPU Clock Driver Strength Requirements
* Matched impedances on both rising and falling edges on the output drivers * Output impedance: 25 (typical) measured at 1.5V * Maximum output impedance: 40 measured at 1.5V
Operating Conditions[3]
Parameter VDD TA CL Supply Voltage 3.3V Supply Voltage 5.0V Operating Ambient Temperature Max. Capacitive Load on CPUCLK PCICLK IOCLK KBDCLK / USBCLK REF0 REF1 Reference Frequency, Oscillator Nominal Value 14.318 Description Min. 3.135 4.5 0 Max. 3.6 5.5 70 20 30 20 20 30 15 14.318 MHz Unit V V C pF
f(REF)
Electrical Characteristics VDD = 3.135V - 3.6V, or 5.0V 10%, TA = 0C to +70C
Parameter VIH VIL VOH[4] Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Except Crystal Inputs Except Crystal Inputs VDD = VDD Min. IOH = 6 mA IOH = 12 mA IOH = 4 mA IOH = 8 mA VOL[4] Low-level Output Voltage VDD = VDD Min. IOL = 6 mA IOL = 12 mA IOL = 4 mA IOL = 8 mA IIH IIL IOZ IDD Input High Current Input Low Current Output Leakage Current Power Supply Current VIH = VDD, VDD = 3.3V VIH = V DD, V DD = 5.0V VIL = 0 V, VDD = 3.3V VIL = 0 V, V DD = 5.0V Three-state VDD = 3.6V, VIN = 0 or VDD VDD = 5.5V, VIN = 0 or VDD -10 CPUCLK PCICLK, REF0 KBDCLK, USBCLK REF1 CPUCLK PCICLK, REF0 KBDCLK, USBCLK REF1 5 10 100 250 +10 90 150 A A A A A mA mA 0.4 V 2.4 Test Conditions Min. 2.0 0.8 Max. Unit V V V
Notes: 3. Electrical parameters are guaranteed with these operating conditions. 4. Guaranteed by design, not tested.
3
CY2254A
Switching Characteristics[5]
Parameter t1 t2
[4]
Output All CPUCLK, PCICLK REF, KBDCLK, USBCLK REF, KBDCLK, USBCLK CPUCLK PCICLK CPUCLK, PCICLK
Name Output Duty Cycle
[6]
Description t1 = t1A / t1B Measured between 0.4 and 2.4V Measured between 0.4 and 2.4V Measured between 2.4 and 0.4V Measured at 1.5V Measured at 1.5V Measured at 1.5V (-1 option) Measured at 1.5V (-2 option)
Min. 45% 1
Max. 55%
Unit
Output Rising and Falling Edge Rate Rise Time Fall Time CPU-CPU Clock Skew PCI-PCI Clock Skew CPU-PCI Skew
V/ns 4 4 250 250 ns ns ps ps ns ps ps
t3[4] t4 t5 t6 t7 t8
[4] [4] [4] [4]
1
4 500 200
[4]
CPUCLK
Cycle-Cycle Clock Jitter CPU Clock Jitter
Switching Waveforms
Duty Cycle Timing
t1B t1A 1.5V 1.5V 1.5V
2254-2
All Outputs Rise/Fall Time
2.4V 0.4V t2 t3 2.4V 0.4V t2 t4 3.3V 0V
2254-3
OUTPUT
Clock Skew
1.5V
CPUCLK/ PCICLK t5 t6
1.5V
2254-4
Notes: 5. All parameters specified with outputs fully loaded. 6. Duty cycle is measured at 1.5V.
4
CY2254A
Switching Waveforms (continued)
CPU-PCI Clock Skew
CPUCLK 1.5V
PCICLK t7
1.5V
2254-5
Test Circuit
VDD
1 0.1 F 4 VDD 0.1 F
26 0.1 F 23
8
20 0.1 F
11
17
14 0.1 F
OUTPUTS CLOAD
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code CY2254ASC-1 CY2254ASC-2 Document #: 38-00504-A Package Name S21 S21 Package Type 28-Pin SOIC 28-Pin SOIC Operating Range Commercial Commercial
5
CY2254A
Package Diagram
28-Lead (300-Mil) Molded SOIC S21
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CY2254A

	To Download CY2254A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .