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1M x 4-Bit Dynamic RAM (Hyper Page Mode (EDO) version)
HYB 314405BJ/BJL-50/-60/-70
Advanced Information
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1 048 576 words by 4-bit organization 0 to 70 C operating temperature Hyper Page Mode - EDO Performance: -50 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns
tRAC tCAC tAA tRC tHPC
RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time
50 13 25 89 20
* *
Single + 3.3 V ( 0.3 V) supply Low power dissipation max. 252 mW active (-50 version) max. 216 mW active (-60 version) max. 198 mW active (-70 version) Standby power dissipation: 7.2 mW max. standby (LVTTL) 3.6 mW max. standby (LVCMOS) 720 W max. standby (LVCMOS) for Low Power Version Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability All inputs and outputs LVTTL compatible 1024 refresh cycles / 16 ms 1024 refresh cycles / 128 ms for Low Power Version Plastic Packages: P-SOJ-26/20-5 with 300 mil width
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Semiconductor Group
1
4.96
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
The HYB 314405BJ/BJL is the new generation dynamic RAM organized as 1 048 576 words by 4-bit. The HYB 314405BJ/BJL utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314405BJ/BJL to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 3.3 V ( 0.3 V) power supply, direct interfacing with high performance logic device families. Ordering Information Type
HYB 314405BJ-50 HYB 314405BJ-60 HYB 314405BJ-70 HYB 314405BJL-50 HYB 314405BJL-60 HYB 314405BJL-70
Ordering Code
Q67100-Q2122 Q67100-Q2124 Q67100-Q2126 on request on request on request
Package
P-SOJ-26/20-5 P-SOJ-26/20-5 P-SOJ-26/20-5 P-SOJ-26/20-5 P-SOJ-26/20-5 P-SOJ-26/20-5
Descriptions
3.3 V EDO-DRAM (access time 50 ns) 3.3 V EDO-DRAM (access time 60 ns) 3.3 V EDO-DRAM (access time 70 ns) 3.3 V Low Power EDO-DRAM (access time 50 ns) 3.3 V Low Power EDO-DRAM (access time 60 ns) 3.3 V Low Power EDO-DRAM (access time 70 ns)
Semiconductor Group
2
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Pin Configuration (top view) P-SOJ-26/20-5
Pin Names A0-A9 RAS CAS WE OE I/O1 - I/O4 Address Input Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output Power Supply (+ 3.3 V) Ground (0 V) No Connection
VCC VSS
N.C.
Semiconductor Group
3
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Block Diagram
Semiconductor Group
4
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range......................................................................................- 55 to + 150 C Input/output voltage ..................................................................................................... - 1 to + 4.6 V Power Supply voltage .................................................................................................. - 1 to + 4.6 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Input high voltage Input low voltage TTL Output high voltage (IOUT = - 2 mA) TTL Output low voltage (IOUT = 2 mA) CMOS Output high voltage (IOUT = - 100 A) CMOS Output low voltage (IOUT = 100 A) Input leakage current, any input (0 V < Vin < VCC + 0.3 V, all other input = 0 V) Output leakage current, any input (DO is disabled, 0 V < VOUT < VCC + 0.3 V) Average VCC supply current -50 version -60 version -70 version Standby VCC supply current (RAS = CAS = WE = VIH) Average VCC supply current during RAS-only refresh cycles -50 version -60 version -70 version Average VCC supply current during hyper page mode (EDO) operation -50 version -60 version -70 version Symbol Limit Values min. max. 0.8 - 0.4 0.2 10 10 2.0 - 1.0 2.4 - - - 10 - 10 Unit Test Condition
1) 1) 1) 1)
VIH VIL VOH VOL VOH VOL II(L) II(L) ICC1
VCC + 0.5 V
V V V V V A A mA
VCC - 0.2 -
1)
2) 3)4)
- - -
70 60 55 2 mA mA -
2)4)
ICC2 ICC3
-
- - -
70 60 55 mA
2) 3)4)
ICC4
- - - 70 60 55
Semiconductor Group
5
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
DC Characteristics (cont'd)
TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V, tT = 2 ns
Parameter Standby VCC supply current (RAS = CAS = WE = VCC - 0.2 V) Average VCC supply current during CAS before RAS refresh mode -50 version -60 version -70 version For Low Power Version only: Battery backup current (average power supply current in battery backup mode): (CAS = CAS before RAS cycling or 0.2 V, WE = VCC - 0.2 V or 0.2 V, A0 to A10 = VCC - 0.2 V or 0.2 V; DI = VCC - 0.2 V or 0.2 V or open, tRC = 125 s, tRAS = tRAS min = 1 s) Symbol Limit Values min. max. 1 200 - Unit Test Condition mA A mA - - - 70 60 55 250 A -
1)
ICC5 ICC6
L-version
2)4)
ICC7
-
AC Characteristics 5)6) TA = 0 to 70 C, VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol -50 min. Limit Values -60 -70 max. max. min. max. min. Unit Note
Common Parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time
tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD
89 35 50 8 0 8 0 8 12 10
- - 10 k 10 k - - - - 37 25
104 40 60 10 0 10 0 10 14 12
- - 10 k 10 k - - - - 45 30
124 50 70 12 0 10 0 12 14 12
- - 10 k 10 k - - - - 53 35
ns ns ns ns ns ns ns ns ns ns
Semiconductor Group
6
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C, VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol -50 min. RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Refresh period for L-version Limit Values -60 15 60 - 50 16 128 5 1 - - - - - 50 16 128 17 70 5 1 - - -70 max. - - - 50 16 128 ns ns ns ns ms ms 7 max. min. max. min. Unit Note
tRSH tCSH tCRP tT tREF tREF
13 50 5 1 - -
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay
tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ tDZC tDZO tCDD tODD
- - - - 25 0 0 0 0 0 0 0 0 10 10
50 13 25 13 - - - - - 13 13 - - - -
- - - - 30 0 0 0 0 0 0 0 0 13 13
60 15 30 15 - - - - - 15 15 - - - -
- - - - 35 0 0 0 0 0 0 0 0 15 15
70 17 35 17 - - - - - 17 17 - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8, 9 8, 9 8,10
11 11 8 12 12 13 13 14 14
Write Cycle
Write command hold time Write command pulse width
tWCH tWP
8 8
- -
10 10
- -
10 10
- -
ns ns
Semiconductor Group
7
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C, VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol -50 min. Write command setup time Limit Values -60 0 15 15 0 10 - - - - - 0 17 17 0 12 -70 max. - - - - - ns ns ns ns ns 16 16 15 max. min. - - - - - max. min. Unit Note
tWCS
0 13 13 0 8
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time
tDS tDH
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time
tRWC tRWD tCWD tAWD tOEH
118 64 27 39 10
- - - - -
138 77 32 47 13
- - - - -
162 89 36 54 15
- - - - -
ns ns ns ns ns 15 15 15
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in hyper page mode CAS precharge to RAS Delay
tHPC tCP tCPA tCOH tRAS tRHCP
20 8 - 5 50 27
- - 27 -
25 10 - 5
- - 32 -
30 10 - 5
- - 37 -
ns ns ns ns 7
200 k 60 - 32
200 k 70 - 37
200 k ns - ns
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) readwrite cycle time CAS precharge to WE
tPRWC tCPWD
58 41
- -
68 49
- -
77 56
- -
ns ns
Semiconductor Group
8
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C, VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol -50 min. Limit Values -60 -70 max. max. min. max. min. Unit Note
CAS before RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS
tCSR tCHR tRPC tWRP tWRH
10 10 5 10 10
- - - - -
10 10 5 10 10
- - - - -
10 10 5 10 10
- - - - -
ns ns ns ns ns
CAS-before-RAS Counter Test Cycle
CAS precharge time (CASbefore-RAS counter test cycle)
tCPT
35
-
40
-
40
-
ns
Test Mode
Write command setup time Write command hold time
tWTS tWTH
10 10
- -
10 10
- -
10 10
- -
ns ns
Capacitance
TA = 0 to 70 C; VCC = 3.3 V 0.3 V; f = 1 MHz
Parameter Input capacitance (A0 to A9) Input capacitance (RAS, CAS, WE,OE) Output capacitance (IO1 to IO4) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CI0
Semiconductor Group
9
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA, tCPA , tOEA, tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles.
Semiconductor Group
10
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Read Cycle
Semiconductor Group
11
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Write Cycle (Early Write)
Semiconductor Group
12
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Write Cycle (OE Controlled Write)
Semiconductor Group
13
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
14
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
15
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
16
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Hyper Page Mode (EDO) Late Write Cycle
Semiconductor Group
17
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Semiconductor Group
18
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
RAS-Only Refresh Cycle
Semiconductor Group
19
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
CAS-Before-RAS Refresh Cycle
Semiconductor Group
20
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Hidden Refresh Cycle (Read)
Semiconductor Group
21
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Hidden Refresh Cycle (Early Write)
Semiconductor Group
22
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
23
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Test Mode Entry
Semiconductor Group
24
HYB 314405BJ/BJL-50/-60/-70 3.3V 1M x 4 EDO - DRAM
Test Mode As the HYB 314405BJ/BT is organized internally as 512 K x 8-bits, a test mode cycle using 8:1 compression can be used to improve test time. Note that in the 1 M x 4 version the test time is reduced by 1/2 for a linear test pattern. In a test mode "write" the data from each I/O1 pin is written into eight bits simultaneously (all "1" s or all "0" s). The I/O2-I/O4 inputs are not used for writing in test mode. In test mode "read" each I/O output is used for indicating the test mode result. If the internal eight bits are equal, the I/O would indicate a "1". If they were not equal, the I/O would indicate a "0". Note that in test mode read" I/ O1-I/O3 are always driven to ones", i.e. all outputs will be 1"s for a test mode pass". The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test mode, a "CAS before RAS refresh", "RAS only refresh" or "Hidden refresh" can be used. Addresses A10R, A10C and A0C are don`t care during test mode. Package Outlines P-SOJ-26/20-5 (Small Outline J-Leaded Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 25
Dimensions in mm
GPJ05627

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