View HYB3165400ATL-60_287323.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16M x 4-Bit Dynamic RAM (4k & 8k Refresh)
HYB 3164400AJ/AT(L) -40/-50/-60 HYB 3165400AJ/AT(L) -40/-50/-60
Advanced Information
* * * *
16 777 216 words by 4-bit organization 0 to 70 C operating temperature Fast Page Mode operation Performance: -40 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/write cycle time Fast page mode cycle time 40 10 20 75 30 -50 50 13 25 90 35 -60 60 15 30 110 40 ns ns ns ns ns
* *
Single + 3.3 V ( 0.3V) power supply Low power dissipation: max. 396 mW active ( HYB 3164400AJ/AT(L) -40) max. 324 mW active ( HYB 3164400AJ/AT(L) -50) max. 270 mW active ( HYB 3164400AJ/AT(L) -60) max. 558 mW active ( HYB 3165400AJ/AT(L) -40) max. 468 mW active ( HYB 3165400AJ/AT(L) -50) max. 378 mW active ( HYB 3165400AJ/AT(L) -60) 7.2 mW standby (LVTTL) 3.24 mW standby (LVCMOS) 720 W standby for L-versions Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh (L-version only)
*
8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164400AJ/AT) 4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165400AJ/AT) * 256 msec refresh period for L-versions
* *
Plastic Package P-SOJ-32-1 400 mil P-TSOPII-32-1 400 mil HYB 3164(5)400AJ HYB 3164(5)400AT
Semiconductor Group
1
6.97
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
This device is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is fabricated on an advanced second generation 64Mbit 0,35 m-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400AJ/AT to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB3164(5)400ATL parts (L-versions) have a very low power sleep mode" supported by Self Refresh Ordering Information Type
HYB 3164400AJ-40 HYB 3164400AJ-50 HYB 3164400AJ-60 HYB 3164400AT-40 HYB 3164400AT-50 HYB 3164400AT-60 HYB 3165400AJ-40 HYB 3165400AJ-50 HYB 3165400AJ-60 HYB 3165400AT-40 HYB 3165400AT-50 HYB 3165400AT-60 HYB 3164(5)400ATL
Ordering Code
Package
P-SOJ-32-1 P-SOJ-32-1 P-SOJ-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-SOJ-32-1 P-SOJ-32-1 P-SOJ-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 400 mil 400 mil 400 mil 400 mil 400 mil 400 mil 400 mil 400 mil 400 mil 400 mil 400 mil 400 mil 400 mil
Descriptions
DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) Low Power DRAMs
Pin Names A0-A12 A0-A11 RAS OE I/O1-I/O4 CAS WE Vcc Vss Address Inputs for 8k-refresh versions HYB 3164400AJ/AT(L) Address Inputs for 4k-refresh versions HYB 3165400AJ/AT(L) Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground
Semiconductor Group
2
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
P-SOJ-32-1 (400 mil) P-TSOPII-32-1 (400 mil)
VCC I/O1 I/O2 N.C. N.C. N.C. N.C. WRITE RAS . A0 A1 A2 A3 A4 A5 VCC
O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS I/O4 I/O3 N.C. N.C. N.C. CAS OE A12 / N.C. * A11 A10 A9 A8 A7 A6 VSS
* Pin 24 is A12 for HYB 3164400AJ/AT(L) and N.C. for HYB 3165400AJ/AT(L) Pin Configuration
Semiconductor Group
3
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
TRUTH TABLE
FUNCTION Standby Read Early-Write Delayed-Write Read-Modify-Write Fast Page Mode Read 1st Cycle 2nd Cycle Fast Page Mode Early Write 1st Cycle 2nd Cycle Fast Page Mode RMW 1st Cycle 2st Cycle RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh READ WRITE
RAS H L L L L L L L L L L L H-L H-L L-H-L L-H-L
CAS H-X L L L L H-L H-L H-L H-L H-L H-L H L L L L
WE X H L H-L H-L H H L L H-L H-L X H L H L
OE X L X H L-H L L X X L-H L-H X X X L X
ROW ADDR X ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X X ROW ROW
COL ADDR X COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL
I/O1I/O4 High Impedance Data Out Data In Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In
Semiconductor Group
4
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
I/O1 I/O2
I/O4
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator 4
Data out Buffer
4
OE
12
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
12
Column Address Buffer(12)
12
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
4
Refresh Counter (12) 12 Row
4096 x4
Address Buffers(12)
12
Decoder 4096
Row
Memory Array 4096 x 4096 x 4
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3165400AJ/AT(L)
Semiconductor Group
5
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
I/O1 I/O2
I/O4
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator 4
Data out Buffer
4
OE
11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Column Address Buffer(11)
11
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
4
Refresh Counter (13) 13 Row 13
2048 x4
Address Buffers(13)
13
Decoder 8192
Row
Memory Array 8192 x 2048 x 4
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3164400AJ/AT(L)
Semiconductor Group
6
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.0 W Data out current (short circuit)..................................................................................................50 mA Note
Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output H" level voltage (Iout = -2mA) Output low voltage (LVTTL) Output L"level voltage (Iout = +2mA) Output high voltage (LVCMOS) Output H" level voltage (Iout = -100uA) Ouput low voltage (LVCMOS) Output L" level voltage (Iout = +100uA) Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 2.0 - 0.3 2.4 -
Unit Note V V V V V V A A 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L)
Vcc-0.2 -2 -2 0.2 2 2
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
7
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
DC-Characteristics (cont'd)
TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V
Parameter Operating Current -40 ns version -50 ns version -60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Symbol refresh version Unit Note 4k 8k 110 90 75 2 mA mA mA mA 2) 3) 4)
ICC1
155 130 105
Standby Current
(RAS=CAS= Vih)
ICC2 ICC3
-40 ns version -50ns version -60 ns version
2
-
RAS Only Refresh Current: -
155 130 105
110 90 75
mA mA mA
2) 4)
(RAS cycling: CAS = VIH: tRC = tRC min.)
Fast Page Mode Current: -40 ns version -50 ns version -60 ns version
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
ICC4
70 60 50 70 60 50 900 200 mA mA mA A A 2) 3) 4)
Standby Current
(RAS=CAS= Vcc-0.2V)
ICC5 ICC5
900 200
- -
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
ICC6 CAS Before RAS Refresh Current -40 ns version -50 ns version -60 ns version
(RAS, CAS cycling: tRC = tRC min.)
155 130 105 400
155 130 105 400
mA mA mA A
2) 4)
Self Refresh Current (L-version only)
(CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
ICC7
Semiconductor Group
8
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
AC Characteristics (note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter
Symbol
AC64-2F
-40 min.
-50
-60 max. -
Unit Note
max. min. - 90
max. min. - 110
Common Parameters
Random read or write cycle time RAS pulse width CAS pulse width RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for 8k-refresh Refresh period for 4k-refresh Refresh period for L-versions tRC tRAS tCAS tRP tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH 75 40 10 25 10 0 5 0 5 15 10 10 40 5 1 - - - ns 100k 50 100k 13 - - - - - - 30 20 - - - 30 128 64 256 30 10 0 7 0 7 17 12 13 50 5 1 - - - 100k 60 100k 15 - - - - - - 37 25 - - - 30 128 64 256 40 10 0 10 0 10 20 15 15 60 5 1 - - - 100k ns 100k ns - - - - - - 45 30 - - - 30 128 64 256 ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms
7
tCRP
tT tREF tREF tREF
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z tRAC tCAC tAA tOEA tRCS tRCH tRRH tCLZ - - - - 20 0 0 0 0 40 10 20 10 - - - - - - - - - 25 0 0 0 0 50 13 25 13 - - - - - - - - - 30 0 0 0 0 60 15 30 15 - - - - - ns ns ns ns ns ns ns ns ns
11 11 8 8, 9 8, 9 8, 10 8
Column address to RAS lead time tRAL
Semiconductor Group
9
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
AC Characteristics (cont'd)(note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter Output buffer turn-off delay Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay
Symbol
AC64-2F
-40 min. - - 0 10 10 10 10 - - - - - 0 13 13
-50 13 13 - - - - - 0 15 15
-60 max. 15 15 - - -
Unit Note
max. min.
max. min.
tOFF tOEZ tDZO tCDD tODD
ns ns ns ns ns
12 12 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 5 5 0 10 10 0 5 0 - - - - - - - - 7 7 0 13 13 0 7 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - ns ns ns ns ns ns ns ns
16 16 13 15
Write command to RAS lead time tR WL Write command to CAS lead time tC WL Data setup time Data hold time CAS delay time from Din tDS tDH tDZC
Read-Modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time OE command hold time tR WC tR WD tC WD tOEH 105 55 25 35 5 - - - - - 126 68 31 43 7 - - - - - 150 80 35 50 10 - - - - - ns ns ns ns ns
15 15 15
Column address to WE delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCPA tRAS tRHPC 30 - 40 25 - 25 - 35 - 30 - 30 - 40 - 35 - 35 - ns ns ns
8
200k 50
200k 60
200k ns
Semiconductor Group
10
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
AC Characteristics (cont'd)(note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter
Symbol
AC64-2F
-40 min.
-50
-60 max. - -
Unit Note
max. min. - - 71 48
max. min. - - 80 55
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time CAS precharge to WE tPR WC tCPWD 60 40 ns ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 5 5 0 5 5 - - - - - 5 5 0 5 5 - - - - - 5 10 0 10 10 - - - - - ns ns ns ns ns
Write hold time referenced to RAS tWRH
Self Refresh Cycle (L-version only)
RAS pulse width RAS precharge time CAS hold time
tRASS
100k - 75 -50 - -
100k - 90 -50 - -
100k - 110 -50 - -
ns ns ns
17 17 17
tRPS tCHS
Test Mode Cycle
Write command setup time Write command hold time
tWTS tWTH
5 5
- -
5 5
- -
5 5
- -
ns ns
18 18
Capacitance TA = 0 to 70 C,VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A11,A12) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1-I/O4) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
11
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
Notes:
1) All voltages are referenced to VSS. Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a fast page mode cycle ( tpc). 5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh. 18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value. These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must be adjusted by 5 ns.
Semiconductor Group
12
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
CAS
VIL
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
Address
AAAAAAA IH AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
VIL
Row
Row
tRCH tRAH tRCS tRRH tAA tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
WE
AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
V
OE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC tDZO tODD tCAC tCLZ
Hi Z
tCDD
I/O (Inputs)
V
AAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
tOFF tOEZ
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
I/O (Outputs) V
V OH OL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Valid Data Out
Hi Z
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL1
Read Cycle
Semiconductor Group
13
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
V
IH
CAS
VIL
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
. Row
Address
IH
Row
VIL
tRAH
V
tWCS t WP
tCWL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
tWCH tRWL
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDS
I/O (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O (Outputs) V OL
V
Hi Z
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
"H" or "L"
WL2
Write Cycle (Early Write)
Semiconductor Group
14
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
CAS
VIL
tRAD tASR tASC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address V AAAAAAAAA Row AAAAAAAAA IL AAAAAAAAA
V AAAAAAAAA IHAAAAAAAAA AAAAAAAAA AAAAAAAAA
. Row
tRAH
V
WE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCWL tRWL tWP
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEH
V
OE
IH AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
tDZO tDZC
tODD tDS tOEZ tCLZ tOEA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDH
I/O (Inputs)
V
IH AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
VIL
Valid Data
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
I/O (Outputs) V
V OH OL
Hi-Z
Hi-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
15
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRWC tRAS
V
tRP
RAS
IH
VIL V IH
tCSH tRCD tRSH tCAS tCRP
CAS
VIL
tRAH tASR
V
tCAH tASC
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
AAAA IH AAAA AAAA AAAA AAAA AAAA AAAA
VIL
Row
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
Row
tRAD
V IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tAWD tCWD tRWD
tCWL tRWL tWP
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
WE
tAA tRCS
V
tOEA
tOEH
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZO tDZC
V
tDS
tDH
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
I/O (Inputs)
IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
Valid Data in
tCLZ tCAC
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tODD tOEZ
AAAAAA AAAAAA Data AAAAAA AAAAAA Out AAAAAA AAAAAA
I/O (Outputs) V OL
V OH
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
16
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRASP
V IH
tRP
RAS
VIL
tRCD
V IH
tPC tCAS
tCP
tCAS
tRHPC tRSH tCAS
tCRP
CAS
VIL
tCSH tRAH tASR tASC tCAH
Column
tASC
tCAH
tCAH tASC AAAAAAAAA AAAAAAAAA AAAAAAAAA Column AAAAAAAAA AAAAAAAAA AAAAAAAAA tRCS
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAA tRRH AAAAAAA
tASR
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA Row AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA tRCH
V
Address
AAAAA AAAAA AAAAA IH AAAAA AAAAA AAAAA Row AAAAA AAAAA AAAAA AAAAA AAAAA VIL AAAAA AAAAA tRAD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tRCH tRCS
V IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRCS
WE
VIL
tAA
V
tCPA tAA tOEA
tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
OE
VIL
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tDZC tDZO tODD
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF
tDZC
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tCPA tAA tOEA tDZC
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tCDD tODD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tDZO tODD
tDZO
I/O (Inputs)
V
IH AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
VIL
tCAC tCLZ
tCAC tCLZ
tRAC
I/O (Outputs) V
V OH OL
tOFF tOEZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tCAC tCLZ
tOFF tOEZ
tOEZ
AAAAA AAAAA AAAAA Valid AAAAA AAAAA Data Out AAAAA AAAAA
AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA
AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
FPM1
Fast Page Mode Read Cycle
Semiconductor Group
17
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRAS
V IH
tRP
RAS
VIL
tPC tRCD
V IH
tRSH tCP tCAS tCAS tCRP
tCAS
CAS
VIL
tRAH tASR
V IH AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRAL tCAH tASC tASC tCAH tASC tCAH tASR
Address
VIL
Row
AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA
tRAD tWCS
V
tCWL tWCH tWP
tWCS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
tCWL
tWCS
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tCWL tRWL
WE
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tWCH tWCH tWP AAAAAAAAAAAAA tWP AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
V
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDH tDS
I/O (Inputs)
V IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
tDH tDS
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tDH tDS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
VIL
Valid Data In
Valid Data In
Valid Data In
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Outputs) V OL
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
V
HI-Z
"H" or "L"
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
18
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tCPWD tCWD
tAWD
tOEA
tCPWD tCWD
tOEA
tCAH
tRWD tCWD
tAWD
tOEA
tCAH
tDZC tCLZ tDZO
tCSH
Column
tASC
tAA
tCAC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tWP
Data In
tOEH
tOEZ tDH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column Address
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tWP
tOEH
Data In
tDH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tASC
tCWL
tDZC
tCAC tAA
tCAH
tCPA
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEH
tWP
Data In
tDH tOEZ tDS
AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRAL
tRWL tCWL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRP
tCRP
tASR
Row
tODD
tCAS
tPRWC
tRAS
tODD
tCAS
tOEZ
tAWD
tASC
tCPA tDZC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCWL
tCP
tAA
AAAAAA AAAAAA AAAAAA AAAAAA
tODD
tCAS
I/O (Inputs) V IL
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
19
OH I/O (Outputs) V
IH
IH
IH
IH
IH
IH
V IL
V IL
V IL
V IL
V
V IL
V
V
V
Address
RAS
CAS
V
WE
OE
V
V
OL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Row
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
"H" or "L"
tRAD
tRAH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRCD
tRCS
tRAC
Data Out
AAAAA AAAAA AAAAA
tDS
Data Out
AAAAA AAAAA AAAAA
tDS
Data Out
AAAAA AAAAA AAAAA
tRSH
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCRP tRPC
V IH
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
CAS
VIL
tRAH tASR
tASR
Row
V
Address
IH AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA VIL AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Outputs) V OL
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
V
HI-Z
"H" or "L"
WL9
RAS-Only Refresh Cycle
Semiconductor Group
20
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRC tRP
V
tRAS
tRP
RAS
IH
VIL
tRPC tCP
tCSR tCHR tRPC
tCRP
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
V
CAS
IH
VIL
tWRP tWRH
V IH AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
VIL
tOEZ
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
IH I/O (Inputs) V IL V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD
OH I/O (Outputs)VOL V
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
21
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRC
V
tRC tRP tRAS tRP
tRAS
IH
RAS
VIL
tRCD
V
tRSH tCHR tCRP
CAS
IH
VIL
tRAD tASC tASR tRAH
AAAAA AAAAA AAAAA
tWRP tCAH tWRH tASR
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
V AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA VIL AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tRCS
WE
V AAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tRRH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tAA tOEA
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
tDZO
V
tODD tCAC tCLZ
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
I/O (Inputs)
IH
VIL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tOFF tOEZ
Valid Data Out
tRAC
OH I/O (Outputs) V OL
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
V
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
HI-Z
"H" or "L"
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
22
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRC tRP
V IH
tRC tRAS tRP
tRAS
RAS
VIL
tRCD
V IH
tRSH
tCHR
tCRP
CAS
VIL
tRAD tRAH tASR
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tASC tCAH
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
V AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA Row VIL AAAAAAA AAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Row
tWCS
tWCH tWP
tWRP
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tWRH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
WE
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA
tDS
I/O (Input)
V AAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA V AAAAAAAAAAAAAAA IL AAAAAAAAAAAAAAA
tDH
Valid Data
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Output) V OL
V
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
23
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRP
V
tRC tRAS tRP
RAS
IH
VIL
tRPC tCP tCSR tCHR tRPC tCRP
V
CAS
IH
VIL
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tASR tRAH
AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAA Address IHAAAAAAAAAAAAAAAAAAAAAAA AAA Row AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA
V
VIL AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tWTS
V
tWTH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
IH AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
VIL
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
IH I/O (Inputs) V IL
V
tODD
HI-Z
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD tOEZ
I/O (Outputs) V
V AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA OHAAAAAAAAAAAAAAAAAAAAAAA OL
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tOFF
"H" or "L"
WL15
Test Mode Entry Cycle
Semiconductor Group
24
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
tRP
V
tRASS
tRPS
RAS
IH
VIL
tRPC tCSR
V
tCHS
tCRP
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tCP
IH
CAS
VIL
tWRP tWRH
V
WE
IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
IH I/O (Inputs) V IL V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD tOEZ
OH I/O (Outputs) VOL
V
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL13
Self Refresh (Sleep Mode") L-version only
Semiconductor Group
25
HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM
Package Outlines
Plastic Package P-SOJ-32-1 (400 mil) (Small Outline J-lead, SMD)
Plastic Package P-TSOPII-32-1 (400 mil) (Small Outline J-lead, SMD)
Semiconductor Group
26

▲Up To Search▲

Price & Availability of HYB3165400ATL-60

	To Download HYB3165400ATL-60 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .