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8M x 8-Bit Dynamic RAM (4k & 8k Refresh, EDO-Version)
HYB 3164805AJ/AT(L) -40/-50/-60 HYB 3165805AJ/AT(L) -40/-50/-60
Advanced Information
* * * *
8 388 608 words by 8-bit organization 0 to 70 C operating temperature Hyper Page Mode - EDO - operation Performance: -40 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/write cycle time Hyper page mode (EDO) cycle time 40 10 20 69 16 -50 50 13 25 84 20 -60 60 15 30 104 25 ns ns ns ns ns
* *
Single + 3.3 V ( 0.3V) power supply Low power dissipation: max. 450 active mW ( HYB 3164805AJ/AT(L)-40) max. 360 active mW ( HYB 3164805AJ/AT(L)-50) max. 324 active mW ( HYB 3164805AJ/AT(L)-60) max. 612 active mW ( HYB 3165805AJ/AT(L)-40) max. 468 active mW ( HYB 3165805AJ/AT(L)-50) max. 432 active mW ( HYB 3165805AJ/AT(L)-60) 7.2 mW standby (LVTTL) 3.24 mW standby (LVMOS) 720 A standby for L-version Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh
*
Self refresh (L-version only) 8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164805AJ/AT) 4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165805AJ/AT) * 256 msec refresh period for L-versions * Plastic Package: P-SOJ-32-1 400 mil HYB 3164(5)805AJ P-TSOPII-32-1 400 mil HYB 3164(5)805AT(L)
* *
Semiconductor Group
1
6.97
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
This HYB3164(5)805A is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated on an advanced second generation 64Mbit 0,35m-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)805A operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)805A to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)805ATL parts have a very low power sleep mode" supported by Self Refresh. Ordering Information Type 8k-refresh versions: HYB 3164805AJ-40 HYB 3164805AJ-50 HYB 3164805AJ-60 HYB 3164805AT-40 HYB 3164805AT-50 HYB 3164805AT-60 HYB 3164805ATL-50 HYB 3164805ATL-60 4k-refresh versions: HYB 3165805AJ-40 HYB 3165805AJ-50 HYB 3165805AJ-60 HYB 3165805AT-40 HYB 3165805AT-50 HYB 3165805AT-60 HYB 3165805ATL-50 HYB 3165805ATL-60 P-SOJ-32-1 P-SOJ-32-1 P-SOJ-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 400 mil DRAM (access time 40 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) 400 mil DRAM (access time 40 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) P-SOJ-32-1 P-SOJ-32-1 P-SOJ-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 400 mil DRAM (access time 40 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) 400 mil DRAM (access time 40 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) Ordering Code Package Descriptions
Semiconductor Group
2
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
P-SOJ-32-1 (400 mil) P-TSOPII-32-1 (400 mil)
VCC I/O1 I/O2 I/O3 I/O4 N.C. VCC WE RAS . A0 A1 A2 A3 A4 A5 VCC
O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS I/O8 I/O7 I/O6 I/O5 VSS CAS OE A12 / N.C. * A11 A10 A9 A8 A7 A6 VSS
* Pin 24 is A12 for HYB 3164805AJ/AT(L) and N.C. for HYB 3165805AJ/AT(L) Pin Configuration Pin Names A0-A12 A0-A11 RAS OE I/O1-I/O8 CAS WE Vcc Vss Address Inputs for 8k-refresh version HYB 3164805AJ/AT(L) Address Inputs for 4k-refresh version HYB 3165805AJ/AT(L) Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground
Semiconductor Group
3
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
TRUTH TABLE
FUNCTION Standby Read Early-Write Delayed-Write Read-Modify-Write Hyper Page Mode Read 1st Cycle 2nd Cycle Hyper Page Mode Write 1st Cycle 2nd Cycle Hyper Page Mode RMW 1st Cycle 2st Cycle RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh READ WRITE Self Refresh (L-version only)
RAS H L L L L L L L L L L L H-L H-L L-H-L L-H-L H-L
CAS H-X L L L L H-L H-L H-L H-L H-L H-L H L L L L L
WE X H L H-L H-L H H L L H-L H-L X H L H L H
OE X L X H L-H L L X X L-H L-H X X X L X X
ROW ADDR X ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X X ROW ROW X
COL ADDR X COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL X
I/O1I/O8 High Impedance Data Out Data In Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In High Impedance
Semiconductor Group
4
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
I/O1 I/O2
I/O8
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator 8
Data out Buffer
8
OE
10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Column Address Buffer(10)
10
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
8
Refresh Counter (13) 13 Row 13
1024 x8
Address Buffers(13)
13
Decoder 8192
Row
Memory Array 8192 x 1024 x 8
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3164805AJ/AT(L)
Semiconductor Group
5
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
I/O1 I/O2
I/O8
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator 8
Data out Buffer
8
OE
11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
12
Column Address Buffer(11)
11
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
8
Refresh Counter (12) 12 Row
2048 x8
Address Buffers(12)
12
Decoder 4096
Row
Memory Array 4096 x 2048 x 8
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3165805AJ/AT(L)
Semiconductor Group
6
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.0 W Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output H" level voltage (Iout = -2mA) Output low voltage (LVTTL) Output L"level voltage (Iout = +2mA) Output high voltage (LVCMOS) Output H" level voltage (Iout = -100uA) Ouput low voltage (LVCMOS) Output L" level voltage (Iout = +100uA) Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 2.0 - 0.3 2.4 -
Unit Note V V V V V V A A 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L)
Vcc-0.2 -2 -2 0.2 2 2
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
7
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
DC-Characteristics (cont'd)
TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V
Parameter Operating Current -40 ns version -50 ns version -60 ns version Symbol refresh version Unit Note 4k row 8k row 125 100 85 2 125 100 85 mA mA mA mA mA mA mA 2) 3) 4)
ICC1
170 140 115
-
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Current (RAS=CAS= Vih) RAS Only Refresh Current: -40 ns version -50 ns version -60 ns version
ICC2 ICC3
2 170 140 115
- 2) 4)
(RAS cycling: CAS = VIH: tRC = tRC min.)
Hyper Page Mode (EDO) Current: ICC4 -40 ns version -50 ns version -60 ns version
(RAS = VIL, CAS, address cycling: tHPC=tHPC min.)
140 105 85 900 200
140 105 85 900 200
mA mA
2) 3) 4)
Standby Current
(RAS=CAS= Vcc-0.2V)
ICC5 ICC5 ICC6
A A
- -
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
CAS Before RAS Refresh Current -40 ns version -50 ns version -60 ns version
(RAS, CAS cycling: tRC = tRC min.)
170 140 115
170 140 115 400
mA mA
2) 4)
Self Refresh Current (L-version only)
(CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
ICC7
400
A
Capacitance
TA = 0 to 70 C,VCC = 3.3 V 0.3 V, f = 1 MHz
Parameter Input capacitance (A0 to A11,A12) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1-I/O8) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
8
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
AC64-2E
Limit Values - 40
min. max.
Unit
Note
- 50
min. max.
- 60
min. max.
Common Parameters
Random read or write cycle time RAS pulse width CAS pulse width RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) tRC tRAS tCAS tRP tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT 69 40 6 25 6 0 5 0 5 9 7 6 32 5 1 - - - -
100k 100k
84 50 8 30 8 0 7 0 7 11 9 8 40 5 1 - - -
-
100k 100k
104 60 10 40 10 0 10 0 10 14 12 10 48
-
100k 100k
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms 7
- - - - - - 30 20 - - - 50 128 64 256
- - - - - - 37 25
- - - - - - 45 30 - - - 50 128 64 256
- 50 128 64 256
5 1 - - -
Refresh period for 8k-refresh-version tREF Refresh period for 4k-refresh version tREF Refresh period for L-versions tREF
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time tRAC tCAC tAA tOEA tRAL tRCS tRCH - - - - 20 0 0 40 10 20 10 - - - - - - - 25 0 0 50 13 25 13 - - - - - - - 30 0 0 60 15 30 15 - - - ns ns ns ns ns ns ns 11 8, 9 8, 9 8,10
Semiconductor Group
9
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
AC64-2E
Limit Values - 40
min. max.
Unit
Note
- 50
min. max.
- 60
min. max.
Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay
tRRH tCLZ tOFF tDZC tDZO tCDD tODD
0 0 0 0 0 0 10 10
- - 10 10 - - - -
0 0 0 0 0 0 13 13
- - 13 13 - - - -
0 0 0 0 0 0 15 15
- - 15 15 - - - -
ns ns ns ns ns ns ns ns
11 8 12 12 13 13 14 14
Output buffer turn-off delay from OE tOEZ
Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 5 5 0 6 6 0 5 - - - - - - - 7 7 0 8 8 0 7 - - - - - - - 10 10 0 10 10 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 89 52 22 32 5 - - - - - 109 65 28 40 7 - - - - - 133 77 32 47 10 - - - - - ns ns ns ns ns 15 15 15
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time Access time from CAS precharge Output data hold time tHPC tCPA tCOH 16 - 3 - 22 - 20 - 5 - 27 - 24 - 5 - 32 - ns ns ns 7
Semiconductor Group
10
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
AC64-2E
Limit Values - 40
min. max. 200k
Unit
Note
- 50
min. max. 200k
- 60
min. max. 200k
RAS pulse width in hyper page mode tRAS CAS precharge to RAS Delay OE pulse width OE hold time from CAS high OE setup time prior to CAS tRHPC tOEP tOEHC tOES
40 22 5 5 0 5
50 27 5 5 0 5
60 32 5 5 0 5
ns ns ns ns ns ns
- - - 10 -
- - - 13 -
- - - 15 -
Output buffer turn-off delay from WE tWEZ
Hyper Page Mode (EDO) Readmodify-Write Cycle
Hyper page mode (EDO) read-write cycle time CAS precharge to WE tPRWC tCPWD 44 34 - - 54 42 - - 63 49 - - ns ns
CAS before RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 5 5 5 5 5 - - - - - 5 5 5 5 5 - - - - - 5 10 5 10 10 - - - - - ns ns ns ns ns
Self Refresh Cycle (L-versions only)
RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS
100k 100k
_ - -
100k
_ - -
ns ns ns
17 17 17
69 -50
- -
84 -50
104 -50
Test Mode Cycle
Write command setup time Write command hold time tWTS tWTH 5 5 - - 5 5 - - 5 5 - - ns ns 18 18
Semiconductor Group
11
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
Notes:
1) All voltages are referenced to VSS. Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a hyper page mode cycle ( thpc). 5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh 18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value. These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must be adjusted by 5 ns.
Semiconductor Group
12
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
CAS
VIL
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
Address
AAAAAAA IH AAAAAAA AAAAAAA AAAAAAA AAAAAAA VIL AAAAAAA
Row
Row
tRCH tRAH tRCS tRRH tAA tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
WE
AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
V
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC tDZO tODD tCAC tCLZ
Hi Z
tCDD
I/O (Inputs)
V
AAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
tOFF tOEZ
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
I/O (Outputs) V
V OH OL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Valid Data Out
Hi Z
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL1
Read Cycle
Semiconductor Group
13
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
V
IH
CAS
VIL
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
. Row
Address
IH AAAAAAA AAAAAAA
Row
VIL
tRAH
V
tWCS t WP
tCWL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWCH
WE
IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
tRWL
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDS
I/O (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O (Outputs) V OL
V
Hi Z
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
"H" or "L"
WL2
Write Cycle (Early Write)
Semiconductor Group
14
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
CAS
VIL
tRAD tASR tASC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
V AAAAAAAAA IHAAAAAAAAA AAAAAAAAA AAAAAAAAA Address V AAAAAAAAA Row AAAAAAAAA IL AAAAAAAAA
. Row
tRAH
V
WE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCWL tRWL tWP
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEH
V
OE
IH AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
VIL
tDZO tDZC
I/O (Inputs)
V IH AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
tODD tDS tOEZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tDH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
Valid Data
tCLZ tOEA
Hi-Z
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
I/O (Outputs) V
V OH OL
Hi-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
15
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRWC tRAS
V
tRP
RAS
IH
VIL V
tCSH tRCD tRSH tCAS tCRP
IH
CAS
VIL
tRAH tASR
V
tCAH tASC
tASR
Row
Address
IH AAAA AAAA AAAA
AAAA AAAA AAAA
VIL
Row
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
tRAD
V
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tAWD
tCWD tRWD
tRWL tWP
WE
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
tAA tRCS
V
tOEA
tOEH
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
OE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZO tDZC
V
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tDS
tDH
Valid Data in
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
I/O (Inputs)
VIL
tCLZ tCAC
tODD tOEZ
AAAAAA AAAAAA Data AAAAAA AAAAAA AAAAAA AAAAAA Out
I/O (Outputs) V OL
V OH
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
16
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V
tRP tRHPC tRSH
RAS
IH
tRCD
VIL
tCRP
V IH
tHPC tCAS
tCRP
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC
AAA AAA
tRAL tCAH tASC tCAH tASC tCAH
AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAA
V
Address
IH AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA
VIL
AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Row AAA Column 1 AAAAAAAAAA Column 2 AAAAAAAAAA Column N AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA
AAAAAAAAAA
tRAD tRRH tRCH
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tRCS
WE
VIH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA VIL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tOES
V
tCAC tAA tCPA
tCAC tAA tCPA
tOFF
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
OE
OH AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA OL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEA
V
tRAC tAA tCAC
I/O IH (Output) V IL
V
tOEZ tCOH
AAAA AAAA AAAA AAAA AAAA AAAA AAAA
tCOH
Data Out 2
AAA AAA AAA AAA AAA AAA AAA
tCLZ
AAAA AAAA AAAA AAAA AAAA AAAA AAAA
Data Out 1
Data Out N
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
WL5
"H" or "L"
Hyper Page Mode (EDO) Read Cycle Semiconductor Group 17
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V IH
tRP tRHCP tRSH tCRP
tRCD
RAS
VIL
tHPC tCRP
V IH
tCAS
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC tCAH tASC tCAH
tRAL tASC tCAH
V
Address
IH AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA
VIL
AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Row AAA Column 1 AAAAAAAAAA Column 2 AAAAAAAAAA Column N AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA
tRAD tRRH tRCH tCAC tAA tCPA tOEHC tOEHC
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
tRCS
WE
VIH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA VIL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tOES
V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCAC tAA tCPA
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tOFF
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEA
V
OL
tRAC tAA tCAC
I/O IH (Output) V IL
V
tOEP tOEZ
tOEA
tOEP tOEA tOEZ
AAA AAA AAA AAA AAA AAA AAA
tOEZ
tCLZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
Data Out 1
Data Out 2
AAA AAA AAA AAA AAA AAA AAA
Data Out N
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
WL6
"H" or "L"
Hyper Page Mode (EDO) Read Cycle (OE Control)
Semiconductor Group
18
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V IH
tRP tRHPC tRSH tCRP
tRCD
RAS
VIL
tHPC tCRP
V IH
tCAS
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC
Row
AAA AAA AAA AAA AAA AAA
tRAL tCAH tASC tCAH
Column
tASC tCAH
Column
AAAAAAAAA AAAAAAAAA AAAAAAAAA N AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
V
Address
IH AAAAA AAAAA
VIL
AAAAA AAAAA AAAAA AAAAA AAAAA
Column
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA 1 AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA 2 AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tRAD
tAA
tAA tRCH tRRH tRCH tRCS
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tRCS
WE
VIH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA VIL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tRCH
tRCS
tWP tOES
V
tCAC tCPA
tWP
tCAC tCPA tOFF
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEA
tRAC tAA tCAC
I/O IH (Output) V IL
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tOEZ tWEZ
AAA AAA AAA AAA AAA AAA AAA
tWEZ
AAAA AAAA AAAA AAAA AAAA AAAA AAAA
V
tCLZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
Data Out 1
Data Out 2
Data Out N
WL7
"H" or "L"
Hyper Page Mode (EDO) Read Cycle (WE Control)
Semiconductor Group
19
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V IH
tRP tRHPC tRSH tCRP
tRCD
RAS
VIL
tHPC tCRP
V IH
tCAS
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC tCAH tASC tCAH
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tRAL tASC tCAH
AAAAAAAA Column N AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Address
V AAAAA AAAAAAAAAA IHAAAAA Row AAA AAA AAAAAAAAAA AAAAA AAAAA Addr AAA Column 1 AAAAAAAAAA Column 2 AAA AAAAAAAAAA AAAAA AAA AAAAAAAAAA VIL AAAAA AAA AAAAAAAAAA
tRAD tCWL tWCS
VIH AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA VIL
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tCWL tWCH tWP tWCS
tRWL tCWL tWCH tWP
tWCH tWCS tWP
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
WE
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
V
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDS
V IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
tDH
AAAAAAAAAA AAAAAAAAAA
tDS
tDH
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tDS
tDH
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
I/O (Input) V IL
AAAAAAAAAA AAAAAAAAAA Data In 1 AAAAAAAAAA Data In 2 AAAAAAAAAA
Data In N
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL8
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
20
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V IH
tRP
tRCD tRSH tCP tCAS tCP tCAS tCRP
RAS
VIL
tHPC tCRP
V IH
tCAS
CAS
VIL
tCSH tASR tRAH tASC
AAA AAA
tRAL tCAH tASC tCAH tASC tCAH
AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAA
V
Address
IH AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA
VIL
AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Row AAA Column 1 AAAAAAAAAA Column 2 AAAAAAAAAA Column N AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA
AAAAAAAAAA
tRAD
tCWL tRCS
tCWL tRCS
tCWL tRWL
tRCS
WE
VIH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA VIL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tWP tOEH
OE
V OH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA V AAAAAAAAAAAAAAA OL AAAAAAAAAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tWP tOEH
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tWP tOEH
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tODD tDS
AAAA AAAA AAAA AAAA AAAA AAAA AAAA
tODD tDS
AAAA AAAA AAAA AAAA AAAA AAAA AAAA
tDS tODD
I/O (Input)
V IH VIL
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tDH
tDH
tDH
Data In 1
Data In 2
Data In N
WL16
"H" or "L"
Hyper Page Mode (EDO) Late Write Cycle
Semiconductor Group
21
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tCPWD tCWD
tAWD
tOEA
tCPWD tCWD
tCAH
tOEA
tRWD tCWD
tAWD
tCSH
tOEA
tCAH
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
Data In
tOEZ tDH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
tCPA
tCLZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tWP
Data In
tDH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tASC
tDZC
tCWL
tOEH
tCAC tAA
tCAH
tCPA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tWP
tRSH
Data In
tDH tDS
AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRP
tCRP
tASR
Row
tRAL
tRWL tCWL
tCAS
tODD
tCLZ
tRASP
tPRWC
tCAS
tODD
tOEZ
tAWD
tDZC
tWP
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tASC
tCWL
tCP
tOEH
tAA
AAAAAA AAAAAA AAAAAA AAAAAA
tODD
tCAS
tRAD tRAH
AAAAA AAAAA AAAAA AAAAA AAAAA
I/O (Inputs) V IL
OH I/O (Outputs) V
IH
IH
IH
IH
IH
IH
V IL
V IL
V IL
V IL
V
V IL
V
V
V
RAS
CAS
Address
V
WE
OE
V
V
OL
WL17
AAAAA AAAAA AAAAA AAAAA AAAAA
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tDZC tCLZ tDZO
Column
tASC
tAA
tCAC
AAAAAA AAAAAA AAAAAA AAAAAA
tRCS
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tRCD
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Semiconductor Group
tASR
Row
22
tRAC
Data Out
AAAAA AAAAA AAAAA
tDS
Data Out
AAAAA AAAAA AAAAA
tDS
Data Out
AAAAA AAAAA AAAAA
tOEH
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCRP tRPC
V IH
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
CAS
VIL
tRAH tASR
tASR
Row
V
Address
IH AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA VIL AAAAAAAAAAAA AAAAAAAAAAAA
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Outputs) V OL
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
V
HI-Z
"H" or "L"
WL9
RAS Only Refresh Cycle
Semiconductor Group
23
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRC tRP
V
tRAS
tRP
RAS
IH
VIL
tRPC tCP
tCSR tCHR tRPC
tCRP
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
V
CAS
IH
VIL
tWRP tWRH
V IH AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
VIL
tOEZ
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
IH I/O (Inputs) V IL V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD
OH I/O (Outputs)VOL V
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL10
CAS-before-RAS Refresh Cycle Semiconductor Group 24
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRC
V
tRC tRP tRAS tRP
tRAS
IH
RAS
VIL
tRCD
V
tRSH tCHR tCRP
CAS
IH
VIL
tRAD tASC tASR tRAH
AAAAA AAAAA AAAAA
tWRP tCAH tWRH tASR
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
V AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA VIL AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tRCS
WE
V AAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tRRH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tAA tOEA
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
tDZO
V
tODD tCAC tCLZ
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
I/O (Inputs)
IH
VIL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tOFF tOEZ
Valid Data Out
tRAC
OH I/O (Outputs) V OL
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
V
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
HI-Z
"H" or "L"
WL11
Hidden Refresh Read Cycle
Semiconductor Group
25
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRC tRP
V IH
tRC tRAS tRP
tRAS
RAS
VIL
tRCD
V IH
tRSH
tCHR
tCRP
CAS
VIL
tRAD tRAH tASR
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tASC tCAH
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
V AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA Row VIL AAAAAAA AAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Row
tWCS
tWCH tWP
tWRP
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tWRH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
WE
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA
tDS
I/O (Input)
V AAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA V AAAAAAAAAAAAAAA IL AAAAAAAAAAAAAAA
tDH
Valid Data
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Output) V OL
V
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL12
Hidden Refresh Early Write Cycle
Semiconductor Group
26
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRP
V
tRASS
tRPS
RAS
IH
VIL
tRPC tCSR
V
tCHS
tCRP
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tCP
IH
CAS
VIL
tWRP tWRH
V
WE
IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
IH I/O (Inputs) V IL V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD tOEZ
OH I/O (Outputs) VOL
V
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL13
Self Refresh (Sleep Mode)
Semiconductor Group
27
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
tRP
V
tRC tRAS tRP
RAS
IH
VIL
tRPC tCP tCSR tCHR tRPC tCRP
V
CAS
IH
VIL
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tASR tRAH
AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAA Address IHAAAAAAAAAAAAAAAAAAAAAAA AAA Row AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA
V
VIL AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tWTS
V
tWTH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
IH AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
VIL
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
IH I/O (Inputs) V IL
V
tODD
HI-Z
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD tOEZ
I/O (Outputs) V
V AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA OHAAAAAAAAAAAAAAAAAAAAAAA OL
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tOFF
"H" or "L"
WL15
Test Mode Entry Cycle
Semiconductor Group
28
HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM
Package Outlines Plastic Package P-SOJ-32-1 (400 mil) (Small Outline J-lead, SMD)
Plastic Package P-TSOPII-32-1 (400 mil) (Small Outline J-lead, SMD)
Semiconductor Group
29

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