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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
FEATURES
* Eight LVCMOS/LVTTL outputs, 15 typical output impedance * Output frequency range: 125MHz - 160MHz * Crystal oscillator interface, 25MHz - 32MHz crystal * VCO range: 500MHz - 640MHz * RMS phase jitter (1.875MHz - 20MHz): 0.52ps (typical) * Output skew: 150ps (maximum) (design target) * Voltages supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS840008-01 is an 8 output LVCMOS/LVTTL Synthesizer designed to generate 125MHz for HiPerClockSTM Gigabit Ethernet applications and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. The ICS840008-01 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Gigabit Ethernet jitter requirements. The ICS840008-01 is packaged in a small 24-pin SSOP package.
ICS
BLOCK DIAGRAM
nPLL_SEL Pulldown
PIN ASSIGNMENT
VDDO nc XTAL_OUT XTAL_IN VDDA OE MR nPLL_SEL VDD nc GND nc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q0 Q1 GND Q2 Q3 VDDO Q4 Q5 GND Q6 Q7 VDDO
25MHz
XTAL_IN
1 Phase Detector VCO 500MHz 640MHz
/4 (fixed)
OSC
XTAL_OUT
0
8
8
Q0:Q7
/20 (fixed)
ICS840008-01
24-Lead SSOP, 150MIL 3.9mm x 8.65mm x 1.5mm package body R Package Top View
MR Pulldown OE Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840008AR-01
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1
REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Type Power Unused Input Power Input Input Pullup Description Output supply pins. No connect. Crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Analog supply pin. Output enable. LVCMOS/LVTTL interface levels Active HIGH Master Reset. When logic HIGH, the internal dividers are Pulldown reset causing the true outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and XTAL as the input to the dividers. Pulldown When HIGH, selects XTAL. When LOW, selects PLL. LVCMOS/LVTTL interface levels. Core supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 13, 19 2, 10, 12 3, 4 5 6 7 Name VDDO nc XTAL_OUT, XTAL_IN VDDA OE MR
8 9
nPLL_SEL VDD
Input Power
11, 16, 22 GND Power Power supply ground. 14, 15, 17, Q7, Q6, Q5, Single-ended outputs.15 impedance. 18, 20, 21, Q4, Q3, Q2, Ouput LVCMOS/LVTTL interface levels. 23, 24 Q1, Q0 NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance VDDO = 3.63V Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance VDDO = 3.63V or 2.625V VDDO = 1.89V VDDO = 2.625V VDDO = 1.89V Test Conditions Minimum Typical 4 TBD TBD TBD 51 51 15 TBD Maximum Units pF pF pF pF K K
840001AR-01
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REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 73.1C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V10%, VDDO = 3.3V10% OR 2.5V5% OR 1.8V5%,
TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.97 2.97 2.97 2.375 1.71 Typical 3.3 3.3 3.3 2.5 1.8 65 5 4 Maximum 3.63 3.63 3.63 2.625 1.89 Units V V V V V mA mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 2.5V5% OR 1.8V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 1.71 Typical 2.5 2.5 2.5 1.8 60 5 4 Maximum 2.625 2.625 2.625 1.89 Units V V V V mA mA mA
840008AR-01
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3
REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions OE, MR, PLL_SEL OE, MR, PLL_SEL MR, nPLL_SEL VDD = 3.3V 10% VDD = 2.5V 5% VDD = 3.3V 10% VDD = 2.5V 5% VDD = 3.3V 10% VDD = 2.5V 5% VDD = 3.3V 10% VDD = 2.5V 5% VDD = 3.3V 10% VDD = 2.5V 5% VDD = 3.3V 10% VDD = 2.5V 5% VDDO = 3.3V 10% VDDO = 2.5V 5% VDDO = 1.8V 5% VDDO = 3.3V10% or 2.5V5% VDDO = 1.8V 5% -5 -5 -150 -150 2.6 1.8 1.5 0.5 0.4 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 1.3 0.7 150 150 5 5 Units V V V V A A A A A A A A V V V V V
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage
IIH
Input High Current OE MR, nPLL_SEL
IIL
Input Low Current OE
VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage: NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. 25 Test Conditions Minimum Typical Maximum 32 50 7 Units MHz MHz pF Fundamental
840001AR-01
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4
REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions Minimum 125 TBD Integration Range: 1.875MHz - 20MHz 20% to 80% 0.52 TBD 550 Typical Maximum 160 Units MHz ps ps ms ps %
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V10%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time Output Rise/Fall Time
tsk(o) tjit(O)
tL tR / tF
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V10%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time Output Rise/Fall Time Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 125 TBD 0.53 TBD 600 Typical Maximum 160 Units MHz ps ps ms ps %
tsk(o) tjit(O)
tL tR / tF
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = 3.3V10%, VDDO = 1.8V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time Output Rise/Fall Time Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 125 TBD 0.49 TBD 630 Typical Maximum 160 Units MHz ps ps ms ps %
tsk(o) tjit(O)
tL tR / tF
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840008AR-01
www.icst.com/products/hiperclocks.html
5
REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions Minimum 125 TBD Integration Range: 1.875MHz - 20MHz 20% to 80% 0.53 TBD 600 Typical Maximum 160 Units MHz ps ps ms ps %
TABLE 5D. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time Output Rise/Fall Time
tsk(o) tjit(O)
tL tR / tF
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5E. AC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time Output Rise/Fall Time Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 125 TBD 0.49 TBD 630 Typical Maximum 160 Units MHz ps ps ms ps %
tsk(o) tjit(O)
tL tR / tF
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840001AR-01
www.icst.com/products/hiperclocks.html
6
REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 125MHZ (3.3V)
0 -10 -20 -30 -40 -50
Gigabit Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -160 -170 -180 -190 100 1k
10k
Phase Noise Result by adding Gigabit Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
840008AR-01
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7
REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V10% 2.05V13% 1.25V5%
VDD, VDDA, VDDO
SCOPE
Qx
VDD, VDDA,
SCOPE
VDDO GND
Qx
LVCMOS
GND
LVCMOS
-1.65V10%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V12% 0.9V5%
1.25V5%
VDD, VDDA,
SCOPE
VDDO GND
Qx
VDD, VDDA, VDDO
SCOPE
Qx
LVCMOS
LVCMOS
GND
-0.9V5%
-1.25V5%
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
1.6V5% 0.9V5%
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
VDD, VDDA,
SCOPE
VDDO GND
Qx
Phase Noise Mask
LVCMOS
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-0.9V5%
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
840001AR-01
RMS PHASE JITTER
REV. A APRIL 7, 2005
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8
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
V
Qx
DDO
2
80% 20% tR
80% 20% tF
V
Qy
DDO
2 tsk(o)
Clock Outputs
OUTPUT SKEW
OUTPUT RISE/FALL TIME
V
DDO
Q0:Q7
Pulse Width t
2
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840008AR-01
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REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840008-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F V DDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840008-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332
ICS840008-01
Figure 2. CRYSTAL INPUt INTERFACE
840001AR-01
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REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
24 LEAD SSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 73.1C/W
1
65.9C/W
2.5
60.5C/W
TRANSISTOR COUNT
The transistor count for ICS840008-01 is: 3378
840008AR-01
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11
REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
24 LEAD SSOP
PACKAGE OUTLINE - R SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L ZD 0.40 0 0.84 REF 0.20 0.18 8.55 5.80 3.80 0.635 BASIC 1.27 8 1.35 0.10 Millimeters Minimum 24 1.75 0.25 1.50 0.30 0.25 8.75 6.20 4.00 Maximum
Reference Document: JEDEC Publication 95, MO-137
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12
REV. A APRIL 7, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840008-01
FEMTOCLOCKSTMCRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Marking ICS840008AR01 ICS840008AR01 Package 24 Lead SSOP 24 Lead SSOP Shipping Packaging tube 2500 tape & reel Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS840008AR-01 ICS840008AR-01T
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840008AR-01
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REV. A APRIL 7, 2005

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