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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
FEATURES
* (2) Differential LVPECL outputs * Selectable CLKx, nCLKx differential input pairs * CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels * Maximum output frequency: 175MHz * FemtoClock VCO frequency range: 560MHz - 700MHz * RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 0.81ps (typical) * Full 3.3V or mixed 3.3V core/2.5V output supply voltage * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS843002I-40 is a member of the HiperClockSTM family of high performance clock HiPerClockSTM solutions from ICS. The ICS843002I-40 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock VCO. PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non-FEC (non-Forward Error Correction) SONET/SDH applications with rates up to OC-48 (SONET) or STM-16 (SDH). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application.
ICS
PIN ASSIGNMENT
XTAL_OUT XTAL_IN R_SEL2 R_SEL1 R_SEL0 nCLK1 CLK1 VEE
The ICS843002I-40 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. "Hitless switching" is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks. Typical ICS843002I-40 configuration in SONET/SDH Systems: * VCXO 19.44MHz crystal * Loop bandwidth: 50Hz - 250Hz * Input Reference clock frequency selections: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz * Output clock frequency selections: 19.44MHz, 77.76MHz, 155.52MHz, Hi-Z
32 31 30 29 28 27 26 25 LF1 LF0 ISET VCC CLK0 nCLK0 CLK_SEL nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
QA_SEL1 QA_SEL0 QB_SEL1 QB_SEL0 VCCA QA nQA nc
24 23 22 21 20 19 18 17
LOR0 LOR1 nc VCCO_LVCMOS VCCO_LVPECL nQB QB VEE
ICS843002I-40
32-Lead VFQFN 5mm x 5mm x 0.75mm package body K Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843002AKI-40
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1
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
BLOCK DIAGRAM
External Loop Components
19.44 MHz Pullable xtal
ICS843002-40
VCCO_LVCMOS CLK1 nCLK1 LOR1
0 Activity Detector
ISET LF0
Phase Detector
LF1
1
R Divider = 1, 2, 4, 8, 16 or 32
Divide by 32
Charge Pump and Loop Filter
VCXO
XTAL_OUT
19.44 MHz
CLK0 nCLK0 LOR0
Divide by 32 VCXO Jitter Attenuation PLL
Activity Detector
XTAL_IN
VCCO_LVPECL
622.08 MHz
110 110
CLK_SEL
FemtoClock PLL x32
C0 Divider = 4, 8, 32, or HiZ
111 2
QA nQA QA_SEL1:0 QB nQB
2
111
R_SEL2:0
3
C1 Divider = 4, 8, 32, or HiZ
QB_SEL1:0
NOTE 1: 19.44MHz VCXO crystal shown is typical for SONET/SDH device applications.
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2
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
Description Loop filter connection node pins. Charge pump current setting pin. Core power supply pin. Pulldown Pullup/ Pulldown Pulldown Pullup Pullup Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 bias voltage when left floating. Input clock select. LVCMOS/LVTTL interface levels. See Table 3A. LVPECL output divider control for QA/nQA outputs. See Table 3C. LVPECL output divider control for QB/nQB outputs. See Table 3C. Analog supply pin. Differential clock output pair. LVPECL interface levels. Negative supply pins. Differential clock output pair. LVPECL interface levels. Output power supply pin for QA, nQA and QB, nQB. Power supply pin for LOR0 and LOR1. No connect. Alarm output, loss of reference for CLK1. LVCMOS/LVTTL interface levels. Alarm output, loss of reference for CLK0. LVCMOS/LVTTL interface levels. Pullup/ Inver ting differential clock input. Pulldown VCC/2 bias voltage when left floating. Pulldown Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3 4 5 6 7 9, 10 12, 13 14 15, 16 17, 27 18, 19 20 21 8, 11, 22 23 24 25 Name LF1, LF0 ISET VCC CLK0 nCLK0 CLK_SEL QA_SEL1, QA_SEL0 QB_SEL1, QB_SEL0 VCCA QA, nQA VEE QB, nQB VCCO_LVPECL VCCO_LVCMOS nc LOR1 LOR0 nCLK1 Type Analog Input/Output Analog Input/Output Power Input Input Input Input Input Power Output Power Output Power Power Unused Output Output Input
26 CLK1 Input 28, R_SEL0, R_SEL1, Input Pulldown Input divider selection. LVCMOS/LVTTL interface. See Table 3B. 29, R_SEL2 30 Cr ystal oscillator interface. XTAL_OUT is the output. 31, XTAL_OUT, Input XTAL_IN is the input. 32 XTAL_IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 50 50 Maximum Units pF k k
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3
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
TABLE 3A. INPUT REFERENCE SELECTION FUNCTION TABLE
Inputs CLK_SEL 0 1 Input Selected CLK0 CLK1
TABLE 3B. INPUT REFERENCE DIVIDER SELECTION FUNCTION TABLE
Inputs R_SEL2:0 000 001 010 011 100 101 110 111 R Divider Value or State /1 /2 /4 /8 /16 /32 bypass VCXO PLL bypass VCXO and FemtoClockTM PLL's
TABLE 3C. OUTPUT DIVIDER SELECTION FUNCTION TABLE
Inputs Qx_SEL1:0 00 01 10 11 Output Divider Value or State Output Q and nQ Hi-Z /32 /8 /4
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4
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
4.6V -0.5V to VCC + 0.5V -0.5V to VCCO + 0.5V 50mA 100mA 34.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_LVCMOS, VCCO_LVPECL = 3.3V5% OR 2.5V5%,
TA = -40C TO 85C
Symbol VCC VCCA VCCO_LVCMOS, VCCO_LVPECL IEE ICCA
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current
Test Conditions
Minimum 3.135 3.135 3.135 2.375
Typical 3.3 3.3 3.3 2.5 175 10
Maximum 3.465 3.465 3.465 2.625
Units V V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_LVCMOS = 3.3V5% OR 2.5V5%,
TA = -40C TO 85C
Symbol VIH VIL IIH
Parameter Input High Voltage Input Low Voltage Input High Current CLK_SEL, R_SEL0:2 QA_SEL0:1, QB_SEL0:1 CLK_SEL, R_SEL0:2 QA_SEL0:1, QB_SEL0:1
Test Conditions
Minimum 2 -0.3
Typical
Maximum VCC + 0.3 0.8 15 0 5
Units V V A A A A V V
VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V VCCO_LVCMOS = 3.3V VCCO_LVCMOS = 2.5V VCCO_LVCMOS = 3.3V or 2.5V -5 -150 2.6 1.8
IIL
Input Low Current
VOH VOL
Output High Voltage Output Low Voltage
LOR0, LOR1; NOTE 1 LOR0, LOR1; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50 to VCCO_LVCMOS/2 .See Parameter Measurement Information Section, "Output Load Test Circuit".
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5
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_LVPECL = 3.3V5% OR 2.5V5%,
TA = -40C TO 85C
Symbol IIH
Parameter CLK0, CLK1 Input High Current nCLK0, nCLK1 CLK0, CLK1 Input Low Current nCLK0, nCLK1 Peak-to-Peak Input Voltage
Test Conditions VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V
Minimum
Typical
Maximum 150 150
Units A A A A
-5 -150 0.15 1.3 VCC - 0.85
IIL VPP
V V
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_LVPECL = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol Parameter VOH VOL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 Typical Maximum VCCO - 0.9 VCCO - 1.7 Units V V V
Peak-to-Peak Output Voltage Swing 0.6 1.0 VSWING NOTE 1: Outputs terminated with 50 to VCCO_LVPECL - 2V. See "Parameter Measurement Information" section, "Output Load Test Circuit".
TABLE 5. CRYSTAL CHARACTERISTICS
Symbol fN fT fS CL CO CO/C1 ESR Parameter Nominal Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Mode of Operation Fundamental 0 12 4 220 240 50 1 mW Test Conditions Minimum Typical 19.44 TBD TBD 70 Maximum Units MHz ppm ppm C pF pF
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6
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
Test Conditions 155.52MHz, Integration range: 12kHz - 20MHz 20% to 80% Minimum 19.44 0.81 105 890 Typical Maximum 175 Units MHz ps ps ps %
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 3.3V5%, TA = -40C TO 85C
Symbol Parameter FOUT Output Frequency RMS Phase Jitter, (Random); NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time
tjit(o) tsk(o)
tR / tF
odc Output Duty Cycle 50 See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_LVCMOS, VCCO_LVPECL = 2.5V5%, TA = -40C TO 85C
Symbol Parameter FOUT Output Frequency RMS Phase Jitter, (Random); NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time Test Conditions 155.52 MHz, Integration range: 12kHz - 20MHz 20% to 80% Minimum 19.44 0.83 95 900 Typical Maximum 175 Units MHz ps ps ps %
tjit(o) tsk(o)
tR / tF
odc Output Duty Cycle 50 See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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7
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
TYPICAL PHASE NOISE AT 155.52MHZ
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
Filter
155.52MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 0.81ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding Filter to raw data OFFSET FREQUENCY (HZ)
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8
843002AKI-40
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
2V 2.8V0.04V 2V
Qx
VCC , VCCA, VCCO_LVPECL
SCOPE
VCC , VCCA VCCO_LVPECL
Qx
SCOPE
LVPECL
VEE
nQx
LVPECL
VEE
nQx
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
VCC
nCLK0, nCLK1
Phase Noise Mask
V
nCLK0, nCLK1
PP
Cross Points
V
CMR
f1
V EE
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
tsk(o)
PHASE JITTER
nQA, nQB QA, QB
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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9
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR APPLICATION INFORMATION
DESCRIPTION OF THE PLL STAGES
The ICS843002I-40 is a two stage device, a VCXO PLL followed by a low phase noise FemtoClock PLL. The VCXO uses an external pullable crystal which can be pulled 100ppm by the VCXO PLL circuitry to phase lock it to the input reference frequency. The FemtoClock PLL is a wide bandwidth PLL (about 800kHz) which means it will phase track the VCXO PLL. Most of the reference clock jitter attenuation needs to be accomplished by VCXO PLL. By using the bypass FemtoClock PLL mode (Table 3B), the selected input reference clock can be passed directly to the FemtoClock PLL which will multiply it up by 32 to a higher frequency. A second mode, VCXO and FemtoClock bypass, routes the selected input refrence directly to the LVPECL output dividers.
SETTING THE VCXO PLL LOOP RESPONSE
The VCXO PLL loop response is determined both by fixed device characteristics and by other characteristics set by the user. This includes the values of RS, CS, CP and RSET as shown in the External VCXO PLL Components figure on this page. The VCXO PLL loop bandwidth is approximated by: NBW (VCXO PLL) = RS x ICP x KO 32
WHERE: RS = Value of resistor RS in loop filter in Ohms ICP = Charge pump current in amps (see table on page 12) KO = VCXO Gain in Hz/V The above equation calculates the "normalized" loop bandwidth (denoted as "NBW") which is approximately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the second pole imposed by CP. It does, however, provide a useful approximation of filter performance. To prevent jitter on the clock output due to modulation of the VCXO PLL by the phase detector frequency, the following general rule should be observed: NBW (VCXO PLL) (Phase Detector) 20
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected by the VCXO feedback divider value (bandwidth and damping factor), and by the external loop filter components (bandwidth, damping factor, and 2 nd frequency response). A practical range of VCXO PLL bandwidth is from about 10Hz to about 1kHz. The setting of VCXO PLL bandwidth and damping factor is covered later in this document. A PC based PLL bandwidth calculator is also under development. For assistance with loop bandwidth suggestions or value calculation, please contact ICS applications.
(Phase Detector) = Input Frequency / (R Divider x 32) The PLL loop damping factor is determined by: DF (VCLK) = RS 2 x ICP x CS x KO 32
WHERE: CS = Value of capacitor CS in loop filter in Farads
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10
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
CP establishes a second pole in the VCXO PLL loop filter. For higher damping factors (> 1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. CP also dampens VCXO PLL input voltage modulation by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where input jitter is high, charge pump current is high, and CP is too small, the VCXO PLL input voltage can hit the supply or ground rail resulting in nonlinear loop response. The best way to set the value of CP is to use the filter response software under development from ICS (please refer to the following section). CP should be increased in value until it just starts affecting the passband peak.
EXTERNAL VCXO PLL COMPONENTS
In general, the loop damping factor should be 0.7 or greater to ensure output stability. A higher damping factor will create less peaking in the passband. A higher damping factor may also increase lock time and output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the PLL to respond to and therefore compensate for phase noise ingress.
LF1 LF0 CP RS CS ISET
32 1 2 3
31
RSET
LOOP FILTER RESPONSE SOFTWARE
Online tools to calculate loop filter response (coming soon) at www.icst.com. Contact your local sales representative if a tool cannot be found for this product.
The external crystal devices and loop filter components should be kept close to the device. Loop filter and crystal PCB connection traces should be kept short and well separated from each other and from other signal traces. Other signal traces should not run underneath the device, the loop filter or crystal components.
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown between pins 32 to ground and between pins 31 to ground. These are optional crystal load capacitors which can be used to center tune the external pullable crystal (the crystal frequency can only be lowered by adding capacitance, it cannot be raised). Note that the addition of external load capacitors will decrease the crystal pull range and the Kvco value.
NOTES ON SETTING THE VALUE OF CP
As another general rule, the following relationship should be maintained between components CS and CP in the loop filter: CP = CS 20
LOSS OF REFERENCE INDICATOR (LOR0
AND
LOR1) OUTPUT PINS.
as an "edge"). The LOR output will otherwise be low. The activity monitor does not flag excessive reference transitions in an phase detector observation interval as an error. The monitor only distinguishes between transitions occurring and no transitions occurring.
The LOR0 and LOR1 pins are controlled by the internal clock activity monitor circuits. The clock activity monitor circuits are clocked by the VCXO PLL phase detector feedback clock. The LOR output is asserted high if there are three consecutive feedback clock edges without any reference clock edges (in both cases, either a negative or positive transition is counted
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11
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth and damping factor.
NOTES ON SETTING CHARGE PUMP CURRENT
The recommended range for the charge pump current is 50A to 300A. Below 50A, loop filter charge leakage, due to PCB or capacitor leakage, can become a problem. This loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise.
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
RSET 17.6k 8.8k 4.4k 2.2k Charge Pump Current (ICP) 62.5A 125A 250A 500A
1E-3
ICP, Amps
100E-6
10E-6 1k 10k RSET,
VS.
100k
FIGURE 1. CHARGE PUMP CURRENT
VALUE
OF
RSET (EXTERNAL
RESISTOR)
GRAPH
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12
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
3.3V VCC .01F VCCA .01F 10F 10
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843002I-40 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION
FOR
2.5V LVPECL OUTPUT
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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13
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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14
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
843002AKI-40
BY
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REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
capacitance, this resistor acts as a low pass signal filter. The typical value for this optional series filter resistor is 100. This will lower both the amplitude and edge rate of the clock input signal. In the case of a very short clock trace a series termination resistor may not be needed.
SINGLE ENDED CLOCK INPUT INTERFACE
When using a LVCMOS or LVTTL clock driver, the clock input is connected to the CLKx (CLK0 or CLK1) input pin. The nCLKx (nCLK0 or nCLK1) pin is left unconnected. To help reduce interference with the internal VCO circuits, an external resistor can be placed in series with the clock signal right near the CLKx input pin. Combined with the input pin
Series Termination LVTTL or LVCMOS
Optional Series Filter Resistor
3.3V CLKx nCLKx 50k 50k
3.3V CLK nCLK
(no connection)
50k
Differential Input Stage
External Circuitry
Internal Device Circuitry
FIGURE 6. SINGLE-ENDED CLOCK INPUT INTERFACE
843002AKI-40
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REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I-40. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843002I-40 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 175mA = 606.375mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 606.375mW + 60mW = 666.38mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming an air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 34.8C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.666W * 34.8C/W = 108.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA
FOR
32-PIN VFQFN, FORCED CONVECTION
JA vs. Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W
843002AKI-40
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REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (V
CCO_MAX
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50) * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843002AKI-40
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REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR A
32 LEAD VFQFN
JA vs. Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W
TRANSISTOR COUNT
The transistor count for ICS843002I-40 is: 5536
843002AKI-40
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REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
32 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR A
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL N A A1 A3 b ND NE D D2 E E2 e L 0.30 1.25 1.25 5.00 BASIC 2.25 5.00 BASIC 2.25 0.50 BASIC 0.40 0.50 3.25 3.25 0.18 0.80 0 MINIMUM NOMINAL 32 --0.25 Ref. 0.25 0.30 8 8 1.00 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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20
REV. A JUNE 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002I-40
175MHZ, FEMTOCLOCKSTM VCXO BASED SONET/SDH JITTER ATTENUATOR
Marking ICS43002A40 ICS43002A40 Package 32 Lead VFQFN 32 Lead VFQFN Shipping Packaging tray 2500 tape & reel Temperature -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS843002AKI-40 ICS843002AKI-40T
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843002AKI-40
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REV. A JUNE 22, 2005

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