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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK MULTIPLIER
FEATURES: DESCRIPTION:
IDT2308
* Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency * Distributes one clock input to two banks of four outputs * Separate output enable for each output bank * External feedback (FBK) pin is used to synchronize the outputs to the clock input * Output Skew <200 ps * Low jitter <200 ps cycle-to-cycle * 1x, 2x, 4x output options (see table): - IDT2308-1 1x - IDT2308-2 1x, 2x - IDT2308-3 2x, 4x - IDT2308-4 2x - IDT2308-1H, -2H, and -5H for High Drive * No external RC network required * Operates at 3.3V VDD * Available in SOIC and TSSOP packages
The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT2308 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25A. The IDT2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT2308 is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4) FBK REF 16 1 2 (-5) 2 PLL 3 2 CLKA1
CLKA2
14 CLKA3 15 CLKA4
S2 S1
8 9 Control Logic (-2, -3) 2 6 CLKB1 7
CLKB2
10 CLKB3 11 CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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1
c 2003 Integrated Device Technology, Inc.
APRIL 2003
DSC 5173/6
IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD Rating Supply Voltage Range Input Voltage Range (REF) Input Voltage Range (except REF) IIK (VI < 0) IOK (VO < 0 or VO > VDD) IO (VO = 0 to VDD) VDD or GND TA = 55C (in still air)(3) TSTG Operating Storage Temperature Range Commercial Temperature Range Industrial Temperature Range -40 to +85 C -65 to +150 0 to +70 C C Continuous Current Maximum Power Dissipation 100 0.7 mA W Input Clamp Current Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) Continuous Output Current 50 mA Max. -0.5 to +4.6 -0.5 to +5.5 -0.5 to VDD+0.5 -50 50 mA mA Unit V V V VI (2) VI
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
SOIC/ TSSOP TOP VIEW
Temperature Operating Temperature
PIN DESCRIPTION
Pin Number REF
(1)
Functional Description Input Reference Clock, 5 Volt Tolerant Input Clock Output for Bank A Clock Output for Bank A 3.3V Supply Ground Clock Output for Bank B Clock Output for Bank B Select Input, Bit 2 Select Input, Bit 1 Clock Output for Bank B Clock Output for Bank B Ground 3.3V Supply Clock Output for Bank A Clock Output for Bank A PLL Feedback Input
1 2 3 4 5
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
CLKA1(2) CLKA2 VDD GND CLKB1 S2(3) S1(3) CLKB3 CLKB4 GND VDD CLKA3(2) CLKA4(2) FBK
(2) (2) (2) (2)
6 7 8 9 10 11 12 13 14 15 16
CLKB2(2)
APPLICATIONS:
* * * * *
SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs
NOTES: 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs.
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
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FUNCTION TABLE(1) SELECT INPUT DECODING
S2 L L H H
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level
S1 L H L H
CLK A Tri-State Driven Driven Driven
CLK B Tri-State Tri-State Driven Driven
Output Source PLL PLL REF PLL
PLL Shut Down Y N Y N
AVAILABLE OPTIONS FOR IDT2308
Device IDT2308-1 IDT2308-1H IDT2308-2 IDT2308-2 IDT2308-2H IDT2308-2H IDT2308-3 IDT2308-3 IDT2308-4 IDT2308-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 x Reference Reference 2 x Reference 2 x Reference 4 x Reference 2 x Reference Reference/2 Bank B Frequency Reference Reference Reference/2 Reference Reference/2 Reference Reference or Reference(1) 2 x Reference 2 x Reference Reference/2
NOTE: 1. Output phase is indeterminant (0 or 180 from input clock).
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
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ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT2308, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the Output Load Difference Chart to calculate loading differences between the feedback output and remaining outputs. Ensure the outputs are loaded equally, for zero output-output skew.
REF TO CLKA/CLKB DELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS
1500
1000
REF to CLKA/CLKB Delay (ps)
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS ( pF)
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
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OPERATING CONDITIONS- COMMERCIAL
Symbol VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance below 100MHz Load Capacitance from 100MHz to 133MHz Input Capacitance
(1)
Parameter
Test Conditions
Min. 3 0 -- -- --
Max. 3.6 70 30 15 7
Unit V
C
pF pF pF
NOTE: 1. Applies to both REF and FBK.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Current VIN = 0V VIN = VDD IOL = 8mA (-1, -2, -3, -4) IOL = 12mA (-1H, -2H, -5H) IOH = -8mA (-1, -2, -3, -4) IOH = -12mA (-1H, -2H, -5H) REF = 0MHz (S2 = S1 = H) 100MHz CLKA (-1, -2, -3, -4) 100MHz CLKA (-1H, -2H, -5H) IDD Supply Current Unloaded Outputs Select Inputs at VDD or GND 66MHz CLKA (-1, -2, -3, -4) 66MHz CLKA (-1H, -2H, -5H) 33MHz CLKA (-1, -2, -3, -4) 33MHz CLKA (-1H, -2H, -5H) -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12 45 70 32 50 18 30 mA A 2.4 -- -- V Conditions Min. -- 2 -- -- -- Typ.(1) -- -- -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V A A V
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
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SWITCHING CHARACTERISTICS - COMMERCIAL
Symbol t1 t1 t1 Parameter Output Frequency Output Frequency Output Frequency Duty Cycle = t2 / t1 (-1, -2, -3, -4, -1H, -2H, -5H) Duty Cycle = t2 / t1 (-1, -2, -3, -4, -1H, -2H, -5H) t3 t3 t3 t4 t4 t4 t5 Rise Time (-1, -2, -3, -4) Rise Time (-1, -2, -3, -4) Rise Time (-1H, -2H, -5H) Fall Time (-1, -2, -3, -4) Fall Time (-1, -2, -3, -4) Fall Time (-1H, -5H) Output to Output Skew on same Bank (-1, -2, -3, -4) Output to Output Skew (-1H, -2H, -5H) Output Bank A to Output Bank B (-1, -4, -2H, -5H) Output Bank A to Output Bank B Skew (-2, -3) t6 t7 t8 tJ Delay, REF Rising Edge to FBK Rising Edge Device to Device Skew Output Slew Rate Cycle to Cycle Jitter (-1, -1H, -4, -5H)
tJ
Conditions 30pF Load, all devices 20pF Load, -1H, -2H, -5H Devices(1) 15pF Load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT = 66.66MHz 30pF Load Measured at 1.4V, FOUT = 50MHz 15pF Load Measured between 0.8V and 2V, 30pF Load Measured between 0.8V and 2V, 15pF Load Measured between 0.8V and 2V, 30pF Load Measured between 0.8V and 2V, 30pF Load Measured between 0.8V and 2V, 15pF Load Measured between 0.8V and 2V, 30pF Load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2V on -1H, -2H, -5H device using Test Circuit 2 Measured at 66.67 MHz, loaded outputs, 15pF Load Measured at 66.67 MHz, loaded outputs, 30pF Load Measured at 133.3 MHz, loaded outputs, 15pF Load Measured at 66.67 MHz, loaded outputs, 30pF Load Measured at 66.67 MHz, loaded outputs, 15pF Load Stable Power Supply, valid clocks presented on REF and FBK pins
Min. 10 10 10 40 45 -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- --
Typ. -- -- -- 50 50 -- -- -- -- -- -- -- -- -- -- 0 0 -- -- -- -- -- -- --
Max. 100 133.3 133.3 60 55 2.2 1.5 1.5 2.2 1.5 1.25 200 200 200 400 250 700 -- 200 200 100 400 400 1
Unit MHz MHz MHz % % ns ns ns ns ns ns ps ps ps ps ps ps V/ns
ps ps ms
Cycle to Cycle Jitter (-2, -2H, -3) PLL Lock Time
tLOCK
NOTE: 1. IDT2308-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67MHz.
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS- INDUSTRIAL
Symbol VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance below 100MHz Load Capacitance from 100MHz to 133MHz Input Capacitance
(1)
Parameter
Test Conditions
Min. 3 -40 -- -- --
Max. 3.6 +85 30 15 7
Unit V
C
pF pF pF
NOTE: 1. Applies to both REF and FBK.
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Current VIN = 0V VIN = VDD IOL = 8mA (-1, -2, -3, -4) IOL = 12mA (-1H, -2H, -5H) IOH = -8mA (-1, -2, -3, -4) IOH = -12mA (-1H, -2H, -5H) REF = 0MHz (S2 = S1 = H) 100MHz CLKA (-1, -2, -3, -4) 100MHz CLKA (-1H, -2H, -5H) IDD Supply Current Unloaded Outputs Select Inputs at VDD or GND 66MHz CLKA (-1, -2, -3, -4) 66MHz CLKA (-1H, -2H, -5H) 33MHz CLKA (-1, -2, -3, -4) 33MHz CLKA (-1H, -2H, -5H) -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25 45 70 32 50 18 30 mA A 2.4 -- -- V Conditions Min. -- 2 -- -- -- Typ.(1) -- -- -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V A A V
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS - INDUSTRIAL
Symbol t1 t1 t1 Parameter Output Frequency Output Frequency Output Frequency Duty Cycle = t2 / t1 (-1, -2, -3, -4, -1H, -2H, -5H) Duty Cycle = t2 / t1 (-1, -2, -3, -4, -1H, -2H, -5H) t3 t3 t3 t4 t4 t4 t5 Rise Time (-1, -2, -3, -4) Rise Time (-1, -2, -3, -4) Rise Time (-1H, -2H, -5H) Fall Time (-1, -2, -3, -4) Fall Time (-1, -2, -3, -4) Fall Time (-1H, -5H) Output to Output Skew on same Bank (-1, -2, -3, -4) Output to Output Skew (-1H, -2H, -5H) Output Bank A to Output Bank B (-1, -4, -2H, -5H) Output Bank A to Output Bank B Skew (-2, -3) t6 t7 t8 tJ Delay, REF Rising Edge to FBK Rising Edge Device to Device Skew Output Slew Rate Cycle to Cycle Jitter (-1, -1H, -4, -5H)
tJ
Conditions 30pF Load, all devices 20pF Load, -1H, -2H, -5H Devices 15pF Load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT = 66.66MHz 30pF Load Measured at 1.4V, FOUT = 50MHz 15pF Load Measured between 0.8V and 2V, 30pF Load Measured between 0.8V and 2V, 15pF Load Measured between 0.8V and 2V, 30pF Load Measured between 0.8V and 2V, 30pF Load Measured between 0.8V and 2V, 15pF Load Measured between 0.8V and 2V, 30pF Load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2V on -1H, -2H, -5H device using Test Circuit 2 Measured at 66.67 MHz, loaded outputs, 15pF Load Measured at 66.67 MHz, loaded outputs, 30pF Load Measured at 133.3 MHz, loaded outputs, 15pF Load Measured at 66.67 MHz, loaded outputs, 30pF Load Measured at 66.67 MHz, loaded outputs, 15pF Load Stable Power Supply, valid clocks presented on REF and FBK pins
(1)
Min. 10 10 10 40 45 1
Typ. 50 50 0 0
Max. 100 133.3 133.3 60 55 2.2 1.5 1.5 2.5 1.5 1.25 200 200 200 400 250 700 200 200 100 400 400 1
Unit MHz MHz MHz % % ns ns ns ns ns ns ps ps ps ps ps ps V/ns
ps ps ms
Cycle to Cycle Jitter (-2, -2H, -3) PLL Lock Time
tLOCK
NOTE: 1. IDT2308-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67MHz.
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING WAVEFORMS
t1 t2 1.4V 1.4V 1.4V
Duty Cycle Timing
Output
0.8V t3
2V
2V
0.8V t4
3.3V 0V
All Outputs Rise/Fall Time
Output
1.4V
Output t5
1.4V
Output to Output Skew
VDD/2 Input FBK t6
Input to Output Propagation Delay
VDD/2
VDD/2 FBK, Device 1 FBK, Device 2 t7
Device to Device Skew
VDD/2
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2308-1, 2, 3, AND 4
Duty Cycle vs VDD (for 30pf loads over frequency - 3.3V, 25C) 60 58 56
Duty Cycle (%) Duty Cycle (%)
Duty Cycle vs VDD (for 15pF loads over frequency - 3.3V, 25C) 60 58 56 54 52 50 48 46 44 42 40
33MHz 66MHz 100MHz 133MHz
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 3.4 3.5 3.6
33MHz 66MHz 100MHz
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
Duty Cycle vs Frequency (for 30pf loads over temperature - 3.3V) 60 58 56
Duty Cycle (%)
VDD (V)
Duty Cycle vs Frequency (for 15pF loads over temperature - 3.3V) 60 58 56
Duty Cycle (%)
54 52 50 48 46 44 42 40 20 40 60 80 100 120 140
-40C 0C 25C 70C 85C
54 52 50 48 46 44 42 40 20 40 60 80 100 120 140
-40C 0C 25C 70C 85C
Frequency (MHz)
IDD vs Number of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) 140 120 100 80 60 40 20 0 0 2 4 6 8 140 120 100 80 60 40 20 0 0 2
Frequency (MHz)
IDD vs Number of Loaded Outputs (for 15pF loads over frequency - 3.3V, 25C)
IDD (mA)
33MHz 66MHz 100MHz
IDD (mA)
33MHz 66MHz 100MHz
4
6
8
Number of Loaded Outputs
Number of Loaded Outputs
NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the Unloaded Current (n = Number of Outputs; C = Capacitance Load per Output (F); V = Voltage Supply(V); f = Frequency (Hz).
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2308-1H, -2H, AND -5H
Duty Cycle vs VDD (for 30pf loads over frequency - 3.3V, 25C) 60 58 56
Duty Cycle (%) Duty Cycle (%)
Duty Cycle vs VDD (for 15pF loads over frequency - 3.3V, 25C) 60 58 56 54 52 50 48 46 44 42 40
33MHz 66MHz 100MHz 133MHz
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 3.4 3.5 3.6
33MHz 66MHz 100MHz
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
Duty Cycle vs Frequency (for 30pf loads over temperature - 3.3V) 60 58 56
Duty Cycle (%)
VDD (V)
Duty Cycle vs Frequency (for 15pF loads over temperature - 3.3V) 60 58 56
Duty Cycle (%)
54 52 50 48 46 44 42 40 20 40 60 80 100 120 140
-40C 0C 25C 70C 85C
54 52 50 48 46 44 42 40 20 40 60 80 100 120 140
-40C 0C 25C 70C 85C
Frequency (MHz)
IDD vs Number of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) 160 140 120 100
IDD (mA) IDD (mA)
Frequency (MHz)
IDD vs Number of Loaded Outputs (for 15pF loads over frequency - 3.3V, 25C) 160 140 120 100 80 60 40 20 0
80 60 40 20 0 0 2 4 6 8
33MHz 66MHz 100MHz
33MHz 66MHz 100MHz
0
2
4
6
8
NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the Unloaded Current (n = Number of Outputs; C = Capacitance Load per Output (F); V = Voltage Supply(V); f = Frequency (Hz).
Number of Loaded Outputs
Number of Loaded Outputs
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS
TEST CIRCUIT 1
TEST CIRCUIT 1
VDD 0.1F OUTPUTS
VDD CLKOUT CLOAD 0.1F OUTPUTS
1K
CLKOUT 10pF
1K VDD 0.1F
VDD 0.1F GND GND
GND
GND
Test Circuit for all Parameters Except t8
Test Circuit for t8, Output Slew Rate On -1H, -2H, and -5H Device
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process Blank I DC PG 2308-1 2308-2 2308-3 2308-4 2308-1H 2308-2H 2308-5H Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Small Outline Thin Shrink Small Outline Package
} }
Zero Delay Clock Buffer With Standard Drive
Zero Delay Clock Buffer with High Drive
Ordering Code IDT2308-1DC IDT2308-1DCI IDT2308-1HDC IDT2308-1HDCI IDT2308-1HPG IDT2308-1HPGI IDT2308-2DC IDT2308-2DCI IDT2308-2HDC IDT2308-2HDCI IDT2308-3DC IDT2308-3DCI IDT2308-4DC IDT2308-4DCI IDT2308-5HDC IDT2308-5HDCI IDT2308-5HPG IDT2308-5HPGI 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin TSSOP 16-Pin TSSOP 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin TSSOP 16-Pin TSSOP
Package Type Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Operating Range
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 13
for Tech Support: logichelp@idt.com (408) 654-6459

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