View GF9331_301310.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

GF9331 HDTV/SDTV Motion Co-processor
GF9331 Data Sheet Features
* * * * * * * * * * * support for 10/8-bit HDTV/SDTV input video signals seamless interface to Gennum's GF9330 high performance de-interlacer through a filter control bus multi-directional edge detection and control support for multiplexed and non-multiplexed Y/C video 3-field vertical motion detection and control fully configurable to support custom video modes ability to extract HVF information from embedded TRS seamless interface to popular ADCs and NTSC/PAL decoders user configuration through a dedicated host interface, supporting parallel and serial interfaces 5V tolerant inputs 3.3V supply for device I/O and 2.5V for core logic
Device Overview The GF9331 is a high performance motion co-processor that is used in conjunction with Gennum's GF9330 HDTV/SDTV 10-bit De-interlacer. Together, the GF9331 and the GF9330 provide 10-bit broadcast quality de-interlacing for standard and high-definition video signals up to 1080p60. Although the GF9330 can fully function as a stand alone de-interlacer, the GF9331 provides added features in the form of a filter selection control bus that enables multi-directional edge and adaptive 3-field vertical motion detection. Edge detection and interpolation removes the edge artifacts that tend to occur while de-interlacing on shallow horizontal edges while vertical motion detection reduces motion artifacts. Filter selection controls are sent to the GF9330 on a pixel-by-pixel basis. The GF9331 integrates all the necessary line delays for the motion and edge detectors. The GF9331 also provides seamless interfaces to off-chip SDRAMs that form the required field delays. Ordering Information
Part Number
GF9331-CBP
Applications
* * * * * * * * HDTV Up/Down Converters Production Equipment Video Walls Projection Systems Plasma Displays LCD TVs Home Theatre Systems HD DVD Players
Package
328 PIN BGA
Temp. Range
0oC to 70oC
Edge Detection
Y/C
Encoder
Control bus to GF9330
Pre-filter
Vertical Motion Detection
Delay
Y/C Delayed Video to GF9330
External Memory Interface
Block Diagram
Proprietary and Confidential
18303 - 4
June 2004
1 of 31 www.gennum.com
GF9331 Data Sheet
Contents
Features ........................................................................................................................1 Applications...................................................................................................................1 Device Overview ...........................................................................................................1 Ordering Information .....................................................................................................1 1. Pin Descriptions ........................................................................................................3 2. Electrical Characteristics ...........................................................................................7 2.1 5V Tolerant Inputs ...........................................................................................7 2.2 ESD Tolerance ................................................................................................7 2.3 3.3V Supply for Device I/0 and 2.5V for Core Logic .......................................7 3. Detailed Device Description ....................................................................................10 3.1 Input Data Formats .......................................................................................10 3.2 Input Synchronization ...................................................................................12 3.2.1 Support for Both 8-bit and 10-bit Input Data ........................................12 3.2.2 Generic Input Format Signalling ..........................................................12 3.3 Seamless Interface to the GF9330 High Performance De-Interlacer for Directional Filter Control ...............................................................................15 3.4 Seamless Interface to External SDRAMs .....................................................16 3.5 Host Interface ................................................................................................16 3.5.1 Host Interface Serial Mode ..................................................................17 3.5.2 Host Interface Parallel Mode ...............................................................20 3.5.3 Control Register Definitions .................................................................23 3.6 Closed Captioning .........................................................................................25 3.7 RESET ..........................................................................................................25 3.8 Modes of Operation ......................................................................................25 3.8.1 Motion Processing Mode (MODE=1) ...................................................26 3.8.2 Disabled Mode (MODE=0)...................................................................26 3.9 Processing of Input Formats .........................................................................26 3.10 Vertical Motion Detection ............................................................................28 3.10.1 Vertical Motion Feature Control .........................................................28 3.11 Edge Direction Detection ............................................................................28 3.11.1 Edge Direction Detection Feature Control .........................................29 3.12 Video Output ...............................................................................................29 3.13 Processing Latency .....................................................................................29 4. Package Dimensions ..............................................................................................30 5. Revision History ......................................................................................................31
Proprietary and Confidential
18303 - 4
June 2004
2 of 31
GF9331 Data Sheet
1. Pin Descriptions
1
RESET
2
NC
3
S2_DAT0
4
S2_DAT2
5
S2_DAT4
6
S2_DAT7
7
S2_DAT10
8
S2_DAT13
9
S2_CLK
10 11 12 13 14 15 16 17 18 19 20
S2_ADDR2 S2_ADDR7 S2_ADDR10 S2_ADDR13 S2_CS S2_WE NC NC NC NC Y_OUT9
A
Y_IN9 NC S2_DAT1 S2_DAT3 S2_DAT5 S2_DAT8 S2_DAT11 S2_DAT14 S2_ADDR0 S2_ADDR3 S2_ADDR6 S2_ADDR9 S2_ADDR12 S2_CAS S2_RAS NC NC NC NC Y_OUT8
B
Y_IN8 Y_IN7 Y_IN6 NC S2_DAT6 S2_DAT9 S2_DAT12 S2_DAT15 S2_ADDR1 S2_ADDR4 S2_ADDR5 S2_ADDR8 S2_ADDR11 NC NC NC NC NC Y_OUT6 Y_OUT7
C
Y_IN5 Y_IN4 Y_IN3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC Y_OUT3 Y_OUT4 Y_OUT5
D
Y_IN2 Y_IN1 Y_IN0 HOST_EN GND VDD_INT VDD_IO NC GND VDD_IO GND VDD_INT NC GND VDD_IO GND NC Y_OUT0 Y_OUT1 Y_OUT2
E
VCLK_IN NC MODE NC VDD_CLKD VDD_INT VDD_IO GND VDD_IO VDD_INT NC NC NC NC
F
SER_MD STD4 STD3 STD2 VSS_CLKD VDD_INT
G
MEMCLK_IN STD1 STD0 GND GND GND
H
GND NC C_IN9 C_IN8 VDD_IO
TOP VIEW GF9331 PIN OUT 328 BGA
TGND TGND TGND TGND
GND
VDD_INT
NC
NC
NC
NC
GND
NC
NC
NC
C_OUT9
VDD_IO
NC
C_OUT6
C_OUT7
C_OUT8
J
C_IN7 C_IN6 C_IN5 C_IN4 GND TGND TGND TGND TGND GND NC C_OUT3 C_OUT4 C_OUT5
K
C_IN0 C_IN1 C_IN2 C_IN3 VDD_INT TGND TGND TGND TGND GND NC C_OUT2 C_OUT1 C_OUT0
L
ED_MODE VM_MODE NC NC GND TGND TGND TGND TGND VDD_IO NC NC FIL_SEL3 FIL_SEL2
M
FVH_EN F_IN V_IN H_IN VDD_IO GND NC NC FIL_SEL1 FIL_SEL0
N
A_D CS R_W NC GND GND GND VDD_INT NC NC NC H_OUT
P
DAT_IO4 DAT_IO5 DAT_IO6 DAT_IO7 NC VDD_INT VDD_IO VDD_IO VDD_INT NC NC NC V_OUT
R
DAT_IO0 DAT_IO1 DAT_IO2 DAT_IO3 GND VDD_INT VDD_IO NC GND VDD_IO GND VDD_INT NC GND VDD_IO GND NC NC NC F_OUT
T
TCLK TMS TDI GND NC NC NC NC NC NC NC NC NC NC NC NC NC GND GND GND
U
GND GND NC NC NC S1_ADDR11 S1_ADDR8 S1_ADDR5 S1_ADDR2 S1_ADDR0 S1_DAT15 S1_DAT12 S1_DAT9 S1_DAT6 S1_DAT3 NC NC NC NC NC
V
TDO NC NC S1_RAS S1_CAS S1_ADDR12 S1_ADDR9 S1_ADDR6 S1_ADDR3 S1_ADDR1 S1_DAT14 S1_DAT11 S1_DAT8 S1_DAT5 S1_DAT2 NC NC NC NC NC
W
NC NC NC S1_WE S1_CS S1_ADDR13 S1_ADDR10 S1_ADDR7 S1_ADDR4 S1_CLK S1_DAT13 S1_DAT10 S1_DAT7 S1_DAT4 S1_DAT1 S1_DAT0 NC NC NC NC
Y
GND/TGND: 0V VDD_IO: +3.3V VDD_INT: +2.5V NC: No Connection
Figure 1-1: Top View Pin Out (328-pin BGA)
Proprietary and Confidential
18303 - 4
June 2004
3 of 31
GF9331 Data Sheet
Table 1-1: Pin Descriptions Symbol
RESET VCLK_IN
Pin Grid
A1 F1
Type
I I
Description
Active low, asynchronous RESET. Resets all internal logic to default conditions. Should be applied on power up. Video input clock. When the input is SDTV the input clock will be 27, 36, 54 or 72MHz. When the input format is HDTV, the input clock will be 74.25 or 74.25/1.001MHz. Memory clock for SDRAM operation when VLCK_IN > 36MHz. 90MHz input (supplied by an off-chip crystal oscillator). 8/10-bit input data bus for separate luminance or multiplexed luminance and colour difference video data. When supplying 8-bit data to the GF9331, Y_IN[1:0] will be set LOW and the 8-bit data supplied to Y_IN[9:2]. 8/10-bit input data bus for colour difference video data. When supplying 8-bit data to the GF9331, C_IN[1:0] will be set LOW and the 8-bit data supplied to C_IN[9:2]. Video timing control. F_IN identifies the ODD and EVEN fields in the incoming video signal. F_IN will be LOW in Field 1 and HIGH in Field 2. Video timing control. V_IN represents the vertical blanking signal associated with the incoming video signal. V_IN is HIGH during the vertical blanking interval and LOW during active video. Video timing control. H_IN represents the horizontal blanking signal associated with the incoming video signal. H_IN is HIGH during horizontal blanking and LOW during active video. Control signal input. When HIGH, the F_IN, V_IN, and H_IN input pins will be used for video data signalling. When LOW, embedded TRS's will be detected for video data signalling. Control signal input. When HIGH, the vertical motion detection is enabled. Control signal input. When HIGH, the edge direction detection is enabled. Video format definition. Defines the video standard when operating without the host interface. See Table 3-1: Encoding of STD[4:0] for Selecting Input Data Format. STD[4:0] is read into the device on a falling transition of HOST_EN or after a RESET. Operating mode selection. When HIGH, the GF9331 motion co-processing is enabled. When LOW, the GF9331 motion co-processing is bypassed. See Modes of Operation. MODE is read into the device on a falling transition of HOST_EN or after a RESET. Host interface enable. When set HIGH, the GF9331 is configured through the host interface. When set LOW, the GF9331 is manually configured via input pins. These values are loaded in on the falling transition of HOST_EN. Host interface mode selection. Enables serial mode operation when HIGH. Enables parallel mode operation when LOW. Functions as an active low chip select input for host interface parallel mode operation. Functions as a serial clock input for host interface serial mode operation. Host interface bi-directional data bus for parallel mode. In serial mode, DAT_IO[7] serves as the serial data output pin and DAT_IO[0] serves as the serial data input pin.
MEMCLK_IN Y_IN[9:0]
H1 B1, C1, C2, C3, D1, D2, D3, E1, E2, E3 J3, J4, K1, K2, K3, K4, L4, L3, L2, L1 N2 N3
I I
C_IN[9:0]
I
F_IN V_IN
I I
H_IN
N4
I
FVH_EN
N1
I
VM_MODE ED_MODE STD[4:0]
M2 M1 G2, G3, G4, H2, H3
I I I
MODE
F3
I
HOST_EN
E4
I
SER_MD CS
G1 P2
I I
DAT_IO[7:0]
R4, R3, R2, R1, T4, T3, T2, T1
I/O
Proprietary and Confidential
18303 - 4
June 2004
4 of 31
GF9331 Data Sheet
Table 1-1: Pin Descriptions (Continued) Symbol
R_W A_D
Pin Grid
P3 P1
Type
I I
Description
Host interface Read/Write control for parallel mode. A read cycle is defined when HIGH, a write cycle is defined when LOW. Host interface Address/Data control for parallel mode. The data bus contains an address when HIGH, a data word when LOW. In serial mode, this pin serves as the chip select (active low). Output data bus for separate luminance or multiplexed luminance and colour difference video data. Output data bus for colour difference video data. Filter selection control bus output to the GF9330. The FIL_SEL[3:0] bus is used to switch the GF9330's internal directional filters on a pixel by pixel basis. Output control signal. H_OUT is a horizontal blanking output. Output control signal. F_OUT is an ODD/EVEN field indicator. Output control signal. V_OUT is a vertical blanking output. SDRAM bank 1 clock. Active low SDRAM chip select for Field Buffer 1. Active low SDRAM row address strobe for Field Buffer 1. Active low SDRAM column address strobe for Field Buffer 1. Active low SDRAM write enable for Field Buffer 1. SDRAM address for Field Buffer 1.
Y_OUT[9:0] C_OUT[9:0] FIL_SEL[3:0] H_OUT F_OUT V_OUT S1_CLK S1_CS S1_RAS S1_CAS S1_WE S1_ADDR[13:0]
A20, B20, C20, C19, D20, D19, D18, E20, E19, E18 H20, J20, J19, J18, K20, K19, K18, L18, L19, L20 M19, M20, N19, N20 P20 T20 R20 Y10 Y5 W4 W5 Y4 Y6, W6, V6, Y7, W7, V7, Y8, W8, V8, Y9, W9, V9, W10, V10 V11, W11, Y11, V12, W12, Y12, V13, W13, Y13, V14, W14, Y14, V15, W15, Y15, Y16 A9 A14 B15 B14 A15 A13, B13, C13, A12, B12, C12, A11, B11, C11, C10, B10, A10, C9, B9 C8, B8, A8, C7, B7, A7, C6, B6, A6, C5, B5, A5, B4, A4, B3, A3 U3 U2
O O O O O O O O O O O O
S1_DAT[15:0]
I/O
SDRAM data for Field Buffer 1.
S2_CLK S2_CS S2_RAS S2_CAS S2_WE S2_ADDR[13:0]
O O O O O O
SDRAM bank 2 clock. Active low SDRAM chip select for Field Buffer 2. Active low SDRAM row address strobe for Field Buffer 2. Active low SDRAM column address strobe for Field Buffer 2. Active low SDRAM write enable for Field Buffer 2. SDRAM address for Field Buffer 2.
S2_DAT[15:0]
I/O
SDRAM data for Field Buffer 2.
TDI TMS
I I
JTAG data input; connect to GND if not used. JTAG mode select; connect to GND if not used.
Proprietary and Confidential
18303 - 4
June 2004
5 of 31
GF9331 Data Sheet
Table 1-1: Pin Descriptions (Continued) Symbol
TCLK TDO VDD_CLKD VSS_CLKD VDD_IO
Pin Grid
U1 W1 F5 G5 E7, E10, E15, F7, F15, J5, J16, M16, N5, R7, R15 T7 T10, T15 E6, E12, F6, F16, G6, G16, L5, P16, R6, R16, T6, T12 E5, E9, E11, E14, E16, F14, G15, H4, H5, H6, H16, J1, J9, J10, J11, J12, K5, K9, K10, K11, K12, K16, L9, L10, L11, L12, L16, M5, M9, M10, M11, M12, N16, P5, P6, P15, T5, T9, T11, T14, T16, U4, U18, U19, U20, V1, V2 A2, A16, A17, A18, A19, B2, B16, B17, B18, B19, C4, C14, C15, C16, C17, C18, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, E8, E13, E17, F2, F4, F17, F18, F19, F20, G17, G18, G19, G20, H17, H18, H19, J2, J17, K17, L17, M3, M4, M17, M18, N17, N18, P4, P17, P18, P19, R5, R17, R18, R19, T8, T13, T17, T18, T19, U5, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, U16, U17, V3, V4, V5, V16, V17, V18, V19, V20, W2, W3, W16, W17, W18, W19, W20, Y1, Y2, Y3, Y17, Y18, Y19, Y20
Type
I O NA NA NA
Description
JTAG test clock; connect to GND if not used. JTAG data output. 2.5 V supply for the internal clock doubler. Ground connection for the internal clock doubler. 3.3 V supply.
VDD_INT
NA
2.5 V supply.
GND / TGND
NA
Device ground / Thermal ground (electrically equivalent).
NC
NA
No connection.
Proprietary and Confidential
18303 - 4
June 2004
6 of 31
GF9331 Data Sheet
2. Electrical Characteristics
2.1 5V Tolerant Inputs
Input cells used in the design are able to withstand 3.3V or 5V CMOS input signals, as well as TTL compatible inputs without degrading performance or long-term reliability.
2.2 ESD Tolerance
The GF9331 has 2kV ESD protection. ESD testing is done in accordance with Gennum's standard ESD testing procedure.
2.3 3.3V Supply for Device I/0 and 2.5V for Core Logic
The GF9331 operates from a single +3.3V supply for device I/O and a single +2.5V supply for core logic.
Table 2-1: Absolute Maximum Ratings Parameter
Device I/O Supply Voltage Device Core Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering 10 seconds) TA TS 0oC < TA < 70oC -40oC < TS < 125oC 260oC
Symbol
VDDIO VDDCORE VIN
Value
-0.5 to TBD V -0.5 to TBD V -0.5 < VIN < +4.6V
Table 2-2: DC Electrical Characteristics VDDIO = 3.0 to 3.6V, VDDCORE = 2.25 to 2.75V, TA = 0 to 70oC, unless otherwise shown. Parameter
Device I/O Supply Voltage Device Core Supply Voltage Device I/O Supply Current Device Core Supply Current Input Leakage Current VDDIO=3.3V VDDCORE=2.5V IIN=0V or IIN=VDD
Conditions
Symbol
VDDIO VDDCORE IDDIO IDDCORE ILEAK
Min
+3.0 +2.25 -
Typ
+3.3 +2.5 43 456 -
Max
+3.6 +2.75 10
Units
V V mA mA A
Notes
a a a a a
Proprietary and Confidential
18303 - 4
June 2004
7 of 31
GF9331 Data Sheet
Table 2-2: DC Electrical Characteristics (Continued) VDDIO = 3.0 to 3.6V, VDDCORE = 2.25 to 2.75V, TA = 0 to 70oC, unless otherwise shown. Parameter
Tristate Leakage Current Input Logic LOW Voltage Input Logic HIGH Voltage Output Logic LOW Voltage Output Logic HIGH Voltage IOL= 4mA IOH= -4mA
Conditions
Symbol
ITRILEAK VIL VIH VOL VOH
Min
2.1 2.7
Typ
0.2 -
Max
10 0.8 0.4 -
Units
A V V V V
Notes
a a a a a
a. Production, test and QA are performed at room temperature.
Table 2-3: AC Electrical Characteristics - SDRAM Interfaces The SDRAM 1 Interface signals include S1_CLK, S1_CS, S1_RAS, S1_CAS, S1_WE, S1_ADDR[13:0] and S1_DAT[15:0]. The SDRAM 2 Interface signals include S2_CLK, S2_CS, S2_RAS, S2_CAS, S2_WE, S2_ADDR[13:0] and S2_DAT[15:0]. VDDIO = 3.0 to 3.6V, VDDCORE = 2.25 to 2.75V, TA = 0 to 70oC, unless otherwise shown. Parameter
Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Delay Time VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load tOD_SD
Conditions
Symbol
FHSCI_SD tSU_SD tIH_SD
Min
2.0 2.5 40 -
Typ
85 -
Max
90 60 9.1
Units
MHz ns ns % ns
Notes
a ab
,
a, b a a
Output Data Hold Time
tOH_SD
2.0
-
-
ns
a
Output Enable Time
tOEN_SD
-
-
20
ns
ac
,
Output Disable Time
tODIS_SD
-
-
20
ns
a, c
Output Data Rise/Fall Time
tODRF_SD
-
-
2.0
ns
ad
,
a.Based on simulation results, verified during device characterization process. b.50% levels. c.Two clock cycles allocated for data bus turnaround. d.20% to 80% levels.
Proprietary and Confidential
18303 - 4
June 2004
8 of 31
GF9331 Data Sheet
Table 2-4: AC Electrical Characteristics - Host Interfaces The Host Interface signals include HOST_EN, SER_MD, CS, DAT_IO[7:0], R_W and A_D. VDDIO = 3.0 to 3.6V, VDDCORE = 2.25 to 2.75V, TA = 0 to 70oC, unless otherwise shown. Parameter
Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Delay Time VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load tOD_HI
Conditions
Symbol
FHSCI_HI tSU_HI tIH_HI
Min
5 1.5 40 -
Typ
-
Max
20 60 10.0
Units
MHz ns ns % ns
Notes
a ab
,
a, b a a
Output Data Hold Time
tOH_HI
2.0
-
-
ns
a
Output Enable Time
tOEN_HI
-
-
15
ns
a
Output Disable Time
tODIS_HI
-
-
15
ns
a
Output Data Rise/Fall Time
tODRF_HI
-
-
2.0
ns
a, c
a.Based on simulation results, verified during device characterization process. b.50% levels. c.20% to 80% levels.
Proprietary and Confidential
18303 - 4
June 2004
9 of 31
GF9331 Data Sheet
3. Detailed Device Description
3.1 Input Data Formats
The GF9331 supports multiple input data formats with multiplexed or separate Y/C channels. Data is supplied to the GF9331 through the Y_IN[9:0] and the C_IN[9:0] busses. Table 3-1: Encoding of STD[4:0] for Selecting Input Data Format outlines the data formats that the GF9331 supports according to the setting of STD[4:0] pins or host interface bits, STD[4:0]. NOTE: For all progressive video standards the GF9331 must be manually set to bypass mode (MODE=0, pin or register). See Host Interface for host interface details.
Table 3-1: Encoding of STD[4:0] for Selecting Input Data Format STD
0
STD[4:0]
00000
Description
525i (30/1.001) component SMPTE 125M. Multiplexed YCbCr data applied to Y_IN. C_IN should be set LOW. NOTE: Input clock is 27MHz.
1 2
00001 00010
Reserved 525i (30/1.001) component 16x9 SMPTE 267M. Multiplexed YCbCr data applied to Y_IN. C_IN should be set LOW. NOTE: Input clock is 36MHz.
3 4
00011 00100
Reserved 625i (25Hz) component EBU tech. 3267E. Multiplexed YCbCr data applied to Y_IN. C_IN should be set LOW. NOTE: Input clock is 27MHz.
5 6
00101 00110
Reserved 625i (25Hz) component 16x9 ITU-R BT.601-5 Part B. Multiplexed YCbCr data applied to Y_IN. C_IN should be set LOW. NOTE: Input clock is 36MHz.
7 8
00111 01000
Reserved 525p (60/1.001Hz) SMPTE 293M. YCbCr data stream applied to Y_IN. C_IN should be set LOW. Timing information is extracted from embedded TRS sequences. NOTE: Input clock is 54MHz.
9 10 11 12
01001 01010 01011 01100
Reserved Reserved Reserved 625p (50Hz) ITU-R BT.1358. YCbCr data stream applied to Y_IN. C_IN should be set LOW. Timing information is extracted from embedded TRS sequences. NOTE: Input clock is 54MHz.
Proprietary and Confidential
18303 - 4
June 2004
10 of 31
GF9331 Data Sheet
Table 3-1: Encoding of STD[4:0] for Selecting Input Data Format (Continued) STD
13
STD[4:0]
01101
Description
625p (50Hz) 16 x 9 with 18MHz sampling. YCbCr data stream applied to Y_IN. C_IN should be set LOW. Timing information is extracted from embedded TRS sequences. NOTE: Input clock is 72MHz.
14
01110
Generic SD input data format with 4:1:1 sampling. YCbCr data is applied to both Y_IN and C_IN. The externally supplied F, V and H signals are used to synchronize the input data stream. NOTE: Input clock is 27MHz.
15
01111
Generic SD input data format with 4:2:2 sampling and single multiplexed YCbCr input format. YCbCr data applied to Y_IN. C_IN should be set LOW. The externally supplied F, V and H signals are used to synchronize the input data stream. NOTE: Input clock is 27 or 36MHz.
16
10000
720p (60 & 60/1.001Hz) SMPTE 296M-2001. Y Data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz or 74.25/1.001MHz.
17
10001
720p (30 & 30/1.001Hz) SMPTE 296M-2001. Y Data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz or 74.25/1.001MHz.
18
10010
1080p (30 & 30/1.001Hz) SMPTE 274M. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz or 74.25/1.001MHz.
19
10011
720p (50Hz) SMPTE 296M-2001. Y Data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz.
20
10100
1080p (25Hz) SMPTE 274M. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz.
21
10101
720p (25Hz) SMPTE 296M-2001. Y Data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz.
22
10110
1080p (24 & 24/1.001Hz) SMPTE 274M. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz or 74.25/1.001MHz.
23
10111
720p (24 & 24/1.001Hz) SMPTE 296M-2001. Y Data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz or 74.25/1.001MHz.
24
11000
1080i (30 & 30/1.001Hz) SMPTE 274M. Y data applied to Y_IN. Cb/Cr data applied to C_IN. NOTE: Input clock is 74.25 MHz or 74.25/1.001MHz.
25
11001
1080p (30 & 30/1.001Hz in Segmented Frame Format) SMPTE RP211-2000. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz or 74.25/1.001MHz.
26
11010
1080i (25Hz) SMPTE 274. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz.
27
11011
1080p (25Hz in Segmented Frame Format) SMPTE RP211-2000. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz.
28
11100
1080i (25Hz) SMPTE 295M. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz.
Proprietary and Confidential
18303 - 4
June 2004
11 of 31
GF9331 Data Sheet
Table 3-1: Encoding of STD[4:0] for Selecting Input Data Format (Continued) STD
29
STD[4:0]
11101
Description
1080p (24 & 24/1.001Hz in Segmented Frame Format) SMPTE RP211-2000. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz or 74.25/1.001MHz.
30
11110
1035i (30Hz) SMPTE 260M. Y data applied to Y_IN. Cb Cr data applied to C_IN. NOTE: Input clock is 74.25MHz.
31
11111
Generic HD input data format with 4:2:2 sampling and a separate Y/C format. Y Data applied to Y_IN. Cb Cr data applied to C_IN. The externally supplied F_IN, V_IN and H_IN signals are used to synchronize the input data stream. NOTE: Input clock is 74.25MHz or 74.25/1.00MHz.
3.2 Input Synchronization
The GF9331 obtains relevant timing information from either embedded TRS information or externally supplied H_IN, V_IN sand F_IN signals. When FVH_EN is set HIGH using either the host interface or the external pin, the GF9331 relies on the externally supplied H_IN, V_IN and F_IN signals for timing information. When FVH_EN is set LOW, the GF9331 extracts the embedded TRS timing information from the video data stream and ignores any timing information present of the F_IN, V_IN and H_IN pins.
3.2.1 Support for Both 8-bit and 10-bit Input Data
The GF9331 supports 8-bit and 10-bit input data. When operating with 8-bit input data, the two LSBs of the GF9331's 10-bit input bus should be set LOW and the input data applied to the 8 MSBs of the input bus.
3.2.2 Generic Input Format Signalling
The GF9331 supports generic input data formats with either 4:1:1 or 4:2:2 sampling structures that require up to 2046 active samples per line and have maximum total line width of 4096 (active + blanking) samples. In addition, there is a limit of 2048 lines per interlaced frame. The following host interface parameters are programmable to describe the generic input data format relative to the F_IN, V_IN and H_IN signals. See Figure 3-1: Generic Input Format Definition.
Proprietary and Confidential
18303 - 4
June 2004
12 of 31
GF9331 Data Sheet
OUTPUT H_BLANK_SIZE 0 EVEN FIELD V_BLANK_SIZE_EVEN ODD FIELD V 1 0 F 1
ODD FIELD
F_OFFSET_ODD V_OFFSET_ODD ODD FIELD V_BLANK_SIZE_ODD EVEN FIELD
EVEN FIELD
F_OFFSET_EVEN V_OFFSET_EVEN EVEN FIELD ODD FIELD
Figure 3-1: Generic Input Format Definition
3.2.2.1 H_BLANK_SIZE This parameter defines the number of samples that comprise the horizontal blanking region. This parameter has a maximum value of 4095 and is to be less than the total line width (active + blanking) sample size. Twelve bits within the host interface are dedicated to this parameter. The GF9331 stores and processes active video samples only (i.e. H_IN =0). 3.2.2.2 V_BLANK_SIZE_ODD This parameter defines the number of lines that comprise the vertical blanking interval that follows the odd field. This parameter has a maximum value of 255. Eight bits within the host interface are dedicated to this parameter. The GF9331 stores and processes active video samples only (i.e. V_IN =0). See Figure 3-1: Generic Input Format Definition. 3.2.2.3 V_BLANK_SIZE_EVEN This parameter defines the number of lines that comprise the vertical blanking interval that follows the even field. This parameter has a maximum value of 255. Eight bits within the host interface are dedicated to this parameter. The GF9331 stores and processes active video samples only (i.e. V_IN =0). See Figure 3-1: Generic Input Format Definition.
Proprietary and Confidential
18303 - 4
June 2004
13 of 31
GF9331 Data Sheet 3.2.2.4 V_OFFSET_ODD This parameter defines the number of lines from the V_IN pin EAV transition to the end of the odd active video field region. This parameter has a maximum value of 255. Eight bits within the host interface are dedicated to this parameter. This parameter has been added to accommodate all video decoders which output non-standard timing for the V _IN signal. See Figure 3-2: V_Offset Definition.
Last active line H_IN Vertical Blanking Region
V_IN
V_OFFSET_ODD/EVEN
Figure 3-2: V_Offset Definition
3.2.2.5 V_OFFSET_EVEN This parameter defines the number of lines from the V_IN pin EAV transition to the end of the even active video field region. This parameter has a maximum value of 255. Eight bits within the host interface are dedicated to this parameter. This parameter has been added to accommodate all video decoders which output non-standard timing for the V_IN signal. See Figure 3-2: V_Offset Definition. 3.2.2.6 F_OFFSET_ODD This parameter defines the number of lines from the F_IN pin EAV transition to the vertical blanking interval following the odd field. This parameter has a maximum value of 255. Eight bits within the host interface are dedicated to this parameter. This parameter has been added to accommodate all video decoders which output non-standard timing for the F_IN signal. See Figure 3-1: Generic Input Format Definition. 3.2.2.7 F_OFFSET_EVEN This parameter defines the number of lines from the F_IN pin EAV transition to the vertical blanking interval following the even field. This parameter has a maximum value of 255. Eight bits within the host interface are dedicated to this parameter. This parameter has been added to accommodate all video decoders which output non-standard timing for the F_IN signal. See Figure 3-1: Generic Input Format Definition. 3.2.2.8 H_POLARITY This parameter defines the polarity of the H_IN pin. With H_POLARITY set LOW, a falling transition on the H_IN pin indicates the end of active video. With H_POLARITY set HIGH, a rising transition on the H_IN pin indicates the end of active video. One bit within the host interface is dedicated to this parameter.
Proprietary and Confidential
18303 - 4
June 2004
14 of 31
GF9331 Data Sheet 3.2.2.9 F_POLARITY This parameter defines the polarity of the F_IN pin. Refer to Table 3-2: F_POLARITY for F_POLARITY encoding. One bit within the host interface is dedicated to this parameter.
Table 3-2: F_POLARITY F_POLARITY Register
0 0 1 1
F_IN Pin
0 1 0 1
F_IN Pin Function
Even Field Odd Field Odd Field Even Field
3.2.2.10 V_POLARITY This parameter defines the polarity of the V_IN pin. With V_POLARITY set LOW, a falling transition on the V_IN pin indicates the end of active video. With V_POLARITY set HIGH, a rising transition on the V_IN pin indicates the end of active video. One bit within the host interface is dedicated to this parameter.
3.3 Seamless Interface to the GF9330 High Performance De-Interlacer for Directional Filter Control
The GF9330 can operate as a stand-alone de-interlacer or can operate in conjunction with the GF9331 Motion Co-processor. The GF9331 contains adaptive multi-directional edge detectors, as well as a vertical motion detector. Edge sensitive control signals are fed directly to the GF9330. These control signals adaptively switch the GF9330's internal de-interlacing filters on a pixel by pixel basis. These control signals are fed to the GF9330 by the GF9331 over the FIL_SEL[3:0] control bus. NOTE: The Y_OUT[9:0] pins of the GF9331 must be connected to the Y_IN[9:0] pins of the GF9330. The C_OUT[9:0] pins of the GF9331 must be connected to the C_IN[9:0] pins of the GF9330. The F_OUT, V_OUT and H_OUT pins of the GF9331 must be connected to the F_IN, V_IN and H_IN pins of the GF9330. The FIL_SEL[3:0] output of the GF9331 must be connected to the FIL_SEL[3:0] input of the GF9330. Refer to Figure 3-3: Using the GF9331 with the GF9330 for Motion Adaptive De-interalcing with edge and vertical motion detection for a pictorial description of connections between the GF9330 and the GF9331.
Y_IN[9:0] Y_OUT[9:0] Y_IN[9:0] C_IN[9:0] FIL_SEL[3:0] Y1_OUT[11:0] C1_OUT[11:0]
C_IN[9:0]
GF9331
C_OUT[9:0] FIL_SEL[3:0]
GF9330
Y2_OUT[11:0] C2_OUT[11:0]
Figure 3-3: Using the GF9331 with the GF9330 for Motion Adaptive De-interalcing with edge and vertical motion detection
Proprietary and Confidential
18303 - 4
June 2004
15 of 31
GF9331 Data Sheet
3.4 Seamless Interface to External SDRAMs
The GF9331 requires two independent external field buffers, each implemented with a 1Mx16-bit (min) SDRAM configuration. This configuration supports all operational modes.
Table 3-3: SDRAM Configuration Format Bypass Configuration per Banka Total of ADDR and BANKb SDRAM properties (per bank) Min. Freq. (MHz)
90 90 90 90
Recomended
Min. Access Time (ns)
5.5 5.5 5.5 5.5
CAS Latency
SD
Yes No
1(1Mx16) 1(1Mx16) 1(1Mx16) 1(1Mx16)
12 12 12 12
3 3 3 3
Micron: MT48LC4M16A2, MT48LC8M16A2
HD
Yes No
a.There are 2. b.This is assuming a 8-column structure.
3.5 Host Interface
The GF9331 provides both serial and parallel host interface control ports for the configuration of internal parameters. The GF9331 is also able to operate in stand-alone mode, with no host interface control. In stand-alone mode, the video standard STD[4:0] and mode of operation MODE (pins or registers, depending on the HOST_EN state). These values are loaded into the device on a falling transition of HOST_EN or after setting RESET LOW. Both the serial and parallel interfaces share common pins as described in Table 3-4: Host Interface Common Pins.
Table 3-4: Host Interface Common Pins GF9331 Pin Name
CS DAT_IO[0] DAT_IO[1] DAT_IO[2] DAT_IO[3] DAT_IO[4] DAT_IO[5] DAT_IO[6]
Parallel Mode
CHIP select Data/address (bit 0) Data/address (bit 1) Data/address (bit 2) Data/address (bit 3) Data/address (bit 4) Data/address (bit 5) Data/address (bit 6)
Serial Mode
SCLK - Serial Clock SDI - Serial data in (not used) (not used) (not used) (not used) (not used) (not used)
Proprietary and Confidential
18303 - 4
June 2004
16 of 31
GF9331 Data Sheet
Table 3-4: Host Interface Common Pins (Continued) GF9331 Pin Name
DAT_IO[7] A_D R_W HOST_EN SER_MD
Parallel Mode
Data/address (bit 7) Address/data select Read/write select Host Interface enable LOW = Parallel mode enable
Serial Mode
SDO - Serial data out SCS - Serial chip select (not used) Host Interface enable HIGH = Serial mode enable
3.5.1 Host Interface Serial Mode
The Gennum Serial Peripheral Interface (GSPI) is a 4 wire interface comprised of serial data in (SDI), serial data out (SDO), an active low serial chip select (SCS), and a clock (SCLK). The interface operates in a master/slave configuration, where the master provides the SCLK, SDI, and SCS signals to the slave or slaves. The master uC_SDO drives the slave(s) SDI input. The SDO pin is a tristate output that allows multiple devices to drive the master uC_SDI. Serial mode operation supports both continuous and burst clock configurations. The interface is illustrated in Figure 3-4: Host Interface Serial Mode.
MASTER (uC)
uC_SCLK uC_SDO uC_SDI uC_SCS
SLAVE (GF9331)
SCLK (CS) SDI (DAT_IO0) SDO (DAT_IO7) SCS (A_D)
Figure 3-4: Host Interface Serial Mode
3.5.1.1 Serial Command Word Description The command word consists of a 16-bit word transmitted MSB first and contains a read/write bit, an Auto-Configure control bit, nine reserved bits and a 5-bit address as shown in Figure 3-5: Serial Command Word Bit Representation.
MSB R/W AC RSV RSV RSV RSV RSV RSV RSV RSV RSV A4 A3 A2 A1 LSB A0
Figure 3-5: Serial Command Word Bit Representation
The R/W bit indicates a Read command if R/W = `1', and a write command when R/W = `1'.
Proprietary and Confidential
18303 - 4
June 2004
17 of 31
GF9331 Data Sheet 3.5.1.2 Auto-Configure The auto-configure feature will be executed when the Auto-Configure control bit is set (used during write operations only). All Auto-Configure registers will be updated to their appropriate settings based on the current video standard and operational mode. When setting the Auto-Configure bit, the command word should be set with only the AC register bit set to `1'. All of the remaining 15 register bits should be set to `0'. To complete the Auto-Configuration 16 more data bits must be loaded into the device. The state of these bits can be either HIGH or LOW. Before Auto-Configuring the device, the standard and mode must be set using either the host interface (HOST_EN = HIGH) or the external pins (with a falling transition of HOST_EN). This simplifies configuration while allowing customization of many features and format parameters. 3.5.1.3 Serial Data Word Description The serial data word consists of a 16-bit word as shown in Figure 3-6: Serial Data Word Bit Representation. Serial data is transmitted or received MSB first.
MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0
Figure 3-6: Serial Data Word Bit Representation
Both command and data words are clocked into the GF9331 on the rising edge of the serial clock (SCLK), which may operate in either a continuous or burst fashion. The first bit (MSB) of the serial output (SDO) is available following the last falling SCLK edge of the "read" command word. The remaining bits are clocked out on the falling edges of SCLK.
Proprietary and Confidential
18303 - 4
June 2004
18 of 31
GF9331 Data Sheet 3.5.1.4 Serial Write Operation All write cycles consist of a command word followed by a data word, both transmitted to the GF9331 via SDI. The first 16-bit word transmitted following a falling transition of SCS is a command word. Several write cycles may be performed while SCS is LOW. See Figure 3-7: Write Cycle.
tSU_HI 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCS tIH_HI SDI R/W AC 0 R R R R R R R R R A4 A3 A2 A1 A0 tSU_HI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
Figure 3-7: Write Cycle
3.5.1.5 Serial Read Operation All read cycles consist of a command word transmitted to the GF9331 via SDI followed by a data word transmitted from the GF9331 via SDO. The first 16-bit word transmitted following a falling transition of SCS is a command word. Several read cycles may be performed while SCS is LOW. See Figure 3-8: Read Cycle.
t OEN_HI 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCS
SDI
R/W 1
AC 0
R
R
R
R
R
R
R
R
R
A4 A3 A2 A1
A0 t OD_HI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 t ODIS_HI
SDO
Figure 3-8: Read Cycle
Proprietary and Confidential
18303 - 4
June 2004
19 of 31
GF9331 Data Sheet
3.5.2 Host Interface Parallel Mode
The Gennum Parallel Peripheral Interface (GPPI) consists of an 8-bit multiplexed address/data bus (DATA_IO[7:0]), a chip select pin (CS), a read/write pin (R_W), and an address/data pin (A_D) as shown in Figure 3-9: Host Interface Parallel Mode.
MASTER (uC) SLAVE (GF9331)
uC_CS
CS
uC_ADDR/DATA
ADDR/DATA (DAT_IO[7:0])
uC_R/W
R_W
uC_A/D
A_D
Figure 3-9: Host Interface Parallel Mode
Data is strobed in/out of the parallel interface on the falling edge of CS. The GF9331 drives the DAT_IO[7:0] bus when the R_W pin is HIGH and the CS pin is LOW, otherwise this port is in a high impedance state. 3.5.2.1 Parallel Address Word Description The 8-bit address word loads in the address to be accessed and allows the Auto-Configure bit to be set. The MSB is the Auto-Configure bit, followed by two reserved bits and a 5-bit address as shown in Figure 3-10: Parallel Address Word Bit Representation.
MSB AC RSV RSV A4 A3 A2 A1 LSB A0
Figure 3-10: Parallel Address Word Bit Representation
Proprietary and Confidential
18303 - 4
June 2004
20 of 31
GF9331 Data Sheet 3.5.2.2 Parallel Write Operation A write cycle to the parallel interface is shown in Figure 3-11: Write Cycle to the Parallel Interface. First an 8-bit address word is provided to the DAT_IO port by setting the R_W pin to LOW and A_D pin to HIGH. The MSB of the address word contains an auto-update flag, which allows automatic configuration of predefined registers (used during write operations only).
tOEN_HI
DAT_IO(7..0)
ADDRESS
(UB) DATA_IN
(LB) DATA_IN
ADDRESS
(UB) DATA_OUT
(LB) DATA_OUT
tSU_HI R_W A_D
tIH_HI
tODIS_HI CS
Figure 3-11: Write Cycle to the Parallel Interface
The 5 LSB's of the address word contain the address location for the read or write operation. The remaining address word bits DAT_IO[6:5] are reserved. The address word is registered on the falling edge of CS. Following this, the A_D pin is driven LOW and two data words are sent upper byte (UB) word first and are each clocked in on the falling edge of CS. Two 8-bit data words must follow each address word to occupy each 16-bit parameter which are defined in Figure 3-12: Host Interface Register Allocation. 3.5.2.3 Parallel Read Operation A read cycle begins with an address write by setting the R_W pin LOW and A_D HIGH. The address is clocked on the falling edge of CS. Following the address, the R_W pin must be driven HIGH and A_D driven LOW to allow the upper byte of data to be clocked out on the first falling edge of CS followed by the lower byte on the second falling edge of CS.
Proprietary and Confidential
18303 - 4
June 2004
21 of 31
GF9331 Data Sheet
Hex
Bit 13
CLK_X1_SEL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
START_OPERATION EXT_MEMCLK_SEL
Address 31
1F 1E 1D 1C 1B 1A 19 18 17 16
FIELD2_HAS_TOP_LINE PROGRESSIVE_INPUT
Bit 15 Bit 14 CMD_RESET
Address 30 Address 29 Address 28 Address 27 Address 26 Address 25
EVEN_LINES_PER_FRAME[1:0]
NO_LINE_DELAYS(9:0) H_BLANK_SIZE(11:0)
FORMAT_SD
15 14 13 12 11 10 F E D C B A 9 8 7 6 5 4 3 2 1 0
ID_MODE(1:0) V_BLANK_SIZE_ODD(7:0)
Address 24 Address 23 Address 22 Address 21 Address 20 Address 19 Address 18 Address 17 Address 16 Address 15 Address 14 Address 13 Address 12 Address 11 Address 10 Address 9
V_BLANK_SIZE_EVEN(7:0)
CC_BLANK_START_LINE(7:0)
CC_BLANK_END_LINE(7:0)
V_OFFSET_ODD(7:0) F_OFFSET_ODD(7:0)
H_POLARITY V_POLARITY F_POLARITY FVH_EN_BIT
CC_BLANK_EN
V_OFFESET_EVEN(7:0) F_OFFESET_EVEN(7:0) EDGE_CTL MODE STD(4:0) VM_CTL
Address 8 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0
Figure 3-12: Host Interface Register Allocation
Proprietary and Confidential
18303 - 4
June 2004
22 of 31
GF9331 Data Sheet
3.5.3 Control Register Definitions
The host interface internal registers are divided into two classes: User Configurable (UC) and Auto-Configurable (AC). Address locations 0 through 6 contain parameters which may be configured by the user. Locations 7 through 31 are automatically configured based on the STD[4:0] and MODE registers, but can be user configured if desired.
Table 3-5: Control Register Definitions Address
0
Bit Location
4:0 5
Register Name
STD[4:0] MODE VM_CTL EDGE_CTL CC_BLANK_EN
Class
UC UC UC UC UC
Description
Defines the video standard as described in Input Data Formats. Enables (MODE=1) or bypasses (MODE=0) the GF9331 processing. Enables (VM_CTL=1) or bypass (VM_CTL=0) vertical motion detection. Enables (EDGE_CTL=1) or bypasses (EDGE_CTL=0) edge detection. Enables (CC_BLANK_EN=1) or bypasses (CC_BLANK_EN=0) blanking in the close captioned video region. Enables the GF9331 to use external F_IN, V_IN, H_IN controls (FVH_EN=1) in place of embedded TRS (FVH_EN=0). When set to '1', F_IN follows normal convention where F_IN is '0' for field 1 (odd) and '1' for field 2 (even). Defines the polarity of the V_IN pin. When set to '1', V_IN follows normal convention where V_IN is HIGH in the vertical blanking region. Defines the polarity of the H_IN pin. When set to '1', H_IN follows normal convention where H_IN is HIGH in the horizontal blanking region. Defines the number of lines from the F_IN pin EAV transition to the vertical blanking interval following the even field. This parameter has a maximum value of 255. Defines the number of lines from the F_IN pin EAV transition to the vertical blanking interval following the odd field. This parameter has a maximum value of 255. Defines the number of lines from the V_IN pin EAV transition to the end of the even active video field region. This parameter has a maximum value of 255. Defines the number of lines from the V_IN pin EAV transition to the end of the odd active video field region. This parameter has a maximum value of 255.
Default
00000 0 0 0 0
1
0 1 6
12
FVH_EN
UC
0
13 14
F_POLARITY V_POLARITY
UC UC
1 1
15
H_POLARITY
UC
1
2
7:0
F_OFFSET_EVEN[7:0]
UC
00000000
15:8
F_OFFSET_ODD[7:0]
UC
00000000
3
7:0
V_OFFSET_EVEN[7:0]
UC
00000000
15:8
V_OFFSET_ODD[7:0]
UC
00000000
Proprietary and Confidential
18303 - 4
June 2004
23 of 31
GF9331 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
6
Bit Location
7:0
Register Name
CC_BLANK_END_ LINE [7:0]
Class
UC
Description
Defines the last line number at which closed captioned blanking ends. For this parameter, line 0 is defined as the first active line of the field/frame. Defines the first line number at which closed captioned blanking starts. For this parameter, line 0 is defined as the first active line of the field/frame. Defines the number of lines that comprise the vertical blanking interval that follows the even input field. This parameter has a maximum value of 255. Defines the number of lines that comprise the vertical blanking interval that follows the odd input field. This parameter has a maximum value of 255. Used to configure the GF9331 SDRAM controller into 8-bit mode for SD video formats. This bit is auto-configured based on the standard and mode selection. Configures the GF9331 to accept a progressive video format. This bit is auto-configured based on the standard and mode selection. Defines the type of video sequence for input video de-multiplexing. When set to "00" the input represents a 4:2:2 sequence, "01" represents a 4:1:1 sequence, and "10" represents an HD format. This word can be auto-configured based on the video standard and mode. Defines the number of horizontal blanked input words per line that corresponds to 2 times the number of blanking pixels per line for 4:2:2 SD modes and is equal to the number of pixels per line for HD formats (maximum 4095). This value can be auto-configured. Set HIGH when field 2, line one is the first line in the video frame (SMPTE 260M). Set to 11 for video standards that have an even number of lines per frame such as SMPTE 295M, otherwise set to 00. Defines the number of line delays to implement within the external field delay. This value is auto-configured based on the standard and mode. The calculation is: NO_LINE_DELAYS = (Number of lines per frame - 3)/2
Default
00000000
15:8
CC_BLANK_START_ LINE [7:0]
V_BLANK_SIZE_EVEN [7:0]
UC
00000000
19
7:0
AC
Auto
15:8
V_BLANK_SIZE_ ODD[7:0]
AC
Auto
21
12
FORMAT_SD
AC
Auto
13
PROGRESSIVE_INPUT
AC
Auto
15:14
ID_MODE[1:0]
AC
Auto
22
11:0
H_BLANK_SIZE[11:0]
AC
Auto
13
FIELD2_HAS_TOP_ LINE
AC
Auto
15:14 23 9:0
EVEN_LINES_PER_ FRAME[1:0]
NO_LINE_DELAYS[9:0]
AC AC
Auto Auto
30
0
EXT_MEMCLK_SEL
AC
Controls the selection of the SDRAM clock source. For VCLK_IN frequencies less than 36MHz, the internal clock doubler can be used. In all other modes an external source is required (MEMCLK_IN). This parameter is normally set for all HD modes and is `0' for all other cases.
Auto
2
CLK_X1_SEL
AC
Auto
Proprietary and Confidential
18303 - 4
June 2004
24 of 31
GF9331 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
31
Bit Location
15
Register Name
CMD_RESET
Class
UC
Description
This parameter forces the GF9331 to enter a reset state. The reset remains in effect until this parameter is cleared with a subsequent command. If using external F_IN, V_IN and H_IN signals, this parameter must be set following the completion of programming the F_IN, V_IN and H_IN offsets.
Default
0
15
START_OPERATION
UC
0
3.6 Closed Captioning
The GF9331 provides a blanking function for selected input video lines. Consecutive lines within each input field are blanked, when this function is enabled, beginning with the CC_BLANK_START_LINE register and ending with the CC_BLANK_END_LINE register. The blanking is applied prior to any processing of the video data. The blanking function is enabled with the CC_BLANK_EN bit. BLANK_START_LINE and BLANK_END_LINE are each allocated 8-bits within the host interface.
3.7 RESET
The RESET pin is an active low pin which will reset all internal logic to it's default conditions when set LOW. On power up it is recommended to reset the device to ensure all internal registers are set to their default state. When applying a reset, the GF9331 will load in the STD[4:0] and MODE[2:0] settings from the external pins. If no further configuration is done, these settings will be used for the operation of the device.
3.8 Modes of Operation
The device supports enabled and disabled modes of operation. The basic operating mode for the GF9331 is selected using the MODE pin or the MODE register within the host interface. See Table 3-6: Modes of Operation.
Table 3-6: Modes of Operation Mode
0 1 Disabled Motion processing of input video signal
Description
Proprietary and Confidential
18303 - 4
June 2004
25 of 31
GF9331 Data Sheet
3.8.1 Motion Processing Mode (MODE=1)
When set to operate as a motion co-processor the GF9331 performs edge and vertical motion detection and provides optimal control of the GF9330 filters through the FIL_SEL[3:0] bus on a pixel by pixel basis.
3.8.2 Disabled Mode (MODE=0)
The GF9331 may also be set to disabled mode of operation. In the disabled mode, no motion co-processing operations are performed and the FIL_SEL[3:0] output bus is set to "0000". In this mode, the input video is still routed to the Y_OUT and C_OUT pins of the GF9330 (NOTE: Only the active portion of the input video signal is passed through the device to the GF9330, all other data will be lost from the input data stream). See Table 3-6: Modes of Operation. The video channel is maintained in bypass mode, however, no processing takes place. Therefore, field buffers are still in use and the chip must be in a known programmed state.
3.9 Processing of Input Formats
The GF9331 provides motion processing for the formats identified in Table 3-7: Processing of Input Formats.
Table 3-7: Processing of Input Formats STD[4:0] Input Format Motion Processing Mode
Supported NA Supported NA Supported NA Supported NA NA NA NA NA NA NA
Disabled Mode
Supported NA Supported NA Supported NA Supported NA Supported NA NA NA Supported Supported
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101
525i (30/1.001) SMPTE 125M Reserved 525i (30/1.001) SMPTE 267M - 16x9 Reserved 625i (25) EBU Tech. 3267 Reserved 625i (25) 16 x9 ITU-R BT.601 Part B Reserved 525p (60/1.001) SMPTE 293M Reserved Reserved Reserved 625p (50) ITU-R BT-1358 625p (50) 16x9
Proprietary and Confidential
18303 - 4
June 2004
26 of 31
GF9331 Data Sheet
Table 3-7: Processing of Input Formats (Continued) STD[4:0] Input Format Motion Processing Mode
Supported Supported NA NA NA NA NA NA NA NA Supported NA Supported NA Supported NA Supported Supported
Disabled Mode
Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported
01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Generic SD 4:1:1 Generic SD 4:2:2 720p (60 & 60/1.001) SMPTE 296M-2001 (System #1 and #2) 720p (30 & 30/1.001) SMPTE 296M-2001 (System #4 and #5) 1080p (30 & 30/1.001) SMPTE 274M (System #7 and #8) 720p (50) SMPTE 296M-2001 (System #3) 1080p (25) SMPTE 274M (System #9) 720p (25) SMPTE 296M-2001 (System #6) 1080p (24 & 24/1.001) SMPTE 274M (System #10 and #11) 720p (24 & 24/1.001) SMPTE 296M-2001 (System #7 and #8) 1080i (30 & 30/1.001) SMPTE 274M (System #4 and #5) 1080PsF (30 & 30/1.001) SMPTE RP211-2000 (System #12 and #13) 1080i (25) SMPTE 274M (System #6) 1080PsF (25) SMPTE RP211-2000 (System #14) 1080i (25) SMPTE 295M (System #2) 1080PsF (24 & 24/1.001) SMPTE RP211-2000 (System #15 & #16) 1035i (30 & 30/1.001) SMPTE 260M Generic HD 4:2:2
Proprietary and Confidential
18303 - 4
June 2004
27 of 31
GF9331 Data Sheet
3.10 Vertical Motion Detection
The GF9331 detects objects moving in the vertical direction (e.g. rolling credits). By performing motion detection, a special vertical filter may be enabled within the GF9331 for interpolating the pixels with vertical motion, thereby reducing slow motion de-interlacing artifacts. This vertical motion detection signal is provided to the GF9330 through the control bus (FIL_SEL[3:0]).
3.10.1 Vertical Motion Feature Control
The GF9331 is able to operate in automatic or disabled mode for vertical motion detection of the video input stream. When set to operate in disabled mode (VM_MODE=0 or VM_CTL=0), the internal vertical motion detection circuitry is disabled. When set to operate in automatic mode (VM_MODE=1 or VM_CTL=1) the GF9331 internally detects vertical motion. See Table 3-8: Vertical Motion Control.
.
Table 3-8: Vertical Motion Control External VM_MODE Pin
0 0 1 1
Host Interface VM_CTL Bit
0 1 0 1
Description
Vertical Motion Detection Disabled Vertical Motion Detection Enabled
3.11 Edge Direction Detection
In order to reduce the edge artifacts caused by the de-interlacing process, pixel gradients are analysed calculated along different edge directions. The analysis is based on several complex techniques including vertical-temporal filtering, gradient and morphological operations. Edge interpolation filters in the GF9330 are enabled based on the edge information provided by the GF9331 through the FIL_SEL[3:0] control bus.
Proprietary and Confidential
18303 - 4
June 2004
28 of 31
GF9331 Data Sheet
3.11.1 Edge Direction Detection Feature Control
The GF9331 is able to operate in automatic or disabled mode for edge detection of the video input stream. When set to operate in disabled mode (ED_MODE=0 or EDGE_CTL=0), the internal edge direction detection circuitry is disabled. When set to operate in automatic mode (ED_MODE=1 or EDGE_CTL=1) the GF9331 internally detects edge directions. See Table 3-9: Edge Detection Feature Control.
.
Table 3-9: Edge Detection Feature Control External ED_MODE Pin
0 0 1 1
Host Interface EDGE_CTL Bit
0 1 0 1
Description
Edge Direction Detection Disabled Edge Direction Detection Enabled
3.12 Video Output
The GF9331 supports all input formats defined in Input Data Formats. Routing of video data to the GF9330 is done via the Y_OUT[9:0] and C_OUT[9:0] busses. Note that only the active portion of the input video signal is passed through the device to the GF9330 unchanged. All other ancillary data is discarded from the input data stream. Timing information is provided by the H_OUT, V_OUT and F_OUT pins.
3.13 Processing Latency
The GF9331 processing latency is constant at 2 lines and 16 pixels for all modes of operation (including bypass).
Proprietary and Confidential
18303 - 4
June 2004
29 of 31
GF9331 Data Sheet
4. Package Dimensions
PIN #1
1 2 3 4 5 6 7 8 9 10 11 1213 14 151617 18 19 20
1.00 (3X) REF.
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.75 0.15 (X328)
A B C D E F G H J K L M N P R T U V W Y
A B C D E F G H J K L M N P R T U V W Y
24.00 REF.
27.00 0.20
4.00, 45 (4X) 24.00 REF. 24.13 27.00 0.20
24.13
1.27
1.27
1.17 REF.
0.56 REF.
Figure 4-1: Package dimensions
0.60 0.10
2.33 0.13
Proprietary and Confidential
18303 - 4
June 2004
30 of 31
GF9331 Data Sheet
5. Revision History
Version
4
ECR
133232
Date
June 2004
Changes and / or Modifications
Corrections to text for bypass mode and memories used. Changed document format.
3
October 2002
Adding row for tri-state leakage current; correcting spelling errors; adding 8-bit serial command word diagram.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET The product is in a development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale.
GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX TEL. +44 (0)1252 747 000 FAX +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright June 2001 Gennum Corporation. All rights reserved. Printed in Canada www.gennum.com Proprietary and Confidential 18303 - 4 31 June 2004 31 of 31

▲Up To Search▲

Price & Availability of GF9331

	To Download GF9331 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .